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GET /api/patches/103751/?format=api
{ "id": 103751, "url": "https://patches.dpdk.org/api/patches/103751/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211104123320.1638915-5-xuemingl@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211104123320.1638915-5-xuemingl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211104123320.1638915-5-xuemingl@nvidia.com", "date": "2021-11-04T12:33:10", "name": "[v4,04/14] common/mlx5: support receive memory pool", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "798b3825428157315a0c47f97da35e87bc65fde7", "submitter": { "id": 1904, "url": "https://patches.dpdk.org/api/people/1904/?format=api", "name": "Xueming Li", "email": "xuemingl@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211104123320.1638915-5-xuemingl@nvidia.com/mbox/", "series": [ { "id": 20310, "url": "https://patches.dpdk.org/api/series/20310/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=20310", "date": "2021-11-04T12:33:06", "name": "net/mlx5: support shared Rx queue", "version": 4, "mbox": "https://patches.dpdk.org/series/20310/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/103751/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/103751/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CB42AA0548;\n\tThu, 4 Nov 2021 13:34:47 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 419DD42717;\n\tThu, 4 Nov 2021 13:34:32 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2057.outbound.protection.outlook.com [40.107.236.57])\n by mails.dpdk.org (Postfix) with ESMTP id 9B2494270B\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Xueming Li <xuemingl@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<xuemingl@nvidia.com>, Lior Margalit <lmargalit@nvidia.com>, \"Slava\n Ovsiienko\" <viacheslavo@nvidia.com>, Matan Azrad <matan@nvidia.com>", "Date": "Thu, 4 Nov 2021 20:33:10 +0800", "Message-ID": "<20211104123320.1638915-5-xuemingl@nvidia.com>", "X-Mailer": "git-send-email 2.33.0", "In-Reply-To": "<20211104123320.1638915-1-xuemingl@nvidia.com>", "References": "<20210727034204.20649-1-xuemingl@nvidia.com>\n <20211104123320.1638915-1-xuemingl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e9b75a21-adad-4056-23ec-08d99f8f6eec", "X-MS-TrafficTypeDiagnostic": "DM5PR12MB2471:", "X-Microsoft-Antispam-PRVS": "\n <DM5PR12MB2471E37A95B3CA22A48D7AAFA18D9@DM5PR12MB2471.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:1122;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n c8H/6J+qHTWDTby7Cxe6K4Q1LqLh8yeQ2fYtI1R2jsWB6nTlaT142n/TCH7AE9qiHxXoxMNxlcjdYcrRns3IP7kiCnR5LNj+htlh5xrMQijj+MO/Z31Qc2i3fiNIQ4rnE+OZ0e76SotKz1lHC7VSWCmrPa7PKuxIJuKHaapjq8Mc3BWgMqGzV+b/VYrtY8SJy4aa59xLC9TE+aErwZWsGfyocyBPzLlbpjdaOd3i+m+7985ibAfUC00+gMIIC4mcRC2G6SUCHcHIX0BrRWcTEJcFxnY3QEF+hRnFhxMSOPAc8GRgeH6qV6WUssq3OJw1y4sMTcsjQ/slQY4RAH6T8psMxHlKuy6KEFbiDTl4el4AHz2BXDcdo9ihq7kujrrGBXAxUBf1N2/+w7JHAHXkkRI73bmhH+3Zxtcmw/Bsxof1R5cFFx0H65jWVolZPj0HxLaJfr8ZVDKa5uUcV4S2AqItKzEju2vV6P51s/HcXrMN8/u7N/JdYLIF+53PV4GkrJiQrin+wf8ovUue9qI+9zwJ47Ed613FkO+1wLDU+nRL3ITaUWCngdBBqKVTawYzx4MCtBDhXiHPYtiAi+3ctHF3eB7eC+j7m/VRhL64Ena4e5L8rhQ+p6f/xFSdeYotJqGHawKbJ5RQFUC3XWctZ09m9nXCcW04RcGBRciaXOul8Vd2pL3DJMaThWHk23RIvvhARfIo8qocA/f+XLKj/A==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(47076005)(6286002)(70586007)(70206006)(54906003)(6916009)(4326008)(426003)(508600001)(2616005)(107886003)(55016002)(2906002)(8676002)(6666004)(356005)(36860700001)(26005)(82310400003)(7696005)(1076003)(5660300002)(8936002)(36756003)(336012)(83380400001)(316002)(7636003)(16526019)(30864003)(186003)(86362001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Nov 2021 12:34:23.6007 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e9b75a21-adad-4056-23ec-08d99f8f6eec", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT058.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR12MB2471", "Subject": "[dpdk-dev] [PATCH v4 04/14] common/mlx5: support receive memory pool", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The hardware Receive Memory Pool (RMP) object holds the destination for\nincoming packets/messages that are routed to the RMP through RQs. RMP\nenables sharing of memory across multiple Receive Queues. Multiple\nReceive Queues can be attached to the same RMP and consume memory\nfrom that shared poll. When using RMPs, completions are reported to the\nCQ pointed to by the RQ, user index that set in RQ creation time is\ncarried to completion entry.\n\nThis patch enables RMP based RQ, RMP is created when mlx5_devx_rq.rmp is\nset.\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\nAcked-by: Slava Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/common/mlx5/mlx5_common_devx.c | 295 +++++++++++++++++++++----\n drivers/common/mlx5/mlx5_common_devx.h | 19 +-\n drivers/net/mlx5/mlx5_devx.c | 4 +-\n 3 files changed, 271 insertions(+), 47 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_common_devx.c b/drivers/common/mlx5/mlx5_common_devx.c\nindex 825f84b1833..85b5282061a 100644\n--- a/drivers/common/mlx5/mlx5_common_devx.c\n+++ b/drivers/common/mlx5/mlx5_common_devx.c\n@@ -271,6 +271,39 @@ mlx5_devx_sq_create(void *ctx, struct mlx5_devx_sq *sq_obj, uint16_t log_wqbb_n,\n \treturn -rte_errno;\n }\n \n+/**\n+ * Destroy DevX Receive Queue resources.\n+ *\n+ * @param[in] rq_res\n+ * DevX RQ resource to destroy.\n+ */\n+static void\n+mlx5_devx_wq_res_destroy(struct mlx5_devx_wq_res *rq_res)\n+{\n+\tif (rq_res->umem_obj)\n+\t\tclaim_zero(mlx5_os_umem_dereg(rq_res->umem_obj));\n+\tif (rq_res->umem_buf)\n+\t\tmlx5_free((void *)(uintptr_t)rq_res->umem_buf);\n+\tmemset(rq_res, 0, sizeof(*rq_res));\n+}\n+\n+/**\n+ * Destroy DevX Receive Memory Pool.\n+ *\n+ * @param[in] rmp\n+ * DevX RMP to destroy.\n+ */\n+static void\n+mlx5_devx_rmp_destroy(struct mlx5_devx_rmp *rmp)\n+{\n+\tMLX5_ASSERT(rmp->ref_cnt == 0);\n+\tif (rmp->rmp) {\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(rmp->rmp));\n+\t\trmp->rmp = NULL;\n+\t}\n+\tmlx5_devx_wq_res_destroy(&rmp->wq);\n+}\n+\n /**\n * Destroy DevX Queue Pair.\n *\n@@ -389,55 +422,48 @@ mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint16_t log_wqbb_n,\n void\n mlx5_devx_rq_destroy(struct mlx5_devx_rq *rq)\n {\n-\tif (rq->rq)\n+\tif (rq->rq) {\n \t\tclaim_zero(mlx5_devx_cmd_destroy(rq->rq));\n-\tif (rq->umem_obj)\n-\t\tclaim_zero(mlx5_os_umem_dereg(rq->umem_obj));\n-\tif (rq->umem_buf)\n-\t\tmlx5_free((void *)(uintptr_t)rq->umem_buf);\n+\t\trq->rq = NULL;\n+\t\tif (rq->rmp)\n+\t\t\trq->rmp->ref_cnt--;\n+\t}\n+\tif (rq->rmp == NULL) {\n+\t\tmlx5_devx_wq_res_destroy(&rq->wq);\n+\t} else {\n+\t\tif (rq->rmp->ref_cnt == 0)\n+\t\t\tmlx5_devx_rmp_destroy(rq->rmp);\n+\t}\n }\n \n /**\n- * Create Receive Queue using DevX API.\n- *\n- * Get a pointer to partially initialized attributes structure, and updates the\n- * following fields:\n- * wq_umem_valid\n- * wq_umem_id\n- * wq_umem_offset\n- * dbr_umem_valid\n- * dbr_umem_id\n- * dbr_addr\n- * log_wq_pg_sz\n- * All other fields are updated by caller.\n+ * Create WQ resources using DevX API.\n *\n * @param[in] ctx\n * Context returned from mlx5 open_device() glue function.\n- * @param[in/out] rq_obj\n- * Pointer to RQ to create.\n * @param[in] wqe_size\n * Size of WQE structure.\n * @param[in] log_wqbb_n\n * Log of number of WQBBs in queue.\n- * @param[in] attr\n- * Pointer to RQ attributes structure.\n * @param[in] socket\n * Socket to use for allocation.\n+ * @param[out] wq_attr\n+ * Pointer to WQ attributes structure.\n+ * @param[out] wq_res\n+ * Pointer to WQ resource to create.\n *\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-int\n-mlx5_devx_rq_create(void *ctx, struct mlx5_devx_rq *rq_obj, uint32_t wqe_size,\n-\t\t uint16_t log_wqbb_n,\n-\t\t struct mlx5_devx_create_rq_attr *attr, int socket)\n+static int\n+mlx5_devx_wq_init(void *ctx, uint32_t wqe_size, uint16_t log_wqbb_n, int socket,\n+\t\t struct mlx5_devx_wq_attr *wq_attr,\n+\t\t struct mlx5_devx_wq_res *wq_res)\n {\n-\tstruct mlx5_devx_obj *rq = NULL;\n \tstruct mlx5dv_devx_umem *umem_obj = NULL;\n \tvoid *umem_buf = NULL;\n \tsize_t alignment = MLX5_WQE_BUF_ALIGNMENT;\n \tuint32_t umem_size, umem_dbrec;\n-\tuint16_t rq_size = 1 << log_wqbb_n;\n \tint ret;\n \n \tif (alignment == (size_t)-1) {\n@@ -446,7 +472,7 @@ mlx5_devx_rq_create(void *ctx, struct mlx5_devx_rq *rq_obj, uint32_t wqe_size,\n \t\treturn -rte_errno;\n \t}\n \t/* Allocate memory buffer for WQEs and doorbell record. */\n-\tumem_size = wqe_size * rq_size;\n+\tumem_size = wqe_size * (1 << log_wqbb_n);\n \tumem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);\n \tumem_size += MLX5_DBR_SIZE;\n \tumem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,\n@@ -464,14 +490,60 @@ mlx5_devx_rq_create(void *ctx, struct mlx5_devx_rq *rq_obj, uint32_t wqe_size,\n \t\trte_errno = errno;\n \t\tgoto error;\n \t}\n+\t/* Fill WQ attributes for RQ/RMP object creation. */\n+\twq_attr->wq_umem_valid = 1;\n+\twq_attr->wq_umem_id = mlx5_os_get_umem_id(umem_obj);\n+\twq_attr->wq_umem_offset = 0;\n+\twq_attr->dbr_umem_valid = 1;\n+\twq_attr->dbr_umem_id = wq_attr->wq_umem_id;\n+\twq_attr->dbr_addr = umem_dbrec;\n+\twq_attr->log_wq_pg_sz = MLX5_LOG_PAGE_SIZE;\n \t/* Fill attributes for RQ object creation. */\n-\tattr->wq_attr.wq_umem_valid = 1;\n-\tattr->wq_attr.wq_umem_id = mlx5_os_get_umem_id(umem_obj);\n-\tattr->wq_attr.wq_umem_offset = 0;\n-\tattr->wq_attr.dbr_umem_valid = 1;\n-\tattr->wq_attr.dbr_umem_id = attr->wq_attr.wq_umem_id;\n-\tattr->wq_attr.dbr_addr = umem_dbrec;\n-\tattr->wq_attr.log_wq_pg_sz = MLX5_LOG_PAGE_SIZE;\n+\twq_res->umem_buf = umem_buf;\n+\twq_res->umem_obj = umem_obj;\n+\twq_res->db_rec = RTE_PTR_ADD(umem_buf, umem_dbrec);\n+\treturn 0;\n+error:\n+\tret = rte_errno;\n+\tif (umem_obj)\n+\t\tclaim_zero(mlx5_os_umem_dereg(umem_obj));\n+\tif (umem_buf)\n+\t\tmlx5_free((void *)(uintptr_t)umem_buf);\n+\trte_errno = ret;\n+\treturn -rte_errno;\n+}\n+\n+/**\n+ * Create standalone Receive Queue using DevX API.\n+ *\n+ * @param[in] ctx\n+ * Context returned from mlx5 open_device() glue function.\n+ * @param[in/out] rq_obj\n+ * Pointer to RQ to create.\n+ * @param[in] wqe_size\n+ * Size of WQE structure.\n+ * @param[in] log_wqbb_n\n+ * Log of number of WQBBs in queue.\n+ * @param[in] attr\n+ * Pointer to RQ attributes structure.\n+ * @param[in] socket\n+ * Socket to use for allocation.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_devx_rq_std_create(void *ctx, struct mlx5_devx_rq *rq_obj,\n+\t\t\tuint32_t wqe_size, uint16_t log_wqbb_n,\n+\t\t\tstruct mlx5_devx_create_rq_attr *attr, int socket)\n+{\n+\tstruct mlx5_devx_obj *rq;\n+\tint ret;\n+\n+\tret = mlx5_devx_wq_init(ctx, wqe_size, log_wqbb_n, socket,\n+\t\t\t\t&attr->wq_attr, &rq_obj->wq);\n+\tif (ret != 0)\n+\t\treturn ret;\n \t/* Create receive queue object with DevX. */\n \trq = mlx5_devx_cmd_create_rq(ctx, attr, socket);\n \tif (!rq) {\n@@ -479,21 +551,160 @@ mlx5_devx_rq_create(void *ctx, struct mlx5_devx_rq *rq_obj, uint32_t wqe_size,\n \t\trte_errno = ENOMEM;\n \t\tgoto error;\n \t}\n-\trq_obj->umem_buf = umem_buf;\n-\trq_obj->umem_obj = umem_obj;\n \trq_obj->rq = rq;\n-\trq_obj->db_rec = RTE_PTR_ADD(rq_obj->umem_buf, umem_dbrec);\n \treturn 0;\n error:\n \tret = rte_errno;\n-\tif (umem_obj)\n-\t\tclaim_zero(mlx5_os_umem_dereg(umem_obj));\n-\tif (umem_buf)\n-\t\tmlx5_free((void *)(uintptr_t)umem_buf);\n+\tmlx5_devx_wq_res_destroy(&rq_obj->wq);\n+\trte_errno = ret;\n+\treturn -rte_errno;\n+}\n+\n+/**\n+ * Create Receive Memory Pool using DevX API.\n+ *\n+ * @param[in] ctx\n+ * Context returned from mlx5 open_device() glue function.\n+ * @param[in/out] rq_obj\n+ * Pointer to RQ to create.\n+ * @param[in] wqe_size\n+ * Size of WQE structure.\n+ * @param[in] log_wqbb_n\n+ * Log of number of WQBBs in queue.\n+ * @param[in] attr\n+ * Pointer to RQ attributes structure.\n+ * @param[in] socket\n+ * Socket to use for allocation.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_devx_rmp_create(void *ctx, struct mlx5_devx_rmp *rmp_obj,\n+\t\t uint32_t wqe_size, uint16_t log_wqbb_n,\n+\t\t struct mlx5_devx_wq_attr *wq_attr, int socket)\n+{\n+\tstruct mlx5_devx_create_rmp_attr rmp_attr = { 0 };\n+\tint ret;\n+\n+\tif (rmp_obj->rmp != NULL)\n+\t\treturn 0;\n+\trmp_attr.wq_attr = *wq_attr;\n+\tret = mlx5_devx_wq_init(ctx, wqe_size, log_wqbb_n, socket,\n+\t\t\t\t&rmp_attr.wq_attr, &rmp_obj->wq);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\trmp_attr.state = MLX5_RMPC_STATE_RDY;\n+\trmp_attr.basic_cyclic_rcv_wqe =\n+\t\twq_attr->wq_type != MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;\n+\t/* Create receive memory pool object with DevX. */\n+\trmp_obj->rmp = mlx5_devx_cmd_create_rmp(ctx, &rmp_attr, socket);\n+\tif (rmp_obj->rmp == NULL) {\n+\t\tDRV_LOG(ERR, \"Can't create DevX RMP object.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\treturn 0;\n+error:\n+\tret = rte_errno;\n+\tmlx5_devx_wq_res_destroy(&rmp_obj->wq);\n+\trte_errno = ret;\n+\treturn -rte_errno;\n+}\n+\n+/**\n+ * Create Shared Receive Queue based on RMP using DevX API.\n+ *\n+ * @param[in] ctx\n+ * Context returned from mlx5 open_device() glue function.\n+ * @param[in/out] rq_obj\n+ * Pointer to RQ to create.\n+ * @param[in] wqe_size\n+ * Size of WQE structure.\n+ * @param[in] log_wqbb_n\n+ * Log of number of WQBBs in queue.\n+ * @param[in] attr\n+ * Pointer to RQ attributes structure.\n+ * @param[in] socket\n+ * Socket to use for allocation.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_devx_rq_shared_create(void *ctx, struct mlx5_devx_rq *rq_obj,\n+\t\t\t uint32_t wqe_size, uint16_t log_wqbb_n,\n+\t\t\t struct mlx5_devx_create_rq_attr *attr, int socket)\n+{\n+\tstruct mlx5_devx_obj *rq;\n+\tint ret;\n+\n+\tret = mlx5_devx_rmp_create(ctx, rq_obj->rmp, wqe_size, log_wqbb_n,\n+\t\t\t\t &attr->wq_attr, socket);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\tattr->mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP;\n+\tattr->rmpn = rq_obj->rmp->rmp->id;\n+\tattr->flush_in_error_en = 0;\n+\tmemset(&attr->wq_attr, 0, sizeof(attr->wq_attr));\n+\t/* Create receive queue object with DevX. */\n+\trq = mlx5_devx_cmd_create_rq(ctx, attr, socket);\n+\tif (!rq) {\n+\t\tDRV_LOG(ERR, \"Can't create DevX RMP RQ object.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\trq_obj->rq = rq;\n+\trq_obj->rmp->ref_cnt++;\n+\treturn 0;\n+error:\n+\tret = rte_errno;\n+\tmlx5_devx_rq_destroy(rq_obj);\n \trte_errno = ret;\n \treturn -rte_errno;\n }\n \n+/**\n+ * Create Receive Queue using DevX API. Shared RQ is created only if rmp set.\n+ *\n+ * Get a pointer to partially initialized attributes structure, and updates the\n+ * following fields:\n+ * wq_umem_valid\n+ * wq_umem_id\n+ * wq_umem_offset\n+ * dbr_umem_valid\n+ * dbr_umem_id\n+ * dbr_addr\n+ * log_wq_pg_sz\n+ * All other fields are updated by caller.\n+ *\n+ * @param[in] ctx\n+ * Context returned from mlx5 open_device() glue function.\n+ * @param[in/out] rq_obj\n+ * Pointer to RQ to create.\n+ * @param[in] wqe_size\n+ * Size of WQE structure.\n+ * @param[in] log_wqbb_n\n+ * Log of number of WQBBs in queue.\n+ * @param[in] attr\n+ * Pointer to RQ attributes structure.\n+ * @param[in] socket\n+ * Socket to use for allocation.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_devx_rq_create(void *ctx, struct mlx5_devx_rq *rq_obj,\n+\t\t uint32_t wqe_size, uint16_t log_wqbb_n,\n+\t\t struct mlx5_devx_create_rq_attr *attr, int socket)\n+{\n+\tif (rq_obj->rmp == NULL)\n+\t\treturn mlx5_devx_rq_std_create(ctx, rq_obj, wqe_size,\n+\t\t\t\t\t log_wqbb_n, attr, socket);\n+\treturn mlx5_devx_rq_shared_create(ctx, rq_obj, wqe_size,\n+\t\t\t\t\t log_wqbb_n, attr, socket);\n+}\n \n /**\n * Change QP state to RTS.\ndiff --git a/drivers/common/mlx5/mlx5_common_devx.h b/drivers/common/mlx5/mlx5_common_devx.h\nindex f699405f69b..7ceac040f8b 100644\n--- a/drivers/common/mlx5/mlx5_common_devx.h\n+++ b/drivers/common/mlx5/mlx5_common_devx.h\n@@ -45,14 +45,27 @@ struct mlx5_devx_qp {\n \tvolatile uint32_t *db_rec; /* The QP doorbell record. */\n };\n \n-/* DevX Receive Queue structure. */\n-struct mlx5_devx_rq {\n-\tstruct mlx5_devx_obj *rq; /* The RQ DevX object. */\n+/* DevX Receive Queue resource structure. */\n+struct mlx5_devx_wq_res {\n \tvoid *umem_obj; /* The RQ umem object. */\n \tvolatile void *umem_buf;\n \tvolatile uint32_t *db_rec; /* The RQ doorbell record. */\n };\n \n+/* DevX Receive Memory Pool structure. */\n+struct mlx5_devx_rmp {\n+\tstruct mlx5_devx_obj *rmp; /* The RMP DevX object. */\n+\tuint32_t ref_cnt; /* Reference count. */\n+\tstruct mlx5_devx_wq_res wq;\n+};\n+\n+/* DevX Receive Queue structure. */\n+struct mlx5_devx_rq {\n+\tstruct mlx5_devx_obj *rq; /* The RQ DevX object. */\n+\tstruct mlx5_devx_rmp *rmp; /* Shared RQ RMP object. */\n+\tstruct mlx5_devx_wq_res wq; /* WQ resource of standalone RQ. */\n+};\n+\n /* mlx5_common_devx.c */\n \n __rte_internal\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 424f77be790..443252df05d 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -515,8 +515,8 @@ mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \tret = mlx5_devx_modify_rq(tmpl, MLX5_RXQ_MOD_RST2RDY);\n \tif (ret)\n \t\tgoto error;\n-\trxq_data->wqes = (void *)(uintptr_t)tmpl->rq_obj.umem_buf;\n-\trxq_data->rq_db = (uint32_t *)(uintptr_t)tmpl->rq_obj.db_rec;\n+\trxq_data->wqes = (void *)(uintptr_t)tmpl->rq_obj.wq.umem_buf;\n+\trxq_data->rq_db = (uint32_t *)(uintptr_t)tmpl->rq_obj.wq.db_rec;\n \trxq_data->cq_arm_sn = 0;\n \trxq_data->cq_ci = 0;\n \tmlx5_rxq_initialize(rxq_data);\n", "prefixes": [ "v4", "04/14" ] }