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GET /api/patches/103392/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 103392,
    "url": "https://patches.dpdk.org/api/patches/103392/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211102031729.35536-2-humin29@huawei.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211102031729.35536-2-humin29@huawei.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211102031729.35536-2-humin29@huawei.com",
    "date": "2021-11-02T03:17:21",
    "name": "[1/9] net/hns3: fix the shift of DMA address in Rx/Tx queue",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "9856d694f2ca3c5dd109808c44de3f7ef5cba98b",
    "submitter": {
        "id": 1944,
        "url": "https://patches.dpdk.org/api/people/1944/?format=api",
        "name": "humin (Q)",
        "email": "humin29@huawei.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211102031729.35536-2-humin29@huawei.com/mbox/",
    "series": [
        {
            "id": 20189,
            "url": "https://patches.dpdk.org/api/series/20189/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=20189",
            "date": "2021-11-02T03:17:27",
            "name": "code optimization for hns3 PMD",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/20189/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/103392/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/103392/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1C569A0C4D;\n\tTue,  2 Nov 2021 04:20:21 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 428B4410FE;\n\tTue,  2 Nov 2021 04:19:41 +0100 (CET)",
            "from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255])\n by mails.dpdk.org (Postfix) with ESMTP id 881E741101\n for <dev@dpdk.org>; Tue,  2 Nov 2021 04:19:32 +0100 (CET)",
            "from dggeme756-chm.china.huawei.com (unknown [172.30.72.56])\n by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4Hjw7S1n6wz1DHwk;\n Tue,  2 Nov 2021 11:17:24 +0800 (CST)",
            "from localhost.localdomain (10.69.192.56) by\n dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id\n 15.1.2308.15; Tue, 2 Nov 2021 11:19:27 +0800"
        ],
        "From": "\"Min Hu (Connor)\" <humin29@huawei.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<ferruh.yigit@intel.com>, <thomas@monjalon.net>",
        "Date": "Tue, 2 Nov 2021 11:17:21 +0800",
        "Message-ID": "<20211102031729.35536-2-humin29@huawei.com>",
        "X-Mailer": "git-send-email 2.33.0",
        "In-Reply-To": "<20211102031729.35536-1-humin29@huawei.com>",
        "References": "<20211102031729.35536-1-humin29@huawei.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.69.192.56]",
        "X-ClientProxiedBy": "dggems702-chm.china.huawei.com (10.3.19.179) To\n dggeme756-chm.china.huawei.com (10.3.19.102)",
        "X-CFilter-Loop": "Reflected",
        "Subject": "[dpdk-dev] [PATCH 1/9] net/hns3: fix the shift of DMA address in\n Rx/Tx queue",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Huisong Li <lihuisong@huawei.com>\n\nThe patch obtains the upper 32 bits of the Rx/Tx queue DMA address in one\nstep instead of two steps.\n\nFixes: bba636698316 (\"net/hns3: support Rx/Tx and related operations\")\n\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\n---\n drivers/net/hns3/hns3_rxtx.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c\nindex ceb98025f8..00af73c850 100644\n--- a/drivers/net/hns3/hns3_rxtx.c\n+++ b/drivers/net/hns3/hns3_rxtx.c\n@@ -322,7 +322,7 @@ hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)\n \n \thns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);\n \thns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,\n-\t\t       (uint32_t)((dma_addr >> 31) >> 1));\n+\t\t       (uint32_t)(dma_addr >> 32));\n \n \thns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,\n \t\t       hns3_buf_size2type(rx_buf_len));\n@@ -337,7 +337,7 @@ hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)\n \n \thns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);\n \thns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,\n-\t\t       (uint32_t)((dma_addr >> 31) >> 1));\n+\t\t       (uint32_t)(dma_addr >> 32));\n \n \thns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,\n \t\t       HNS3_CFG_DESC_NUM(txq->nb_tx_desc));\n",
    "prefixes": [
        "1/9"
    ]
}