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GET /api/patches/103331/?format=api
{ "id": 103331, "url": "https://patches.dpdk.org/api/patches/103331/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211101110509.17359-2-ting.xu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211101110509.17359-2-ting.xu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211101110509.17359-2-ting.xu@intel.com", "date": "2021-11-01T11:05:07", "name": "[v2,1/3] net/ice/base: support add HW profile for RSS raw flow", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e930ffdea9b5344c0cf2ecea6b19cbf75d4707ac", "submitter": { "id": 1363, "url": "https://patches.dpdk.org/api/people/1363/?format=api", "name": "Xu, Ting", "email": "ting.xu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211101110509.17359-2-ting.xu@intel.com/mbox/", "series": [ { "id": 20170, "url": "https://patches.dpdk.org/api/series/20170/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=20170", "date": "2021-11-01T11:05:07", "name": "[v2,1/3] net/ice/base: support add HW profile for RSS raw flow", "version": 2, "mbox": "https://patches.dpdk.org/series/20170/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/103331/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/103331/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BA0FDA0C57;\n\tMon, 1 Nov 2021 12:03:20 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AAA44410E6;\n\tMon, 1 Nov 2021 12:03:20 +0100 (CET)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n by mails.dpdk.org (Postfix) with ESMTP id 1FAA940DF6\n for <dev@dpdk.org>; Mon, 1 Nov 2021 12:03:18 +0100 (CET)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 01 Nov 2021 04:03:18 -0700", "from dpdk-xuting-second.sh.intel.com ([10.67.116.150])\n by orsmga007.jf.intel.com with ESMTP; 01 Nov 2021 04:03:16 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10154\"; a=\"291831716\"", "E=Sophos;i=\"5.87,199,1631602800\"; d=\"scan'208\";a=\"291831716\"", "E=Sophos;i=\"5.87,199,1631602800\"; d=\"scan'208\";a=\"488582286\"" ], "X-ExtLoop1": "1", "From": "Ting Xu <ting.xu@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, qiming.yang@intel.com, Ting Xu <ting.xu@intel.com>", "Date": "Mon, 1 Nov 2021 19:05:07 +0800", "Message-Id": "<20211101110509.17359-2-ting.xu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211101110509.17359-1-ting.xu@intel.com>", "References": "<20211008070934.6956-1-ting.xu@intel.com>\n <20211101110509.17359-1-ting.xu@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 1/3] net/ice/base: support add HW profile for\n RSS raw flow", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Based on the parser library, we can directly set HW profile and\nassociate VSI for RSS raw flows. Add symmetric hash configuration\nfor raw flow.\n\nSigned-off-by: Ting Xu <ting.xu@intel.com>\n---\n drivers/net/ice/base/ice_flow.c | 109 ++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_flow.h | 16 +++++\n 2 files changed, 125 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex f699dbbc74..da27d157c0 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -4071,6 +4071,115 @@ ice_rss_update_symm(struct ice_hw *hw,\n \t}\n }\n \n+/**\n+ * ice_rss_cfg_raw_symm - configure symmetric hash parameters\n+ * for raw pattern\n+ * @hw: pointer to the hardware structure\n+ * @prof: pointer to parser profile\n+ * @prof_id: profile ID\n+ *\n+ * Calculate symmetric hash parameters based on input protocol type.\n+ */\n+static void\n+ice_rss_cfg_raw_symm(struct ice_hw *hw,\n+\t\t struct ice_parser_profile *prof, u64 prof_id)\n+{\n+\tu8 src_idx, dst_idx, proto_id;\n+\tint len, i = 0;\n+\n+\twhile (i < prof->fv_num) {\n+\t\tproto_id = prof->fv[i].proto_id;\n+\n+\t\tswitch (proto_id) {\n+\t\tcase ICE_PROT_IPV4_OF_OR_S:\n+\t\t\tlen = ICE_FLOW_FLD_SZ_IPV4_ADDR /\n+\t\t\t ICE_FLOW_FV_EXTRACT_SZ;\n+\t\t\tif (prof->fv[i].offset ==\n+\t\t\t ICE_FLOW_FIELD_IPV4_SRC_OFFSET &&\n+\t\t\t prof->fv[i + len].proto_id == proto_id &&\n+\t\t\t prof->fv[i + len].offset ==\n+\t\t\t ICE_FLOW_FIELD_IPV4_DST_OFFSET) {\n+\t\t\t\tsrc_idx = i;\n+\t\t\t\tdst_idx = i + len;\n+\t\t\t\ti += 2 * len;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\ti++;\n+\t\t\tcontinue;\n+\t\tcase ICE_PROT_IPV6_OF_OR_S:\n+\t\t\tlen = ICE_FLOW_FLD_SZ_IPV6_ADDR /\n+\t\t\t ICE_FLOW_FV_EXTRACT_SZ;\n+\t\t\tif (prof->fv[i].offset ==\n+\t\t\t ICE_FLOW_FIELD_IPV6_SRC_OFFSET &&\n+\t\t\t prof->fv[i + len].proto_id == proto_id &&\n+\t\t\t prof->fv[i + len].offset ==\n+\t\t\t ICE_FLOW_FIELD_IPV6_DST_OFFSET) {\n+\t\t\t\tsrc_idx = i;\n+\t\t\t\tdst_idx = i + len;\n+\t\t\t\ti += 2 * len;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\ti++;\n+\t\t\tcontinue;\n+\t\tcase ICE_PROT_TCP_IL:\n+\t\tcase ICE_PROT_UDP_IL_OR_S:\n+\t\tcase ICE_PROT_SCTP_IL:\n+\t\t\tlen = ICE_FLOW_FLD_SZ_PORT /\n+\t\t\t ICE_FLOW_FV_EXTRACT_SZ;\n+\t\t\tif (prof->fv[i].offset ==\n+\t\t\t ICE_FLOW_FIELD_SRC_PORT_OFFSET &&\n+\t\t\t prof->fv[i + len].proto_id == proto_id &&\n+\t\t\t prof->fv[i + len].offset ==\n+\t\t\t ICE_FLOW_FIELD_DST_PORT_OFFSET) {\n+\t\t\t\tsrc_idx = i;\n+\t\t\t\tdst_idx = i + len;\n+\t\t\t\ti += 2 * len;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\ti++;\n+\t\t\tcontinue;\n+\t\tdefault:\n+\t\t\ti++;\n+\t\t\tcontinue;\n+\t\t}\n+\t\tice_rss_config_xor(hw, prof_id, src_idx, dst_idx, len);\n+\t}\n+}\n+\n+/* Max registers index per packet profile */\n+#define ICE_SYMM_REG_INDEX_MAX 6\n+\n+/**\n+ * ice_rss_update_raw_symm - update symmetric hash configuration\n+ * for raw pattern\n+ * @hw: pointer to the hardware structure\n+ * @cfg: configure parameters for raw pattern\n+ * @id: profile tracking ID\n+ *\n+ * Update symmetric hash configuration for raw pattern if required.\n+ * Otherwise only clear to default.\n+ */\n+void\n+ice_rss_update_raw_symm(struct ice_hw *hw,\n+\t\t\tstruct ice_rss_raw_cfg *cfg, u64 id)\n+{\n+\tstruct ice_prof_map *map;\n+\tu8 prof_id, m;\n+\n+\tice_acquire_lock(&hw->blk[ICE_BLK_RSS].es.prof_map_lock);\n+\tmap = ice_search_prof_id(hw, ICE_BLK_RSS, id);\n+\tif (map)\n+\t\tprof_id = map->prof_id;\n+\tice_release_lock(&hw->blk[ICE_BLK_RSS].es.prof_map_lock);\n+\tif (!map)\n+\t\treturn;\n+\t/* clear to default */\n+\tfor (m = 0; m < ICE_SYMM_REG_INDEX_MAX; m++)\n+\t\twr32(hw, GLQF_HSYMM(prof_id, m), 0);\n+\tif (cfg->symm)\n+\t\tice_rss_cfg_raw_symm(hw, &cfg->prof, prof_id);\n+}\n+\n /**\n * ice_add_rss_cfg_sync - add an RSS configuration\n * @hw: pointer to the hardware structure\ndiff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h\nindex dea7b3c0e8..aac7ead891 100644\n--- a/drivers/net/ice/base/ice_flow.h\n+++ b/drivers/net/ice/base/ice_flow.h\n@@ -149,6 +149,13 @@\n #define ICE_FLOW_HASH_NAT_T_ESP_IPV6_SPI \\\n \t(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_NAT_T_ESP_SPI)\n \n+#define ICE_FLOW_FIELD_IPV4_SRC_OFFSET 12\n+#define ICE_FLOW_FIELD_IPV4_DST_OFFSET 16\n+#define ICE_FLOW_FIELD_IPV6_SRC_OFFSET 8\n+#define ICE_FLOW_FIELD_IPV6_DST_OFFSET 24\n+#define ICE_FLOW_FIELD_SRC_PORT_OFFSET 0\n+#define ICE_FLOW_FIELD_DST_PORT_OFFSET 2\n+\n /* Protocol header fields within a packet segment. A segment consists of one or\n * more protocol headers that make up a logical group of protocol headers. Each\n * logical group of protocol headers encapsulates or is encapsulated using/by\n@@ -493,11 +500,18 @@ struct ice_flow_prof {\n \tstruct ice_flow_action *acts;\n };\n \n+struct ice_rss_raw_cfg {\n+\tstruct ice_parser_profile prof;\n+\tbool raw_ena;\n+\tbool symm;\n+};\n+\n struct ice_rss_cfg {\n \tstruct LIST_ENTRY_TYPE l_entry;\n \t/* bitmap of VSIs added to the RSS entry */\n \tice_declare_bitmap(vsis, ICE_MAX_VSI);\n \tstruct ice_rss_hash_cfg hash;\n+\tstruct ice_rss_raw_cfg raw;\n };\n \n enum ice_flow_action_type {\n@@ -585,5 +599,7 @@ ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle,\n enum ice_status\n ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle,\n \t\tconst struct ice_rss_hash_cfg *cfg);\n+void ice_rss_update_raw_symm(struct ice_hw *hw,\n+\t\t\tstruct ice_rss_raw_cfg *cfg, u64 id);\n u64 ice_get_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u32 hdrs);\n #endif /* _ICE_FLOW_H_ */\n", "prefixes": [ "v2", "1/3" ] }