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GET /api/patches/103268/?format=api
{ "id": 103268, "url": "https://patches.dpdk.org/api/patches/103268/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211030103619.29924-5-fengchengwen@huawei.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211030103619.29924-5-fengchengwen@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211030103619.29924-5-fengchengwen@huawei.com", "date": "2021-10-30T10:36:17", "name": "[4/6] dma/hisilicon: add data path functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "89e2c55f829219765e20dc4073645c20d8b800ce", "submitter": { "id": 2146, "url": "https://patches.dpdk.org/api/people/2146/?format=api", "name": "fengchengwen", "email": "fengchengwen@huawei.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211030103619.29924-5-fengchengwen@huawei.com/mbox/", "series": [ { "id": 20148, "url": "https://patches.dpdk.org/api/series/20148/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=20148", "date": "2021-10-30T10:36:19", "name": "dma: add hisilicon DMA driver", "version": 1, "mbox": "https://patches.dpdk.org/series/20148/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/103268/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/103268/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9BBC7A0C4B;\n\tSat, 30 Oct 2021 12:41:11 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 95E0E4111C;\n\tSat, 30 Oct 2021 12:40:57 +0200 (CEST)", "from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188])\n by mails.dpdk.org (Postfix) with ESMTP id 855DD40DDB\n for <dev@dpdk.org>; Sat, 30 Oct 2021 12:40:52 +0200 (CEST)", "from dggemv704-chm.china.huawei.com (unknown [172.30.72.56])\n by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4HhG6N19V6z90Nc;\n Sat, 30 Oct 2021 18:40:44 +0800 (CST)", "from dggpeml500024.china.huawei.com (7.185.36.10) by\n dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.1.2308.15; Sat, 30 Oct 2021 18:40:49 +0800", "from localhost.localdomain (10.67.165.24) by\n dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.1.2308.15; Sat, 30 Oct 2021 18:40:49 +0800" ], "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<thomas@monjalon.net>", "CC": "<dev@dpdk.org>", "Date": "Sat, 30 Oct 2021 18:36:17 +0800", "Message-ID": "<20211030103619.29924-5-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.33.0", "In-Reply-To": "<20211030103619.29924-1-fengchengwen@huawei.com>", "References": "<20211030103619.29924-1-fengchengwen@huawei.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.165.24]", "X-ClientProxiedBy": "dggems705-chm.china.huawei.com (10.3.19.182) To\n dggpeml500024.china.huawei.com (7.185.36.10)", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH 4/6] dma/hisilicon: add data path functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch add data path functions for Kunpeng DMA devices.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\n---\n drivers/dma/hisilicon/hisi_dmadev.c | 206 ++++++++++++++++++++++++++++\n drivers/dma/hisilicon/hisi_dmadev.h | 16 +++\n 2 files changed, 222 insertions(+)", "diff": "diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c\nindex bcdcf4de4b..d03967cae3 100644\n--- a/drivers/dma/hisilicon/hisi_dmadev.c\n+++ b/drivers/dma/hisilicon/hisi_dmadev.c\n@@ -529,6 +529,206 @@ hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f)\n \treturn 0;\n }\n \n+static int\n+hisi_dma_copy(void *dev_private, uint16_t vchan,\n+\t\t rte_iova_t src, rte_iova_t dst,\n+\t\t uint32_t length, uint64_t flags)\n+{\n+\tstruct hisi_dma_dev *hw = dev_private;\n+\tstruct hisi_dma_sqe *sqe = &hw->sqe[hw->sq_tail];\n+\n+\tRTE_SET_USED(vchan);\n+\n+\tif (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head)\n+\t\treturn -ENOSPC;\n+\n+\tsqe->dw0 = rte_cpu_to_le_32(SQE_OPCODE_M2M);\n+\tsqe->dw1 = 0;\n+\tsqe->dw2 = 0;\n+\tsqe->length = rte_cpu_to_le_32(length);\n+\tsqe->src_addr = rte_cpu_to_le_64(src);\n+\tsqe->dst_addr = rte_cpu_to_le_64(dst);\n+\thw->sq_tail = (hw->sq_tail + 1) & hw->sq_depth_mask;\n+\thw->submitted++;\n+\n+\tif (flags & RTE_DMA_OP_FLAG_FENCE)\n+\t\tsqe->dw0 |= rte_cpu_to_le_32(SQE_FENCE_FLAG);\n+\tif (flags & RTE_DMA_OP_FLAG_SUBMIT)\n+\t\trte_write32(rte_cpu_to_le_32(hw->sq_tail), hw->sq_tail_reg);\n+\n+\treturn hw->ridx++;\n+}\n+\n+static int\n+hisi_dma_submit(void *dev_private, uint16_t vchan)\n+{\n+\tstruct hisi_dma_dev *hw = dev_private;\n+\n+\tRTE_SET_USED(vchan);\n+\trte_write32(rte_cpu_to_le_32(hw->sq_tail), hw->sq_tail_reg);\n+\n+\treturn 0;\n+}\n+\n+static inline void\n+hisi_dma_scan_cq(struct hisi_dma_dev *hw)\n+{\n+\tvolatile struct hisi_dma_cqe *cqe;\n+\tuint16_t csq_head = hw->cq_sq_head;\n+\tuint16_t cq_head = hw->cq_head;\n+\tuint16_t count = 0;\n+\tuint64_t misc;\n+\n+\twhile (true) {\n+\t\tcqe = &hw->cqe[cq_head];\n+\t\tmisc = cqe->misc;\n+\t\tmisc = rte_le_to_cpu_64(misc);\n+\t\tif (FIELD_GET(CQE_VALID_B, misc) != hw->cqe_vld)\n+\t\t\tbreak;\n+\n+\t\tcsq_head = FIELD_GET(CQE_SQ_HEAD_MASK, misc);\n+\t\tif (unlikely(misc & CQE_STATUS_MASK))\n+\t\t\thw->status[csq_head] = FIELD_GET(CQE_STATUS_MASK,\n+\t\t\t\t\t\t\t misc);\n+\n+\t\tcount++;\n+\t\tcq_head++;\n+\t\tif (cq_head == hw->cq_depth) {\n+\t\t\thw->cqe_vld = !hw->cqe_vld;\n+\t\t\tcq_head = 0;\n+\t\t}\n+\t}\n+\n+\tif (count == 0)\n+\t\treturn;\n+\n+\thw->cq_head = cq_head;\n+\thw->cq_sq_head = (csq_head + 1) & hw->sq_depth_mask;\n+\thw->cqs_completed += count;\n+\tif (hw->cqs_completed >= HISI_DMA_CQ_RESERVED) {\n+\t\trte_write32(rte_cpu_to_le_32(cq_head), hw->cq_head_reg);\n+\t\thw->cqs_completed = 0;\n+\t}\n+}\n+\n+static inline uint16_t\n+hisi_dma_calc_cpls(struct hisi_dma_dev *hw, const uint16_t nb_cpls)\n+{\n+\tuint16_t cpl_num;\n+\n+\tif (hw->cq_sq_head >= hw->sq_head)\n+\t\tcpl_num = hw->cq_sq_head - hw->sq_head;\n+\telse\n+\t\tcpl_num = hw->sq_depth_mask + 1 - hw->sq_head + hw->cq_sq_head;\n+\n+\tif (cpl_num > nb_cpls)\n+\t\tcpl_num = nb_cpls;\n+\n+\treturn cpl_num;\n+}\n+\n+static uint16_t\n+hisi_dma_completed(void *dev_private,\n+\t\t uint16_t vchan, const uint16_t nb_cpls,\n+\t\t uint16_t *last_idx, bool *has_error)\n+{\n+\tstruct hisi_dma_dev *hw = dev_private;\n+\tuint16_t sq_head = hw->sq_head;\n+\tuint16_t cpl_num, i;\n+\n+\tRTE_SET_USED(vchan);\n+\thisi_dma_scan_cq(hw);\n+\n+\tcpl_num = hisi_dma_calc_cpls(hw, nb_cpls);\n+\tfor (i = 0; i < cpl_num; i++) {\n+\t\tif (hw->status[sq_head]) {\n+\t\t\t*has_error = true;\n+\t\t\tbreak;\n+\t\t}\n+\t\tsq_head = (sq_head + 1) & hw->sq_depth_mask;\n+\t}\n+\tif (i > 0) {\n+\t\thw->cridx += i;\n+\t\t*last_idx = hw->cridx - 1;\n+\t\thw->sq_head = sq_head;\n+\t}\n+\thw->completed += i;\n+\n+\treturn i;\n+}\n+\n+static enum rte_dma_status_code\n+hisi_dma_convert_status(uint16_t status)\n+{\n+\tswitch (status) {\n+\tcase HISI_DMA_STATUS_SUCCESS:\n+\t\treturn RTE_DMA_STATUS_SUCCESSFUL;\n+\tcase HISI_DMA_STATUS_INVALID_OPCODE:\n+\t\treturn RTE_DMA_STATUS_INVALID_OPCODE;\n+\tcase HISI_DMA_STATUS_INVALID_LENGTH:\n+\t\treturn RTE_DMA_STATUS_INVALID_LENGTH;\n+\tcase HISI_DMA_STATUS_USER_ABORT:\n+\t\treturn RTE_DMA_STATUS_USER_ABORT;\n+\tcase HISI_DMA_STATUS_REMOTE_READ_ERROR:\n+\tcase HISI_DMA_STATUS_AXI_READ_ERROR:\n+\t\treturn RTE_DMA_STATUS_BUS_READ_ERROR;\n+\tcase HISI_DMA_STATUS_AXI_WRITE_ERROR:\n+\t\treturn RTE_DMA_STATUS_BUS_WRITE_ERROR;\n+\tcase HISI_DMA_STATUS_DATA_POISON:\n+\tcase HISI_DMA_STATUS_REMOTE_DATA_POISION:\n+\t\treturn RTE_DMA_STATUS_DATA_POISION;\n+\tcase HISI_DMA_STATUS_SQE_READ_ERROR:\n+\tcase HISI_DMA_STATUS_SQE_READ_POISION:\n+\t\treturn RTE_DMA_STATUS_DESCRIPTOR_READ_ERROR;\n+\tcase HISI_DMA_STATUS_LINK_DOWN_ERROR:\n+\t\treturn RTE_DMA_STATUS_DEV_LINK_ERROR;\n+\tdefault:\n+\t\treturn RTE_DMA_STATUS_ERROR_UNKNOWN;\n+\t}\n+}\n+\n+static uint16_t\n+hisi_dma_completed_status(void *dev_private,\n+\t\t\t uint16_t vchan, const uint16_t nb_cpls,\n+\t\t\t uint16_t *last_idx, enum rte_dma_status_code *status)\n+{\n+\tstruct hisi_dma_dev *hw = dev_private;\n+\tuint16_t sq_head = hw->sq_head;\n+\tuint16_t cpl_num, i;\n+\n+\tRTE_SET_USED(vchan);\n+\thisi_dma_scan_cq(hw);\n+\n+\tcpl_num = hisi_dma_calc_cpls(hw, nb_cpls);\n+\tfor (i = 0; i < cpl_num; i++) {\n+\t\tstatus[i] = hisi_dma_convert_status(hw->status[sq_head]);\n+\t\thw->errors += !!status[i];\n+\t\thw->status[sq_head] = HISI_DMA_STATUS_SUCCESS;\n+\t\tsq_head = (sq_head + 1) & hw->sq_depth_mask;\n+\t}\n+\tif (likely(cpl_num > 0)) {\n+\t\thw->cridx += cpl_num;\n+\t\t*last_idx = hw->cridx - 1;\n+\t\thw->sq_head = sq_head;\n+\t}\n+\thw->completed += cpl_num;\n+\n+\treturn cpl_num;\n+}\n+\n+static uint16_t\n+hisi_dma_burst_capacity(const void *dev_private, uint16_t vchan)\n+{\n+\tconst struct hisi_dma_dev *hw = dev_private;\n+\tuint16_t sq_head = hw->sq_head;\n+\tuint16_t sq_tail = hw->sq_tail;\n+\n+\tRTE_SET_USED(vchan);\n+\n+\treturn (sq_tail >= sq_head) ? hw->sq_depth_mask - sq_tail + sq_head :\n+\t\t\t\t sq_head - 1 - sq_tail;\n+}\n+\n static void\n hisi_dma_gen_pci_device_name(const struct rte_pci_device *pci_dev,\n \t\t\t char *name, size_t size)\n@@ -597,6 +797,12 @@ hisi_dma_create(struct rte_pci_device *pci_dev, uint8_t queue_id,\n \n \tdev->device = &pci_dev->device;\n \tdev->dev_ops = &hisi_dmadev_ops;\n+\tdev->fp_obj->dev_private = dev->data->dev_private;\n+\tdev->fp_obj->copy = hisi_dma_copy;\n+\tdev->fp_obj->submit = hisi_dma_submit;\n+\tdev->fp_obj->completed = hisi_dma_completed;\n+\tdev->fp_obj->completed_status = hisi_dma_completed_status;\n+\tdev->fp_obj->burst_capacity = hisi_dma_burst_capacity;\n \n \thw = dev->data->dev_private;\n \thw->data = dev->data;\ndiff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h\nindex dd0315cd31..12e209c86e 100644\n--- a/drivers/dma/hisilicon/hisi_dmadev.h\n+++ b/drivers/dma/hisilicon/hisi_dmadev.h\n@@ -115,6 +115,22 @@ enum {\n \tHISI_DMA_STATE_RUN,\n };\n \n+/**\n+ * Hardware complete status define:\n+ */\n+#define HISI_DMA_STATUS_SUCCESS\t\t\t0x0\n+#define HISI_DMA_STATUS_INVALID_OPCODE\t\t0x1\n+#define HISI_DMA_STATUS_INVALID_LENGTH\t\t0x2\n+#define HISI_DMA_STATUS_USER_ABORT\t\t0x4\n+#define HISI_DMA_STATUS_REMOTE_READ_ERROR\t0x10\n+#define HISI_DMA_STATUS_AXI_READ_ERROR\t\t0x20\n+#define HISI_DMA_STATUS_AXI_WRITE_ERROR\t\t0x40\n+#define HISI_DMA_STATUS_DATA_POISON\t\t0x80\n+#define HISI_DMA_STATUS_SQE_READ_ERROR\t\t0x100\n+#define HISI_DMA_STATUS_SQE_READ_POISION\t0x200\n+#define HISI_DMA_STATUS_REMOTE_DATA_POISION\t0x400\n+#define HISI_DMA_STATUS_LINK_DOWN_ERROR\t\t0x800\n+\n /**\n * After scanning the CQ array, the CQ head register needs to be updated.\n * Updating the register involves write memory barrier operations.\n", "prefixes": [ "4/6" ] }