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GET /api/patches/102636/?format=api
{ "id": 102636, "url": "https://patches.dpdk.org/api/patches/102636/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211022091142.51397-8-xuemingl@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211022091142.51397-8-xuemingl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211022091142.51397-8-xuemingl@nvidia.com", "date": "2021-10-22T09:11:41", "name": "[v4,7/8] net/mlx5: enable DevX Tx queue creation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b37227245ae3955973fe1a830d4918bba271b9ed", "submitter": { "id": 1904, "url": "https://patches.dpdk.org/api/people/1904/?format=api", "name": "Xueming Li", "email": "xuemingl@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211022091142.51397-8-xuemingl@nvidia.com/mbox/", "series": [ { "id": 19903, "url": "https://patches.dpdk.org/api/series/19903/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19903", "date": "2021-10-22T09:11:34", "name": "net/mlx5: support more than 255 representors", "version": 4, "mbox": "https://patches.dpdk.org/series/19903/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/102636/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/102636/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 871CFA0C43;\n\tFri, 22 Oct 2021 11:12:49 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1165741181;\n\tFri, 22 Oct 2021 11:12:48 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2060.outbound.protection.outlook.com [40.107.244.60])\n by mails.dpdk.org (Postfix) with ESMTP id CBCA841149\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Xueming Li <xuemingl@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<xuemingl@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Lior\n Margalit <lmargalit@nvidia.com>, Matan Azrad <matan@nvidia.com>", "Date": "Fri, 22 Oct 2021 17:11:41 +0800", "Message-ID": "<20211022091142.51397-8-xuemingl@nvidia.com>", "X-Mailer": "git-send-email 2.33.0", "In-Reply-To": "<20211022091142.51397-1-xuemingl@nvidia.com>", "References": "<20210927083256.337450-1-xuemingl@nvidia.com>\n <20211022091142.51397-1-xuemingl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "99d71a84-887e-487d-e1d6-08d9953c1ad8", "X-MS-TrafficTypeDiagnostic": "SA0PR12MB4382:", "X-Microsoft-Antispam-PRVS": "\n <SA0PR12MB4382B80CA9AFAFCAFC2BEC39A1809@SA0PR12MB4382.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:3513;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 2je4VI58s2CQfUdXkGzPSb84GSZyc5w760ilcz0NdeYAynwZGnkJdQ3XT03W4MUk9wyoZraVdOEZ2yLrnuHl0SRyF6rk9NgQg+vTvvlnp/Edt6TfrhYLM1DUzj/AmFH+1MVQx4XUd7+ZgeFPSOdEU/J8PsssvVhYx+8UYNHNzlCqBJfOOnECfIWqvjvOaGE+B1C+zRA8fkJ0zWD8+NXNzq8gw/2ljaw0Rta0BezkCCJDNYEPlpFD7AUpXQUBxSFzgy5dFo/iS7hi1afuB1lRA48a9l+zPVH74MoRqaRrOlg21+3YxDyORnvlBR1Zy67CLD9he4dJ0ukbh/wV2OuuA1KA6C6h8ZbgPpv0vNij9vwTLlkPle+4f3ioK38h11qzBflRGdr1NaH1kAm2ocWozcKVLn+32NqAMntPoKMxGkaEuDPn/CpmzxVqTvkM7itWuYL8oWD3yO9UouANDPoN/OyA6WhHsmjJBLARRmX4Yi4UWf91/JTZp1EylsMY/xBXqJ2KwUg/1w6NZiiL/EKu7+u/vTh2OaYFLAAchlPoLEIHFL1c/+oL8mcH9zLGtay1RPZyTXA15Yg7IFycHON6HMM+PFdFKjaJpu16XyUa149mt/onGqRYZuZdvIzha+v0++CVxXs8RshxQCzkAK/bDJet9BNknGibeTsbXO+UFZDEnguzz8hYCi0IdNjM/KjCVQoN9dE1Zg+G1ORUfCSXuw==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(36860700001)(7696005)(508600001)(8676002)(36756003)(16526019)(336012)(1076003)(186003)(7636003)(6286002)(70206006)(70586007)(4326008)(55016002)(6916009)(2616005)(8936002)(86362001)(5660300002)(36906005)(83380400001)(54906003)(107886003)(82310400003)(316002)(426003)(2906002)(356005)(26005)(47076005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Oct 2021 09:12:42.9534 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 99d71a84-887e-487d-e1d6-08d9953c1ad8", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT005.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA0PR12MB4382", "Subject": "[dpdk-dev] [PATCH v4 7/8] net/mlx5: enable DevX Tx queue creation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Verbs API does not support Infiniband device port number larger 255 by\ndesign. To support more representors on a single Infiniband device DevX\nAPI should be engaged.\n\nWhile creating Send Queue (SQ) object with Verbs API, the PMD assigned\nIB device port attribute and kernel created the default miss flows in\nFDB domain, to redirect egress traffic from the queue being created to\nrepresentor appropriate peer (wire, HPF, VF or SF).\n\nWith DevX API there is no IB-device port attribute (it is merely kernel\none, DevX operates in PRM terms) and PMD must create default miss flows\nin FDB explicitly. PMD did not provide this and using DevX API for\nE-Switch configurations was disabled.\n\nThe default miss FDB flow matches E-Switch manager vport (to make sure\nthe source is some representor) and SQn (Send Queue number - device\ninternal queue index). The root flow table managed by kernel/firmware\nand it does not support vport redirect action, we have to split the\ndefault miss flow into two ones:\n\n- flow with lowest priority in the root table that matches E-Switch\nmanager vport ID and jump to group 1.\n- flow in group 1 that matches E-Switch manager vport ID and SQn and\nforwards packet to peer vport\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 62 +-------------------------\n drivers/net/mlx5/mlx5.h | 2 +\n drivers/net/mlx5/mlx5_devx.c | 10 ++---\n drivers/net/mlx5/mlx5_devx.h | 2 +\n drivers/net/mlx5/mlx5_flow.c | 74 ++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_trigger.c | 11 ++++-\n 6 files changed, 94 insertions(+), 67 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 101ef943f42..2db842cb983 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -646,56 +646,6 @@ mlx5_init_once(void)\n \treturn ret;\n }\n \n-/**\n- * Create the Tx queue DevX/Verbs object.\n- *\n- * @param dev\n- * Pointer to Ethernet device.\n- * @param idx\n- * Queue index in DPDK Tx queue array.\n- *\n- * @return\n- * 0 on success, a negative errno value otherwise and rte_errno is set.\n- */\n-static int\n-mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n-{\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_txq_data *txq_data = (*priv->txqs)[idx];\n-\tstruct mlx5_txq_ctrl *txq_ctrl =\n-\t\t\tcontainer_of(txq_data, struct mlx5_txq_ctrl, txq);\n-\n-\tif (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN)\n-\t\treturn mlx5_txq_devx_obj_new(dev, idx);\n-#ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET\n-\tif (!priv->config.dv_esw_en)\n-\t\treturn mlx5_txq_devx_obj_new(dev, idx);\n-#endif\n-\treturn mlx5_txq_ibv_obj_new(dev, idx);\n-}\n-\n-/**\n- * Release an Tx DevX/verbs queue object.\n- *\n- * @param txq_obj\n- * DevX/Verbs Tx queue object.\n- */\n-static void\n-mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj)\n-{\n-\tif (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {\n-\t\tmlx5_txq_devx_obj_release(txq_obj);\n-\t\treturn;\n-\t}\n-#ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET\n-\tif (!txq_obj->txq_ctrl->priv->config.dv_esw_en) {\n-\t\tmlx5_txq_devx_obj_release(txq_obj);\n-\t\treturn;\n-\t}\n-#endif\n-\tmlx5_txq_ibv_obj_release(txq_obj);\n-}\n-\n /**\n * DV flow counter mode detect and config.\n *\n@@ -1744,16 +1694,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\t\t\tibv_obj_ops.drop_action_create;\n \t\tpriv->obj_ops.drop_action_destroy =\n \t\t\t\t\t\tibv_obj_ops.drop_action_destroy;\n-#ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET\n-\t\tpriv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify;\n-#else\n-\t\tif (config->dv_esw_en)\n-\t\t\tpriv->obj_ops.txq_obj_modify =\n-\t\t\t\t\t\tibv_obj_ops.txq_obj_modify;\n-#endif\n-\t\t/* Use specific wrappers for Tx object. */\n-\t\tpriv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new;\n-\t\tpriv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release;\n \t\tmlx5_queue_counter_id_prepare(eth_dev);\n \t\tpriv->obj_ops.lb_dummy_queue_create =\n \t\t\t\t\tmlx5_rxq_ibv_obj_dummy_lb_create;\n@@ -1764,7 +1704,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t}\n \tif (config->tx_pp &&\n \t (priv->config.dv_esw_en ||\n-\t priv->obj_ops.txq_obj_new != mlx5_os_txq_obj_new)) {\n+\t priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new)) {\n \t\t/*\n \t\t * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support\n \t\t * packet pacing and already checked above.\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 6f5a78b2493..adef86d3ae0 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1664,6 +1664,8 @@ int mlx5_ctrl_flow(struct rte_eth_dev *dev,\n \t\t struct rte_flow_item_eth *eth_mask);\n int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);\n struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);\n+uint32_t mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev,\n+\t\t\t\t\t uint32_t txq);\n void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,\n \t\t\t\t uint64_t async_id, int status);\n void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 6b6b9c77ae4..9050a32eb1c 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -102,9 +102,9 @@ mlx5_devx_modify_rq(struct mlx5_rxq_obj *rxq_obj, uint8_t type)\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static int\n-mlx5_devx_modify_sq(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,\n-\t\t uint8_t dev_port)\n+int\n+mlx5_txq_devx_modify(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,\n+\t\t uint8_t dev_port)\n {\n \tstruct mlx5_devx_modify_sq_attr msq_attr = { 0 };\n \tint ret;\n@@ -1121,7 +1121,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \t*txq_data->qp_db = 0;\n \ttxq_data->qp_num_8s = txq_obj->sq_obj.sq->id << 8;\n \t/* Change Send Queue state to Ready-to-Send. */\n-\tret = mlx5_devx_modify_sq(txq_obj, MLX5_TXQ_MOD_RST2RDY, 0);\n+\tret = mlx5_txq_devx_modify(txq_obj, MLX5_TXQ_MOD_RST2RDY, 0);\n \tif (ret) {\n \t\trte_errno = errno;\n \t\tDRV_LOG(ERR,\n@@ -1190,7 +1190,7 @@ struct mlx5_obj_ops devx_obj_ops = {\n \t.drop_action_create = mlx5_devx_drop_action_create,\n \t.drop_action_destroy = mlx5_devx_drop_action_destroy,\n \t.txq_obj_new = mlx5_txq_devx_obj_new,\n-\t.txq_obj_modify = mlx5_devx_modify_sq,\n+\t.txq_obj_modify = mlx5_txq_devx_modify,\n \t.txq_obj_release = mlx5_txq_devx_obj_release,\n \t.lb_dummy_queue_create = NULL,\n \t.lb_dummy_queue_release = NULL,\ndiff --git a/drivers/net/mlx5/mlx5_devx.h b/drivers/net/mlx5/mlx5_devx.h\nindex bc8a8d6b73c..a95207a6b9a 100644\n--- a/drivers/net/mlx5/mlx5_devx.h\n+++ b/drivers/net/mlx5/mlx5_devx.h\n@@ -8,6 +8,8 @@\n #include \"mlx5.h\"\n \n int mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx);\n+int mlx5_txq_devx_modify(struct mlx5_txq_obj *obj,\n+\t\t\t enum mlx5_txq_modify_type type, uint8_t dev_port);\n void mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj);\n \n extern struct mlx5_obj_ops devx_obj_ops;\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 4abeae8ce2d..1d493f12075 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -6596,6 +6596,80 @@ mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev)\n \t\t\t\t\t\t actions, false, &error);\n }\n \n+/**\n+ * Create a dedicated flow rule on e-switch table 1, matches ESW manager\n+ * and sq number, directs all packets to peer vport.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param txq\n+ * Txq index.\n+ *\n+ * @return\n+ * Flow ID on success, 0 otherwise and rte_errno is set.\n+ */\n+uint32_t\n+mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq)\n+{\n+\tstruct rte_flow_attr attr = {\n+\t\t.group = 0,\n+\t\t.priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR,\n+\t\t.ingress = 1,\n+\t\t.egress = 0,\n+\t\t.transfer = 1,\n+\t};\n+\tstruct rte_flow_item_port_id port_spec = {\n+\t\t.id = MLX5_PORT_ESW_MGR,\n+\t};\n+\tstruct mlx5_rte_flow_item_tx_queue txq_spec = {\n+\t\t.queue = txq,\n+\t};\n+\tstruct rte_flow_item pattern[] = {\n+\t\t{\n+\t\t\t.type = RTE_FLOW_ITEM_TYPE_PORT_ID,\n+\t\t\t.spec = &port_spec,\n+\t\t},\n+\t\t{\n+\t\t\t.type = (enum rte_flow_item_type)\n+\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,\n+\t\t\t.spec = &txq_spec,\n+\t\t},\n+\t\t{\n+\t\t\t.type = RTE_FLOW_ITEM_TYPE_END,\n+\t\t},\n+\t};\n+\tstruct rte_flow_action_jump jump = {\n+\t\t.group = 1,\n+\t};\n+\tstruct rte_flow_action_port_id port = {\n+\t\t.id = dev->data->port_id,\n+\t};\n+\tstruct rte_flow_action actions[] = {\n+\t\t{\n+\t\t\t.type = RTE_FLOW_ACTION_TYPE_JUMP,\n+\t\t\t.conf = &jump,\n+\t\t},\n+\t\t{\n+\t\t\t.type = RTE_FLOW_ACTION_TYPE_END,\n+\t\t},\n+\t};\n+\tstruct rte_flow_error error;\n+\n+\t/*\n+\t * Creates group 0, highest priority jump flow.\n+\t * Matches txq to bypass kernel packets.\n+\t */\n+\tif (flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, actions,\n+\t\t\t false, &error) == 0)\n+\t\treturn 0;\n+\t/* Create group 1, lowest priority redirect flow for txq. */\n+\tattr.group = 1;\n+\tactions[0].conf = &port;\n+\tactions[0].type = RTE_FLOW_ACTION_TYPE_PORT_ID;\n+\treturn flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern,\n+\t\t\t\tactions, false, &error);\n+}\n+\n /**\n * Validate a flow supported by the NIC.\n *\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 54c28934372..ca43bd51aab 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -1308,9 +1308,18 @@ mlx5_traffic_enable(struct rte_eth_dev *dev)\n \t\t\t\tgoto error;\n \t\t\t}\n \t\t}\n+\t\tif ((priv->representor || priv->master) &&\n+\t\t priv->config.dv_esw_en) {\n+\t\t\tif (mlx5_flow_create_devx_sq_miss_flow(dev, i) == 0) {\n+\t\t\t\tDRV_LOG(ERR,\n+\t\t\t\t\t\"Port %u Tx queue %u SQ create representor devx default miss rule failed.\",\n+\t\t\t\t\tdev->data->port_id, i);\n+\t\t\t\tgoto error;\n+\t\t\t}\n+\t\t}\n \t\tmlx5_txq_release(dev, i);\n \t}\n-\tif (priv->config.dv_esw_en && !priv->config.vf && !priv->config.sf) {\n+\tif ((priv->master || priv->representor) && priv->config.dv_esw_en) {\n \t\tif (mlx5_flow_create_esw_table_zero_flow(dev))\n \t\t\tpriv->fdb_def_rule = 1;\n \t\telse\n", "prefixes": [ "v4", "7/8" ] }