Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/102288/?format=api
{ "id": 102288, "url": "https://patches.dpdk.org/api/patches/102288/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211019181459.1709976-1-jerinj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211019181459.1709976-1-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211019181459.1709976-1-jerinj@marvell.com", "date": "2021-10-19T18:14:57", "name": "[RFC,0/1] Dataplane Workload Accelerator library", "commit_ref": null, "pull_url": null, "state": null, "archived": false, "hash": null, "submitter": { "id": 1188, "url": "https://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211019181459.1709976-1-jerinj@marvell.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/102288/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/102288/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 40C7CA0547;\n\tTue, 19 Oct 2021 20:18:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 318CD40142;\n\tTue, 19 Oct 2021 20:18:55 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 997CE4003E\n for <dev@dpdk.org>; Tue, 19 Oct 2021 20:18:53 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id\n 19JFUWjs021326;\n Tue, 19 Oct 2021 11:18:19 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 3bt05g0xt3-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 19 Oct 2021 11:18:19 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 19 Oct 2021 11:18:17 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 19 Oct 2021 11:18:17 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n by maili.marvell.com (Postfix) with ESMTP id 09BC23F708C;\n Tue, 19 Oct 2021 11:17:52 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=q1YGfCaKuhE3NNAaMA761Nu6p3wU8GmqgnloCiYENw4=;\n b=BQICw3p2EBvme9luShW20nkgJqFHSzbk+0WgRIIM90I61XHMW6sTi7uwgdbievG9X25D\n HQe+1heQrJ6ItOyMGgKKzNxj0iWiBuJ+q6YUfXo5Bs4ijAM37uc+tKfsSQf8Pzi3EW9H\n 6s7yRFIy4NLLxGKhk9bzk9etquZSVwNuY1iKJIn1NEH+3qbsyXedcGF3phYLxzs3eW+J\n M3sXXUGsi8ZxQxflkEWTI2FaLxwLxQaF3+20PaM5njJUudGfLtS+ZH2TEXybhRYdE6m1\n C4nKq6jYLD4Uvy6K510t5/UwmfShUMmG7zxFoXRL1Cp8DefWAVW9eNOUuSUt/WO/m7/4 ew==", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <ferruh.yigit@intel.com>,\n <ajit.khaparde@broadcom.com>, <aboyer@pensando.io>,\n <andrew.rybchenko@oktetlabs.ru>, <beilei.xing@intel.com>,\n <bruce.richardson@intel.com>, <chas3@att.com>, <chenbo.xia@intel.com>,\n <ciara.loftus@intel.com>, <dsinghrawat@marvell.com>,\n <ed.czeck@atomicrules.com>, <evgenys@amazon.com>, <grive@u256.net>,\n <g.singh@nxp.com>, <zhouguoyang@huawei.com>, <haiyue.wang@intel.com>,\n <hkalra@marvell.com>, <heinrich.kuhn@corigine.com>,\n <hemant.agrawal@nxp.com>, <hyonkim@cisco.com>, <igorch@amazon.com>,\n <irusskikh@marvell.com>, <jgrajcia@cisco.com>,\n <jasvinder.singh@intel.com>, <jianwang@trustnetic.com>,\n <jiawenwu@trustnetic.com>, <jingjing.wu@intel.com>,\n <johndale@cisco.com>, <john.miller@atomicrules.com>,\n <linville@tuxdriver.com>, <keith.wiles@intel.com>,\n <kirankumark@marvell.com>, <oulijun@huawei.com>, <lironh@marvell.com>,\n <longli@microsoft.com>, <mw@semihalf.com>, <spinler@cesnet.cz>,\n <matan@nvidia.com>, <matt.peters@windriver.com>,\n <maxime.coquelin@redhat.com>, <mk@semihalf.com>, <humin29@huawei.com>,\n <pnalla@marvell.com>, <ndabilpuram@marvell.com>,\n <qiming.yang@intel.com>, <qi.z.zhang@intel.com>, <radhac@marvell.com>,\n <rahul.lakkireddy@chelsio.com>, <rmody@marvell.com>,\n <rosen.xu@intel.com>, <sachin.saxena@oss.nxp.com>,\n <skoteshwar@marvell.com>, <shshaikh@marvell.com>,\n <shaibran@amazon.com>, <shepard.siegel@atomicrules.com>,\n <asomalap@amd.com>, <somnath.kotur@broadcom.com>,\n <sthemmin@microsoft.com>, <steven.webster@windriver.com>,\n <skori@marvell.com>, <mtetsuyah@gmail.com>, <vburru@marvell.com>,\n <viacheslavo@nvidia.com>, <xiao.w.wang@intel.com>,\n <cloud.wangxiaoyun@huawei.com>, <yisen.zhuang@huawei.com>,\n <yongwang@vmware.com>, <xuanziyang2@huawei.com>, <pkapoor@marvell.com>,\n <nadavh@marvell.com>, <sburla@marvell.com>, <pathreya@marvell.com>,\n <gakhil@marvell.com>, <mdr@ashroe.eu>, <dmitry.kozliuk@gmail.com>,\n <anatoly.burakov@intel.com>, <cristian.dumitrescu@intel.com>,\n <honnappa.nagarahalli@arm.com>, <mattias.ronnblom@ericsson.com>,\n <ruifeng.wang@arm.com>, <drc@linux.vnet.ibm.com>,\n <konstantin.ananyev@intel.com>, <olivier.matz@6wind.com>,\n <jay.jayatheerthan@intel.com>, <asekhar@marvell.com>,\n <pbhagavatula@marvell.com>, <eagostini@nvidia.com>, Jerin Jacob\n <jerinj@marvell.com>", "Date": "Tue, 19 Oct 2021 23:44:57 +0530", "Message-ID": "<20211019181459.1709976-1-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.33.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "shEq2UHVEPlj56DkLggvfoaCue2uPEzi", "X-Proofpoint-ORIG-GUID": "shEq2UHVEPlj56DkLggvfoaCue2uPEzi", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475\n definitions=2021-10-19_02,2021-10-19_01,2020-04-07_01", "Subject": "[dpdk-dev] [RFC PATCH 0/1] Dataplane Workload Accelerator library", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\n\nDataplane Workload Accelerator library\n======================================\n\nDefinition of Dataplane Workload Accelerator\n--------------------------------------------\nDataplane Workload Accelerator(DWA) typically contains a set of CPUs,\nNetwork controllers and programmable data acceleration engines for\npacket processing, cryptography, regex engines, baseband processing, etc. \nThis allows DWA to offload compute/packet processing/baseband/\ncryptography-related workload from the host CPU to save the cost and power. \nAlso to enable scaling the workload by adding DWAs to the Host CPU as needed.\n\nUnlike other devices in DPDK, the DWA device is not fixed-function\ndue to the fact that it has CPUs and programmable HW accelerators.\nThis enables DWA personality/workload to be completely programmable.\nTypical examples of DWA offloads are Flow/Session management,\nVirtual switch, TLS offload, IPsec offload, l3fwd offload, etc.\n\n\nMotivation for the new library\n------------------------------\nEven though, a lot of semiconductor vendors offers a different form of DWA,\nsuch as DPU(often called Smart-NIC), GPU, IPU, XPU, etc., \nDue to the lack of standard APIs to \"Define the workload\" and\n\"Communication between HOST and DWA\", it is difficult for DPDK\nconsumers to use them in a portable way across different DWA vendors\nand enable it in cloud environments.\n\n\nContents of RFC \n------------------\nThis RFC attempts to define standard APIs for: \n\n1) Definition of Profiles corresponding to well defined workloads, which includes\n a set of TLV(Messages) as a request and response scheme to define \n the contract between host and DWA to offload a workload.\n (See lib/dwa/rte_dwa_profile_* header files)\n2) Discovery of a DWAs capabilities (e.g. which specific workloads it can support) \n in a vendor independent fashion. (See rte_dwa_dev_disc_profiles())\n3) Attaching a set of profiles to a DWA device(See rte_dwa_dev_attach())\n4) A communication framework between Host and DWA(See rte_dwa_ctrl_op() for\n control plane and rte_dwa_port_host_* for user plane)\n5) Virtualization of DWA hardware and firmware (Use standard DPDK device/bus model) \n6) Enablement of administrative functions such as FW updates,\n resource partitioning in a DWA like items in global in\n nature that is applicable for all DWA device under the DWA.\n (See rte_dwa_profile_admin.h) \n\nAlso, this RFC define the L3FWD profile to offload L3FWD workload to DWA.\nThis RFC defines an ethernet-style host port for Host to DWA communication.\nDifferent host port types may be required to cover the large spectrum of DWA types as\ntransports like PCIe DMA, Shared Memory, or Ethernet are fundamentally different,\nand optimal performance need host port specific APIs.\n\nThe framework does not force an abstract of different transport interfaces as\nsingle API, instead, decouples TLV from the transport interface and focuses on \ndefining the TLVs and leaving vendors to specify the host ports\nspecific to their DWA architecture.\n\n \nRoadmap\n-------\n1) Address the comments for this RFC and enable the common code\n2) SW drivers/infrastructure for `DWA` and `DWA device`\nas two separate DPDK processes over `memif` DPDK ethdev driver for \nL3FWD offload. This is to enable the framework without any special HW.\n3) Example DWA device application for L3FWD profile.\n4) Marvell DWA Device drivers.\n5) Based on community interest new profile can be added in the future.\n\n\nDWA library framework\n---------------------\n\nDWA components:\n\n +--> rte_dwa_port_host_*()\n | (User Plane traffic as TLV)\n |\n +----------------------+ | +--------------------+\n | | | | DPDK DWA Device[0] |\n | +----------------+ | Host Port | +----------------+ |\n | | | |<========+==>| | | |\n | | Profile 0 | | | | Profile X | |\n | | | | | | | |\n <=============>| +----------------+ | Control Port| +----------------+ |\n DWA Port0 | +----------------+ |<========+==>| |\n | | | | | +--------------------+\n | | Profile 1 | | |\n | | | | +--> rte_dwa_ctrl_op()\n | +----------------+ | (Control Plane traffic as TLV)\n <=============>| Dataplane |\n DWA Port1 | Workload |\n | Accelerator | +---------- ---------+\n | (HW/FW/SW) | | DPDK DWA Device[N] |\n | | Host Port | +----------------+ |\n <=============>| +----------------+ |<===========>| | | |\n DWA PortN | | | | | | Profile Y | |\n | | Profile N | | | | ^ | |\n | | | | Control Port| +-----------|----+ |\n | +-------|--------+ |<===========>| | |\n | | | +-------------|------+\n +----------|-----------+ | \n | | \n +---------------------------------------+\n ^\n |\n +--rte_dwa_dev_attach()\n\n\nDataplane Workload Accelerator: It is an abstract model. The model is\ncapable of offloading the dataplane workload from application via\nDPDK API over host and control ports of a DWA device.\nDataplane Workload Accelerator(DWA) typically contains a set of CPUs,\nNetwork controllers, and programmable data acceleration engines for\npacket processing, cryptography, regex engines, base-band processing, etc. \nThis allows DWA to offload compute/packet processing/base-band/cryptography-related\nworkload from the host CPU to save cost and power. Also, \nenable scaling the workload by adding DWAs to the host CPU as needed.\n\nDWA device: A DWA can be sliced to N number of DPDK DWA device(s)\nbased on the resources available in DWA.\nThe DPDK API interface operates on the DPDK DWA device.\nIt is a representation of a set of resources in DWA.\n\nTLV: TLV (tag-length-value) encoded data stream contain tag as\nmessage ID, followed by message length, and finally the message payload.\nThe 32bit message ID consists of two parts, 16bit Tag and 16bit Subtag.\nThe tag represents ID of the group of the similar message,\nwhereas, subtag represents a message tag ID under the group.\n\nControl Port: Used for transferring the control plane TLVs. Every DPDK\nDWA device must have a control port. Only one outstanding TLV can be\nprocessed via this port by a single DWA device. This makes the control\nport suitable for the control plane.\n\nHost Port: Used for transferring the user plane TLVs. \nEthernet, PCIe DMA, Shared Memory, etc.are the example of \ndifferent transport mechanisms abstracted under the host port.\nThe primary purpose of host port to decouple the user plane TLVs with\nunderneath transport mechanism differences.\nUnlike control port, more than one outstanding TLVs can be processed by \na single DWA device via this port.\nThis makes, the host port transfer to be in asynchronous nature,\nto support large volumes and less latency user plane traffic.\n\nDWA Port: Used for transferring data between the external source and DWA.\nEthernet, eCPRI are examples of DWA ports. Unlike host ports,\nthe host CPU is not involved in transferring the data to/from DWA ports.\nThese ports typically connected to the Network controller inside the \nDWA to transfer the traffic from the external source.\n\nTLV direction: `Host to DWA` and `DWA to Host` are the directions\nof TLV messages. The former one is specified as H2D, and the later one is \nspecified as D2H. The H2D control TLVs, used for requesting DWA to perform \nspecific action and D2H control TLVs are used to respond to the requested\nactions. The H2D user plane messages are used for transferring data from the\nhost to the DWA. The D2H user plane messages are used for transferring \ndata from the DWA to the host.\n\nDWA device states: Following are the different states of a DWA device.\n- READY: DWA Device is ready to attach the profile.\nSee rte_dwa_dev_disc_profiles() API to discover the profile.\n- ATTACHED: DWA Device attached to one or more profiles.\nSee rte_dwa_dev_attach() API to attach the profile(s).\n- STOPPED: Profile is in the stop state.\nTLV type `TYPE_ATTACHED`and `TYPE_STOPPED` messages are valid in this state.\nAfter rte_dwa_dev_attach() or explicitly invoking the rte_dwa_stop() API\nbrings device to this state.\n- RUNNING: Invoking rte_dwa_start() brings the device to this state.\nTLV type `TYPE_STARTED` and `TYPE_USER_PLANE` are valid in this state.\n- DETACHED: Invoking rte_dwa_dev_detach() brings the device to this state.\nThe device and profile must be in the STOPPED state prior to\ninvoking the rte_dwa_dev_detach().\n- CLOSED: Closed a stopped/detached DWA device.The device cannot be restarted!.\nInvoking rte_dwa_dev_close() brings the device to this state.\n\nTLV types: Following are the different TLV types\n- TYPE_ATTACHED: Valid when the device is in `ATTACHED`, `STOPPED` and `RUNNING` state.\n- TYPE_STOPPED: Valid when the device is in `STOPPED` state.\n- TYPE_STARTED: Valid when the device is in `RUNNING` state.\n- TYPE_USER_PLANE: Valid when the device is in `RUNNING` state and\nused to transfer only user plane traffic.\n\nProfile: Specifies a workload that dataplane workload accelerator \nprocess on behalf of a DPDK application through a DPDK DWA device.\nA profile is expressed as a set of TLV messages for control plane and user plane\nfunctions. Each TLV message must have Tag, SubTag, Direction, Type, Payload attributes.\n\nProgramming model: Typical application programming sequence is as follows,\n1) In the EAL initialization phase, the DWA devices shall be probed,\n the application can query the number of available DWA devices with\n rte_dwa_dev_count() API.\n2) Application discovers the available profile(s) in a DWA device using\n rte_dwa_dev_disc_profiles() API.\n3) Application attaches one or more profile(s) to a DWA device using\n rte_dwa_dev_attach().\n4) Once the profile is attached, The device shall be in the STOPPED state.\n Configure the profile(s) with `TYPE_ATTACHED`and `TYPE_STOPPED` \n type TLVs using rte_dwa_ctrl_op() API.\n5) Once the profile is configured, move the profile to the `RUNNING` state\n by invoking rte_dwa_start() API.\n6) Once the profile is in running state and if it has user plane TLV,\n transfer those TLVs using rte_dwa_port_host_() API based on the available \n host port for the given profile attached.\n7) Application can change the dynamic configuration aspects in\n `RUNNING` state using rte_dwa_ctrl_op() API by issuing `TYPE_STARTED` type\n of TLV messages.\n8) Finally, use rte_dwa_stop(), rte_dwa_dev_detach(), rte_dwa_dev_close()\n sequence for tear-down.\n\n\nL3FWD profile\n-------------\n\n +-------------->--[1]--------------+\n | |\n +-----------|----------+ |\n | | | |\n | +--------|-------+ | |\n | | | | |\n | | L3FWD Profile | | |\n \\ | | | | |\n <====\\========>| +----------------+ | |\n DWA \\Port0 | Lookup Table | +---------|----------+\n \\ | +----------------+ | | DPDK DWA|Device[0] |\n \\ | | IP | Dport | | Host Port | +-------|--------+ |\n \\ | +----------------+ |<===========>| | | | |\n +~[3]~~~|~~~~~~~|~~~~~~~~|~~~~~~~~~~~~~~~~~>|->L3FWD Profile | |\n <=============>| +----------------+ | | | | |\n DWA Port1 | | | | | Control Port| +-|---------|----+ |\n | +----------------+ |<===========>| | | |\n ~~~>~~[5]~~~~|~~|~~~+ | | | +---|---------|------+\n | +---+------------+ | | |\n ~~~<~~~~~~~~~|~~|~~~+ | |<-|------[2]--------+ |\n | +----------------+<-|------[4]------------------+\n | Dataplane |\n <=============>| Workload |\n DWA PortN | Accelerator |\n | (HW/FW/SW) |\n +----------------------+\n\n\nL3FWD profile offloads Layer-3 forwarding between the DWA Ethernet ports.\n\nThe above diagram depicts the profile and application programming sequence.\n1) DWA device attaches the L3FWD profile using rte_dwa_dev_attach().\n2) Configure the L3FWD profile:\na) The application requests L3FWD profile capabilities of the DWA\n by using RTE_DWA_STAG_PROFILE_L3FWD_H2D_INFO, On response,\n the RTE_DWA_STAG_PROFILE_L3FWD_D2H_INFO returns the lookup modes\n supported, max rules supported, and available host ports for this profile.\t\nb) The application configures a set of DWA ports to use a \n lookup mode(EM, LPM, or FIB) via RTE_DWA_STAG_PROFILE_L3FWD_H2D_CONFIG.\nc) The application configures a valid host port to receive exception packets.\n3) The exception that is not matching forwarding table entry comes as\n RTE_DWA_STAG_PROFILE_L3FWD_D2H_EXCEPTION_PACKETS TLV to host. DWA stores the exception \n packet send back destination ports after completing step (4).\n4) Parse the exception packet and add rules to the FWD table using\n RTE_DWA_STAG_PROFILE_L3FWD_H2D_LOOKUP_ADD. If the application knows the rules beforehand,\n it can add the rules in step 2.\n5) When DWA ports receive the matching flows in the lookup table, DWA forwards\n to DWA Ethernet ports without host CPU intervention.\n\n\nExample application usage with L3FWD profile\n--------------------------------------------\nThis example application is to demonstrate the programming model of DWA library.\nThis example omits the error checks to simply the application.\n\nvoid \ndwa_profile_l3fwd_add_rule(rte_dwa_obj_t obj obj, struct rte_mbuf *mbuf)\n{\n\tstruct rte_dwa_profile_l3fwd_h2d_lookup_add *lookup;\n\tstruct rte_dwa_tlv *h2d, *d2h;\n\tstruct rte_ether_hdr *eth_hdr;\n\tstruct rte_ipv4_hdr *ipv4_hdr;\n\tuint32_t id;\n\tsize_t len;\n\n\tid = RTE_DWA_TLV_MK_ID(PROFILE_L3FWD, H2D_LOOKUP_ADD);\n\tlen = sizeof(struct rte_dwa_profile_l3fwd_h2d_config);\n\th2d = malloc(RTE_DWA_TLV_HDR_SZ + len);\n\n\tlookup = h2d->msg;\n /* Simply hardcode to IPv4 instead of looking for Packet type to simplify example */\n\tlookup->rule_type = RTE_DWA_PROFILE_L3FWD_RULE_TYPE_IPV4;\n\tlookup->v4_rule.prefix.depth = 24;\n\n\teth_hdr = rte_pktmbuf_mtod(mbuf, struct rte_ether_hdr *);\n\tipv4_hdr = (struct rte_ipv4_hdr *)(eth_hdr + 1);\n\tlookup->v4_rule.prefix.ip_dst = rte_be_to_cpu_32(ipv4_hdr->dst_addr);\n\tlookup->eth_port_dst = mbuf->port;\n\n\trte_dwa_tlv_fill(h2d, id, len, h2d);\n\td2h = rte_dwa_ctrl_op(obj, h2h);\n\tfree(h2d);\n\tfree(d2h);\n}\n\nvoid\ndwa_profile_l3fwd_port_host_ethernet_worker(rte_dwa_obj_t obj, struct app_ctx *ctx)\n{\n\tstruct rte_dwa_profile_l3fwd_d2h_exception_pkts *msg;\n\tstruct rte_dwa_tlv *tlv;\n\tuint16_t i, rc, nb_tlvs;\n\tstruct rte_mbuf *mbuf;\n\n\twhile (!ctx->done) {\n\t\trc = rte_dwa_port_host_ethernet_rx(obj, 0, &tlv, 1);\n\t\tif (!rc)\n\t\t\tcontinue;\n\n\t\t/* Since L3FWD profile has only one User Plane TLV, Message must be \n\t * RTE_DWA_STAG_PROFILE_L3FWD_D2H_EXCEPTION_PACKETS message\n \t */\n\t\tmsg = (struct rte_dwa_profile_l3fwd_d2h_exception_pkts *)tlv->msg;\n\t\tfor (i = 0; i < msg->nb_pkts; i++) {\n\t\t\t\tmbuf = msg->pkts[i];\n\t\t\t\t/* Got a exception pkt from DWA, handle it by adding as new rule in\n * lookup table in DWA\n\t\t\t\t */ \t\t\t\t\n\t\t\t\tdwa_profile_l3fwd_add_rule(obj, mbuf);\n\t\t\t\t/* Free the mbuf to pool */\n\t\t\t\trte_pktmbuf_free(mbuf);\n\t\t}\n\t\t\n\t\t/* Done with TLV mbuf container, free it back */\n\t\trte_mempool_ops_enqueue_bulk(ctx->tlv_pool, tlv, 1);\n}\n\nbool\ndwa_port_host_ethernet_config(rte_dwa_obj_t obj, struct app_ctx *ctx)\n{\n\tstruct rte_dwa_tlv info_h2d, *info_d2h, *h2d = NULL, *d2h;\n\tstruct rte_dwa_port_host_ethernet_d2h_info *info;\n\tint tlv_pool_element_sz;\n\tbool rc = false;\n\tsize_t len;\n\n\t/* Get the Ethernet host port info */\n\tid = RTE_DWA_TLV_MK_ID(PORT_HOST_ETHERNET, H2D_INFO);\n\trte_dwa_tlv_fill(&info_h2d, id, 0, NULL);\n\tinfo_d2h = rte_dwa_ctrl_op(obj, &info_h2d)\n\n\tinfo = rte_dwa_tlv_d2h_to_msg(info_d2h);\n\tif (info == NULL)\n\t\tgoto fail;\n\t/* Need min one Rx queue to Receive exception traffic */ \n\tif (info->nb_rx_queues == 0)\n\t\tgoto fail;\n\t/* Done with message from DWA. Free back to implementation */\n\tfree(obj, info_d2h);\n\n\t/* Allocate exception packet pool */\n\tctx->pkt_pool = rte_pktmbuf_pool_create(\"exception pool\", /* Name */\n ctx->pkt_pool_depth, /* Number of elements*/\n 512, /* Cache size*/\n 0,\n RTE_MBUF_DEFAULT_BUF_SIZE,\n ctx->socket_id));\n\n\n\ttlv_pool_element_sz = DWA_EXCEPTION_PACKETS_PKT_BURST_MAX_SZ * sizeof(rte_mbuf *);\n\ttlv_pool_element_sz += sizeof(rte_dwa_profile_l3fwd_d2h_exception_pkts);\n\n\t/* Allocate TLV pool for RTE_DWA_STLV_PROFILE_L3FWD_D2H_EXCEPTION_PACKETS_PACKETS tag */\n\tctx->tlv_pool = rte_mempool_create(\"TLV pool\", /* mempool name */\n ctx->tlv_pool_depth, /* Number of elements*/\n tlv_pool_element_sz, /* Element size*/\n 512, /* cache size*/\n 0, NULL, NULL, NULL /* Obj constructor */, NULL,\n ctx->socket_id, 0 /* flags *);\n\n\n\t/* Configure Ethernet host port */\n\tid = RTE_DWA_TLV_MK_ID(PORT_HOST_ETHERNET, H2D_CONFIG);\n\tlen = sizeof(struct rte_dwa_port_host_ethernet_config);\n\th2d = malloc(RTE_DWA_TLV_HDR_SZ + len);\n\n\tcfg = h2d->msg;\n\t/* Update the Ethernet configuration parameters */\n\tcfg->nb_rx_queues = 1;\n\tcfg->nb_tx_queues = 0;\n\tcfg->max_burst = DWA_EXCEPTION_PACKETS_PKT_BURST_MAX_SZ;\n\tcfg->pkt_pool = ctx->pkt_pool;\n\tcfg->tlv_pool = ctx->tlv_pool;\n\trte_dwa_tlv_fill(h2d, id, len, h2d);\n\td2h = rte_dwa_ctrl_op(obj, h2d);\n\tif (d2h == NULL))\n\t\tgoto fail;\n\n\tfree(h2d);\n\n\t/* Configure Rx queue 0 receive expectation traffic */\n\tid = RTE_DWA_TLV_MK_ID(PORT_HOST_ETHERNET, H2D_QUEUE_CONFIG);\n\tlen = sizeof(struct rte_dwa_port_host_ethernet_queue_config);\n\th2d = malloc(RTE_DWA_TLV_HDR_SZ + len);\n\n\tcfg = h2d->msg;\n\tcfg->id = 0; /* 0th Queue */\n\tcfg->enable= 1;\n\tcfg->is_tx = 0; /* Rx queue */\n\tcfg->depth = ctx->rx_queue_depth;\n\trte_dwa_tlv_fill(h2d, id, len, h2d);\n\td2h = rte_dwa_ctrl_op(obj, h2d);\n\tif (d2h == NULL))\n\t\tgoto fail;\n\n\tfree(h2d);\n\n\treturn true;\nfail:\n\tif (h2d)\n\t\tfree(h2d);\n\treturn rc;\n}\n\nbool\ndwa_profile_l3fwd_config(rte_dwa_obj_t obj, struct app_ctx *ctx)\n{\n\tstruct rte_dwa_tlv info_h2d, *info_d2h = NULL, *h2d, *d2h = NULL;\n\tstruct rte_dwa_port_dwa_ethernet_d2h_info *info;\n\tstruct rte_dwa_profile_l3fwd_h2d_config *cfg;\n\tbool rc = false;\n \tuint32_t id;\n\tsize_t len;\n\n\t/* Get DWA Ethernet port info */ \n\tid = RTE_DWA_TLV_MK_ID(PORT_DWA_ETHERNET, H2D_INFO);\n\trte_dwa_tlv_fill(&info_h2d, id, 0, NULL);\n\tinfo_d2h = rte_dwa_ctrl_op(obj, &info_h2d);\n\n\tinfo = rte_dwa_tlv_d2h_to_msg(info_d2h);\n\tif (info == NULL)\n\t\tgoto fail;\n\t\n\t/* Not found any DWA ethernet ports */\n\tif (info->nb_ports == 0)\n\t\tgoto fail;\n\n\t/* Configure L3FWD profile */\n\tid = RTE_DWA_TLV_MK_ID(PROFILE_L3FWD, H2D_CONFIG);\n\tlen = sizeof(struct rte_dwa_profile_l3fwd_h2d_config) + (sizeof(uint16_t) * info->nb_ports);\n\th2d = malloc(RTE_DWA_TLV_HDR_SZ + len);\n\n\tcfg = h2d->msg;\n\t/* Update the L3FWD configuration parameters */\n\tcfg->mode = ctx->mode;\n\t/* Attach all DWA Ethernet ports onto L3FWD profile */\n\tcfg->nb_eth_ports = info->nb_ports;\n\tmemcpy(cfg->eth_ports, info->avail_ports, sizeof(uint16_t) * info->nb_ports);\n\n\trte_dwa_tlv_fill(h2d, id, len, h2d);\n\td2h = rte_dwa_ctrl_op(obj, h2d);\n\tfree(h2d);\n\n\t/* All good */\n\trc = true;\nfail:\n\tif (info_d2h)\n\t\tfree(obj, info_d2h);\n\tif (d2h)\n\t\tfree(obj, d2h);\n\n\treturn rc;\n}\n\nbool\ndwa_profile_l3fwd_has_capa(rte_dwa_obj_t obj, struct app_ctx *ctx)\n{\n\tstruct rte_dwa_profile_l3fwd_d2h_info *info;\n\tstruct rte_dwa_tlv h2d, *d2h;\n\tbool found = false;\n \tuint32_t id;\n\n\t/* Get L3FWD profile info */\n\tid = RTE_DWA_TLV_MK_ID(PROFILE_L3FWD, H2D_INFO);\n\trte_dwa_tlv_fill(&h2d, id, 0, NULL);\n\td2h = rte_dwa_ctrl_op(obj, &h2d);\n\n\tinfo = rte_dwa_tlv_d2h_to_msg(d2h);\n\t/* Request failed */\n\tif (info == NULL)\n\t\tgoto fail;\n\t/* Required lookup modes is not supported */\n\tif (!(info->modes_supported & ctx->mode))\n\t\tgoto fail;\n\n\t/* Check profile supports HOST_ETHERNET port as this application\n * supports only host port as Ethernet\n */\n\tfor (i = 0; i < info->nb_host_ports; i++) {\n\t\tif (info->host_ports[i] == RTE_DWA_TAG_PORT_HOST_ETHERNET); {\n\t\t\tfound = true;\n\t\t}\t\n\t}\n\n\t/* Done with response, Free the d2h memory allocated by implementation */\n\tfree(obj, d2h);\nfail:\n\treturn found;\n}\n\n\nbool\ndwa_has_profile(enum rte_dwa_tag_profile pf)\n{\n\tenum rte_dwa_tlv_profile *pfs = NULL;\n\tbool found = false;\n\tint nb_pfs;\n\n\t/* Get the number of profiles on the DWA device */\n\tnb_pfs = rte_dwa_dev_disc_profiles(0, NULL);\n\tpfs = malloc(sizeof(enum rte_dwa_tag_profile) * nb_pfs);\n\t/* Fetch all the profiles */\n\tnb_pfs = rte_dwa_dev_disc_profiles(0, pfs);\n\n\t/* Check the list has requested profile */\n\tfor (i = 0; i < nb_pfs; i++) {\n\t\tif (pfs[i] == pf);\n\t\t\tfound = true;\n\t}\n\tfree(pfs);\n\n\n\treturn found;\n}\n\n\n#include <rte_dwa.h>\n\n#define DWA_EXCEPTION_PACKETS_PKT_BURST_MAX_SZ\t\t32\n\nstruct app_ctx {\n\tbool done;\n\tstruct rte_mempool *pkt_pool;\n\tstruct rte_mempool *tlv_pool;\n\tenum rte_dwa_profile_l3fwd_lookup_mode mode;\n\tint socket_id;\n\tint pkt_pool_depth;\t\n\tint tlv_pool_depth;\n\tint rx_queue_depth;\n} __rte_cache_aligned;\n\nint\nmain(int argc, char **argv)\n{\n\trte_dwa_obj_t obj = NULL;\n\tstruct app_ctx ctx;\n\tint rc;\n\t\t\n\t/* Initialize EAL */ \n\trc= rte_eal_init(argc, argv);\n if (rc < 0)\n rte_exit(EXIT_FAILURE, \"Invalid EAL arguments\\n\");\n argc -= ret;\n argv += ret;\n\n\n\tmemset(&ctx, 0, sizeof(ctx));\n\t/* Set application default values */\n\tctx->mode = RTE_DWA_PROFILE_L3FWD_MODE_LPM;\n\tctx->socket_id = SOCKET_ID_ANY;\n\tctx->pkt_pool_depth = 10000;\n\tctx->tlv_pool_depth = 10000;\n\tctx->rx_queue_depth = 10000;\n\n\t/* Step 1: Check any DWA devices present */\n\trc = rte_dwa_dev_count();\n\tif (rc <= 0)\n\t\trte_exit(EXIT_FAILURE, \"Failed to find DWA devices\\n\");\n\n\t/* Step 2: Check DWA device has L3FWD profile or not */\n\tif (!dwa_has_profile(RTE_DWA_TAG_PROFILE_L3FWD))\n\t\trte_exit(EXIT_FAILURE, \"L3FWD profile not found\\n\");\n\n\t/*\n \t * Step 3: Now that, workload accelerator has L3FWD profile,\n \t * offload L3FWD workload to accelerator by attaching the profile\n\t * to accelerator.\n \t */ \n\tenum rte_dwa_tlv_profile profile[] = {RTE_DWA_TAG_PROFILE_L3FWD};\n\tobj = rte_dwa_dev_attach(0, \"my_custom_accelerator_device\", profile, 1).;\n\n\t/* Step 4: Check Attached L3FWD profile has required capability to proceed */\n\tif (!dwa_profile_l3fwd_has_capa(obj, &ctx))\n\t\trte_exit(EXIT_FAILURE, \"L3FWD profile does not have enough capability \\n\");\n\n\t/* Step 5: Configure l3fwd profile */ \n\tif (!dwa_profile_l3fwd_config(obj, &ctx))\n\t\trte_exit(EXIT_FAILURE, \"L3FWD profile configure failed \\n\");\n\n\t/* Step 6: Configure ethernet host port to receive exception packets */\n\tif (!dwa_port_host_ethernet_config(obj, &ctx))\n\t\trte_exit(EXIT_FAILURE, \"L3FWD profile configure failed \\n\");\n\n\t/* Step 7 : Move DWA profiles to start state */\n\trte_dwa_start(obj);\n\n\t/* Step 8: Handle expectation packets and add lookup rules for it */\n\tdwa_profile_l3fwd_port_host_ethernet_worker(obj, &ctx);\n\n\t/* Step 9: Clean up */\n\trte_dwa_stop(obj);\n\trte_dwa_dev_detach(0, obj);\n\trte_dwa_dev_close(0);\n\t\n\treturn 0;\n}\n\n\nJerin Jacob (1):\n dwa: introduce dataplane workload accelerator subsystem\n\n doc/api/doxy-api-index.md | 13 +\n doc/api/doxy-api.conf.in | 1 +\n lib/dwa/dwa.c | 7 +\n lib/dwa/meson.build | 17 ++\n lib/dwa/rte_dwa.h | 184 +++++++++++++\n lib/dwa/rte_dwa_core.h | 264 +++++++++++++++++++\n lib/dwa/rte_dwa_dev.h | 154 +++++++++++\n lib/dwa/rte_dwa_port_dwa_ethernet.h | 68 +++++\n lib/dwa/rte_dwa_port_host_ethernet.h | 178 +++++++++++++\n lib/dwa/rte_dwa_profile_admin.h | 85 ++++++\n lib/dwa/rte_dwa_profile_l3fwd.h | 378 +++++++++++++++++++++++++++\n lib/dwa/version.map | 3 +\n lib/meson.build | 1 +\n 13 files changed, 1353 insertions(+)\n create mode 100644 lib/dwa/dwa.c\n create mode 100644 lib/dwa/meson.build\n create mode 100644 lib/dwa/rte_dwa.h\n create mode 100644 lib/dwa/rte_dwa_core.h\n create mode 100644 lib/dwa/rte_dwa_dev.h\n create mode 100644 lib/dwa/rte_dwa_port_dwa_ethernet.h\n create mode 100644 lib/dwa/rte_dwa_port_host_ethernet.h\n create mode 100644 lib/dwa/rte_dwa_profile_admin.h\n create mode 100644 lib/dwa/rte_dwa_profile_l3fwd.h\n create mode 100644 lib/dwa/version.map", "diff": null, "prefixes": [ "RFC", "0/1" ] }