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GET /api/patches/102226/?format=api
{ "id": 102226, "url": "https://patches.dpdk.org/api/patches/102226/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211019123722.3414694-7-dkozlyuk@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211019123722.3414694-7-dkozlyuk@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211019123722.3414694-7-dkozlyuk@nvidia.com", "date": "2021-10-19T12:37:22", "name": "[v3,6/6] net/mlx5: preserve indirect actions on restart", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6ce59bdbe82b6969cee47e272a1e03286633d6c4", "submitter": { "id": 2367, "url": "https://patches.dpdk.org/api/people/2367/?format=api", "name": "Dmitry Kozlyuk", "email": "dkozlyuk@oss.nvidia.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211019123722.3414694-7-dkozlyuk@nvidia.com/mbox/", "series": [ { "id": 19791, "url": "https://patches.dpdk.org/api/series/19791/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19791", "date": "2021-10-19T12:37:16", "name": "Flow entites behavior on port restart", "version": 3, "mbox": "https://patches.dpdk.org/series/19791/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/102226/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/102226/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B3686A0C4D;\n\tTue, 19 Oct 2021 14:38:34 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DE05E411CA;\n\tTue, 19 Oct 2021 14:38:13 +0200 (CEST)", "from AZHDRRW-EX02.NVIDIA.COM (azhdrrw-ex02.nvidia.com\n [20.64.145.131])\n by mails.dpdk.org (Postfix) with ESMTP id 2FB2E4119B;\n Tue, 19 Oct 2021 14:38:10 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com (104.47.58.169)\n by mxs.oss.nvidia.com (10.13.234.37) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.858.15; 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helo=mail.nvidia.com;", "From": "Dmitry Kozlyuk <dkozlyuk@oss.nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<bingz@oss.nvidia.com>, <stable@dpdk.org>, Matan Azrad\n <matan@oss.nvidia.com>, Viacheslav Ovsiienko <viacheslavo@oss.nvidia.com>", "Date": "Tue, 19 Oct 2021 15:37:22 +0300", "Message-ID": "<20211019123722.3414694-7-dkozlyuk@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211019123722.3414694-1-dkozlyuk@nvidia.com>", "References": "<20211015161822.3099818-1-dkozlyuk@nvidia.com>\n <20211019123722.3414694-1-dkozlyuk@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e7e9710e-7a70-44b9-c367-08d992fd4d5a", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB2969:", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB2969B74EAD28E5B22E012442B9BD9@DM6PR12MB2969.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:291;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n LAs/9nhMfrM594Od/mDBwTAGdTSqTfH6XpLCA3yIUg7uhNAZsLhd+DxY8SahVq07AQNhiefBZycpIbuSakIpnQH0yEx5zPIqQSlZzFXvDTuKs7vRLq4haQ6ewLjTJagrAKFYniu9JYdZ6XahOl1sCKyrch8XqRmoJPajIA6I5MCe/fYOnRwgsxq5dtWsOk6M9I1+T+KV6C1X2vFtJch3NmJmBCkUI3RAqW7MW5ZNFpJZyJTPVL576PxNk0CGcc1oSOJo+Ny6lq4TP312u8Vqu7pUpqGZxxCldEt4DnRUrIIOanOmrLOlPBTgjRPHPSO7eu3F6QDPi8z9KcbphvHQVzdLI61NWOeIabp5aUSr58lKsgDNtLvy7E5tmV81tzhdbpeuSdZZox7M/oowQWAAgfuPgjJeJqMPA3y7pqM02rEHdZI3QS03sJtaQpzHD71rmljRnI1MwxuVAvLve2P1M4LHtE5ZUeyQ7ZFJWlg5N2BN7RFbqx7jSvs/SK8RzdgBaSY2FMnhxIb6HKjqsZn18yjBmSTM5M5S4zHurtJuFw4vQHpb0MQGS5r/J9Ro/6xhutWug9XFXUDJBfjtznMtR6KSLKdttsmnncnFCAk+pA/i8eLrevkjeaCkSFkDZUrHuvEcjq5I42joCKH1L4j4xCwuJJ7EcDutbQ6PSkZuhkJC4FYHofzl5C4hwdUncgcwAzTMFqS85FiR6Vz01PzmyA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(7696005)(70206006)(70586007)(107886003)(54906003)(316002)(6916009)(86362001)(6666004)(36860700001)(6286002)(26005)(426003)(83380400001)(1076003)(30864003)(8936002)(186003)(356005)(508600001)(2616005)(82310400003)(7636003)(336012)(4326008)(450100002)(47076005)(8676002)(36756003)(55016002)(16526019)(2906002)(5660300002);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Oct 2021 12:38:06.6983 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e7e9710e-7a70-44b9-c367-08d992fd4d5a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT013.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB2969", "Subject": "[dpdk-dev] [PATCH v3 6/6] net/mlx5: preserve indirect actions on\n restart", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "MLX5 PMD uses reference counting to manage RX queue resources.\nAfter port stop shared RSS actions kept references to RX queues,\npreventing resource release. As a result, internal PMD mempool\nfor such queues had been exhausted after a number of port restarts.\nDiagnostic message from rte_eth_dev_start():\n\n Rx queue allocation failed: Cannot allocate memory\n\nDereference RX queues used by indirect actions on port stop (detach)\nand restore references on port start (attach) in order to allow RX queue\nresource release, but keep indirect RSS across the port restart.\nReplace queue IDs in HW by drop queue ID on detach and restore actual\nqueue IDs on attach.\n\nWhen the port is stopped, create indirect RSS in the detached state.\nAs a result, MLX5 PMD is able to keep all its indirect actions\nacross port restart. Advertise this capability.\n\nFixes: 4b61b8774be9 (\"ethdev: introduce indirect flow action\")\nCc: bingz@nvidia.com\nCc: stable@dpdk.org\n\nSigned-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_ethdev.c | 1 +\n drivers/net/mlx5/mlx5_flow.c | 194 ++++++++++++++++++++++++++++----\n drivers/net/mlx5/mlx5_flow.h | 2 +\n drivers/net/mlx5/mlx5_rx.h | 4 +\n drivers/net/mlx5/mlx5_rxq.c | 99 ++++++++++++++--\n drivers/net/mlx5/mlx5_trigger.c | 10 ++\n 6 files changed, 276 insertions(+), 34 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex 82e2284d98..419fec3e4e 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -321,6 +321,7 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n \tinfo->rx_offload_capa = (mlx5_get_rx_port_offloads() |\n \t\t\t\t info->rx_queue_offload_capa);\n \tinfo->tx_offload_capa = mlx5_get_tx_port_offloads(dev);\n+\tinfo->dev_capa = RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP;\n \tinfo->if_index = mlx5_ifindex(dev);\n \tinfo->reta_size = priv->reta_idx_n ?\n \t\tpriv->reta_idx_n : config->ind_table_max_size;\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex bfc3e20c9a..c10b911259 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -1560,6 +1560,58 @@ mlx5_flow_validate_action_queue(const struct rte_flow_action *action,\n \treturn 0;\n }\n \n+/**\n+ * Validate queue numbers for device RSS.\n+ *\n+ * @param[in] dev\n+ * Configured device.\n+ * @param[in] queues\n+ * Array of queue numbers.\n+ * @param[in] queues_n\n+ * Size of the @p queues array.\n+ * @param[out] error\n+ * On error, filled with a textual error description.\n+ * @param[out] queue\n+ * On error, filled with an offending queue index in @p queues array.\n+ *\n+ * @return\n+ * 0 on success, a negative errno code on error.\n+ */\n+static int\n+mlx5_validate_rss_queues(const struct rte_eth_dev *dev,\n+\t\t\t const uint16_t *queues, uint32_t queues_n,\n+\t\t\t const char **error, uint32_t *queue_idx)\n+{\n+\tconst struct mlx5_priv *priv = dev->data->dev_private;\n+\tenum mlx5_rxq_type rxq_type = MLX5_RXQ_TYPE_UNDEFINED;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i != queues_n; ++i) {\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n+\n+\t\tif (queues[i] >= priv->rxqs_n) {\n+\t\t\t*error = \"queue index out of range\";\n+\t\t\t*queue_idx = i;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (!(*priv->rxqs)[queues[i]]) {\n+\t\t\t*error = \"queue is not configured\";\n+\t\t\t*queue_idx = i;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\trxq_ctrl = container_of((*priv->rxqs)[queues[i]],\n+\t\t\t\t\tstruct mlx5_rxq_ctrl, rxq);\n+\t\tif (i == 0)\n+\t\t\trxq_type = rxq_ctrl->type;\n+\t\tif (rxq_type != rxq_ctrl->type) {\n+\t\t\t*error = \"combining hairpin and regular RSS queues is not supported\";\n+\t\t\t*queue_idx = i;\n+\t\t\treturn -ENOTSUP;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n /*\n * Validate the rss action.\n *\n@@ -1580,8 +1632,9 @@ mlx5_validate_action_rss(struct rte_eth_dev *dev,\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tconst struct rte_flow_action_rss *rss = action->conf;\n-\tenum mlx5_rxq_type rxq_type = MLX5_RXQ_TYPE_UNDEFINED;\n-\tunsigned int i;\n+\tint ret;\n+\tconst char *message;\n+\tuint32_t queue_idx;\n \n \tif (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT &&\n \t rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ)\n@@ -1645,27 +1698,12 @@ mlx5_validate_action_rss(struct rte_eth_dev *dev,\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION_CONF,\n \t\t\t\t\t NULL, \"No queues configured\");\n-\tfor (i = 0; i != rss->queue_num; ++i) {\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n-\n-\t\tif (rss->queue[i] >= priv->rxqs_n)\n-\t\t\treturn rte_flow_error_set\n-\t\t\t\t(error, EINVAL,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION_CONF,\n-\t\t\t\t &rss->queue[i], \"queue index out of range\");\n-\t\tif (!(*priv->rxqs)[rss->queue[i]])\n-\t\t\treturn rte_flow_error_set\n-\t\t\t\t(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF,\n-\t\t\t\t &rss->queue[i], \"queue is not configured\");\n-\t\trxq_ctrl = container_of((*priv->rxqs)[rss->queue[i]],\n-\t\t\t\t\tstruct mlx5_rxq_ctrl, rxq);\n-\t\tif (i == 0)\n-\t\t\trxq_type = rxq_ctrl->type;\n-\t\tif (rxq_type != rxq_ctrl->type)\n-\t\t\treturn rte_flow_error_set\n-\t\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION_CONF,\n-\t\t\t\t &rss->queue[i],\n-\t\t\t\t \"combining hairpin and regular RSS queues is not supported\");\n+\tret = mlx5_validate_rss_queues(dev, rss->queue, rss->queue_num,\n+\t\t\t\t &message, &queue_idx);\n+\tif (ret != 0) {\n+\t\treturn rte_flow_error_set(error, -ret,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION_CONF,\n+\t\t\t\t\t &rss->queue[queue_idx], message);\n \t}\n \treturn 0;\n }\n@@ -8547,6 +8585,116 @@ mlx5_action_handle_flush(struct rte_eth_dev *dev)\n \treturn ret;\n }\n \n+/**\n+ * Validate existing indirect actions against current device configuration\n+ * and attach them to device resources.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_action_handle_attach(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_indexed_pool *ipool =\n+\t\t\tpriv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS];\n+\tstruct mlx5_shared_action_rss *shared_rss, *shared_rss_last;\n+\tint ret = 0;\n+\tuint32_t idx;\n+\n+\tILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) {\n+\t\tstruct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl;\n+\t\tconst char *message;\n+\t\tuint32_t queue_idx;\n+\n+\t\tret = mlx5_validate_rss_queues(dev, ind_tbl->queues,\n+\t\t\t\t\t ind_tbl->queues_n,\n+\t\t\t\t\t &message, &queue_idx);\n+\t\tif (ret != 0) {\n+\t\t\tDRV_LOG(ERR, \"Port %u cannot use queue %u in RSS: %s\",\n+\t\t\t\tdev->data->port_id, ind_tbl->queues[queue_idx],\n+\t\t\t\tmessage);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tif (ret != 0)\n+\t\treturn ret;\n+\tILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) {\n+\t\tstruct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl;\n+\n+\t\tret = mlx5_ind_table_obj_attach(dev, ind_tbl);\n+\t\tif (ret != 0) {\n+\t\t\tDRV_LOG(ERR, \"Port %u could not attach \"\n+\t\t\t\t\"indirection table obj %p\",\n+\t\t\t\tdev->data->port_id, (void *)ind_tbl);\n+\t\t\tgoto error;\n+\t\t}\n+\t}\n+\treturn 0;\n+error:\n+\tshared_rss_last = shared_rss;\n+\tILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) {\n+\t\tstruct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl;\n+\n+\t\tif (shared_rss == shared_rss_last)\n+\t\t\tbreak;\n+\t\tif (mlx5_ind_table_obj_detach(dev, ind_tbl) != 0)\n+\t\t\tDRV_LOG(CRIT, \"Port %u could not detach \"\n+\t\t\t\t\"indirection table obj %p on rollback\",\n+\t\t\t\tdev->data->port_id, (void *)ind_tbl);\n+\t}\n+\treturn ret;\n+}\n+\n+/**\n+ * Detach indirect actions of the device from its resources.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_action_handle_detach(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_indexed_pool *ipool =\n+\t\t\tpriv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS];\n+\tstruct mlx5_shared_action_rss *shared_rss, *shared_rss_last;\n+\tint ret = 0;\n+\tuint32_t idx;\n+\n+\tILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) {\n+\t\tstruct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl;\n+\n+\t\tret = mlx5_ind_table_obj_detach(dev, ind_tbl);\n+\t\tif (ret != 0) {\n+\t\t\tDRV_LOG(ERR, \"Port %u could not detach \"\n+\t\t\t\t\"indirection table obj %p\",\n+\t\t\t\tdev->data->port_id, (void *)ind_tbl);\n+\t\t\tgoto error;\n+\t\t}\n+\t}\n+\treturn 0;\n+error:\n+\tshared_rss_last = shared_rss;\n+\tILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) {\n+\t\tstruct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl;\n+\n+\t\tif (shared_rss == shared_rss_last)\n+\t\t\tbreak;\n+\t\tif (mlx5_ind_table_obj_attach(dev, ind_tbl) != 0)\n+\t\t\tDRV_LOG(CRIT, \"Port %u could not attach \"\n+\t\t\t\t\"indirection table obj %p on rollback\",\n+\t\t\t\tdev->data->port_id, (void *)ind_tbl);\n+\t}\n+\treturn ret;\n+}\n+\n #ifndef HAVE_MLX5DV_DR\n #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1))\n #else\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 8f94125f26..6bc7946cc3 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1574,6 +1574,8 @@ void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,\n \t\tstruct mlx5_flow_meter_policy *mtr_policy);\n int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);\n int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev);\n+int mlx5_action_handle_attach(struct rte_eth_dev *dev);\n+int mlx5_action_handle_detach(struct rte_eth_dev *dev);\n int mlx5_action_handle_flush(struct rte_eth_dev *dev);\n void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);\n int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex 2b7ad3e48b..d44c8078de 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -222,6 +222,10 @@ int mlx5_ind_table_obj_modify(struct rte_eth_dev *dev,\n \t\t\t struct mlx5_ind_table_obj *ind_tbl,\n \t\t\t uint16_t *queues, const uint32_t queues_n,\n \t\t\t bool standalone);\n+int mlx5_ind_table_obj_attach(struct rte_eth_dev *dev,\n+\t\t\t struct mlx5_ind_table_obj *ind_tbl);\n+int mlx5_ind_table_obj_detach(struct rte_eth_dev *dev,\n+\t\t\t struct mlx5_ind_table_obj *ind_tbl);\n struct mlx5_list_entry *mlx5_hrxq_create_cb(void *tool_ctx, void *cb_ctx);\n int mlx5_hrxq_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,\n \t\t void *cb_ctx);\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex b68443bed5..fd2b5779ff 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -2015,6 +2015,26 @@ mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,\n \treturn ind_tbl;\n }\n \n+static int\n+mlx5_ind_table_obj_check_standalone(struct rte_eth_dev *dev __rte_unused,\n+\t\t\t\t struct mlx5_ind_table_obj *ind_tbl)\n+{\n+\tuint32_t refcnt;\n+\n+\trefcnt = __atomic_load_n(&ind_tbl->refcnt, __ATOMIC_RELAXED);\n+\tif (refcnt <= 1)\n+\t\treturn 0;\n+\t/*\n+\t * Modification of indirection tables having more than 1\n+\t * reference is unsupported.\n+\t */\n+\tDRV_LOG(DEBUG,\n+\t\t\"Port %u cannot modify indirection table %p (refcnt %u > 1).\",\n+\t\tdev->data->port_id, (void *)ind_tbl, refcnt);\n+\trte_errno = EINVAL;\n+\treturn -rte_errno;\n+}\n+\n /**\n * Modify an indirection table.\n *\n@@ -2047,18 +2067,8 @@ mlx5_ind_table_obj_modify(struct rte_eth_dev *dev,\n \n \tMLX5_ASSERT(standalone);\n \tRTE_SET_USED(standalone);\n-\tif (__atomic_load_n(&ind_tbl->refcnt, __ATOMIC_RELAXED) > 1) {\n-\t\t/*\n-\t\t * Modification of indirection ntables having more than 1\n-\t\t * reference unsupported. Intended for standalone indirection\n-\t\t * tables only.\n-\t\t */\n-\t\tDRV_LOG(DEBUG,\n-\t\t\t\"Port %u cannot modify indirection table (refcnt> 1).\",\n-\t\t\tdev->data->port_id);\n-\t\trte_errno = EINVAL;\n+\tif (mlx5_ind_table_obj_check_standalone(dev, ind_tbl) < 0)\n \t\treturn -rte_errno;\n-\t}\n \tfor (i = 0; i != queues_n; ++i) {\n \t\tif (!mlx5_rxq_get(dev, queues[i])) {\n \t\t\tret = -rte_errno;\n@@ -2084,6 +2094,73 @@ mlx5_ind_table_obj_modify(struct rte_eth_dev *dev,\n \treturn ret;\n }\n \n+/**\n+ * Attach an indirection table to its queues.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param ind_table\n+ * Indirection table to attach.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_ind_table_obj_attach(struct rte_eth_dev *dev,\n+\t\t\t struct mlx5_ind_table_obj *ind_tbl)\n+{\n+\tunsigned int i;\n+\tint ret;\n+\n+\tret = mlx5_ind_table_obj_modify(dev, ind_tbl, ind_tbl->queues,\n+\t\t\t\t\tind_tbl->queues_n, true);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"Port %u could not modify indirect table obj %p\",\n+\t\t\tdev->data->port_id, (void *)ind_tbl);\n+\t\treturn ret;\n+\t}\n+\tfor (i = 0; i < ind_tbl->queues_n; i++)\n+\t\tmlx5_rxq_get(dev, ind_tbl->queues[i]);\n+\treturn 0;\n+}\n+\n+/**\n+ * Detach an indirection table from its queues.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param ind_table\n+ * Indirection table to detach.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_ind_table_obj_detach(struct rte_eth_dev *dev,\n+\t\t\t struct mlx5_ind_table_obj *ind_tbl)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tconst unsigned int n = rte_is_power_of_2(ind_tbl->queues_n) ?\n+\t\t\t log2above(ind_tbl->queues_n) :\n+\t\t\t log2above(priv->config.ind_table_max_size);\n+\tunsigned int i;\n+\tint ret;\n+\n+\tret = mlx5_ind_table_obj_check_standalone(dev, ind_tbl);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\tMLX5_ASSERT(priv->obj_ops.ind_table_modify);\n+\tret = priv->obj_ops.ind_table_modify(dev, n, NULL, 0, ind_tbl);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"Port %u could not modify indirect table obj %p\",\n+\t\t\tdev->data->port_id, (void *)ind_tbl);\n+\t\treturn ret;\n+\t}\n+\tfor (i = 0; i < ind_tbl->queues_n; i++)\n+\t\tmlx5_rxq_release(dev, ind_tbl->queues[i]);\n+\treturn ret;\n+}\n+\n int\n mlx5_hrxq_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,\n \t\t void *cb_ctx)\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 54173bfacb..c3adf5082e 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -14,6 +14,7 @@\n #include <mlx5_malloc.h>\n \n #include \"mlx5.h\"\n+#include \"mlx5_flow.h\"\n #include \"mlx5_mr.h\"\n #include \"mlx5_rx.h\"\n #include \"mlx5_tx.h\"\n@@ -1113,6 +1114,14 @@ mlx5_dev_start(struct rte_eth_dev *dev)\n \tmlx5_rxq_timestamp_set(dev);\n \t/* Set a mask and offset of scheduling on timestamp into Tx queues. */\n \tmlx5_txq_dynf_timestamp_set(dev);\n+\t/* Attach indirection table objects detached on port stop. */\n+\tret = mlx5_action_handle_attach(dev);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"port %u failed to attach indirect actions: %s\",\n+\t\t\tdev->data->port_id, rte_strerror(rte_errno));\n+\t\tgoto error;\n+\t}\n \t/*\n \t * In non-cached mode, it only needs to start the default mreg copy\n \t * action and no flow created by application exists anymore.\n@@ -1185,6 +1194,7 @@ mlx5_dev_stop(struct rte_eth_dev *dev)\n \t/* All RX queue flags will be cleared in the flush interface. */\n \tmlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);\n \tmlx5_flow_meter_rxq_flush(dev);\n+\tmlx5_action_handle_detach(dev);\n \tmlx5_rx_intr_vec_disable(dev);\n \tpriv->sh->port[priv->dev_port - 1].ih_port_id = RTE_MAX_ETHPORTS;\n \tpriv->sh->port[priv->dev_port - 1].devx_ih_port_id = RTE_MAX_ETHPORTS;\n", "prefixes": [ "v3", "6/6" ] }