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GET /api/patches/102189/?format=api
{ "id": 102189, "url": "https://patches.dpdk.org/api/patches/102189/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211019105629.11731-3-mk@semihalf.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211019105629.11731-3-mk@semihalf.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211019105629.11731-3-mk@semihalf.com", "date": "2021-10-19T10:56:24", "name": "[v3,2/7] net/ena: support Tx/Rx free thresholds", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "0935fd871df241b45ec622c81724f5cab5d07fc9", "submitter": { "id": 786, "url": "https://patches.dpdk.org/api/people/786/?format=api", "name": "Michal Krawczyk", "email": "mk@semihalf.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211019105629.11731-3-mk@semihalf.com/mbox/", "series": [ { "id": 19785, "url": "https://patches.dpdk.org/api/series/19785/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19785", "date": "2021-10-19T10:56:22", "name": "net/ena: update ENA PMD to v2.5.0", "version": 3, "mbox": "https://patches.dpdk.org/series/19785/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/102189/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/102189/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 50070A0C43;\n\tTue, 19 Oct 2021 12:56:58 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E79B941157;\n\tTue, 19 Oct 2021 12:56:51 +0200 (CEST)", "from mail-lj1-f182.google.com (mail-lj1-f182.google.com\n [209.85.208.182])\n by mails.dpdk.org (Postfix) with ESMTP id 1BA024114A\n for <dev@dpdk.org>; Tue, 19 Oct 2021 12:56:49 +0200 (CEST)", "by mail-lj1-f182.google.com with SMTP id o11so5311654ljg.10\n for <dev@dpdk.org>; Tue, 19 Oct 2021 03:56:49 -0700 (PDT)", "from DESKTOP-U5LNN3J.localdomain (89-79-181-52.dynamic.chello.pl.\n [89.79.181.52])\n by smtp.gmail.com with ESMTPSA id bn17sm1496058ljb.4.2021.10.19.03.56.47\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 19 Oct 2021 03:56:48 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=semihalf-com.20210112.gappssmtp.com; s=20210112;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=MPd0Vsn6Fll2A/g6WRRlq3/VnswplingoXitMWsVBq0=;\n b=1tsioCDOBnqWV4ppURHC36dib1xfJKASxdM/I/iZe65P8/qkOyIwbBLP9TLiOO55qe\n gTgQnVUuLOV9ITpq0EaMbJENxZW2V6y/J3aM3Ci92RAR1707VtlSlSSvLARmdqrbWA0K\n dkVXWh5igytqMFoWnrF2Tm2S/X4RKoMgqlYIhA24+8YLPd2YEktKbbR0f6fpuXZgMbeg\n YaZaG6u79psSkzTXAgTa9EBpYiucaKTXvyMJjggIQljk68g377TuEFYejkSUpONq9i0R\n 8N+4pXA1e4dPdVwz+P3JrVljRXh5sykY9QBmzX6hHHDk5XLZHsMfKMPKmTk4mY+4FnYC\n 1/TQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20210112;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=MPd0Vsn6Fll2A/g6WRRlq3/VnswplingoXitMWsVBq0=;\n b=YtpzV2M/S0tBzRTTLiagOWAGY6TV3DyK8AHoEL7506qgr+g/GWq1McgX6ErmT9hPDI\n vhMZgkQl8P08k/7y5Nn/o9tbjTyGnZwDEqCIpJP1XxKf24SnL2MFTqxz5qXqiSziTEY0\n wXXq3mT+dcpNhstEo6F7KbztYOoHyYQSjAR7Ef+8uqJpJYYDzZKLAyk9MsrgKV/oi52d\n t6oa7Lq2ea9q8dMqjTwnt1oxZJHWXb5DEOBdTUKc/fKRO0fS9qDlS65GWtsApWkaQ/pP\n OAJvO1UhZIC6ZXiFh/KaD+KT955YP0/anZ2iU1OwIiIk6i/JX38eTklK7nUB48w2RRnC\n tfWA==", "X-Gm-Message-State": "AOAM531GdwP1FRACgrKK4UzdZZeY8jeXanBz6hhGx2F9//3IhvMJ6Fp0\n QSEvNO2btF3qtVqpjl4e4Ys6vg==", "X-Google-Smtp-Source": "\n ABdhPJydrw88h2plChfltEhDrZX2ZW4JcHcFXea4oMOwO088Ngq8aQNArPCTmX1r8c0VeeA+4sYeUw==", "X-Received": "by 2002:a2e:bc03:: with SMTP id b3mr6053934ljf.54.1634641008724;\n Tue, 19 Oct 2021 03:56:48 -0700 (PDT)", "From": "Michal Krawczyk <mk@semihalf.com>", "To": "ferruh.yigit@intel.com", "Cc": "dev@dpdk.org, upstream@semihalf.com, shaibran@amazon.com,\n ndagan@amazon.com, igorch@amazon.com, Michal Krawczyk <mk@semihalf.com>", "Date": "Tue, 19 Oct 2021 12:56:24 +0200", "Message-Id": "<20211019105629.11731-3-mk@semihalf.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211019105629.11731-1-mk@semihalf.com>", "References": "<20211015162701.16324-1-mk@semihalf.com>\n <20211019105629.11731-1-mk@semihalf.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 2/7] net/ena: support Tx/Rx free thresholds", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The caller can pass Tx or Rx free threshold value to the configuration\nstructure for each ring. It determines when the Tx/Rx function should\nstart cleaning up/refilling the descriptors. ENA was ignoring this value\nand doing it's own calulcations.\n\nNow the user can configure ENA's behavior using this parameter and if\nthis variable won't be set, the ENA will continue with the old behavior\nand will use it's own threshold value.\n\nThe default value is not provided by the ENA in the ena_infos_get(), as\nit's being determined dynamically, depending on the requested ring size.\n\nNote that NULL check for Tx conf was removed from the function\nena_tx_queue_setup(), as at this place the configuration will be\neither provided by the user or the default config will be used and it's\nhandled by the upper (rte_ethdev) layer.\n\nTx threshold shouldn't be used for the Tx cleanup budget as it can be\ninadequate to the used burst. Now the PMD tries to release mbufs for the\nring until it will be depleted.\n\nSigned-off-by: Michal Krawczyk <mk@semihalf.com>\nReviewed-by: Igor Chauskin <igorch@amazon.com>\nReviewed-by: Shai Brandes <shaibran@amazon.com>\n---\nv2:\n* Fix calculations of the default tx_free_thresh if it wasn't provided by\n the user. RTE_MIN was replaced with RTE_MAX.\n\n doc/guides/rel_notes/release_21_11.rst | 7 ++++\n drivers/net/ena/ena_ethdev.c | 44 ++++++++++++++++++--------\n drivers/net/ena/ena_ethdev.h | 5 +++\n 3 files changed, 42 insertions(+), 14 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst\nindex bd6a388c9d..8341d979aa 100644\n--- a/doc/guides/rel_notes/release_21_11.rst\n+++ b/doc/guides/rel_notes/release_21_11.rst\n@@ -102,6 +102,13 @@ New Features\n \n * Disabled secondary process support.\n \n+* **Updated Amazon ENA PMD.**\n+\n+ Updated the Amazon ENA PMD. The new driver version (v2.5.0) introduced\n+ bug fixes and improvements, including:\n+\n+ * Support for the tx_free_thresh and rx_free_thresh configuration parameters.\n+\n * **Updated Broadcom bnxt PMD.**\n \n * Added flow offload support for Thor.\ndiff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c\nindex 197cb7ecd4..fe9bac8888 100644\n--- a/drivers/net/ena/ena_ethdev.c\n+++ b/drivers/net/ena/ena_ethdev.c\n@@ -1128,6 +1128,7 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev,\n \tstruct ena_ring *txq = NULL;\n \tstruct ena_adapter *adapter = dev->data->dev_private;\n \tunsigned int i;\n+\tuint16_t dyn_thresh;\n \n \ttxq = &adapter->tx_ring[queue_idx];\n \n@@ -1194,10 +1195,18 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev,\n \tfor (i = 0; i < txq->ring_size; i++)\n \t\ttxq->empty_tx_reqs[i] = i;\n \n-\tif (tx_conf != NULL) {\n-\t\ttxq->offloads =\n-\t\t\ttx_conf->offloads | dev->data->dev_conf.txmode.offloads;\n+\ttxq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;\n+\n+\t/* Check if caller provided the Tx cleanup threshold value. */\n+\tif (tx_conf->tx_free_thresh != 0) {\n+\t\ttxq->tx_free_thresh = tx_conf->tx_free_thresh;\n+\t} else {\n+\t\tdyn_thresh = txq->ring_size -\n+\t\t\ttxq->ring_size / ENA_REFILL_THRESH_DIVIDER;\n+\t\ttxq->tx_free_thresh = RTE_MAX(dyn_thresh,\n+\t\t\ttxq->ring_size - ENA_REFILL_THRESH_PACKET);\n \t}\n+\n \t/* Store pointer to this queue in upper layer */\n \ttxq->configured = 1;\n \tdev->data->tx_queues[queue_idx] = txq;\n@@ -1216,6 +1225,7 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev,\n \tstruct ena_ring *rxq = NULL;\n \tsize_t buffer_size;\n \tint i;\n+\tuint16_t dyn_thresh;\n \n \trxq = &adapter->rx_ring[queue_idx];\n \tif (rxq->configured) {\n@@ -1295,6 +1305,14 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev,\n \n \trxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;\n \n+\tif (rx_conf->rx_free_thresh != 0) {\n+\t\trxq->rx_free_thresh = rx_conf->rx_free_thresh;\n+\t} else {\n+\t\tdyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER;\n+\t\trxq->rx_free_thresh = RTE_MIN(dyn_thresh,\n+\t\t\t(uint16_t)(ENA_REFILL_THRESH_PACKET));\n+\t}\n+\n \t/* Store pointer to this queue in upper layer */\n \trxq->configured = 1;\n \tdev->data->rx_queues[queue_idx] = rxq;\n@@ -2124,7 +2142,6 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n {\n \tstruct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);\n \tunsigned int free_queue_entries;\n-\tunsigned int refill_threshold;\n \tuint16_t next_to_clean = rx_ring->next_to_clean;\n \tuint16_t descs_in_use;\n \tstruct rte_mbuf *mbuf;\n@@ -2206,12 +2223,9 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \trx_ring->next_to_clean = next_to_clean;\n \n \tfree_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);\n-\trefill_threshold =\n-\t\tRTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,\n-\t\t(unsigned int)ENA_REFILL_THRESH_PACKET);\n \n \t/* Burst refill to save doorbells, memory barriers, const interval */\n-\tif (free_queue_entries > refill_threshold) {\n+\tif (free_queue_entries >= rx_ring->rx_free_thresh) {\n \t\tena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);\n \t\tena_populate_rx_queue(rx_ring, free_queue_entries);\n \t}\n@@ -2578,12 +2592,12 @@ static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)\n \n static void ena_tx_cleanup(struct ena_ring *tx_ring)\n {\n-\tunsigned int cleanup_budget;\n \tunsigned int total_tx_descs = 0;\n+\tuint16_t cleanup_budget;\n \tuint16_t next_to_clean = tx_ring->next_to_clean;\n \n-\tcleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,\n-\t\t(unsigned int)ENA_REFILL_THRESH_PACKET);\n+\t/* Attempt to release all Tx descriptors (ring_size - 1 -> size_mask) */\n+\tcleanup_budget = tx_ring->size_mask;\n \n \twhile (likely(total_tx_descs < cleanup_budget)) {\n \t\tstruct rte_mbuf *mbuf;\n@@ -2624,6 +2638,7 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t\t uint16_t nb_pkts)\n {\n \tstruct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);\n+\tint available_desc;\n \tuint16_t sent_idx = 0;\n \n #ifdef RTE_ETHDEV_DEBUG_TX\n@@ -2643,8 +2658,8 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\ttx_ring->size_mask)]);\n \t}\n \n-\ttx_ring->tx_stats.available_desc =\n-\t\tena_com_free_q_entries(tx_ring->ena_com_io_sq);\n+\tavailable_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq);\n+\ttx_ring->tx_stats.available_desc = available_desc;\n \n \t/* If there are ready packets to be xmitted... */\n \tif (likely(tx_ring->pkts_without_db)) {\n@@ -2654,7 +2669,8 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\ttx_ring->pkts_without_db = false;\n \t}\n \n-\tena_tx_cleanup(tx_ring);\n+\tif (available_desc < tx_ring->tx_free_thresh)\n+\t\tena_tx_cleanup(tx_ring);\n \n \ttx_ring->tx_stats.available_desc =\n \t\tena_com_free_q_entries(tx_ring->ena_com_io_sq);\ndiff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h\nindex 26d425a893..176d713dff 100644\n--- a/drivers/net/ena/ena_ethdev.h\n+++ b/drivers/net/ena/ena_ethdev.h\n@@ -142,6 +142,11 @@ struct ena_ring {\n \tstruct ena_com_io_cq *ena_com_io_cq;\n \tstruct ena_com_io_sq *ena_com_io_sq;\n \n+\tunion {\n+\t\tuint16_t tx_free_thresh;\n+\t\tuint16_t rx_free_thresh;\n+\t};\n+\n \tstruct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]\n \t\t\t\t\t\t__rte_cache_aligned;\n \n", "prefixes": [ "v3", "2/7" ] }