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GET /api/patches/101215/?format=api
{ "id": 101215, "url": "https://patches.dpdk.org/api/patches/101215/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211012124554.21296-7-talshn@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211012124554.21296-7-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211012124554.21296-7-talshn@nvidia.com", "date": "2021-10-12T12:45:47", "name": "[v2,06/13] net/mlx5: query tunneling support on Windows", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e10b803a9a63fa0345e9de2831bd691cf858b60d", "submitter": { "id": 1893, "url": "https://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211012124554.21296-7-talshn@nvidia.com/mbox/", "series": [ { "id": 19558, "url": "https://patches.dpdk.org/api/series/19558/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19558", "date": "2021-10-12T12:45:41", "name": "Expand NIC offloads support on Windows", "version": 2, "mbox": "https://patches.dpdk.org/series/19558/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/101215/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/101215/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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<kcollins@nvidia.com>, <idanhac@nvidia.com>", "Date": "Tue, 12 Oct 2021 15:45:47 +0300", "Message-ID": "<20211012124554.21296-7-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20211012124554.21296-1-talshn@nvidia.com>", "References": "<20211012124554.21296-1-talshn@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "2b91557d-054f-4eb0-43e7-08d98d7e5815", "X-MS-TrafficTypeDiagnostic": "MW3PR12MB4395:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <MW3PR12MB439557FB81187C0818CA0891A4B69@MW3PR12MB4395.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:741;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": 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SFS:(4636009)(36840700001)(46966006)(7696005)(36860700001)(7636003)(316002)(6666004)(186003)(336012)(356005)(70206006)(508600001)(1076003)(2906002)(107886003)(70586007)(4326008)(54906003)(83380400001)(26005)(5660300002)(55016002)(36756003)(6916009)(6286002)(47076005)(8936002)(82310400003)(2616005)(8676002)(426003)(86362001)(16526019);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Oct 2021 12:46:43.1640 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2b91557d-054f-4eb0-43e7-08d98d7e5815", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT025.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW3PR12MB4395", "Subject": "[dpdk-dev] [PATCH v2 06/13] net/mlx5: query tunneling support on\n Windows", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Query tunneling supported on the NIC.\n\nSave the offloads values in a config parameter.\nThis is needed for the following TSO support:\n\nDEV_TX_OFFLOAD_VXLAN_TNL_TSO\nDEV_TX_OFFLOAD_GRE_TNL_TSO\nDEV_TX_OFFLOAD_GENEVE_TNL_TSO\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\nTested-by: Idan Hackmon <idanhac@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 14 ++++++++++++++\n drivers/net/mlx5/mlx5.h | 2 ++\n drivers/net/mlx5/windows/mlx5_os.c | 20 ++++++++++++++++++--\n 3 files changed, 34 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex add07db755..a957bc9938 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -966,6 +966,20 @@ mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)\n \treturn sw_parsing_offloads;\n }\n \n+uint32_t\n+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)\n+{\n+\tuint32_t tn_offloads = 0;\n+\n+\tif (attr->tunnel_stateless_vxlan)\n+\t\ttn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;\n+\tif (attr->tunnel_stateless_gre)\n+\t\ttn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;\n+\tif (attr->tunnel_stateless_geneve_rx)\n+\t\ttn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;\n+\treturn tn_offloads;\n+}\n+\n /*\n * Allocate Rx and Tx UARs in robust fashion.\n * This routine handles the following UAR allocation issues:\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 58f12cd75c..0dbb9aacb8 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1830,5 +1830,7 @@ int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,\n \t\t\t struct mlx5_aso_ct_action *ct);\n uint32_t\n mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);\n+uint32_t\n+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr);\n \n #endif /* RTE_PMD_MLX5_H_ */\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex 1e258e044e..fab7d7efcb 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -171,6 +171,8 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)\n \t}\n \tdevice_attr->sw_parsing_offloads =\n \t\tmlx5_get_supported_sw_parsing_offloads(&hca_attr);\n+\tdevice_attr->tunnel_offloads_caps =\n+\t\tmlx5_get_supported_tunneling_offloads(&hca_attr);\n \tpv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);\n \tif (pv_iseg == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to get device hca_iseg\");\n@@ -402,8 +404,22 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tsh->device_attr.max_rwq_indirection_table_size;\n \tcqe_comp = 0;\n \tconfig->cqe_comp = cqe_comp;\n-\tDRV_LOG(DEBUG, \"tunnel offloading is not supported\");\n-\tconfig->tunnel_en = 0;\n+\tconfig->tunnel_en = device_attr.tunnel_offloads_caps &\n+\t\t(MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |\n+\t\t MLX5_TUNNELED_OFFLOADS_GRE_CAP |\n+\t\t MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);\n+\tif (config->tunnel_en) {\n+\t\tDRV_LOG(DEBUG, \"tunnel offloading is supported for %s%s%s\",\n+\t\tconfig->tunnel_en &\n+\t\tMLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? \"[VXLAN]\" : \"\",\n+\t\tconfig->tunnel_en &\n+\t\tMLX5_TUNNELED_OFFLOADS_GRE_CAP ? \"[GRE]\" : \"\",\n+\t\tconfig->tunnel_en &\n+\t\tMLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? \"[GENEVE]\" : \"\"\n+\t\t);\n+\t} else {\n+\t\tDRV_LOG(DEBUG, \"tunnel offloading is not supported\");\n+\t}\n \tDRV_LOG(DEBUG, \"MPLS over GRE/UDP tunnel offloading is no supported\");\n \tconfig->mpls_en = 0;\n \t/* Allocate private eth device data. */\n", "prefixes": [ "v2", "06/13" ] }