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GET /api/patches/101085/?format=api
{ "id": 101085, "url": "https://patches.dpdk.org/api/patches/101085/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211011155057.302142-7-skori@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211011155057.302142-7-skori@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211011155057.302142-7-skori@marvell.com", "date": "2021-10-11T15:50:34", "name": "[v4,06/28] common/cnxk: support RoC API to configure bandwidth profile", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cba39b7cc7fc694e3b6b498aeb4a5036a7fbc02e", "submitter": { "id": 1318, "url": "https://patches.dpdk.org/api/people/1318/?format=api", "name": "Sunil Kumar Kori", "email": "skori@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211011155057.302142-7-skori@marvell.com/mbox/", "series": [ { "id": 19528, "url": "https://patches.dpdk.org/api/series/19528/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19528", "date": "2021-10-11T15:50:28", "name": "Support ingress policer", "version": 4, "mbox": "https://patches.dpdk.org/series/19528/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/101085/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/101085/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 69087A034F;\n\tMon, 11 Oct 2021 17:51:43 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 69FE441166;\n\tMon, 11 Oct 2021 17:51:22 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 88E1F41164\n for <dev@dpdk.org>; Mon, 11 Oct 2021 17:51:20 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id\n 19BE6eNe030296;\n Mon, 11 Oct 2021 08:51:17 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 3bmpqt0gh7-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 11 Oct 2021 08:51:17 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 11 Oct 2021 08:51:15 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 11 Oct 2021 08:51:15 -0700", "from localhost.localdomain (unknown [10.28.34.25])\n by maili.marvell.com (Postfix) with ESMTP id 04A603F7079;\n Mon, 11 Oct 2021 08:51:13 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=NUJYu3EX0HP3/gquf+TjgHfdBlOD9TdqzFW2aONxlpw=;\n b=ekbJjGPuHoRvPo2MV4dfxGI7jX4B4p7EBc12LeSeSwubvEkFqkbV1WLuZVxLF8PkesgW\n o7SZ5Qu2pvdXyNBTQ+frm5R4PCZusQuoj5y+zw83np5ioTWqpNh9hu1FaO0phrI1nfN/\n 6uAI1wvopNByXbGRdp7Yha7c6SpnJ/5crnCnEmHCDdqGrvHqscuNMYpWdQhO+nh1KT7E\n fR6CdXnIMc4gAYLFT9IeOW551a/EbEPGPRNwX7Uu7M40vyNEFHE/5HVKmxyfRLovwG50\n UFyhp+KaN6al4XTA6qU6z+2O/wBi8jQU0AIbERAWVOS8u4vXB8uHstfD0YYZfiwcO0L9 PQ==", "From": "<skori@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<dev@dpdk.org>", "Date": "Mon, 11 Oct 2021 21:20:34 +0530", "Message-ID": "<20211011155057.302142-7-skori@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211011155057.302142-1-skori@marvell.com>", "References": "<20210930090844.1059326-1-skori@marvell.com>\n <20211011155057.302142-1-skori@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "X1Svf7mBHmc0NnOzI4TezLNuemeSboMo", "X-Proofpoint-GUID": "X1Svf7mBHmc0NnOzI4TezLNuemeSboMo", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475\n definitions=2021-10-11_05,2021-10-11_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH v4 06/28] common/cnxk: support RoC API to\n configure bandwidth profile", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nImplement RoC API to configure HW bandwidth profile for\nCN10K platform.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\nv4:\n - Rebase support on dpdk-next-net-mrvl branch\n - Handled meter action during flow destroy\n - Handled meter cleanup during port shutdown\n \nv3:\n - Rebase support on latest DPDK\n - Handled multilevel chaining for tree hierarchy\n - Fix naming convention\nv2:\n - Rebase support on latest DPDK\n - Handled multilevel chaining for linear hierarchy\n - Review comments incorporated\n\n drivers/common/cnxk/hw/nix.h | 49 ++++++\n drivers/common/cnxk/roc_nix.h | 63 ++++++++\n drivers/common/cnxk/roc_nix_bpf.c | 239 ++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 1 +\n 4 files changed, 352 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h\nindex 7685b7dc1b..b9e65c942f 100644\n--- a/drivers/common/cnxk/hw/nix.h\n+++ b/drivers/common/cnxk/hw/nix.h\n@@ -2113,6 +2113,55 @@ struct nix_lso_format {\n #define NIX_RPM_MAX_HW_FRS 16380UL\n #define NIX_MIN_HW_FRS\t 60UL\n \n+/** NIX policer rate limits */\n+#define NIX_BPF_MAX_RATE_DIV_EXP 12\n+#define NIX_BPF_MAX_RATE_EXPONENT 0xf\n+#define NIX_BPF_MAX_RATE_MANTISSA 0xff\n+\n+#define NIX_BPF_RATE_CONST 2000000ULL\n+\n+/* NIX rate calculation in Bits/Sec\n+ *\tPIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA])\n+ *\t\t<< NIX_*_PIR[RATE_EXPONENT]) / 256\n+ *\tPIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))\n+ *\n+ *\tCIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA])\n+ *\t\t<< NIX_*_CIR[RATE_EXPONENT]) / 256\n+ *\tCIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))\n+ */\n+#define NIX_BPF_RATE(exponent, mantissa, div_exp) \\\n+\t((NIX_BPF_RATE_CONST * ((256 + (mantissa)) << (exponent))) / \\\n+\t (((1ull << (div_exp)) * 256)))\n+\n+/* Meter rate limits in Bits/Sec */\n+#define NIX_BPF_RATE_MIN NIX_BPF_RATE(0, 0, NIX_BPF_MAX_RATE_DIV_EXP)\n+#define NIX_BPF_RATE_MAX \\\n+\tNIX_BPF_RATE(NIX_BPF_MAX_RATE_EXPONENT, NIX_BPF_MAX_RATE_MANTISSA, 0)\n+\n+#define NIX_BPF_DEFAULT_ADJUST_MANTISSA 511\n+#define NIX_BPF_DEFAULT_ADJUST_EXPONENT 0\n+\n+/** NIX burst limits */\n+#define NIX_BPF_MAX_BURST_EXPONENT 0xf\n+#define NIX_BPF_MAX_BURST_MANTISSA 0xff\n+\n+/* NIX burst calculation\n+ *\tPIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA])\n+ *\t\t<< (NIX_*_PIR[BURST_EXPONENT] + 1))\n+ *\t\t\t/ 256\n+ *\n+ *\tCIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA])\n+ *\t\t<< (NIX_*_CIR[BURST_EXPONENT] + 1))\n+ *\t\t\t/ 256\n+ */\n+#define NIX_BPF_BURST(exponent, mantissa) \\\n+\t(((256 + (mantissa)) << ((exponent) + 1)) / 256)\n+\n+/** Meter burst limits */\n+#define NIX_BPF_BURST_MIN NIX_BPF_BURST(0, 0)\n+#define NIX_BPF_BURST_MAX \\\n+\tNIX_BPF_BURST(NIX_BPF_MAX_BURST_EXPONENT, NIX_BPF_MAX_BURST_MANTISSA)\n+\n /* NIX rate limits */\n #define NIX_TM_MAX_RATE_DIV_EXP\t 12\n #define NIX_TM_MAX_RATE_EXPONENT 0xf\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex a5642337b2..c2cc823516 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -39,6 +39,65 @@ enum roc_nix_bpf_level_flag {\n \tROC_NIX_BPF_LEVEL_F_TOP = BIT(2),\n };\n \n+enum roc_nix_bpf_color {\n+\tROC_NIX_BPF_COLOR_GREEN,\n+\tROC_NIX_BPF_COLOR_YELLOW,\n+\tROC_NIX_BPF_COLOR_RED,\n+\tROC_NIX_BPF_COLOR_MAX\n+};\n+\n+enum roc_nix_bpf_algo {\n+\tROC_NIX_BPF_ALGO_NONE,\n+\tROC_NIX_BPF_ALGO_2698,\n+\tROC_NIX_BPF_ALGO_4115,\n+\tROC_NIX_BPF_ALGO_2697\n+};\n+\n+enum roc_nix_bpf_lmode { ROC_NIX_BPF_LMODE_BYTE, ROC_NIX_BPF_LMODE_PACKET };\n+\n+enum roc_nix_bpf_action {\n+\tROC_NIX_BPF_ACTION_PASS,\n+\tROC_NIX_BPF_ACTION_DROP,\n+\tROC_NIX_BPF_ACTION_RED\n+};\n+\n+struct roc_nix_bpf_cfg {\n+\tenum roc_nix_bpf_algo alg;\n+\tenum roc_nix_bpf_lmode lmode;\n+\tenum roc_nix_bpf_color icolor;\n+\tenum roc_nix_bpf_pc_mode pc_mode;\n+\tbool tnl_ena;\n+\tunion {\n+\t\t/* Valid when *alg* is set to ROC_NIX_BPF_ALGO_2697. */\n+\t\tstruct {\n+\t\t\tuint64_t cir;\n+\t\t\tuint64_t cbs;\n+\t\t\tuint64_t ebs;\n+\t\t} algo2697;\n+\n+\t\t/* Valid when *alg* is set to ROC_NIX_BPF_ALGO_2698. */\n+\t\tstruct {\n+\t\t\tuint64_t cir;\n+\t\t\tuint64_t pir;\n+\t\t\tuint64_t cbs;\n+\t\t\tuint64_t pbs;\n+\t\t} algo2698;\n+\n+\t\t/* Valid when *alg* is set to ROC_NIX_BPF_ALGO_4115. */\n+\t\tstruct {\n+\t\t\tuint64_t cir;\n+\t\t\tuint64_t eir;\n+\t\t\tuint64_t cbs;\n+\t\t\tuint64_t ebs;\n+\t\t} algo4115;\n+\t};\n+\n+\tenum roc_nix_bpf_action action[ROC_NIX_BPF_COLOR_MAX];\n+\n+\t/* Reserved for future config*/\n+\tuint32_t rsvd[3];\n+};\n+\n struct roc_nix_bpf_objs {\n \tuint16_t level;\n \tuint16_t count;\n@@ -539,6 +598,10 @@ int __roc_api roc_nix_bpf_free(struct roc_nix *roc_nix,\n \n int __roc_api roc_nix_bpf_free_all(struct roc_nix *roc_nix);\n \n+int __roc_api roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id,\n+\t\t\t\t enum roc_nix_bpf_level_flag lvl_flag,\n+\t\t\t\t struct roc_nix_bpf_cfg *cfg);\n+\n uint8_t __roc_api\n roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag);\n \ndiff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c\nindex 41d31bc6cd..aa5829ee42 100644\n--- a/drivers/common/cnxk/roc_nix_bpf.c\n+++ b/drivers/common/cnxk/roc_nix_bpf.c\n@@ -26,6 +26,105 @@ get_mbox(struct roc_nix *roc_nix)\n \treturn dev->mbox;\n }\n \n+static inline uint64_t\n+meter_rate_to_nix(uint64_t value, uint64_t *exponent_p, uint64_t *mantissa_p,\n+\t\t uint64_t *div_exp_p)\n+{\n+\tuint64_t div_exp, exponent, mantissa;\n+\n+\t/* Boundary checks */\n+\tif (value < NIX_BPF_RATE_MIN || value > NIX_BPF_RATE_MAX)\n+\t\treturn 0;\n+\n+\tif (value <= NIX_BPF_RATE(0, 0, 0)) {\n+\t\t/* Calculate rate div_exp and mantissa using\n+\t\t * the following formula:\n+\t\t *\n+\t\t * value = (2E6 * (256 + mantissa)\n+\t\t * / ((1 << div_exp) * 256))\n+\t\t */\n+\t\tdiv_exp = 0;\n+\t\texponent = 0;\n+\t\tmantissa = NIX_BPF_MAX_RATE_MANTISSA;\n+\n+\t\twhile (value < (NIX_BPF_RATE_CONST / (1 << div_exp)))\n+\t\t\tdiv_exp += 1;\n+\n+\t\twhile (value < ((NIX_BPF_RATE_CONST * (256 + mantissa)) /\n+\t\t\t\t((1 << div_exp) * 256)))\n+\t\t\tmantissa -= 1;\n+\t} else {\n+\t\t/* Calculate rate exponent and mantissa using\n+\t\t * the following formula:\n+\t\t *\n+\t\t * value = (2E6 * ((256 + mantissa) << exponent)) / 256\n+\t\t *\n+\t\t */\n+\t\tdiv_exp = 0;\n+\t\texponent = NIX_BPF_MAX_RATE_EXPONENT;\n+\t\tmantissa = NIX_BPF_MAX_RATE_MANTISSA;\n+\n+\t\twhile (value < (NIX_BPF_RATE_CONST * (1 << exponent)))\n+\t\t\texponent -= 1;\n+\n+\t\twhile (value <\n+\t\t ((NIX_BPF_RATE_CONST * ((256 + mantissa) << exponent)) /\n+\t\t\t256))\n+\t\t\tmantissa -= 1;\n+\t}\n+\n+\tif (div_exp > NIX_BPF_MAX_RATE_DIV_EXP ||\n+\t exponent > NIX_BPF_MAX_RATE_EXPONENT ||\n+\t mantissa > NIX_BPF_MAX_RATE_MANTISSA)\n+\t\treturn 0;\n+\n+\tif (div_exp_p)\n+\t\t*div_exp_p = div_exp;\n+\tif (exponent_p)\n+\t\t*exponent_p = exponent;\n+\tif (mantissa_p)\n+\t\t*mantissa_p = mantissa;\n+\n+\t/* Calculate real rate value */\n+\treturn NIX_BPF_RATE(exponent, mantissa, div_exp);\n+}\n+\n+static inline uint64_t\n+meter_burst_to_nix(uint64_t value, uint64_t *exponent_p, uint64_t *mantissa_p)\n+{\n+\tuint64_t exponent, mantissa;\n+\n+\tif (value < NIX_BPF_BURST_MIN || value > NIX_BPF_BURST_MAX)\n+\t\treturn 0;\n+\n+\t/* Calculate burst exponent and mantissa using\n+\t * the following formula:\n+\t *\n+\t * value = (((256 + mantissa) << (exponent + 1)\n+\t / 256)\n+\t *\n+\t */\n+\texponent = NIX_BPF_MAX_BURST_EXPONENT;\n+\tmantissa = NIX_BPF_MAX_BURST_MANTISSA;\n+\n+\twhile (value < (1ull << (exponent + 1)))\n+\t\texponent -= 1;\n+\n+\twhile (value < ((256 + mantissa) << (exponent + 1)) / 256)\n+\t\tmantissa -= 1;\n+\n+\tif (exponent > NIX_BPF_MAX_BURST_EXPONENT ||\n+\t mantissa > NIX_BPF_MAX_BURST_MANTISSA)\n+\t\treturn 0;\n+\n+\tif (exponent_p)\n+\t\t*exponent_p = exponent;\n+\tif (mantissa_p)\n+\t\t*mantissa_p = mantissa;\n+\n+\treturn NIX_BPF_BURST(exponent, mantissa);\n+}\n+\n uint8_t\n roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag level_f)\n {\n@@ -210,3 +309,143 @@ roc_nix_bpf_free_all(struct roc_nix *roc_nix)\n \treq->free_all = true;\n \treturn mbox_process(mbox);\n }\n+\n+int\n+roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id,\n+\t\t enum roc_nix_bpf_level_flag lvl_flag,\n+\t\t struct roc_nix_bpf_cfg *cfg)\n+{\n+\tuint64_t exponent_p = 0, mantissa_p = 0, div_exp_p = 0;\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix_cn10k_aq_enq_req *aq;\n+\tuint8_t level_idx;\n+\n+\tif (roc_model_is_cn9k())\n+\t\treturn NIX_ERR_HW_NOTSUP;\n+\n+\tif (!cfg)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tlevel_idx = roc_nix_bpf_level_to_idx(lvl_flag);\n+\tif (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\tif (aq == NULL)\n+\t\treturn -ENOSPC;\n+\taq->qidx = (sw_to_hw_lvl_map[level_idx] << 14) | id;\n+\taq->ctype = NIX_AQ_CTYPE_BAND_PROF;\n+\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\taq->prof.adjust_exponent = NIX_BPF_DEFAULT_ADJUST_EXPONENT;\n+\taq->prof.adjust_mantissa = NIX_BPF_DEFAULT_ADJUST_MANTISSA;\n+\tif (cfg->lmode == ROC_NIX_BPF_LMODE_BYTE)\n+\t\taq->prof.adjust_mantissa = NIX_BPF_DEFAULT_ADJUST_MANTISSA / 2;\n+\n+\taq->prof_mask.adjust_exponent = ~(aq->prof_mask.adjust_exponent);\n+\taq->prof_mask.adjust_mantissa = ~(aq->prof_mask.adjust_mantissa);\n+\n+\tswitch (cfg->alg) {\n+\tcase ROC_NIX_BPF_ALGO_2697:\n+\t\tmeter_rate_to_nix(cfg->algo2697.cir, &exponent_p, &mantissa_p,\n+\t\t\t\t &div_exp_p);\n+\t\taq->prof.cir_mantissa = mantissa_p;\n+\t\taq->prof.cir_exponent = exponent_p;\n+\n+\t\tmeter_burst_to_nix(cfg->algo2697.cbs, &exponent_p, &mantissa_p);\n+\t\taq->prof.cbs_mantissa = mantissa_p;\n+\t\taq->prof.cbs_exponent = exponent_p;\n+\n+\t\tmeter_burst_to_nix(cfg->algo2697.ebs, &exponent_p, &mantissa_p);\n+\t\taq->prof.pebs_mantissa = mantissa_p;\n+\t\taq->prof.pebs_exponent = exponent_p;\n+\n+\t\taq->prof_mask.cir_mantissa = ~(aq->prof_mask.cir_mantissa);\n+\t\taq->prof_mask.cbs_mantissa = ~(aq->prof_mask.cbs_mantissa);\n+\t\taq->prof_mask.pebs_mantissa = ~(aq->prof_mask.pebs_mantissa);\n+\t\taq->prof_mask.cir_exponent = ~(aq->prof_mask.cir_exponent);\n+\t\taq->prof_mask.cbs_exponent = ~(aq->prof_mask.cbs_exponent);\n+\t\taq->prof_mask.pebs_exponent = ~(aq->prof_mask.pebs_exponent);\n+\t\tbreak;\n+\n+\tcase ROC_NIX_BPF_ALGO_2698:\n+\t\tmeter_rate_to_nix(cfg->algo2698.cir, &exponent_p, &mantissa_p,\n+\t\t\t\t &div_exp_p);\n+\t\taq->prof.cir_mantissa = mantissa_p;\n+\t\taq->prof.cir_exponent = exponent_p;\n+\n+\t\tmeter_rate_to_nix(cfg->algo2698.pir, &exponent_p, &mantissa_p,\n+\t\t\t\t &div_exp_p);\n+\t\taq->prof.peir_mantissa = mantissa_p;\n+\t\taq->prof.peir_exponent = exponent_p;\n+\n+\t\tmeter_burst_to_nix(cfg->algo2698.cbs, &exponent_p, &mantissa_p);\n+\t\taq->prof.cbs_mantissa = mantissa_p;\n+\t\taq->prof.cbs_exponent = exponent_p;\n+\n+\t\tmeter_burst_to_nix(cfg->algo2698.pbs, &exponent_p, &mantissa_p);\n+\t\taq->prof.pebs_mantissa = mantissa_p;\n+\t\taq->prof.pebs_exponent = exponent_p;\n+\n+\t\taq->prof_mask.cir_mantissa = ~(aq->prof_mask.cir_mantissa);\n+\t\taq->prof_mask.peir_mantissa = ~(aq->prof_mask.peir_mantissa);\n+\t\taq->prof_mask.cbs_mantissa = ~(aq->prof_mask.cbs_mantissa);\n+\t\taq->prof_mask.pebs_mantissa = ~(aq->prof_mask.pebs_mantissa);\n+\t\taq->prof_mask.cir_exponent = ~(aq->prof_mask.cir_exponent);\n+\t\taq->prof_mask.peir_exponent = ~(aq->prof_mask.peir_exponent);\n+\t\taq->prof_mask.cbs_exponent = ~(aq->prof_mask.cbs_exponent);\n+\t\taq->prof_mask.pebs_exponent = ~(aq->prof_mask.pebs_exponent);\n+\t\tbreak;\n+\n+\tcase ROC_NIX_BPF_ALGO_4115:\n+\t\tmeter_rate_to_nix(cfg->algo4115.cir, &exponent_p, &mantissa_p,\n+\t\t\t\t &div_exp_p);\n+\t\taq->prof.cir_mantissa = mantissa_p;\n+\t\taq->prof.cir_exponent = exponent_p;\n+\n+\t\tmeter_rate_to_nix(cfg->algo4115.eir, &exponent_p, &mantissa_p,\n+\t\t\t\t &div_exp_p);\n+\t\taq->prof.peir_mantissa = mantissa_p;\n+\t\taq->prof.peir_exponent = exponent_p;\n+\n+\t\tmeter_burst_to_nix(cfg->algo4115.cbs, &exponent_p, &mantissa_p);\n+\t\taq->prof.cbs_mantissa = mantissa_p;\n+\t\taq->prof.cbs_exponent = exponent_p;\n+\n+\t\tmeter_burst_to_nix(cfg->algo4115.ebs, &exponent_p, &mantissa_p);\n+\t\taq->prof.pebs_mantissa = mantissa_p;\n+\t\taq->prof.pebs_exponent = exponent_p;\n+\n+\t\taq->prof_mask.cir_mantissa = ~(aq->prof_mask.cir_mantissa);\n+\t\taq->prof_mask.peir_mantissa = ~(aq->prof_mask.peir_mantissa);\n+\t\taq->prof_mask.cbs_mantissa = ~(aq->prof_mask.cbs_mantissa);\n+\t\taq->prof_mask.pebs_mantissa = ~(aq->prof_mask.pebs_mantissa);\n+\n+\t\taq->prof_mask.cir_exponent = ~(aq->prof_mask.cir_exponent);\n+\t\taq->prof_mask.peir_exponent = ~(aq->prof_mask.peir_exponent);\n+\t\taq->prof_mask.cbs_exponent = ~(aq->prof_mask.cbs_exponent);\n+\t\taq->prof_mask.pebs_exponent = ~(aq->prof_mask.pebs_exponent);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treturn NIX_ERR_PARAM;\n+\t}\n+\n+\taq->prof.lmode = cfg->lmode;\n+\taq->prof.icolor = cfg->icolor;\n+\taq->prof.pc_mode = cfg->pc_mode;\n+\taq->prof.tnl_ena = cfg->tnl_ena;\n+\taq->prof.gc_action = cfg->action[ROC_NIX_BPF_COLOR_GREEN];\n+\taq->prof.yc_action = cfg->action[ROC_NIX_BPF_COLOR_YELLOW];\n+\taq->prof.rc_action = cfg->action[ROC_NIX_BPF_COLOR_RED];\n+\n+\taq->prof_mask.lmode = ~(aq->prof_mask.lmode);\n+\taq->prof_mask.icolor = ~(aq->prof_mask.icolor);\n+\taq->prof_mask.pc_mode = ~(aq->prof_mask.pc_mode);\n+\taq->prof_mask.tnl_ena = ~(aq->prof_mask.tnl_ena);\n+\taq->prof_mask.gc_action = ~(aq->prof_mask.gc_action);\n+\taq->prof_mask.yc_action = ~(aq->prof_mask.yc_action);\n+\taq->prof_mask.rc_action = ~(aq->prof_mask.rc_action);\n+\n+\treturn mbox_process(mbox);\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 3d474f8a96..f34fd3b4a4 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -83,6 +83,7 @@ INTERNAL {\n \troc_se_auth_key_set;\n \troc_se_ciph_key_set;\n \troc_nix_bpf_alloc;\n+\troc_nix_bpf_config;\n \troc_nix_bpf_count_get;\n \troc_nix_bpf_free;\n \troc_nix_bpf_free_all;\n", "prefixes": [ "v4", "06/28" ] }