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GET /api/patches/100503/?format=api
{ "id": 100503, "url": "https://patches.dpdk.org/api/patches/100503/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211005122733.12444-4-rzidane@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211005122733.12444-4-rzidane@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211005122733.12444-4-rzidane@nvidia.com", "date": "2021-10-05T12:27:31", "name": "[V6,3/5] common/mlx5: add MMO configuration for the DevX QP", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a5305ca24aa5cb1f57a96ce565a1e14d5beb71a9", "submitter": { "id": 2300, "url": "https://patches.dpdk.org/api/people/2300/?format=api", "name": "Raja Zidane", "email": "rzidane@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211005122733.12444-4-rzidane@nvidia.com/mbox/", "series": [ { "id": 19387, "url": "https://patches.dpdk.org/api/series/19387/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19387", "date": "2021-10-05T12:27:28", "name": "mlx5: replaced hardware queue object", "version": 6, "mbox": "https://patches.dpdk.org/series/19387/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/100503/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/100503/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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SFS:(4636009)(36840700001)(46966006)(70206006)(83380400001)(316002)(356005)(426003)(6286002)(8676002)(6666004)(8936002)(7696005)(2906002)(36860700001)(336012)(7636003)(5660300002)(26005)(86362001)(70586007)(16526019)(55016002)(47076005)(1076003)(6916009)(82310400003)(36756003)(186003)(2616005)(508600001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Oct 2021 12:28:06.9280 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 04712319-f8dd-4cc4-0c46-08d987fb95dd", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT027.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4274", "Subject": "[dpdk-dev] [PATCH V6 3/5] common/mlx5: add MMO configuration for\n the DevX QP", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "A new configuration MMO was added to QP Context.\nIf set, MMO WQEs are supported on this QP.\nFor DMA MMO, supported only when dma_mmo_qp==1.\nFor REGEXP MMO, supported only when regexp_mmo_qp==1.\nFor COMPRESS MMO, supported only when compress_mmo_qp==1.\nFor DECOMPRESS MMO, supported only when decompress_mmo_qp==1.\nAdd support to DevX interface to set MMO bit.\n\nSigned-off-by: Raja Zidane <rzidane@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 7 +++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 28 +++++++++++++++++++++++++++-\n 3 files changed, 35 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 00c78b1288..eefb869b7d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -2032,6 +2032,13 @@ mlx5_devx_cmd_create_qp(void *ctx,\n \tMLX5_SET(qpc, qpc, ts_format, attr->ts_format);\n \tMLX5_SET(qpc, qpc, user_index, attr->user_index);\n \tif (attr->uar_index) {\n+\t\tif (attr->mmo) {\n+\t\t\tvoid *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,\n+\t\t\t\tin, qpc_extension_and_pas_list);\n+\t\t\tvoid *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,\n+\t\t\t\tqpc_ext_and_pas_list, qpc_data_extension);\n+\t\t\tMLX5_SET(qpc_extension, qpc_ext, mmo, 1);\n+\t\t}\n \t\tMLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);\n \t\tMLX5_SET(qpc, qpc, uar_page, attr->uar_index);\n \t\tif (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex b21df0fd9b..e149f8b4f5 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -403,6 +403,7 @@ struct mlx5_devx_qp_attr {\n \tuint32_t wq_umem_id;\n \tuint64_t wq_umem_offset;\n \tuint32_t user_index:24;\n+\tuint32_t mmo:1;\n };\n \n struct mlx5_devx_virtio_q_couners_attr {\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex ec5f871c61..54e62aa153 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3243,6 +3243,28 @@ struct mlx5_ifc_create_qp_out_bits {\n \tu8 reserved_at_60[0x20];\n };\n \n+struct mlx5_ifc_qpc_extension_bits {\n+\tu8 reserved_at_0[0x2];\n+\tu8 mmo[0x1];\n+\tu8 reserved_at_3[0x5fd];\n+};\n+\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+struct mlx5_ifc_qpc_pas_list_bits {\n+\tu8 pas[0][0x40];\n+};\n+\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+struct mlx5_ifc_qpc_extension_and_pas_list_bits {\n+\tstruct mlx5_ifc_qpc_extension_bits qpc_data_extension;\n+\tu8 pas[0][0x40];\n+};\n+\n+\n #ifdef PEDANTIC\n #pragma GCC diagnostic ignored \"-Wpedantic\"\n #endif\n@@ -3260,7 +3282,11 @@ struct mlx5_ifc_create_qp_in_bits {\n \tu8 wq_umem_id[0x20];\n \tu8 wq_umem_valid[0x1];\n \tu8 reserved_at_861[0x1f];\n-\tu8 pas[0][0x40];\n+\tunion {\n+\t\tstruct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;\n+\t\tstruct mlx5_ifc_qpc_extension_and_pas_list_bits\n+\t\t\t\t\tqpc_extension_and_pas_list;\n+\t};\n };\n #ifdef PEDANTIC\n #pragma GCC diagnostic error \"-Wpedantic\"\n", "prefixes": [ "V6", "3/5" ] }