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GET /api/patches/100259/?format=api
{ "id": 100259, "url": "https://patches.dpdk.org/api/patches/100259/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211001134022.22700-14-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211001134022.22700-14-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211001134022.22700-14-ndabilpuram@marvell.com", "date": "2021-10-01T13:40:07", "name": "[v3,13/28] common/cnxk: setup aura BP conf based on nix", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a84e6fda748e92bcf6aa65dbb574be4c60f231ee", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211001134022.22700-14-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 19325, "url": "https://patches.dpdk.org/api/series/19325/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19325", "date": "2021-10-01T13:39:54", "name": "net/cnxk: support for inline ipsec", "version": 3, "mbox": "https://patches.dpdk.org/series/19325/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/100259/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/100259/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 30DADA0032;\n\tFri, 1 Oct 2021 15:42:03 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 982E2411D6;\n\tFri, 1 Oct 2021 15:41:06 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 390D8411D9\n for <dev@dpdk.org>; Fri, 1 Oct 2021 15:41:05 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 191ACEFH001661\n for <dev@dpdk.org>; Fri, 1 Oct 2021 06:41:04 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 3bdrxmhxb6-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 01 Oct 2021 06:41:04 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Fri, 1 Oct 2021 06:41:01 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Fri, 1 Oct 2021 06:41:01 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 0FCFB3F7041;\n Fri, 1 Oct 2021 06:40:59 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=3NvcO7fH0TlSKAazKmJC/M5/EBYIhT649nQ+GHoyYpM=;\n b=jiGICsjgBiWDZKq92vEjafsSRyDnSY30Z3ks7sgEtyXrtiqZA4IouZ+cRv6OKCel2Y8A\n ifZr13d8EFr6jLBlM5hd9MT/aZD3xzudmYhFHj4fxmyL7JpMHiuFhYwz0PCFmyByW64b\n TFFcZ7ET1o75DbeN3szxa0UC4P4git10hjR0xfMOp19XiDjXQSWPrFhwmXRYQ68HXyQh\n qBFzGzudcGG90n24HHsLdbmMjsJSKu//8WYbApzsfvruTKBpDWz+wo32CPC83vQDEm1U\n usamIyrSuNLCa1EQ5x+Xd40+NBiKgIcHgs7CUI6y2EwLhxYZlyVFbRBKkRfc4Xp3lcjV gA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 1 Oct 2021 19:10:07 +0530", "Message-ID": "<20211001134022.22700-14-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20211001134022.22700-1-ndabilpuram@marvell.com>", "References": "<20210902021505.17607-1-ndabilpuram@marvell.com>\n <20211001134022.22700-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "9FG16XQiUv1p2YY_7Yi0SbeEyFuC-Ozb", "X-Proofpoint-ORIG-GUID": "9FG16XQiUv1p2YY_7Yi0SbeEyFuC-Ozb", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-10-01_02,2021-10-01_02,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH v3 13/28] common/cnxk: setup aura BP conf based\n on nix", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Currently only NIX0 conf is setup in AURA for backpressure.\nThis patch adds support for NIX1 as well.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix_fc.c | 23 +++++++++++++++++++----\n 1 file changed, 19 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex f17eba4..7eac7d0 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -284,8 +284,18 @@ rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \tlimit = rsp->aura.limit;\n \t/* BP is already enabled. */\n \tif (rsp->aura.bp_ena) {\n+\t\tuint16_t bpid;\n+\t\tbool nix1;\n+\n+\t\tnix1 = !!(rsp->aura.bp_ena & 0x2);\n+\t\tif (nix1)\n+\t\t\tbpid = rsp->aura.nix1_bpid;\n+\t\telse\n+\t\t\tbpid = rsp->aura.nix0_bpid;\n+\n \t\t/* If BP ids don't match disable BP. */\n-\t\tif ((rsp->aura.nix0_bpid != nix->bpid[0]) && !force) {\n+\t\tif (((nix1 != nix->is_nix1) || (bpid != nix->bpid[0])) &&\n+\t\t !force) {\n \t\t\treq = mbox_alloc_msg_npa_aq_enq(mbox);\n \t\t\tif (req == NULL)\n \t\t\t\treturn;\n@@ -315,14 +325,19 @@ rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \treq->op = NPA_AQ_INSTOP_WRITE;\n \n \tif (ena) {\n-\t\treq->aura.nix0_bpid = nix->bpid[0];\n-\t\treq->aura_mask.nix0_bpid = ~(req->aura_mask.nix0_bpid);\n+\t\tif (nix->is_nix1) {\n+\t\t\treq->aura.nix1_bpid = nix->bpid[0];\n+\t\t\treq->aura_mask.nix1_bpid = ~(req->aura_mask.nix1_bpid);\n+\t\t} else {\n+\t\t\treq->aura.nix0_bpid = nix->bpid[0];\n+\t\t\treq->aura_mask.nix0_bpid = ~(req->aura_mask.nix0_bpid);\n+\t\t}\n \t\treq->aura.bp = NIX_RQ_AURA_THRESH(\n \t\t\tlimit > 128 ? 256 : limit); /* 95% of size*/\n \t\treq->aura_mask.bp = ~(req->aura_mask.bp);\n \t}\n \n-\treq->aura.bp_ena = !!ena;\n+\treq->aura.bp_ena = (!!ena << nix->is_nix1);\n \treq->aura_mask.bp_ena = ~(req->aura_mask.bp_ena);\n \n \tmbox_process(mbox);\n", "prefixes": [ "v3", "13/28" ] }