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GET /api/patches/100249/?format=api
{ "id": 100249, "url": "https://patches.dpdk.org/api/patches/100249/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211001134022.22700-4-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211001134022.22700-4-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211001134022.22700-4-ndabilpuram@marvell.com", "date": "2021-10-01T13:39:57", "name": "[v3,03/28] common/cnxk: allow reuse of SSO API for inline dev", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "545bcd963d2510269eb43e064e63e4d5a7ae4f9a", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211001134022.22700-4-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 19325, "url": "https://patches.dpdk.org/api/series/19325/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19325", "date": "2021-10-01T13:39:54", "name": "net/cnxk: support for inline ipsec", "version": 3, "mbox": "https://patches.dpdk.org/series/19325/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/100249/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/100249/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 22142A0032;\n\tFri, 1 Oct 2021 15:40:50 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2156E4119C;\n\tFri, 1 Oct 2021 15:40:40 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id C98E741194\n for <dev@dpdk.org>; Fri, 1 Oct 2021 15:40:37 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 191AGFYY009954\n for <dev@dpdk.org>; Fri, 1 Oct 2021 06:40:37 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 3bdrxmhx8a-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 01 Oct 2021 06:40:37 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Fri, 1 Oct 2021 06:40:35 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Fri, 1 Oct 2021 06:40:35 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 296643F7053;\n Fri, 1 Oct 2021 06:40:32 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=t6honXfmtcqYmDJNjDIYxLOGZEKGvr4l4QluIiON4VE=;\n b=CSmOBNTTKDGyNaJH2MG2gLB9c8UNnVLRsem7WlfoJhgru4Oe4Aliz+zdeaK3XuRpBdnY\n GOkDtSCwcqB36nIkCZF4f6uiRCeUsylIeAvnEP8WX1nSCccgjrhjrV45Xko2OGF9VQdw\n 77ep9iJ1dQroN5xn7sckkoe93iGinulJvrR905d4tqUoSOyg0kgpYrmX3+beK/0/fo1I\n 4fPieXsFpgcDLy5BlpYGqc3PgHNfYewFBPVZXjcLI10fPQaWwULJOgOnsBdrIPoq4zgY\n 5GPus6qcy5zWEt67XXhLK3fk5rqSf/7GVdyMppiyKcJQWemf+y9XnMDdBXVf7Gb3ckHG /w==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 1 Oct 2021 19:09:57 +0530", "Message-ID": "<20211001134022.22700-4-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20211001134022.22700-1-ndabilpuram@marvell.com>", "References": "<20210902021505.17607-1-ndabilpuram@marvell.com>\n <20211001134022.22700-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "B-OHOuIRT1hL53O1vjEfTgRvlMzWoQfA", "X-Proofpoint-ORIG-GUID": "B-OHOuIRT1hL53O1vjEfTgRvlMzWoQfA", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-10-01_02,2021-10-01_02,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH v3 03/28] common/cnxk: allow reuse of SSO API for\n inline dev", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Rework interface of SSO internal functions to use for NIX inline dev's\nSSO LF's.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_sso.c | 52 ++++++++++++++++++++++++--------------\n drivers/common/cnxk/roc_sso_priv.h | 9 +++++++\n 2 files changed, 42 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c\nindex 1ccf262..bdf973f 100644\n--- a/drivers/common/cnxk/roc_sso.c\n+++ b/drivers/common/cnxk/roc_sso.c\n@@ -6,11 +6,10 @@\n #include \"roc_priv.h\"\n \n /* Private functions. */\n-static int\n-sso_lf_alloc(struct roc_sso *roc_sso, enum sso_lf_type lf_type, uint16_t nb_lf,\n+int\n+sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf,\n \t void **rsp)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n \tint rc = -ENOSPC;\n \n \tswitch (lf_type) {\n@@ -41,10 +40,9 @@ sso_lf_alloc(struct roc_sso *roc_sso, enum sso_lf_type lf_type, uint16_t nb_lf,\n \treturn 0;\n }\n \n-static int\n-sso_lf_free(struct roc_sso *roc_sso, enum sso_lf_type lf_type, uint16_t nb_lf)\n+int\n+sso_lf_free(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n \tint rc = -ENOSPC;\n \n \tswitch (lf_type) {\n@@ -152,7 +150,7 @@ sso_rsrc_get(struct roc_sso *roc_sso)\n \treturn 0;\n }\n \n-static void\n+void\n sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp,\n \t\t uint16_t hwgrp[], uint16_t n, uint16_t enable)\n {\n@@ -172,8 +170,10 @@ sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp,\n \t\tk = k ? k : 4;\n \t\tfor (j = 0; j < k; j++) {\n \t\t\tmask[j] = hwgrp[i + j] | enable << 14;\n-\t\t\tenable ? plt_bitmap_set(bmp, hwgrp[i + j]) :\n-\t\t\t\t plt_bitmap_clear(bmp, hwgrp[i + j]);\n+\t\t\tif (bmp) {\n+\t\t\t\tenable ? plt_bitmap_set(bmp, hwgrp[i + j]) :\n+\t\t\t\t\t plt_bitmap_clear(bmp, hwgrp[i + j]);\n+\t\t\t}\n \t\t\tplt_sso_dbg(\"HWS %d Linked to HWGRP %d\", hws,\n \t\t\t\t hwgrp[i + j]);\n \t\t}\n@@ -388,10 +388,8 @@ roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos,\n }\n \n int\n-roc_sso_hwgrp_alloc_xaq(struct roc_sso *roc_sso, uint32_t npa_aura_id,\n-\t\t\tuint16_t hwgrps)\n+sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n \tstruct sso_hw_setconfig *req;\n \tint rc = -ENOSPC;\n \n@@ -406,9 +404,17 @@ roc_sso_hwgrp_alloc_xaq(struct roc_sso *roc_sso, uint32_t npa_aura_id,\n }\n \n int\n-roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps)\n+roc_sso_hwgrp_alloc_xaq(struct roc_sso *roc_sso, uint32_t npa_aura_id,\n+\t\t\tuint16_t hwgrps)\n {\n \tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\n+\treturn sso_hwgrp_alloc_xaq(dev, npa_aura_id, hwgrps);\n+}\n+\n+int\n+sso_hwgrp_release_xaq(struct dev *dev, uint16_t hwgrps)\n+{\n \tstruct sso_hw_xaq_release *req;\n \n \treq = mbox_alloc_msg_sso_hw_release_xaq_aura(dev->mbox);\n@@ -420,6 +426,14 @@ roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps)\n }\n \n int\n+roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\n+\treturn sso_hwgrp_release_xaq(dev, hwgrps);\n+}\n+\n+int\n roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, uint16_t hwgrp,\n \t\t\t uint8_t weight, uint8_t affinity, uint8_t priority)\n {\n@@ -468,13 +482,13 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp)\n \t\tgoto hwgrp_atch_fail;\n \t}\n \n-\trc = sso_lf_alloc(roc_sso, SSO_LF_TYPE_HWS, nb_hws, NULL);\n+\trc = sso_lf_alloc(&sso->dev, SSO_LF_TYPE_HWS, nb_hws, NULL);\n \tif (rc < 0) {\n \t\tplt_err(\"Unable to alloc SSO HWS LFs\");\n \t\tgoto hws_alloc_fail;\n \t}\n \n-\trc = sso_lf_alloc(roc_sso, SSO_LF_TYPE_HWGRP, nb_hwgrp,\n+\trc = sso_lf_alloc(&sso->dev, SSO_LF_TYPE_HWGRP, nb_hwgrp,\n \t\t\t (void **)&rsp_hwgrp);\n \tif (rc < 0) {\n \t\tplt_err(\"Unable to alloc SSO HWGRP Lfs\");\n@@ -503,9 +517,9 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp)\n \n \treturn 0;\n sso_msix_fail:\n-\tsso_lf_free(roc_sso, SSO_LF_TYPE_HWGRP, nb_hwgrp);\n+\tsso_lf_free(&sso->dev, SSO_LF_TYPE_HWGRP, nb_hwgrp);\n hwgrp_alloc_fail:\n-\tsso_lf_free(roc_sso, SSO_LF_TYPE_HWS, nb_hws);\n+\tsso_lf_free(&sso->dev, SSO_LF_TYPE_HWS, nb_hws);\n hws_alloc_fail:\n \tsso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWGRP);\n hwgrp_atch_fail:\n@@ -523,8 +537,8 @@ roc_sso_rsrc_fini(struct roc_sso *roc_sso)\n \n \tsso_unregister_irqs_priv(roc_sso, &sso->pci_dev->intr_handle,\n \t\t\t\t roc_sso->nb_hws, roc_sso->nb_hwgrp);\n-\tsso_lf_free(roc_sso, SSO_LF_TYPE_HWS, roc_sso->nb_hws);\n-\tsso_lf_free(roc_sso, SSO_LF_TYPE_HWGRP, roc_sso->nb_hwgrp);\n+\tsso_lf_free(&sso->dev, SSO_LF_TYPE_HWS, roc_sso->nb_hws);\n+\tsso_lf_free(&sso->dev, SSO_LF_TYPE_HWGRP, roc_sso->nb_hwgrp);\n \n \tsso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWS);\n \tsso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWGRP);\ndiff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h\nindex 5361d4f..8dffa3f 100644\n--- a/drivers/common/cnxk/roc_sso_priv.h\n+++ b/drivers/common/cnxk/roc_sso_priv.h\n@@ -39,6 +39,15 @@ roc_sso_to_sso_priv(struct roc_sso *roc_sso)\n \treturn (struct sso *)&roc_sso->reserved[0];\n }\n \n+/* SSO LF ops */\n+int sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf,\n+\t\t void **rsp);\n+int sso_lf_free(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf);\n+void sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp,\n+\t\t\t uint16_t hwgrp[], uint16_t n, uint16_t enable);\n+int sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps);\n+int sso_hwgrp_release_xaq(struct dev *dev, uint16_t hwgrps);\n+\n /* SSO IRQ */\n int sso_register_irqs_priv(struct roc_sso *roc_sso,\n \t\t\t struct plt_intr_handle *handle, uint16_t nb_hws,\n", "prefixes": [ "v3", "03/28" ] }