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GET /api/patches/100158/?format=api
{ "id": 100158, "url": "https://patches.dpdk.org/api/patches/100158/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210930170113.29030-28-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210930170113.29030-28-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210930170113.29030-28-ndabilpuram@marvell.com", "date": "2021-09-30T17:01:12", "name": "[v2,27/28] net/cnxk: support configuring channel mask via devargs", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "b2bf43816be6d60ebda3847e2e22b4808af5e4aa", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210930170113.29030-28-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 19307, "url": "https://patches.dpdk.org/api/series/19307/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19307", "date": "2021-09-30T17:00:48", "name": "net/cnxk: support for inline ipsec", "version": 2, "mbox": "https://patches.dpdk.org/series/19307/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/100158/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/100158/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F3E5BA0C43;\n\tThu, 30 Sep 2021 19:04:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A33B341143;\n\tThu, 30 Sep 2021 19:03:40 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id CBAD44111D\n for <dev@dpdk.org>; Thu, 30 Sep 2021 19:02:39 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18UF7lC6018456\n for <dev@dpdk.org>; Thu, 30 Sep 2021 10:02:39 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 3bd3g3ba1x-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 30 Sep 2021 10:02:38 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 30 Sep 2021 10:02:36 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 30 Sep 2021 10:02:36 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 1DAEA3F7068;\n Thu, 30 Sep 2021 10:02:33 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=W4lZ7WXvFbVMKfzr3Oi2pvmU5pYhiF8i6TnL4pxnfm4=;\n b=MugwuQRa/hEo5mObIdgOw3RsYmnVlpb9rMFHb5iP7WnSgW7QrCr4XmzPruxRP80tE64y\n tZqki9PacEoUA9lcrsDI45DY6zA9trWdMSVLkJeSc5pEFe2qI8eqkkP5ErpRBK89u7gQ\n 2UO+PdOy+N0tuCuaKx63uUJsS9tn/3WB1EeCUStKuaAxBI8wgtQiwNuhwh2RGuWNZOt9\n q3R8YizbYJjgqLVdfrU2Xh9zFsVfeAruobKFKXd+QSBoq6ZZlUWfbbJgJfkK4hOs9aa2\n rXGj0U/Ibayc0yo/owzy9STsDHrEsZ+CwYKj9yPr/3ARMhwa8E2AiECPNiVx78TNZi7/ cQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Satheesh Paul <psatheesh@marvell.com>", "Date": "Thu, 30 Sep 2021 22:31:12 +0530", "Message-ID": "<20210930170113.29030-28-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210930170113.29030-1-ndabilpuram@marvell.com>", "References": "<20210902021505.17607-1-ndabilpuram@marvell.com>\n <20210930170113.29030-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "oSpeGyB_TY2Qu0P0UTfLFcHPbE95EDE0", "X-Proofpoint-ORIG-GUID": "oSpeGyB_TY2Qu0P0UTfLFcHPbE95EDE0", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-30_06,2021-09-30_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH v2 27/28] net/cnxk: support configuring channel\n mask via devargs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Satheesh Paul <psatheesh@marvell.com>\n\nThis patch adds support to configure channel mask which will\nbe used by rte flow when adding flow rules with inline IPsec\naction.\n\nSigned-off-by: Satheesh Paul <psatheesh@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 20 +++++++++++++++++++\n drivers/net/cnxk/cnxk_ethdev_sec.c | 39 +++++++++++++++++++++++++++++++++++++-\n 2 files changed, 58 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex b542437..dd955d3 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -255,6 +255,26 @@ Runtime Config Options\n With the above configuration, inbound encrypted traffic from both the ports\n is received by ipsec inline device.\n \n+- ``Inline IPsec device channel and mask`` (default ``none``)\n+\n+ Set channel and channel mask configuration for the inline IPSec device. This\n+ will be used when creating flow rules with RTE_FLOW_ACTION_TYPE_SECURITY\n+ action.\n+\n+ By default, RTE Flow API sets the channel number of the port on which the\n+ rule is created in the MCAM entry and matches it exactly. This behaviour can\n+ be modified using the ``inl_cpt_channel`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -a 0002:1d:00.0,inl_cpt_channel=0x100/0xf00\n+\n+ With the above configuration, RTE Flow rules API will set the channel\n+ and channel mask as 0x100 and 0xF00 in the MCAM entries of the flow rules\n+ created with RTE_FLOW_ACTION_TYPE_SECURITY action. Since channel number is\n+ set with this custom mask, inbound encrypted traffic from all ports with\n+ matching channel number pattern will be directed to the inline IPSec device.\n+\n .. note::\n \n Above devarg parameters are configurable per device, user needs to pass the\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c\nindex c76e230..ae3e49c 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_sec.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c\n@@ -6,6 +6,13 @@\n \n #define CNXK_NIX_INL_SELFTEST\t \"selftest\"\n #define CNXK_NIX_INL_IPSEC_IN_MAX_SPI \"ipsec_in_max_spi\"\n+#define CNXK_INL_CPT_CHANNEL\t \"inl_cpt_channel\"\n+\n+struct inl_cpt_channel {\n+\tbool is_multi_channel;\n+\tuint16_t channel;\n+\tuint16_t mask;\n+};\n \n #define CNXK_NIX_INL_DEV_NAME RTE_STR(cnxk_nix_inl_dev_)\n #define CNXK_NIX_INL_DEV_NAME_LEN \\\n@@ -137,13 +144,37 @@ parse_selftest(const char *key, const char *value, void *extra_args)\n }\n \n static int\n+parse_inl_cpt_channel(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint16_t chan = 0, mask = 0;\n+\tchar *next = 0;\n+\n+\t/* next will point to the separator '/' */\n+\tchan = strtol(value, &next, 16);\n+\tmask = strtol(++next, 0, 16);\n+\n+\tif (chan > GENMASK(12, 0) || mask > GENMASK(12, 0))\n+\t\treturn -EINVAL;\n+\n+\t((struct inl_cpt_channel *)extra_args)->channel = chan;\n+\t((struct inl_cpt_channel *)extra_args)->mask = mask;\n+\t((struct inl_cpt_channel *)extra_args)->is_multi_channel = true;\n+\n+\treturn 0;\n+}\n+\n+static int\n nix_inl_parse_devargs(struct rte_devargs *devargs,\n \t\t struct roc_nix_inl_dev *inl_dev)\n {\n \tuint32_t ipsec_in_max_spi = BIT(8) - 1;\n+\tstruct inl_cpt_channel cpt_channel;\n \tstruct rte_kvargs *kvlist;\n \tuint8_t selftest = 0;\n \n+\tmemset(&cpt_channel, 0, sizeof(cpt_channel));\n+\n \tif (devargs == NULL)\n \t\tgoto null_devargs;\n \n@@ -155,11 +186,16 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,\n \t\t\t &selftest);\n \trte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MAX_SPI,\n \t\t\t &parse_ipsec_in_max_spi, &ipsec_in_max_spi);\n+\trte_kvargs_process(kvlist, CNXK_INL_CPT_CHANNEL, &parse_inl_cpt_channel,\n+\t\t\t &cpt_channel);\n \trte_kvargs_free(kvlist);\n \n null_devargs:\n \tinl_dev->ipsec_in_max_spi = ipsec_in_max_spi;\n \tinl_dev->selftest = selftest;\n+\tinl_dev->channel = cpt_channel.channel;\n+\tinl_dev->chan_mask = cpt_channel.mask;\n+\tinl_dev->is_multi_channel = cpt_channel.is_multi_channel;\n \treturn 0;\n exit:\n \treturn -EINVAL;\n@@ -275,4 +311,5 @@ RTE_PMD_REGISTER_KMOD_DEP(cnxk_nix_inl, \"vfio-pci\");\n \n RTE_PMD_REGISTER_PARAM_STRING(cnxk_nix_inl,\n \t\t\t CNXK_NIX_INL_SELFTEST \"=1\"\n-\t\t\t CNXK_NIX_INL_IPSEC_IN_MAX_SPI \"=<1-65535>\");\n+\t\t\t CNXK_NIX_INL_IPSEC_IN_MAX_SPI \"=<1-65535>\"\n+\t\t\t CNXK_INL_CPT_CHANNEL \"=<1-4095>/<1-4095>\");\n", "prefixes": [ "v2", "27/28" ] }