From patchwork Wed Apr 1 14:20:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67586 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C396CA057B; Wed, 1 Apr 2020 16:21:46 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 25BEF1BE9B; Wed, 1 Apr 2020 16:21:41 +0200 (CEST) Received: from mail-lj1-f194.google.com (mail-lj1-f194.google.com [209.85.208.194]) by dpdk.org (Postfix) with ESMTP id 25CBF3B5 for ; Wed, 1 Apr 2020 16:21:39 +0200 (CEST) Received: by mail-lj1-f194.google.com with SMTP id n17so25945640lji.8 for ; Wed, 01 Apr 2020 07:21:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m6OL7pgoqyLwVGSBretiCVE6yK1LNicxN0enE1mBvwY=; b=jZgHJo7n1gUTw+uY21VOmQrK+DPZXr8lhgP6i2EZjRM51/x05jQHxEeI5SkmtcAk3t Z5xuSqAWig2j7IUubmbm25VmyEFJVsUw/2lT1QVvG5kDxH0W9ruxF6NepKqjixmCBv6H r3rncJ2za6D6cENMKmRcHXCHfG2EeGaeu4XoCzPS3Jh8ol/VRx5y2KStayVmRd8WIAIY hpWc1PtU3LELqVSf1oGBRZonYIyzmErV17gi9hPqJ7GmOCcToXcf4xOk5YIVFQ93P3lX 0ORxpzFhmIX1nk8RBAx1u5YFg2JmZvDRwVVrATdVekzaYzVAatWIVReGiMenBmzUPsZh 6rEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m6OL7pgoqyLwVGSBretiCVE6yK1LNicxN0enE1mBvwY=; b=O25WHuVcuTkiGbyQ4eEJ3WEKkTWntHMlj5BOnh6TssrS7tGiSwslizadEEDNoHgEZz oqtFhqSBcAcCk7ODTOfGbU6K3VMeAp+n8qhcEb0qMVvovo185ZosxWDcPusrskI4gW1b PZGO6WNn+WnO95U9tnhGg7ha/E+g4y9PCL1espEpqmT4LrXlDAVxxhj3FKDPYv+R3JVt 5gNET1Xd7pVjOMjU+uzrzUE8dRh8txnPD6n5ILL03dlODd9js1tM4IWosfOJaBwGLJOs hEMYIkkKb77yoOnO9wrZhTqnN710T4iD16e+ILT8jg9ARsC8WeWL6PrydA1yii9QtFSE 86bg== X-Gm-Message-State: AGi0PuY0HrMmOA4j3lyLDTYe65srB2wlcKhWGRqir3XP5g+pp+fzoS4G KaZk7h3t1tP5YiQdK0Jt0ct4uF1TTBc= X-Google-Smtp-Source: APiQypK6xCHa4FsbLJ6TGeiXYmQBt67MHOHEySp4QLwuFQvwS2f3RJzC2hh7eEsDlePgZ9TNlDawnw== X-Received: by 2002:a2e:a16d:: with SMTP id u13mr12957548ljl.140.1585750898503; Wed, 01 Apr 2020 07:21:38 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:37 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:20:59 +0200 Message-Id: <20200401142127.13715-2-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 01/29] net/ena: check if size of buffer is at least 1400B X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Some of the ENA devices can't handle buffers which are smaller than a 1400B. Because of this limitation, size of the buffer is being checked and limited during the Rx queue setup. If it's below the allowed value, PMD won't finish it's configuration successfully.. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- v2: * Remove debug printout * Change the way of acquiring mempool size drivers/net/ena/ena_ethdev.c | 10 ++++++++++ drivers/net/ena/ena_ethdev.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 665afee4f0..292526466c 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -1282,6 +1282,7 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, { struct ena_adapter *adapter = dev->data->dev_private; struct ena_ring *rxq = NULL; + size_t buffer_size; int i; rxq = &adapter->rx_ring[queue_idx]; @@ -1309,6 +1310,15 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, return -EINVAL; } + /* ENA isn't supporting buffers smaller than 1400 bytes */ + buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; + if (buffer_size < ENA_RX_BUF_MIN_SIZE) { + PMD_DRV_LOG(ERR, + "Unsupported size of RX buffer: %zu (min size: %d)\n", + buffer_size, ENA_RX_BUF_MIN_SIZE); + return -EINVAL; + } + rxq->port_id = dev->data->port_id; rxq->next_to_clean = 0; rxq->next_to_use = 0; diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index af5eeea280..c1457defeb 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -20,6 +20,7 @@ #define ENA_MIN_FRAME_LEN 64 #define ENA_NAME_MAX_LEN 20 #define ENA_PKT_MAX_BUFS 17 +#define ENA_RX_BUF_MIN_SIZE 1400 #define ENA_MIN_MTU 128 From patchwork Wed Apr 1 14:21:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67587 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C9877A057B; Wed, 1 Apr 2020 16:21:57 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8D9AD1BEB0; Wed, 1 Apr 2020 16:21:42 +0200 (CEST) Received: from mail-lj1-f194.google.com (mail-lj1-f194.google.com [209.85.208.194]) by dpdk.org (Postfix) with ESMTP id 79D461BE91 for ; Wed, 1 Apr 2020 16:21:40 +0200 (CEST) Received: by mail-lj1-f194.google.com with SMTP id t17so25991312ljc.12 for ; Wed, 01 Apr 2020 07:21:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ml9WG5T39h/X9RwlD+wafkPNAZJw+p0Y2bxqSiZewx8=; b=rJzYfHfQAw8gi7JT/ConxqsmYJBNqgJdwT3EYu/CaJRjW1ENqcTGN7fsJZRY/ZK+29 FpKs7YdBnjrxh4dZJCymBdd9EDOokuG0K0IhrLp/+sRW20C7A/eUR+GmwO8kHBCHW5mC i+EPr6wJf9Dw2SMz20HUppVF8wIamlhMPtMxw37RLzDKFBxjVUA+To4jUeUBApE62Vgu GJzsCHU2RJJpq3kpLVDwQ+FvmS+MsO/xY6X/G+qr6U1z+4k0e35QYUFcIuFVaWMEfNbl FEGatdxheU8PL0OQPJeHgWcSBOHinz0UW/Zo3oeGP16lg3osOP965rvAQq4w4/RMZt3S 6+Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ml9WG5T39h/X9RwlD+wafkPNAZJw+p0Y2bxqSiZewx8=; b=is53xvfp03doKsT1ViL5dfbugnrQm93VT0wqCA2MtmminG0BP0j9NGUcKRaa2gM1TA ykfIN8DAgKRm0O3weVJm6kAndRGtwjsZXQsO7VWl0h/IChPOh0IClS7v1IyuafRL0MIb n5iFLUmSTyajhkXqa0KSZ90XfXXu1jheClsbuWuvehNsVjIstO4JhzxXxaU+jEtvP8av rHpNtnsPR9TYwdZtNMYgm4nmKk+kx8PqKIeZtZTC8YCUjnB8MFG4Brups/ZSy0TYsel8 yxkH0wG8JyPjlgMGFTNvsOF0Z21xOoqGfoKfxBa8BEoo0R+a6vndhl9QsVEhoKdAU8nS l3Jg== X-Gm-Message-State: AGi0PubPoHK9kFNuNjNM+tLttLK2ah0ELXzgZxubQ9+0+/7vADd7oZLa 7ZtAwC1A7LHPtJvwKRFj6aMG5iEqXfM= X-Google-Smtp-Source: APiQypI8ZbHUms4IxV2Z13RujQPaVRl2HEX3/DHZdsRNwlC+22DZ7SduEI8DVbfS1gXhYobY6+7/RQ== X-Received: by 2002:a2e:8e2a:: with SMTP id r10mr13123189ljk.276.1585750899786; Wed, 01 Apr 2020 07:21:39 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:39 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, stable@dpdk.org, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:00 +0200 Message-Id: <20200401142127.13715-3-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 02/29] net/ena/base: make allocation macros thread-safe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Igor Chauskin Memory allocation region id could possibly be non-unique due to non-atomic increment, causing allocation failure. Fixes: 9ba7981ec992 ("ena: add communication layer for DPDK") Cc: stable@dpdk.org Signed-off-by: Igor Chauskin Reviewed-by: Michal Krawczyk Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_plat_dpdk.h | 8 +++++--- drivers/net/ena/ena_ethdev.c | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index b611fb204b..192bbaefcf 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -180,7 +180,7 @@ do { \ * Each rte_memzone should have unique name. * To satisfy it, count number of allocations and add it to name. */ -extern uint32_t ena_alloc_cnt; +extern rte_atomic32_t ena_alloc_cnt; #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle) \ do { \ @@ -188,7 +188,8 @@ extern uint32_t ena_alloc_cnt; char z_name[RTE_MEMZONE_NAMESIZE]; \ ENA_TOUCH(dmadev); ENA_TOUCH(handle); \ snprintf(z_name, sizeof(z_name), \ - "ena_alloc_%d", ena_alloc_cnt++); \ + "ena_alloc_%d", \ + rte_atomic32_add_return(&ena_alloc_cnt, 1)); \ mz = rte_memzone_reserve(z_name, size, SOCKET_ID_ANY, \ RTE_MEMZONE_IOVA_CONTIG); \ handle = mz; \ @@ -213,7 +214,8 @@ extern uint32_t ena_alloc_cnt; char z_name[RTE_MEMZONE_NAMESIZE]; \ ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ snprintf(z_name, sizeof(z_name), \ - "ena_alloc_%d", ena_alloc_cnt++); \ + "ena_alloc_%d", \ + rte_atomic32_add_return(&ena_alloc_cnt, 1)); \ mz = rte_memzone_reserve(z_name, size, node, \ RTE_MEMZONE_IOVA_CONTIG); \ mem_handle = mz; \ diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 292526466c..854c724e32 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -89,7 +89,7 @@ struct ena_stats { * Each rte_memzone should have unique name. * To satisfy it, count number of allocation and add it to name. */ -uint32_t ena_alloc_cnt; +rte_atomic32_t ena_alloc_cnt; static const struct ena_stats ena_stats_global_strings[] = { ENA_STAT_GLOBAL_ENTRY(wd_expired), From patchwork Wed Apr 1 14:21:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67588 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7EBEBA057B; Wed, 1 Apr 2020 16:22:09 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1F12E1BEC0; Wed, 1 Apr 2020 16:21:44 +0200 (CEST) Received: from mail-lf1-f65.google.com (mail-lf1-f65.google.com [209.85.167.65]) by dpdk.org (Postfix) with ESMTP id D05B51BEB5 for ; Wed, 1 Apr 2020 16:21:42 +0200 (CEST) Received: by mail-lf1-f65.google.com with SMTP id w145so1450284lff.3 for ; Wed, 01 Apr 2020 07:21:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gTIPi4Ugjdgbn6lIzbN7KYyY2v2TxtQAFwVJtkB2Hh8=; b=lTR6E8iF1FZAAlTCoAF0f5mosGj9qw9GqAjYIhwq7MtHTgta62GTzCCYvPUR2AMfLH zDo9YSzETr81CjDJPZQmRWNY/seBmOE0ujmqParR2BlSEA6jX0NVMALgAhtbgL38tqFe LsTOmDYue3KmeGzyt0zZLj/bmTVBzVBflplKozwdwZBx65GdWEAoCRdEVdzsxv5+19wq //3Bbto6qU22n9xLEeYUupA1n4jJTNt7E24amVH8CrzzUkQlveGqZfG4u7dTSW/ZRtwu aj39UxqfG4TZSgpf3AYh0zUVhlJBojLpx94Ym6xgGIdIVjyKrIJZke0GbQYsTNfXm0vZ AzWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gTIPi4Ugjdgbn6lIzbN7KYyY2v2TxtQAFwVJtkB2Hh8=; b=smNrrJsmnZtwalRFeMQOrRO6JmAc5xbtqCuJn/YKa2N8DpC3Q7g768BK6lI98Ig+o7 BoPauG9Kkzf19I2L3JxfQCHrsSqbO2sCweBpF+lR5RQ+hd7PRfPY0ZB0HuGiAQy9yd7U Osuh+FrvroysTYmN6MDxufBpzV7WmwCkaDd6E4GJCgjdVzsrUFIU0onuY402oCgWn5FM 7GyQ45foVRjh9ChhUoec7kHjnwu64axtVpXWXTj+EI5e3JmF1wScp4Ri5uQvNKgrZCJL wZ+kQf+EV/zVfogqsHCpkDyAyLzTM/B2Wl4bu7KhiVSQ5SMEV3LANzOscIz+MWUFxKY1 Lc6g== X-Gm-Message-State: AGi0PuZOubEAON0sldWKpwl9chn9YvM7eG+hkAoHg9FsXxypgOfYK6t8 slc75z2E67w84tlcUAJrzvq+MVeFbhc= X-Google-Smtp-Source: APiQypKWgDAvmcW0jotpKZZ7/0DdGBI2qCSGnx62w419VhWLM2IylHl52vBc2QJfJ/KlFXXcrrq6bg== X-Received: by 2002:a05:6512:695:: with SMTP id t21mr3511260lfe.158.1585750901113; Wed, 01 Apr 2020 07:21:41 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:40 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, stable@dpdk.org, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:01 +0200 Message-Id: <20200401142127.13715-4-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 03/29] net/ena/base: prevent allocation of 0-sized memory X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Igor Chauskin rte_memzone_reserve() will reserve the biggest contiguous memzone available if received 0 as size param. Fixes: 9ba7981ec992 ("ena: add communication layer for DPDK") Cc: stable@dpdk.org Signed-off-by: Igor Chauskin Reviewed-by: Michal Krawczyk Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_plat_dpdk.h | 29 ++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 192bbaefcf..793ba8a957 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -184,15 +184,18 @@ extern rte_atomic32_t ena_alloc_cnt; #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle) \ do { \ - const struct rte_memzone *mz; \ - char z_name[RTE_MEMZONE_NAMESIZE]; \ + const struct rte_memzone *mz = NULL; \ ENA_TOUCH(dmadev); ENA_TOUCH(handle); \ - snprintf(z_name, sizeof(z_name), \ + if (size > 0) { \ + char z_name[RTE_MEMZONE_NAMESIZE]; \ + snprintf(z_name, sizeof(z_name), \ "ena_alloc_%d", \ rte_atomic32_add_return(&ena_alloc_cnt, 1)); \ - mz = rte_memzone_reserve(z_name, size, SOCKET_ID_ANY, \ - RTE_MEMZONE_IOVA_CONTIG); \ - handle = mz; \ + mz = rte_memzone_reserve(z_name, size, \ + SOCKET_ID_ANY, \ + RTE_MEMZONE_IOVA_CONTIG); \ + handle = mz; \ + } \ if (mz == NULL) { \ virt = NULL; \ phys = 0; \ @@ -210,15 +213,17 @@ extern rte_atomic32_t ena_alloc_cnt; #define ENA_MEM_ALLOC_COHERENT_NODE( \ dmadev, size, virt, phys, mem_handle, node, dev_node) \ do { \ - const struct rte_memzone *mz; \ - char z_name[RTE_MEMZONE_NAMESIZE]; \ + const struct rte_memzone *mz = NULL; \ ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ - snprintf(z_name, sizeof(z_name), \ + if (size > 0) { \ + char z_name[RTE_MEMZONE_NAMESIZE]; \ + snprintf(z_name, sizeof(z_name), \ "ena_alloc_%d", \ - rte_atomic32_add_return(&ena_alloc_cnt, 1)); \ - mz = rte_memzone_reserve(z_name, size, node, \ + rte_atomic32_add_return(&ena_alloc_cnt, 1)); \ + mz = rte_memzone_reserve(z_name, size, node, \ RTE_MEMZONE_IOVA_CONTIG); \ - mem_handle = mz; \ + mem_handle = mz; \ + } \ if (mz == NULL) { \ virt = NULL; \ phys = 0; \ From patchwork Wed Apr 1 14:21:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67589 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9B484A057B; Wed, 1 Apr 2020 16:22:19 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 682641BEB7; Wed, 1 Apr 2020 16:21:45 +0200 (CEST) Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) by dpdk.org (Postfix) with ESMTP id D43311BEB5 for ; Wed, 1 Apr 2020 16:21:43 +0200 (CEST) Received: by mail-lj1-f170.google.com with SMTP id i20so25941663ljn.6 for ; Wed, 01 Apr 2020 07:21:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q1Ky4ZcIZ3T0IYx41HIiIe87L5tdMft4QyvoUOQbrV4=; b=x8KFQWXQSUTxUcVz+SX4+Sy7Gmr4mVZ22ptJsiO+iK2bZQHW/acHP2rGCREkNpW4FA O0h0I+sB9t0yqz2RbSS8wrmQHhU7hWa5IdqmFBAcY2d/FbCKOV0YSYQS0ZEO7Of8Jrm/ N8tuWcyguK0F3As8vzMy2n7Hx7I4cE5J5VWBTF0sXf4/8cA3SGXDB+zzSgd7qkOQfRza 4Fyhz7MP1H6fcJJRN7Hrdpz7FoCTco/oFlhxn/JHF7FENMwViTaOrqb8cX+9PAoKlalG TpjPYCT1NgihAsKoyxywHnv1Lv5dDYddWEtbJ2yQL2Le/vMy70bmkr5PwD11SgcEkl8h nX9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q1Ky4ZcIZ3T0IYx41HIiIe87L5tdMft4QyvoUOQbrV4=; b=JyDMO/WJOIWdUAkc9VBXTT4W4zBGy/tNX4HskaABTrxLAKzpruyP3JmNAtk4y0jLy2 4pDf19GwMKQrSOC6wGR33YzpuWXFPhkxmbtKbpkIHKSnpV5B27RLbqgyTHyua+FqNnMA DMKhuPWCjGBKU5X7cSpbTPqUP9KiiOLD9hkqpcXT0Fr07Vzrgylw7ly1vE693Tg7Lc/u CGCRDQDUize4W0AVeI7r64wZmfeXlnha7ohnoKiJOQncL41+DxJzAbj4ROpAH+WB2Beb CYKTWlM7L5YBZlIde76EZjQvTY6FXlG+KU1hVwA/PC54+ovtaIEVTcvGoOuyvvyn3WaY zPwA== X-Gm-Message-State: AGi0PuahaDCxC6lkXflRgGS2AL4zmPaJF7obt5+Gn/RYfJDjxGuP2PB7 79zdY72bsg6e55XQKtPLo3E0UlP37t8= X-Google-Smtp-Source: APiQypJG278P5/k2WIpPs6X0gJqidtldrVLZLAmLCSNiy9UviXfDpy9tOui/TE7HHgucvvUdQo0t4A== X-Received: by 2002:a2e:7807:: with SMTP id t7mr13181830ljc.203.1585750902613; Wed, 01 Apr 2020 07:21:42 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:41 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:02 +0200 Message-Id: <20200401142127.13715-5-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 04/29] net/ena/base: set default hash key X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The RSS hash key was present in the device, but it wasn't exposed to the user. The other key still cannot be set, but now it can be accessed if one needs to do that. By default, the random hash key is used and it is generated only once when requested for the first time. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- v2: * Remove variable declaration inside the for loop * Remove unlikely in condition check drivers/net/ena/base/ena_com.c | 103 ++++++++++++++------------- drivers/net/ena/base/ena_com.h | 30 ++++++-- drivers/net/ena/base/ena_plat_dpdk.h | 6 ++ drivers/net/ena/ena_ethdev.c | 17 +++++ 4 files changed, 102 insertions(+), 54 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 17b51b5a11..a5753997ed 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -1032,6 +1032,24 @@ static int ena_com_get_feature(struct ena_com_dev *ena_dev, feature_ver); } +int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev) +{ + return ena_dev->rss.hash_func; +} + +static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev) +{ + struct ena_admin_feature_rss_flow_hash_control *hash_key = + (ena_dev->rss).hash_key; + + ENA_RSS_FILL_KEY(&hash_key->key, sizeof(hash_key->key)); + /* The key is stored in the device in uint32_t array + * as well as the API requires the key to be passed in this + * format. Thus the size of our array should be divided by 4 + */ + hash_key->keys_num = sizeof(hash_key->key) / sizeof(uint32_t); +} + static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) { struct ena_rss *rss = &ena_dev->rss; @@ -1266,30 +1284,6 @@ static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) return 0; } -static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev) -{ - u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 }; - struct ena_rss *rss = &ena_dev->rss; - u8 idx; - u16 i; - - for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++) - dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i; - - for (i = 0; i < 1 << rss->tbl_log_size; i++) { - if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES) - return ENA_COM_INVAL; - idx = (u8)rss->rss_ind_tbl[i].cq_idx; - - if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES) - return ENA_COM_INVAL; - - rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx]; - } - - return 0; -} - static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev) { size_t size; @@ -2381,12 +2375,14 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, enum ena_admin_hash_functions func, const u8 *key, u16 key_len, u32 init_val) { - struct ena_rss *rss = &ena_dev->rss; + struct ena_admin_feature_rss_flow_hash_control *hash_key; struct ena_admin_get_feat_resp get_resp; - struct ena_admin_feature_rss_flow_hash_control *hash_key = - rss->hash_key; + enum ena_admin_hash_functions old_func; + struct ena_rss *rss = &ena_dev->rss; int rc; + hash_key = rss->hash_key; + /* Make sure size is a mult of DWs */ if (unlikely(key_len & 0x3)) return ENA_COM_INVAL; @@ -2398,22 +2394,23 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, if (unlikely(rc)) return rc; - if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) { + if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) { ena_trc_err("Flow hash function %d isn't supported\n", func); return ENA_COM_UNSUPPORTED; } switch (func) { case ENA_ADMIN_TOEPLITZ: - if (key_len > sizeof(hash_key->key)) { - ena_trc_err("key len (%hu) is bigger than the max supported (%zu)\n", - key_len, sizeof(hash_key->key)); - return ENA_COM_INVAL; + if (key) { + if (key_len != sizeof(hash_key->key)) { + ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n", + key_len, sizeof(hash_key->key)); + return ENA_COM_INVAL; + } + memcpy(hash_key->key, key, key_len); + rss->hash_init_val = init_val; + hash_key->keys_num = key_len >> 2; } - - memcpy(hash_key->key, key, key_len); - rss->hash_init_val = init_val; - hash_key->keys_num = key_len >> 2; break; case ENA_ADMIN_CRC32: rss->hash_init_val = init_val; @@ -2423,26 +2420,27 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, return ENA_COM_INVAL; } + old_func = rss->hash_func; rss->hash_func = func; rc = ena_com_set_hash_function(ena_dev); /* Restore the old function */ if (unlikely(rc)) - ena_com_get_hash_function(ena_dev, NULL, NULL); + rss->hash_func = old_func; return rc; } int ena_com_get_hash_function(struct ena_com_dev *ena_dev, - enum ena_admin_hash_functions *func, - u8 *key) + enum ena_admin_hash_functions *func) { struct ena_rss *rss = &ena_dev->rss; struct ena_admin_get_feat_resp get_resp; - struct ena_admin_feature_rss_flow_hash_control *hash_key = - rss->hash_key; int rc; + if (unlikely(!func)) + return ENA_COM_INVAL; + rc = ena_com_get_feature_ex(ena_dev, &get_resp, ENA_ADMIN_RSS_HASH_FUNCTION, rss->hash_key_dma_addr, @@ -2450,9 +2448,20 @@ int ena_com_get_hash_function(struct ena_com_dev *ena_dev, if (unlikely(rc)) return rc; - rss->hash_func = get_resp.u.flow_hash_func.selected_func; - if (func) - *func = rss->hash_func; + /* ENA_FFS returns 1 in case the lsb is set */ + rss->hash_func = ENA_FFS(get_resp.u.flow_hash_func.selected_func); + if (rss->hash_func) + rss->hash_func--; + + *func = rss->hash_func; + + return 0; +} + +int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key) +{ + struct ena_admin_feature_rss_flow_hash_control *hash_key = + ena_dev->rss.hash_key; if (key) memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2); @@ -2714,10 +2723,6 @@ int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) if (!ind_tbl) return 0; - rc = ena_com_ind_tbl_convert_from_device(ena_dev); - if (unlikely(rc)) - return rc; - for (i = 0; i < (1 << rss->tbl_log_size); i++) ind_tbl[i] = rss->host_rss_ind_tbl[i]; @@ -2738,6 +2743,8 @@ int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size) if (unlikely(rc)) goto err_hash_key; + ena_com_hash_key_fill_default_key(ena_dev); + rc = ena_com_hash_ctrl_init(ena_dev); if (unlikely(rc)) goto err_hash_ctrl; diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index f2ef26c91b..dc7e0d3930 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -53,6 +53,7 @@ #define ENA_INTR_DELAY_NEW_VALUE_WEIGHT 4 #define ENA_INTR_MODER_LEVEL_STRIDE 1 #define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED 0xFFFFFF +#define ENA_HASH_KEY_SIZE 40 #define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF @@ -693,6 +694,14 @@ int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size); */ void ena_com_rss_destroy(struct ena_com_dev *ena_dev); +/* ena_com_get_current_hash_function - Get RSS hash function + * @ena_dev: ENA communication layer struct + * + * Return the current hash function. + * @return: 0 or one of the ena_admin_hash_functions values. + */ +int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev); + /* ena_com_fill_hash_function - Fill RSS hash function * @ena_dev: ENA communication layer struct * @func: The hash function (Toeplitz or crc) @@ -724,13 +733,11 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, */ int ena_com_set_hash_function(struct ena_com_dev *ena_dev); -/* ena_com_get_hash_function - Retrieve the hash function and the hash key - * from the device. +/* ena_com_get_hash_function - Retrieve the hash function from the device. * @ena_dev: ENA communication layer struct * @func: hash function - * @key: hash key * - * Retrieve the hash function and the hash key from the device. + * Retrieve the hash function from the device. * * @note: If the caller called ena_com_fill_hash_function but didn't flash * it to the device, the new configuration will be lost. @@ -738,9 +745,20 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev); * @return: 0 on Success and negative value otherwise. */ int ena_com_get_hash_function(struct ena_com_dev *ena_dev, - enum ena_admin_hash_functions *func, - u8 *key); + enum ena_admin_hash_functions *func); +/* ena_com_get_hash_key - Retrieve the hash key + * @ena_dev: ENA communication layer struct + * @key: hash key + * + * Retrieve the hash key. + * + * @note: If the caller called ena_com_fill_hash_key but didn't flash + * it to the device, the new configuration will be lost. + * + * @return: 0 on Success and negative value otherwise. + */ +int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key); /* ena_com_fill_hash_ctrl - Fill RSS hash control * @ena_dev: ENA communication layer struct. * @proto: The protocol to configure. diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 793ba8a957..24a831f4d4 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -301,6 +301,12 @@ extern rte_atomic32_t ena_alloc_cnt; #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) +#define ENA_FFS(x) ffs(x) + +void ena_rss_key_fill(void *key, size_t size); + +#define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size) + #include "ena_includes.h" #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */ diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 854c724e32..21c25b21b1 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -256,6 +256,23 @@ static const struct eth_dev_ops ena_dev_ops = { .reta_query = ena_rss_reta_query, }; +void ena_rss_key_fill(void *key, size_t size) +{ + static bool key_generated; + static uint8_t default_key[ENA_HASH_KEY_SIZE]; + size_t i; + + RTE_ASSERT(size <= ENA_HASH_KEY_SIZE); + + if (!key_generated) { + for (i = 0; i < ENA_HASH_KEY_SIZE; ++i) + default_key[i] = rte_rand() & 0xff; + key_generated = true; + } + + rte_memcpy(key, default_key, size); +} + static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, struct ena_com_rx_ctx *ena_rx_ctx) { From patchwork Wed Apr 1 14:21:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67590 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DCA37A057B; Wed, 1 Apr 2020 16:22:32 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1731D1BED9; Wed, 1 Apr 2020 16:21:47 +0200 (CEST) Received: from mail-lf1-f67.google.com (mail-lf1-f67.google.com [209.85.167.67]) by dpdk.org (Postfix) with ESMTP id 3F7961BEB5 for ; Wed, 1 Apr 2020 16:21:45 +0200 (CEST) Received: by mail-lf1-f67.google.com with SMTP id n20so20577512lfl.10 for ; Wed, 01 Apr 2020 07:21:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L4rGZkls6z+oK9UingF9l/t0LrvKB3RiUWnKcuTIYDE=; b=GhtRu/bZz9OWB3cBf+/zjxtc6ZXf/D89anihiV//pXZiHNlQXkpXYbYS1M9sqQXOiW ZiQRJbNwd1ykfGFT7lQXpDJn1Zj9bgieWDYh2HfzNzv+wkcr15Lunku0suBv1+62qB86 7a0WXZxvRBHF0momoIkrQ41TzA6Hcgc2/VowMsAMdt9HeGJ4cStZUYywuVR51TcD/rzf t+4Dll96MT/YGQEIkHEgUp+9eWvdpHCQxQYWLYCiL+4EWyD7BO3LggNsJaIOGtpg0cWo /3l3D31ZB4dIvSa4OBhbiIKCD4a3hgOA/SvJQpDeM0XDqgGBktKH+5MDRGA272z0eLiA Z18A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L4rGZkls6z+oK9UingF9l/t0LrvKB3RiUWnKcuTIYDE=; b=nehBqDQWVKhUFEOJFvRuLwGdLCioLok5qJHaQxPvR7Akw7dIfX42ZoFpkjrWDX4Mly DJdM1flyQd5PY0jrrD2szn9T2P3saGw8Nq1IDjvhL21OmkKsxXZ4IonkZsH0xkD+VmBw sDeBxUt6b3YZzFz8z/njTM9sOV8WI6Ph9Dy6j2Q+5VTgZBdNlt4uc7oVR7msLZA+NUJP iaduJ63uEzkKPyfW8CVyKAxq1G18YAOx4jdMfjNLPOgy8KOUdGF1Be7kZT/b9GSHBUM3 462KWp/klues/kxR4vby12fEu9+2DWxhp1c7qYX/hRjlSgQsH3J/4iSZv47KGjLZEp8e mOsg== X-Gm-Message-State: AGi0PuarEcrdbNHYcmDj1d8L7muC0JasUo7JdtgYqjeTTPpECnN9uz0k 03Zsxle8hBfW7PNQAu0xjkj38eEW/mA= X-Google-Smtp-Source: APiQypIOGG/GGPHBW/imQ3hjBqgGG2pFf4q94bKgiCb+8bKgnDTE6Ev/nphBRSqeNRAFc0PxdsvgwA== X-Received: by 2002:a19:700a:: with SMTP id h10mr15553659lfc.184.1585750903942; Wed, 01 Apr 2020 07:21:43 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:43 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:03 +0200 Message-Id: <20200401142127.13715-6-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 05/29] net/ena/base: rework interrupt moderation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This feature allows for adaptive interrupt moderation. It's not used by the DPDK PMD, but is a part of the newest HAL version. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.c | 171 +++++---------------------- drivers/net/ena/base/ena_com.h | 154 ++---------------------- drivers/net/ena/base/ena_plat_dpdk.h | 3 +- 3 files changed, 42 insertions(+), 286 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index a5753997ed..cb2114acb7 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -1284,39 +1284,29 @@ static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) return 0; } -static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev) -{ - size_t size; - - size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS; - - ena_dev->intr_moder_tbl = ENA_MEM_ALLOC(ena_dev->dmadev, size); - if (!ena_dev->intr_moder_tbl) - return ENA_COM_NO_MEM; - - ena_com_config_default_interrupt_moderation_table(ena_dev); - - return 0; -} - static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, u16 intr_delay_resolution) { - struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; - unsigned int i; + u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution; - if (!intr_delay_resolution) { + if (unlikely(!intr_delay_resolution)) { ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); - intr_delay_resolution = 1; + intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION; } - ena_dev->intr_delay_resolution = intr_delay_resolution; /* update Rx */ - for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++) - intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution; + ena_dev->intr_moder_rx_interval = + ena_dev->intr_moder_rx_interval * + prev_intr_delay_resolution / + intr_delay_resolution; /* update Tx */ - ena_dev->intr_moder_tx_interval /= intr_delay_resolution; + ena_dev->intr_moder_tx_interval = + ena_dev->intr_moder_tx_interval * + prev_intr_delay_resolution / + intr_delay_resolution; + + ena_dev->intr_delay_resolution = intr_delay_resolution; } /*****************************************************************************/ @@ -2892,44 +2882,35 @@ bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) ENA_ADMIN_INTERRUPT_MODERATION); } -int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, - u32 tx_coalesce_usecs) +static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs, + u32 intr_delay_resolution, + u32 *intr_moder_interval) { - if (!ena_dev->intr_delay_resolution) { + if (!intr_delay_resolution) { ena_trc_err("Illegal interrupt delay granularity value\n"); return ENA_COM_FAULT; } - ena_dev->intr_moder_tx_interval = tx_coalesce_usecs / - ena_dev->intr_delay_resolution; + *intr_moder_interval = coalesce_usecs / intr_delay_resolution; return 0; } -int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, - u32 rx_coalesce_usecs) -{ - if (!ena_dev->intr_delay_resolution) { - ena_trc_err("Illegal interrupt delay granularity value\n"); - return ENA_COM_FAULT; - } - /* We use LOWEST entry of moderation table for storing - * nonadaptive interrupt coalescing values - */ - ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval = - rx_coalesce_usecs / ena_dev->intr_delay_resolution; - - return 0; +int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, + u32 tx_coalesce_usecs) +{ + return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs, + ena_dev->intr_delay_resolution, + &ena_dev->intr_moder_tx_interval); } -void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev) +int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, + u32 rx_coalesce_usecs) { - if (ena_dev->intr_moder_tbl) - ENA_MEM_FREE(ena_dev->dmadev, - ena_dev->intr_moder_tbl, - (sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS)); - ena_dev->intr_moder_tbl = NULL; + return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs, + ena_dev->intr_delay_resolution, + &ena_dev->intr_moder_rx_interval); } int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) @@ -2956,10 +2937,6 @@ int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) return rc; } - rc = ena_com_init_interrupt_moderation_table(ena_dev); - if (rc) - goto err; - /* if moderation is supported by device we set adaptive moderation */ delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution; ena_com_update_intr_delay_resolution(ena_dev, delay_resolution); @@ -2968,52 +2945,6 @@ int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) ena_com_disable_adaptive_moderation(ena_dev); return 0; -err: - ena_com_destroy_interrupt_moderation(ena_dev); - return rc; -} - -void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev) -{ - struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; - - if (!intr_moder_tbl) - return; - - intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval = - ENA_INTR_LOWEST_USECS; - intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval = - ENA_INTR_LOWEST_PKTS; - intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval = - ENA_INTR_LOWEST_BYTES; - - intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval = - ENA_INTR_LOW_USECS; - intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval = - ENA_INTR_LOW_PKTS; - intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval = - ENA_INTR_LOW_BYTES; - - intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval = - ENA_INTR_MID_USECS; - intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval = - ENA_INTR_MID_PKTS; - intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval = - ENA_INTR_MID_BYTES; - - intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval = - ENA_INTR_HIGH_USECS; - intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval = - ENA_INTR_HIGH_PKTS; - intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval = - ENA_INTR_HIGH_BYTES; - - intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval = - ENA_INTR_HIGHEST_USECS; - intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval = - ENA_INTR_HIGHEST_PKTS; - intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval = - ENA_INTR_HIGHEST_BYTES; } unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev) @@ -3023,49 +2954,7 @@ unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev * unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev) { - struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; - - if (intr_moder_tbl) - return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval; - - return 0; -} - -void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev, - enum ena_intr_moder_level level, - struct ena_intr_moder_entry *entry) -{ - struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; - - if (level >= ENA_INTR_MAX_NUM_OF_LEVELS) - return; - - intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval; - if (ena_dev->intr_delay_resolution) - intr_moder_tbl[level].intr_moder_interval /= - ena_dev->intr_delay_resolution; - intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval; - - /* use hardcoded value until ethtool supports bytecount parameter */ - if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED) - intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval; -} - -void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev, - enum ena_intr_moder_level level, - struct ena_intr_moder_entry *entry) -{ - struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; - - if (level >= ENA_INTR_MAX_NUM_OF_LEVELS) - return; - - entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval; - if (ena_dev->intr_delay_resolution) - entry->intr_moder_interval *= ena_dev->intr_delay_resolution; - entry->pkts_per_interval = - intr_moder_tbl[level].pkts_per_interval; - entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval; + return ena_dev->intr_moder_rx_interval; } int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index dc7e0d3930..5935d024dd 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -27,47 +27,16 @@ /*****************************************************************************/ /* ENA adaptive interrupt moderation settings */ -#define ENA_INTR_LOWEST_USECS (0) -#define ENA_INTR_LOWEST_PKTS (3) -#define ENA_INTR_LOWEST_BYTES (2 * 1524) - -#define ENA_INTR_LOW_USECS (32) -#define ENA_INTR_LOW_PKTS (12) -#define ENA_INTR_LOW_BYTES (16 * 1024) - -#define ENA_INTR_MID_USECS (80) -#define ENA_INTR_MID_PKTS (48) -#define ENA_INTR_MID_BYTES (64 * 1024) - -#define ENA_INTR_HIGH_USECS (128) -#define ENA_INTR_HIGH_PKTS (96) -#define ENA_INTR_HIGH_BYTES (128 * 1024) - -#define ENA_INTR_HIGHEST_USECS (192) -#define ENA_INTR_HIGHEST_PKTS (128) -#define ENA_INTR_HIGHEST_BYTES (192 * 1024) - -#define ENA_INTR_INITIAL_TX_INTERVAL_USECS 196 -#define ENA_INTR_INITIAL_RX_INTERVAL_USECS 4 -#define ENA_INTR_DELAY_OLD_VALUE_WEIGHT 6 -#define ENA_INTR_DELAY_NEW_VALUE_WEIGHT 4 -#define ENA_INTR_MODER_LEVEL_STRIDE 1 -#define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED 0xFFFFFF +#define ENA_INTR_INITIAL_TX_INTERVAL_USECS ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT +#define ENA_INTR_INITIAL_RX_INTERVAL_USECS 0 +#define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1 + #define ENA_HASH_KEY_SIZE 40 #define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF #define ENA_FEATURE_MAX_QUEUE_EXT_VER 1 -enum ena_intr_moder_level { - ENA_INTR_MODER_LOWEST = 0, - ENA_INTR_MODER_LOW, - ENA_INTR_MODER_MID, - ENA_INTR_MODER_HIGH, - ENA_INTR_MODER_HIGHEST, - ENA_INTR_MAX_NUM_OF_LEVELS, -}; - struct ena_llq_configurations { enum ena_admin_llq_header_location llq_header_location; enum ena_admin_llq_ring_entry_size llq_ring_entry_size; @@ -76,12 +45,6 @@ struct ena_llq_configurations { u16 llq_ring_entry_size_value; }; -struct ena_intr_moder_entry { - unsigned int intr_moder_interval; - unsigned int pkts_per_interval; - unsigned int bytes_per_interval; -}; - enum queue_direction { ENA_COM_IO_QUEUE_DIRECTION_TX, ENA_COM_IO_QUEUE_DIRECTION_RX @@ -353,7 +316,13 @@ struct ena_com_dev { struct ena_host_attribute host_attr; bool adaptive_coalescing; u16 intr_delay_resolution; + + /* interrupt moderation intervals are in usec divided by + * intr_delay_resolution, which is supplied by the device. + */ u32 intr_moder_tx_interval; + u32 intr_moder_rx_interval; + struct ena_intr_moder_entry *intr_moder_tbl; struct ena_com_llq_info llq_info; @@ -938,11 +907,6 @@ int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, */ int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev); -/* ena_com_destroy_interrupt_moderation - Destroy interrupt moderation resources - * @ena_dev: ENA communication layer struct - */ -void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev); - /* ena_com_interrupt_moderation_supported - Return if interrupt moderation * capability is supported by the device. * @@ -950,12 +914,6 @@ void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev); */ bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev); -/* ena_com_config_default_interrupt_moderation_table - Restore the interrupt - * moderation table back to the default parameters. - * @ena_dev: ENA communication layer struct - */ -void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev); - /* ena_com_update_nonadaptive_moderation_interval_tx - Update the * non-adaptive interval in Tx direction. * @ena_dev: ENA communication layer struct @@ -992,29 +950,6 @@ unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev * */ unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev); -/* ena_com_init_intr_moderation_entry - Update a single entry in the interrupt - * moderation table. - * @ena_dev: ENA communication layer struct - * @level: Interrupt moderation table level - * @entry: Entry value - * - * Update a single entry in the interrupt moderation table. - */ -void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev, - enum ena_intr_moder_level level, - struct ena_intr_moder_entry *entry); - -/* ena_com_get_intr_moderation_entry - Init ena_intr_moder_entry. - * @ena_dev: ENA communication layer struct - * @level: Interrupt moderation table level - * @entry: Entry to fill. - * - * Initialize the entry according to the adaptive interrupt moderation table. - */ -void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev, - enum ena_intr_moder_level level, - struct ena_intr_moder_entry *entry); - /* ena_com_config_dev_mode - Configure the placement policy of the device. * @ena_dev: ENA communication layer struct * @llq_features: LLQ feature descriptor, retrieve via @@ -1040,75 +975,6 @@ static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_d ena_dev->adaptive_coalescing = false; } -/* ena_com_calculate_interrupt_delay - Calculate new interrupt delay - * @ena_dev: ENA communication layer struct - * @pkts: Number of packets since the last update - * @bytes: Number of bytes received since the last update. - * @smoothed_interval: Returned interval - * @moder_tbl_idx: Current table level as input update new level as return - * value. - */ -static inline void ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev, - unsigned int pkts, - unsigned int bytes, - unsigned int *smoothed_interval, - unsigned int *moder_tbl_idx) -{ - enum ena_intr_moder_level curr_moder_idx, new_moder_idx; - struct ena_intr_moder_entry *curr_moder_entry; - struct ena_intr_moder_entry *pred_moder_entry; - struct ena_intr_moder_entry *new_moder_entry; - struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; - unsigned int interval; - - /* We apply adaptive moderation on Rx path only. - * Tx uses static interrupt moderation. - */ - if (!pkts || !bytes) - /* Tx interrupt, or spurious interrupt, - * in both cases we just use same delay values - */ - return; - - curr_moder_idx = (enum ena_intr_moder_level)(*moder_tbl_idx); - if (unlikely(curr_moder_idx >= ENA_INTR_MAX_NUM_OF_LEVELS)) { - ena_trc_err("Wrong moderation index %u\n", curr_moder_idx); - return; - } - - curr_moder_entry = &intr_moder_tbl[curr_moder_idx]; - new_moder_idx = curr_moder_idx; - - if (curr_moder_idx == ENA_INTR_MODER_LOWEST) { - if ((pkts > curr_moder_entry->pkts_per_interval) || - (bytes > curr_moder_entry->bytes_per_interval)) - new_moder_idx = - (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE); - } else { - pred_moder_entry = &intr_moder_tbl[curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE]; - - if ((pkts <= pred_moder_entry->pkts_per_interval) || - (bytes <= pred_moder_entry->bytes_per_interval)) - new_moder_idx = - (enum ena_intr_moder_level)(curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE); - else if ((pkts > curr_moder_entry->pkts_per_interval) || - (bytes > curr_moder_entry->bytes_per_interval)) { - if (curr_moder_idx != ENA_INTR_MODER_HIGHEST) - new_moder_idx = - (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE); - } - } - new_moder_entry = &intr_moder_tbl[new_moder_idx]; - - interval = new_moder_entry->intr_moder_interval; - *smoothed_interval = ( - (interval * ENA_INTR_DELAY_NEW_VALUE_WEIGHT + - ENA_INTR_DELAY_OLD_VALUE_WEIGHT * (*smoothed_interval)) + 5) / - 10; - - *moder_tbl_idx = new_moder_idx; -} - /* ena_com_update_intr_reg - Prepare interrupt register * @intr_reg: interrupt register to update. * @rx_delay_interval: Rx interval in usecs diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 24a831f4d4..2989df8f7e 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -307,6 +307,7 @@ void ena_rss_key_fill(void *key, size_t size); #define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size) -#include "ena_includes.h" +#define ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT 0 +#include "ena_includes.h" #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */ From patchwork Wed Apr 1 14:21:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67591 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9A4CDA057B; Wed, 1 Apr 2020 16:22:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6B5121BEE6; Wed, 1 Apr 2020 16:21:48 +0200 (CEST) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by dpdk.org (Postfix) with ESMTP id E1F3D1BECC for ; Wed, 1 Apr 2020 16:21:45 +0200 (CEST) Received: by mail-lj1-f193.google.com with SMTP id 19so25904069ljj.7 for ; Wed, 01 Apr 2020 07:21:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OS8Wq+90JkQ6fUmpk+hKywyQCRi+8rx7LJ5V0ISP0lY=; b=KtwWJkUmkrcW5fkDdgyAEVPNO/AKU05hEms02mchaATNlGGU86TJm7za46ZzLk1Otl H10lTct4v1XEGN6QWLb3em536dQxUFijEstxqAy5ndyEWBnHQo/XGS25gySr/DeocpZi tcWArb2e3wr0YmPMc0FbmkRPtx0CxmmZCqfnYR3U7Wr2KLpChFKCm2J9RpDV43M3a1po fPHSCsm4YwkWe56wnRN5eZ2ysG4lLF9GVsMHuybz8sZk8DJtpiQ/wXsx5tp2/DOm2Xbr YlxQbFNYEC1wKdYa61dIUIwyyaKRjuX4iCPG04ljsucSmqDmncvpnQaWzAQVztxrunZj jbbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OS8Wq+90JkQ6fUmpk+hKywyQCRi+8rx7LJ5V0ISP0lY=; b=EkDFbDL8TAWEoxohA8rYmn6S2IUx+Dyzh7Oynse1klHUCrxjYBQVeQrx7TbG6Uywry RU47TzcHf4EL78sADq12N+BOQEvDeitN8rm+WS03YKRgCCtn1LSFrins0zOn2tOmuSA5 7RQE8agGJh2FooVkocn+PGZZmMBpSXjfwaDzL3geu/7h/hQfihUYjrH/jtiF+a85wTF7 tPuhTvJrnbjO0QNJjNAERPg9/ipXBi/xtujlrHfwFv2cAGC4GD/QYhzSjyTBBP9Fev5f icipKb0BX9KUl0tDkPJMnBLxy9hHSW42SLgqugo+urwrnxUZ621HF/oI/RU+An4qJtox A3Uw== X-Gm-Message-State: AGi0PuauWAGK6agznVQ9RBfa+tcMEKZpDjTXk1zQtfmujBbdL2ITAmnn xnlYJaO2ir2IS+r8oQmO8EZkQhfDPYo= X-Google-Smtp-Source: APiQypKyIXi3AUAIGqW2/zy1AyZ6zQvx5tsYQqNnMTCJ2KBQCXCCso1HdReTRMcGYrULyzCliT+uaA== X-Received: by 2002:a2e:b175:: with SMTP id a21mr13384478ljm.213.1585750905242; Wed, 01 Apr 2020 07:21:45 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:44 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:04 +0200 Message-Id: <20200401142127.13715-7-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 06/29] net/ena/base: remove extra properties strings X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This buffer was never used by the ENA PMD. It could be used for debugging, but it's presence is redundant now. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.c | 56 ---------------------------------- drivers/net/ena/base/ena_com.h | 33 -------------------- 2 files changed, 89 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index cb2114acb7..19815db9ad 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -1910,62 +1910,6 @@ int ena_com_get_link_params(struct ena_com_dev *ena_dev, return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0); } -int ena_com_extra_properties_strings_init(struct ena_com_dev *ena_dev) -{ - struct ena_admin_get_feat_resp resp; - struct ena_extra_properties_strings *extra_properties_strings = - &ena_dev->extra_properties_strings; - u32 rc; - extra_properties_strings->size = ENA_ADMIN_EXTRA_PROPERTIES_COUNT * - ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN; - - ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, - extra_properties_strings->size, - extra_properties_strings->virt_addr, - extra_properties_strings->dma_addr, - extra_properties_strings->dma_handle); - if (unlikely(!extra_properties_strings->virt_addr)) { - ena_trc_err("Failed to allocate extra properties strings\n"); - return 0; - } - - rc = ena_com_get_feature_ex(ena_dev, &resp, - ENA_ADMIN_EXTRA_PROPERTIES_STRINGS, - extra_properties_strings->dma_addr, - extra_properties_strings->size, 0); - if (rc) { - ena_trc_dbg("Failed to get extra properties strings\n"); - goto err; - } - - return resp.u.extra_properties_strings.count; -err: - ena_com_delete_extra_properties_strings(ena_dev); - return 0; -} - -void ena_com_delete_extra_properties_strings(struct ena_com_dev *ena_dev) -{ - struct ena_extra_properties_strings *extra_properties_strings = - &ena_dev->extra_properties_strings; - - if (extra_properties_strings->virt_addr) { - ENA_MEM_FREE_COHERENT(ena_dev->dmadev, - extra_properties_strings->size, - extra_properties_strings->virt_addr, - extra_properties_strings->dma_addr, - extra_properties_strings->dma_handle); - extra_properties_strings->virt_addr = NULL; - } -} - -int ena_com_get_extra_properties_flags(struct ena_com_dev *ena_dev, - struct ena_admin_get_feat_resp *resp) -{ - return ena_com_get_feature(ena_dev, resp, - ENA_ADMIN_EXTRA_PROPERTIES_FLAGS, 0); -} - int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, struct ena_com_dev_get_features_ctx *get_feat_ctx) { diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index 5935d024dd..0e34a13fde 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -284,13 +284,6 @@ struct ena_host_attribute { ena_mem_handle_t host_info_dma_handle; }; -struct ena_extra_properties_strings { - u8 *virt_addr; - dma_addr_t dma_addr; - ena_mem_handle_t dma_handle; - u32 size; -}; - /* Each ena_dev is a PCI function. */ struct ena_com_dev { struct ena_com_admin_queue admin_queue; @@ -326,7 +319,6 @@ struct ena_com_dev { struct ena_intr_moder_entry *intr_moder_tbl; struct ena_com_llq_info llq_info; - struct ena_extra_properties_strings extra_properties_strings; }; struct ena_com_dev_get_features_ctx { @@ -564,31 +556,6 @@ int ena_com_validate_version(struct ena_com_dev *ena_dev); int ena_com_get_link_params(struct ena_com_dev *ena_dev, struct ena_admin_get_feat_resp *resp); -/* ena_com_extra_properties_strings_init - Initialize the extra properties strings buffer. - * @ena_dev: ENA communication layer struct - * - * Initialize the extra properties strings buffer. - */ -int ena_com_extra_properties_strings_init(struct ena_com_dev *ena_dev); - -/* ena_com_delete_extra_properties_strings - Free the extra properties strings buffer. - * @ena_dev: ENA communication layer struct - * - * Free the allocated extra properties strings buffer. - */ -void ena_com_delete_extra_properties_strings(struct ena_com_dev *ena_dev); - -/* ena_com_get_extra_properties_flags - Retrieve extra properties flags. - * @ena_dev: ENA communication layer struct - * @resp: Extra properties flags. - * - * Retrieve the extra properties flags. - * - * @return - 0 on Success negative value otherwise. - */ -int ena_com_get_extra_properties_flags(struct ena_com_dev *ena_dev, - struct ena_admin_get_feat_resp *resp); - /* ena_com_get_dma_width - Retrieve physical dma address width the device * supports. * @ena_dev: ENA communication layer struct From patchwork Wed Apr 1 14:21:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67592 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7FBCEA057B; Wed, 1 Apr 2020 16:22:55 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B9B051BF0B; Wed, 1 Apr 2020 16:21:49 +0200 (CEST) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by dpdk.org (Postfix) with ESMTP id A34821BEDF for ; Wed, 1 Apr 2020 16:21:47 +0200 (CEST) Received: by mail-lj1-f193.google.com with SMTP id p10so25711074ljn.1 for ; Wed, 01 Apr 2020 07:21:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JkIhcQNPmRKfzIfELRoF5vpS3N2p0O4RxY3SsWLr2XY=; b=fJbL3qcW5i6Yu+oKXyBI1jMxuukT0ImC6dWRDPTLNnuL9RhwCQyvsM8UahKpJuY3DY PsIaf1ikOgotLvUVIGA6b9vaacvM7X1hf1v85LeKkn86VNNINyZgzy0+74qAH23THCN3 UlvTqSujFSltCXrjXe7vDvetZBgYUbJMTnSnJ6yNZXltgcvKvtp4u8ME3XwodLLBzDGs P5D+3YpIFdIZtm03Ex2t6gua6iXqJZzc+zvNRJD0jnEzrJqUw+WJSNbfCrviTs8jgJdd TYb4X+rdQzm2/T1CSNdwoBmqEbrqGiedLJjXiDc8ONK4v5Lnb/xGb8rcAp+D3X4WxCzo HYfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JkIhcQNPmRKfzIfELRoF5vpS3N2p0O4RxY3SsWLr2XY=; b=HWregM+hGqCpzvHRzzfNtvcGAkQ1/QzCRF+0VVaPkGgcfnoTkTIME29dY1AUg6OGb2 RIqfL0mfvX7Vd9OUbQVfUqy2ElPsx2T5KQdtcXmvPnGQfCBVGumzdmhU13vEijcIEBe7 S5KjgOetouiBZ99nBraxcFZTB/7BExEYSFguWy/gLoYkfqOKZ/qsse18rNptaprD4MJ5 ydzEtHcB7t+imobL/zjmuwVPsYyYO5RDtM/PQ4r0ANoCzfUE79vqU1iRf4wapTo0z8W9 L6ZMDX7JGwb/GHOLauX0ISZy2nRIh/zpYvZpNRpMvRD5wXQGwYwAOJjpeSZPKdCXowBi 31HA== X-Gm-Message-State: AGi0Pubeb/u5yjNsS1bGZFLdWY+McubYBt4sB4k8F7+kFhpKtj+Rwi6X DwhH82Cc8lJbabOJ9Wi6e6P8dbXnKmA= X-Google-Smtp-Source: APiQypIg64DRPAYQLtPOiQWKqQXmkKX/HhErxHgSjVGxJs23ZCW3oJEk4osJWGJjh+EWswQd8ZXtng== X-Received: by 2002:a2e:9585:: with SMTP id w5mr13775051ljh.178.1585750906763; Wed, 01 Apr 2020 07:21:46 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:45 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:05 +0200 Message-Id: <20200401142127.13715-8-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 07/29] net/ena/base: add accelerated LLQ mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In order to use the accelerated LLQ, the driver must limit the Tx burst and be aware that the device has the meta caching disabled. In that situation, the meta descriptor must be valid on each Tx packet. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.c | 20 +++++++- drivers/net/ena/base/ena_com.h | 3 ++ .../net/ena/base/ena_defs/ena_admin_defs.h | 39 +++++++++++++-- drivers/net/ena/base/ena_eth_com.c | 49 +++++++++++++------ 4 files changed, 91 insertions(+), 20 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 19815db9ad..d15b7f22dc 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -378,6 +378,8 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, 0x0, io_sq->llq_info.desc_list_entry_size); io_sq->llq_buf_ctrl.descs_left_in_line = io_sq->llq_info.descs_num_before_header; + io_sq->disable_meta_caching = + io_sq->llq_info.disable_meta_caching; if (io_sq->llq_info.max_entries_in_tx_burst > 0) io_sq->entries_in_tx_burst_left = @@ -595,6 +597,14 @@ static int ena_com_set_llq(struct ena_com_dev *ena_dev) cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header; cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl; + if (llq_info->disable_meta_caching) + cmd.u.llq.accel_mode.u.set.enabled_flags |= + BIT(ENA_ADMIN_DISABLE_META_CACHING); + + if (llq_info->max_entries_in_tx_burst) + cmd.u.llq.accel_mode.u.set.enabled_flags |= + BIT(ENA_ADMIN_LIMIT_TX_BURST); + ret = ena_com_execute_admin_command(admin_queue, (struct ena_admin_aq_entry *)&cmd, sizeof(cmd), @@ -714,9 +724,15 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, supported_feat, llq_info->descs_num_before_header); } + /* Check for accelerated queue supported */ + llq_info->disable_meta_caching = + llq_features->accel_mode.u.get.supported_flags & + BIT(ENA_ADMIN_DISABLE_META_CACHING); - llq_info->max_entries_in_tx_burst = - (u16)(llq_features->max_tx_burst_size / llq_default_cfg->llq_ring_entry_size_value); + if (llq_features->accel_mode.u.get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST)) + llq_info->max_entries_in_tx_burst = + llq_features->accel_mode.u.get.max_tx_burst_size / + llq_default_cfg->llq_ring_entry_size_value; rc = ena_com_set_llq(ena_dev); if (rc) diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index 0e34a13fde..9f2c6ea8ee 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -82,6 +82,7 @@ struct ena_com_llq_info { u16 descs_num_before_header; u16 descs_per_entry; u16 max_entries_in_tx_burst; + bool disable_meta_caching; }; struct ena_com_io_cq { @@ -146,6 +147,8 @@ struct ena_com_io_sq { enum queue_direction direction; enum ena_admin_placement_policy_type mem_queue_type; + bool disable_meta_caching; + u32 msix_vector; struct ena_com_tx_meta cached_tx_meta; struct ena_com_llq_info llq_info; diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index fb4d4d03f0..020dc78e26 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -469,6 +469,36 @@ enum ena_admin_llq_stride_ctrl { ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, }; +enum ena_admin_accel_mode_feat { + ENA_ADMIN_DISABLE_META_CACHING = 0, + ENA_ADMIN_LIMIT_TX_BURST = 1, +}; + +struct ena_admin_accel_mode_get { + /* bit field of enum ena_admin_accel_mode_feat */ + uint16_t supported_flags; + + /* maximum burst size between two doorbells. The size is in bytes */ + uint16_t max_tx_burst_size; +}; + +struct ena_admin_accel_mode_set { + /* bit field of enum ena_admin_accel_mode_feat */ + uint16_t enabled_flags; + + uint16_t reserved; +}; + +struct ena_admin_accel_mode_req { + union { + uint32_t raw[2]; + + struct ena_admin_accel_mode_get get; + + struct ena_admin_accel_mode_set set; + } u; +}; + struct ena_admin_feature_llq_desc { uint32_t max_llq_num; @@ -514,10 +544,13 @@ struct ena_admin_feature_llq_desc { /* the stride control the driver selected to use */ uint16_t descriptors_stride_ctrl_enabled; - /* Maximum size in bytes taken by llq entries in a single tx burst. - * Set to 0 when there is no such limit. + /* reserved */ + uint32_t reserved1; + + /* accelerated low latency queues requirment. driver needs to + * support those requirments in order to use accelerated llq */ - uint32_t max_tx_burst_size; + struct ena_admin_accel_mode_req accel_mode; }; struct ena_admin_queue_ext_feature_fields { diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index d4d44226df..aabc294fb7 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -258,11 +258,10 @@ static u16 ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, return count; } -static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq, - struct ena_com_tx_ctx *ena_tx_ctx) +static int ena_com_create_meta(struct ena_com_io_sq *io_sq, + struct ena_com_tx_meta *ena_meta) { struct ena_eth_io_tx_meta_desc *meta_desc = NULL; - struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; meta_desc = get_sq_desc(io_sq); memset(meta_desc, 0x0, sizeof(struct ena_eth_io_tx_meta_desc)); @@ -282,12 +281,13 @@ static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq, /* Extended meta desc */ meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK; - meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_STORE_MASK; meta_desc->len_ctrl |= (io_sq->phase << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_META_DESC_PHASE_MASK; meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_FIRST_MASK; + meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_STORE_MASK; + meta_desc->word2 |= ena_meta->l3_hdr_len & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; meta_desc->word2 |= (ena_meta->l3_hdr_offset << @@ -298,13 +298,34 @@ static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq, ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK; - meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_STORE_MASK; + return ena_com_sq_update_tail(io_sq); +} - /* Cached the meta desc */ - memcpy(&io_sq->cached_tx_meta, ena_meta, - sizeof(struct ena_com_tx_meta)); +static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq, + struct ena_com_tx_ctx *ena_tx_ctx, + bool *have_meta) +{ + struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; - return ena_com_sq_update_tail(io_sq); + /* When disable meta caching is set, don't bother to save the meta and + * compare it to the stored version, just create the meta + */ + if (io_sq->disable_meta_caching) { + if (unlikely(!ena_tx_ctx->meta_valid)) + return ENA_COM_INVAL; + + *have_meta = true; + return ena_com_create_meta(io_sq, ena_meta); + } else if (ena_com_meta_desc_changed(io_sq, ena_tx_ctx)) { + *have_meta = true; + /* Cache the meta desc */ + memcpy(&io_sq->cached_tx_meta, ena_meta, + sizeof(struct ena_com_tx_meta)); + return ena_com_create_meta(io_sq, ena_meta); + } else { + *have_meta = false; + return ENA_COM_OK; + } } static void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx, @@ -380,12 +401,10 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, if (unlikely(rc)) return rc; - have_meta = ena_tx_ctx->meta_valid && ena_com_meta_desc_changed(io_sq, - ena_tx_ctx); - if (have_meta) { - rc = ena_com_create_and_store_tx_meta_desc(io_sq, ena_tx_ctx); - if (unlikely(rc)) - return rc; + rc = ena_com_create_and_store_tx_meta_desc(io_sq, ena_tx_ctx, &have_meta); + if (unlikely(rc)) { + ena_trc_err("failed to create and store tx meta desc\n"); + return rc; } /* If the caller doesn't want to send packets */ From patchwork Wed Apr 1 14:21:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67593 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D6059A057B; Wed, 1 Apr 2020 16:23:08 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8D97D1BF68; Wed, 1 Apr 2020 16:21:51 +0200 (CEST) Received: from mail-lj1-f196.google.com (mail-lj1-f196.google.com [209.85.208.196]) by dpdk.org (Postfix) with ESMTP id D7E981BED1 for ; Wed, 1 Apr 2020 16:21:48 +0200 (CEST) Received: by mail-lj1-f196.google.com with SMTP id r7so18241998ljg.13 for ; Wed, 01 Apr 2020 07:21:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6P+giP8LKjB888Y0vXn6sFEo01Yk/pgwf/Ofq/QEU+Y=; b=HKLp44bBieO6asI3crHrKNiT3tjds2lWiED16opsxoR472g8pCwYMEwRJCWBX97Ysc N1meKQC01uCOwCSXCwBaO5jDElRnfotaDOPcFqvS4A0wAxZFanAd5/7vjOcR4EFiyk8m 3cmrBOJwDsJz1zR6/TNqg9sedm8A5HcH4nWHu7qT7nvfdG4cf/FImvuT86haVhK1QOQ7 rfx8dZ5wcEW6meyRlwC+7yHoTvOdDSf6WGIUVpoM/LsGKMpx3TjC4Lx+4Uj0FnCnXRiZ YgZtSY3ksVzS9LyP7cYlV+XpweXSZ41QIlPJ1ioDXeBLp3ri8NYCowx4scCl1SluXDfp 9QcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6P+giP8LKjB888Y0vXn6sFEo01Yk/pgwf/Ofq/QEU+Y=; b=N9VPGgFoGICp3k82Yhwu2bLLKsBuKIqkI0DTfNqI9xfqEYj2Gr/02BnZQe7Sp0efeu Hpl0SEO69AKgZMCjNQ53Jhqh2qKJJEysYbY27D3KyphvwVAwO6yMR9e2eAYHlh5fakkq 7lOut689z1jjCDNPpIUuk7XR4oGtC31eU97NzkxHCbp8kw+NN/iXUGyAu7VCkAA0VXv1 wnl4qXRO6GdPMX7RydJKdFg6dRHaycpea5aTbcaLCxlkTLcXZzAgjzdzTrYI78/rlq3Z PC5X8i2TRFO6MdMd2wDCOhaImnskEtVqcQtlwPFb3WyiOFzDEicbMGbx8FRlHVmCK7bI 2ZSg== X-Gm-Message-State: AGi0PubvAXSU+jUv6j0vP6O4Taiqb9QzkZd98rKjvl8NY3kjJYDXXXxb IuPi6XxRhDyQWrB+ccEVsSb8MVnP5LM= X-Google-Smtp-Source: APiQypJO95tjreBb2Hx6aoPxOjjIIB0NU4EX2goHtKM5jZZm9hed20CDT+QjE5y9/4gYAyBxb94IVQ== X-Received: by 2002:a2e:9789:: with SMTP id y9mr12855645lji.207.1585750908095; Wed, 01 Apr 2020 07:21:48 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:47 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:06 +0200 Message-Id: <20200401142127.13715-9-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 08/29] net/ena/base: fix documentation of the functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The documentation format was aligned and few typos were fixed. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index 9f2c6ea8ee..9b87fa94e4 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -370,7 +370,7 @@ extern "C" { */ int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev); -/* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism +/* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism * @ena_dev: ENA communication layer struct * @readless_supported: readless mode (enable/disable) */ @@ -504,7 +504,7 @@ void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev, /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler * @ena_dev: ENA communication layer struct * - * This method go over the admin completion queue and wake up all the pending + * This method goes over the admin completion queue and wakes up all the pending * threads that wait on the commands wait event. * * @note: Should be called after MSI-X interrupt. @@ -514,7 +514,7 @@ void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev); /* ena_com_aenq_intr_handler - AENQ interrupt handler * @ena_dev: ENA communication layer struct * - * This method go over the async event notification queue and call the proper + * This method goes over the async event notification queue and calls the proper * aenq handler. */ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data); @@ -531,14 +531,14 @@ void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev); /* ena_com_wait_for_abort_completion - Wait for admin commands abort. * @ena_dev: ENA communication layer struct * - * This method wait until all the outstanding admin commands will be completed. + * This method waits until all the outstanding admin commands are completed. */ void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev); /* ena_com_validate_version - Validate the device parameters * @ena_dev: ENA communication layer struct * - * This method validate the device parameters are the same as the saved + * This method verifies the device parameters are the same as the saved * parameters in ena_dev. * This method is useful after device reset, to validate the device mac address * and the device offloads are the same as before the reset. @@ -732,7 +732,7 @@ int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev); * * Retrieve the hash control from the device. * - * @note, If the caller called ena_com_fill_hash_ctrl but didn't flash + * @note: If the caller called ena_com_fill_hash_ctrl but didn't flash * it to the device, the new configuration will be lost. * * @return: 0 on Success and negative value otherwise. @@ -784,7 +784,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev); * * Retrieve the RSS indirection table from the device. * - * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash + * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flush * it to the device, the new configuration will be lost. * * @return: 0 on Success and negative value otherwise. @@ -810,14 +810,14 @@ int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, /* ena_com_delete_debug_area - Free the debug area resources. * @ena_dev: ENA communication layer struct * - * Free the allocate debug area. + * Free the allocated debug area. */ void ena_com_delete_debug_area(struct ena_com_dev *ena_dev); /* ena_com_delete_host_info - Free the host info resources. * @ena_dev: ENA communication layer struct * - * Free the allocate host info. + * Free the allocated host info. */ void ena_com_delete_host_info(struct ena_com_dev *ena_dev); @@ -858,9 +858,9 @@ int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, * @cmd_completion: command completion return value. * @cmd_comp_size: command completion size. - * Submit an admin command and then wait until the device will return a + * Submit an admin command and then wait until the device returns a * completion. - * The completion will be copyed into cmd_comp. + * The completion will be copied into cmd_comp. * * @return - 0 on success, negative value on failure. */ @@ -949,7 +949,7 @@ static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_d * @intr_reg: interrupt register to update. * @rx_delay_interval: Rx interval in usecs * @tx_delay_interval: Tx interval in usecs - * @unmask: unask enable/disable + * @unmask: unmask enable/disable * * Prepare interrupt update register with the supplied parameters. */ From patchwork Wed Apr 1 14:21:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67594 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 74379A057B; Wed, 1 Apr 2020 16:23:20 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C200C1BFB7; Wed, 1 Apr 2020 16:21:52 +0200 (CEST) Received: from mail-lj1-f196.google.com (mail-lj1-f196.google.com [209.85.208.196]) by dpdk.org (Postfix) with ESMTP id E4EA71BF3C for ; Wed, 1 Apr 2020 16:21:50 +0200 (CEST) Received: by mail-lj1-f196.google.com with SMTP id q19so25894740ljp.9 for ; Wed, 01 Apr 2020 07:21:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mILA2OXX5JY1RnMY5aIZAnl0BBgbyyTfBaMA5jASz7o=; b=DyWNxRN2QO0SpkOSzcrS7Z4QNK+7SW52PkbX2yROuIKr3ojwdhgQmVOHmJkrjFJTbX 8HgijWIE5eUi5XBavX77SfkqO5HeBD757iuCa+AsKGL3OQMpSN+VWd9ZKIt5omgX//dq YZ8y2XKgn1MvbkTtgOsj0HxqSwpU3yOQA61S+hPnWqyJ1MMhL6tKvttGsoz2JdUXfdVb Gm5v9eS5MylikA2W19bG+IV9JY77FNQ5v+7LEcKonrlPi6BLTcf4RR6SO7exITkYA58d VpmiwUNU72oFfJ2IV00S7g5mg6fRyGp/KbZdwcKrfMm/wDfQtAzXqxAKpVCkae/K2+0A Pvzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mILA2OXX5JY1RnMY5aIZAnl0BBgbyyTfBaMA5jASz7o=; b=mVlmWZkOCD/5wovXH6vvEowTYTC/ohnibIKKyCcwUmvnU32bggu6/b7oMvPHqzeSCe RGFELLkE9oUmqXjBuJCEIqrcV+19ILMIsrgjlPE5kYnR5oClhtjFODnIU6NtHi9Q5TjU d9cHlzrPNA7JHDKWEMnlDb+CT9jiH47W5IFQ8YOYZwER8Kle2EGvzfkPyFj1v7MZfNa9 dLF5yYVLSbEtcxcN4Ktewlmb8fnTnu84SEpN4ywFMY+pnOxNF8Ir41XqyiRmH4DPAwli JKsJhSSkuXgamgp/IfTPjbFJbQWWh+iLTtDMs9AXgvrt4jOABFqL8M30effHAOJy01+Z tUHA== X-Gm-Message-State: AGi0Pub1V6JayOg/vAPZT8La0s2JOfsvCtXI+KZMmNI6CB3xCn/q1ymB jNz3DdL0gxw3y2zXzwiqsiHYzjY0lo4= X-Google-Smtp-Source: APiQypJ6snZcogPnnbkPDpJBSuSl2Xm0cqYjABensnzqPFGuW4faR7ANnPdO4I0PbTXF28sWjHsqcQ== X-Received: by 2002:a2e:9752:: with SMTP id f18mr13437986ljj.181.1585750909368; Wed, 01 Apr 2020 07:21:49 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:48 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:07 +0200 Message-Id: <20200401142127.13715-10-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 09/29] net/ena/base: fix indentation in cq polling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The spaces instead of tabs were used for the indent. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index d15b7f22dc..7c1d0aef20 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -532,11 +532,11 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout); while (1) { - ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); - ena_com_handle_admin_completion(admin_queue); - ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); + ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); + ena_com_handle_admin_completion(admin_queue); + ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); - if (comp_ctx->status != ENA_CMD_SUBMITTED) + if (comp_ctx->status != ENA_CMD_SUBMITTED) break; if (ENA_TIME_EXPIRE(timeout)) { From patchwork Wed Apr 1 14:21:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67595 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BA858A057B; Wed, 1 Apr 2020 16:23:30 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 12A2D1BFC4; Wed, 1 Apr 2020 16:21:54 +0200 (CEST) Received: from mail-lj1-f196.google.com (mail-lj1-f196.google.com [209.85.208.196]) by dpdk.org (Postfix) with ESMTP id 27C851BEBF for ; Wed, 1 Apr 2020 16:21:52 +0200 (CEST) Received: by mail-lj1-f196.google.com with SMTP id p10so25711347ljn.1 for ; Wed, 01 Apr 2020 07:21:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VMKzfoDtixxDfKwL4LmA5K/5OQb+WO9qXPNwnHDPCk0=; b=RTLYUFnjNw91T1BSQjFTGgGCOGK9OOFKe7umgo2cWqZb93h8tiIgR0SdI1VDXghuZT 7uzfWqH+FqP1ZbPevDRzCmFHu1ZmDZeDDzx35vZ256hseEIughocgL7NepUQT0wKcKKI Tk387xZIaH6uBaiyxa0yh2+V+tJbhe8C5k3DRYQlwKaVqCMPZDkCThFbJvaqOdzOZth8 pNw6dSPHJxYKycbZcnm0xMgfu38Wfmv/lOFxnYD+KaZuM+kmqyLdpeK7oHnBIiSF5lEE 7zEmoaGvAXpVkaSLDiMj9UnHXdta2FCYRzGIgdnMWmHaRnmrbXWFFfrucaojOg5M6cp2 OBaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VMKzfoDtixxDfKwL4LmA5K/5OQb+WO9qXPNwnHDPCk0=; b=tiIDIU2Itf1AlMUoKj3IcP2YeTYJb+6082X4S1N53k6pQK57wvhq0q3QBgNoPYjnsT Ltf0cIH0NCwYGdOr94vu2TQTntjoXggPEyJYbWexCJ1IPI5esUcGydDhefL5MPijgzad rNBJ84LX0eFCa1sbT97QQPGQ0G/VdX/ZkpRtDVb/Ls5auwSRxkLJFM8vgg+nPOS5k2JG fO7K+gd9+sewX4yLbFvhNAlOQoXBT2qGqcOBckk/adxigmSNWOk6ag6lEtbUnlEq4sa/ sEdkjvh6VfjtOz94TpKD3LP2EiKfIrqRGjwkmaKG84fATecCsU7wJur82Xiy1TV2370R bG/w== X-Gm-Message-State: AGi0Pub8YNJqkFGSOI5n/zFUZC86oGuOojvt7TP+8XQ0OHHkXLF2ZeU4 cf+s/PIAfGl9+Liy6/EkkxhgyeZsaqE= X-Google-Smtp-Source: APiQypJUQZ94znh/HX/Yg8PganRDFAXZJ0y3ItVP4u9J5ExYJ8XlixYlWKsvNxlxvIFChnxis8johQ== X-Received: by 2002:a05:651c:c7:: with SMTP id 7mr10943605ljr.124.1585750911519; Wed, 01 Apr 2020 07:21:51 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:49 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:08 +0200 Message-Id: <20200401142127.13715-11-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 10/29] net/ena/base: add error logs when preparing Tx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To make the debugging easier, the error logs were added in the Tx path. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_eth_com.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index aabc294fb7..747450fec5 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -148,8 +148,10 @@ static int ena_com_close_bounce_buffer(struct ena_com_io_sq *io_sq) if (pkt_ctrl->idx) { rc = ena_com_write_bounce_buffer_to_dev(io_sq, pkt_ctrl->curr_bounce_buf); - if (unlikely(rc)) + if (unlikely(rc)) { + ena_trc_err("failed to write bounce buffer to device\n"); return rc; + } pkt_ctrl->curr_bounce_buf = ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl); @@ -179,8 +181,10 @@ static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq) if (!pkt_ctrl->descs_left_in_line) { rc = ena_com_write_bounce_buffer_to_dev(io_sq, pkt_ctrl->curr_bounce_buf); - if (unlikely(rc)) + if (unlikely(rc)) { + ena_trc_err("failed to write bounce buffer to device\n"); return rc; + } pkt_ctrl->curr_bounce_buf = ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl); @@ -394,8 +398,10 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, } if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV - && !buffer_to_push)) + && !buffer_to_push)) { + ena_trc_err("push header wasn't provided on LLQ mode\n"); return ENA_COM_INVAL; + } rc = ena_com_write_header_to_bounce(io_sq, buffer_to_push, header_len); if (unlikely(rc)) @@ -410,6 +416,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, /* If the caller doesn't want to send packets */ if (unlikely(!num_bufs && !header_len)) { rc = ena_com_close_bounce_buffer(io_sq); + if (rc) + ena_trc_err("failed to write buffers to LLQ\n"); *nb_hw_desc = io_sq->tail - start_tail; return rc; } @@ -469,8 +477,10 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, /* The first desc share the same desc as the header */ if (likely(i != 0)) { rc = ena_com_sq_update_tail(io_sq); - if (unlikely(rc)) + if (unlikely(rc)) { + ena_trc_err("failed to update sq tail\n"); return rc; + } desc = get_sq_desc(io_sq); if (unlikely(!desc)) @@ -499,10 +509,14 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, desc->len_ctrl |= ENA_ETH_IO_TX_DESC_LAST_MASK; rc = ena_com_sq_update_tail(io_sq); - if (unlikely(rc)) + if (unlikely(rc)) { + ena_trc_err("failed to update sq tail of the last descriptor\n"); return rc; + } rc = ena_com_close_bounce_buffer(io_sq); + if (rc) + ena_trc_err("failed when closing bounce buffer\n"); *nb_hw_desc = io_sq->tail - start_tail; return rc; From patchwork Wed Apr 1 14:21:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67596 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 98BF5A057B; Wed, 1 Apr 2020 16:23:41 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4452F1BFD9; Wed, 1 Apr 2020 16:21:55 +0200 (CEST) Received: from mail-lf1-f65.google.com (mail-lf1-f65.google.com [209.85.167.65]) by dpdk.org (Postfix) with ESMTP id 551091BEC6 for ; Wed, 1 Apr 2020 16:21:53 +0200 (CEST) Received: by mail-lf1-f65.google.com with SMTP id j17so20586576lfe.7 for ; Wed, 01 Apr 2020 07:21:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CKG0MQd4cMNVIj/se7rzP6dTkI60VC1aDRThmCsVKHM=; b=wNxVwnW9wH+eMQ2FHZ6UjV9ZklzYEQfjQk3KC9PNchjHwLK7awjElr4SRkNvbIlPyU 0VqTZ+aMkTxEt3WQTBfYEHQhRjFmwEVPRiNl6tDB1wh/h8ckRiGPCS4vjUHUhT6v3iJo JHlOGIRz9hY3hvZjDGyadPeM9EMEojw2PyXdNJA+qTXXXp843ZGfJbf6ZQflfzNFl9G2 OkInh7ZJzelv1cbo40ApOg4BA1R2UBR0H1yVBVP8nZNib27rVD3XZxOik4pc4RbwI+IL hucHLhuzEkf6KTELgjwcgNqIDabaNbZfNS3XOzhFZfqbV/BD75AAxO7Eg5rm9W92diJ5 Hmcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CKG0MQd4cMNVIj/se7rzP6dTkI60VC1aDRThmCsVKHM=; b=kM+sWb8TsLGl9YmPH8b9EW9lyoFFQStpAEdbUHNgLicHgMFfHCaqF/jgcaihPTXUsS LX9R5nae3nL+iBVe1wPGTTyxY4FibqAsFxeVQs96oS/Bbbx5st1tyvhHtCf+89m/fNCv xUlSOJdOMpMwtG0ZtTRFcR9L5gvDcHEaoqfhNWBqRzUK8zts02BI7mC0oEVoCAbSQfj7 IQanMGG38xh5YmQ7WHhcFzO9L0NMqY4VA0J/IAScI5NszjwIfawtgRuFmI3Pgp+e6MHD /fFUB2Yvp2+qpH8ZZshl/hVaqu4BmopD/vp5OOBbGZCN4VbNWs+2/7eiXCDphEEQP8wy s2WQ== X-Gm-Message-State: AGi0Pua67SEmBMX/YrFkwGomzTBVIBZ2Pa61U8Pnx6yj/yIeTzNbyGOz ug9HVJ/0pJoOi/r/UdY235mgvhH6s2I= X-Google-Smtp-Source: APiQypJnaVJ3EP7F+qy084XeUK9EnIYrJaDbnVzCqvAEQ6Ug7NmYnQWLCYv17sWkUcEil3gRL1rZWw== X-Received: by 2002:a19:be92:: with SMTP id o140mr14441237lff.217.1585750912755; Wed, 01 Apr 2020 07:21:52 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:52 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:09 +0200 Message-Id: <20200401142127.13715-12-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 11/29] net/ena/base: use 48-bit memory addresses in ena_com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" ENA device is using 48-bit memory for IO. because of that, the upper limit had to be updated. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.c | 2 +- drivers/net/ena/base/ena_defs/ena_common_defs.h | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 7c1d0aef20..b7749209b3 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -73,7 +73,7 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, } ena_addr->mem_addr_low = lower_32_bits(addr); - ena_addr->mem_addr_high = upper_32_bits(addr); + ena_addr->mem_addr_high = (u16)upper_32_bits(addr); return 0; } diff --git a/drivers/net/ena/base/ena_defs/ena_common_defs.h b/drivers/net/ena/base/ena_defs/ena_common_defs.h index 1818c29a87..349474d265 100644 --- a/drivers/net/ena/base/ena_defs/ena_common_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_common_defs.h @@ -9,10 +9,14 @@ #define ENA_COMMON_SPEC_VERSION_MAJOR 2 #define ENA_COMMON_SPEC_VERSION_MINOR 0 +/* ENA operates with 48-bit memory addresses. ena_mem_addr_t */ struct ena_common_mem_addr { uint32_t mem_addr_low; - uint32_t mem_addr_high; + uint16_t mem_addr_high; + + /* MBZ */ + uint16_t reserved16; }; #endif /* _ENA_COMMON_H_ */ From patchwork Wed Apr 1 14:21:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67597 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 74CCBA057B; Wed, 1 Apr 2020 16:23:51 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7C8821C02D; Wed, 1 Apr 2020 16:21:56 +0200 (CEST) Received: from mail-lf1-f67.google.com (mail-lf1-f67.google.com [209.85.167.67]) by dpdk.org (Postfix) with ESMTP id A01EC1BF54 for ; Wed, 1 Apr 2020 16:21:54 +0200 (CEST) Received: by mail-lf1-f67.google.com with SMTP id c5so20628679lfp.5 for ; Wed, 01 Apr 2020 07:21:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/nS3uCYGEDq7Kw8ZnxvzeGNCHqKwiv5JMie+u58iUgM=; b=l5fu+yCXww/VBr9BLyHvyXx2NrQEWnyoEtPzHygrXDNWTYtnodKKauFAJfnoLQec/W gqsmmvy7pd5GqLjCbqvNV6EH5UoWJikISq7W3mD9Q0qlDKAFRlbTsvJaTrASfgmVKrqQ T1hoMkEZk+KfF2692uIwsx9FFSfQqrXOr5CpfSX+d/PLW8ZkZ60k0mSe6allum2WrDhW yiDzNrhns5mWaFMMH71T6FehKFCA6uzKASRaimLPsLS0U8zH6VDrAcrmKFa0NBqW0Abx tGQn39Wmqdfy0w6edG9cMBMS/bfyVy0sidshVrPhx7q60u+TSeLVmsPNyiaLhUFw2hiJ dz/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/nS3uCYGEDq7Kw8ZnxvzeGNCHqKwiv5JMie+u58iUgM=; b=C4dSpSxM5neSPg7+Pa7hySycNme8MRjLQR0yVwx4CWeGAzXpAe9GnnkoBxzjPcUqhQ If0vEcBWwqFzpGfrqkgq4mXcIfrqAn/6c3kRVT34q8TbggIFAtXWkAyvHWZ4Z+uYqI3X hsxaAaPSASkhQsBA9qsSsIACG9JpNoL9F1flIjVRzdpNe7oBxXR/u8d+NvLOasy2zl+1 qRXRjceFLrrN/DFcF6keQ0WQowDeKkW5SEh6TJARPYKVnJ5YGtd3B6KhuLykVIVunaIx kEW+OlwNjtRXGwV9pMzREpL7BdYFEkdq5L5I22/vbYrvf53a5aS7SLtur2SKG2g4tVfx 9akw== X-Gm-Message-State: AGi0PubHlZMhauYuoJZo9KXR+dQXHD4Vx59NxZqNlLNb9EixcLbIFEaz 4EazpSZnkmtqo1wpDTpkbSS6gjv8imo= X-Google-Smtp-Source: APiQypLEU0k5ypfzjbekEehZjW+0nWw11TKZvAJmHQunB+frxXfA6r+IIcpon+arbt10Fk6dtCpFKQ== X-Received: by 2002:a05:6512:66:: with SMTP id i6mr14975334lfo.48.1585750913962; Wed, 01 Apr 2020 07:21:53 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:53 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:10 +0200 Message-Id: <20200401142127.13715-13-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 12/29] net/ena/base: fix types for printing timestamps X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Because ena_com is being used by multiple platforms which are using different C versions, PRIu64 cannot be used directly and must be defined in the platform file. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.c | 2 +- drivers/net/ena/base/ena_plat_dpdk.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index b7749209b3..45f1647699 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -2068,7 +2068,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) timestamp = (u64)aenq_common->timestamp_low | ((u64)aenq_common->timestamp_high << 32); ENA_TOUCH(timestamp); /* In case debug is disabled */ - ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%"PRIu64"]\n", + ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n", aenq_common->group, aenq_common->syndrom, timestamp); diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 2989df8f7e..c69426a062 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -309,5 +309,7 @@ void ena_rss_key_fill(void *key, size_t size); #define ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT 0 +#define ENA_PRIu64 PRIu64 + #include "ena_includes.h" #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */ From patchwork Wed Apr 1 14:21:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67598 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B17AA057B; Wed, 1 Apr 2020 16:24:02 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C4F1A1C045; Wed, 1 Apr 2020 16:21:57 +0200 (CEST) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by dpdk.org (Postfix) with ESMTP id CBEAD1BF4F for ; Wed, 1 Apr 2020 16:21:55 +0200 (CEST) Received: by mail-lj1-f193.google.com with SMTP id b1so5389744ljp.3 for ; Wed, 01 Apr 2020 07:21:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nlLsOBxFZOP6jpzMwj14vEMzQXXfKXh8UF45x0bBkf8=; b=alipajx0GmcDKGaa0qBMoXqqu1ixrKfLSun+HPaxrxTT/bUDr5HHk6q3cPpXsRd9hD BqUg0MruVp4B3x/lS56bjAk+09liMIckyWCSZgVpiDe35FOI2jEWZ83skcoeJ9WEk+jj ziTE/2q8qg4rfaQSK4BefcwSyf1pRnqpsDDFuTnup22vzGFRa+TQ3/icEZqDiMJx6nbP OPchsSKMYVh960XyPkrqB7+XSepxbaF+ACoKiJ4yrE0BTriQsJgJaRsET0YyqKXQzP5x e4W9snD9cTI2YO6yg/1e0gc/MC+gplPDnwwC62eBCsk/fTAoEg5ORUNClzdrN1TKjkTB Q3jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nlLsOBxFZOP6jpzMwj14vEMzQXXfKXh8UF45x0bBkf8=; b=DMeUYmS7OlcME/yYs0TMXYywtSQc/4LA2lfaMEajpeQW0qcwsnvKb639Esx/hm9APY zPo/evQdF7NQHJ9BxVzVREVDZe58Puv12/tRhVC1h9hTzKOC3rCZeqcD7EV9zIrRooYP r5iBM2IvPS6sCaOmENQA9japwNIMGXpnM8lCcH7X1/aDSeIUHNs3XEbxKXf8KZpsNtuH FkLc7oYUlXjNfznjQFGzOOOZdp+XW4Z/5hYimeRkG2FRIIEc6SJ+RJufV0k6XygiCoW2 zBSWp9x4SHL3K3y5CWLjZo97mWmMXmmBXxHCLTPT0vcZ9Sg9lahBWaEYYU5c6hgRLh8x YURg== X-Gm-Message-State: AGi0PuYEFCa5snBFHWAhtnUtLW39OTESb4Kh4Fv1QSuRmdjnAKE3nlC/ oyirKqsaiJS/zq1R7X4kZZAoKqpcJzk= X-Google-Smtp-Source: APiQypKlyJWnEcawmyHkd6hDpV43DORnpKDAjGaz5ZvKdYnrutrnQPHDmQIT3tFYq4fYdA6BHW9FFQ== X-Received: by 2002:a2e:8795:: with SMTP id n21mr13752700lji.71.1585750915226; Wed, 01 Apr 2020 07:21:55 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:54 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:11 +0200 Message-Id: <20200401142127.13715-14-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 13/29] net/ena/base: fix indentation of multiple defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As the alignemnt of the defines wasn't valid, it was removed at all, so instead of using multiple spaces or tabs, the single space after define name is being used. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index 9b87fa94e4..274c0cd9f5 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -8,9 +8,9 @@ #include "ena_plat.h" -#define ENA_MAX_NUM_IO_QUEUES 128U +#define ENA_MAX_NUM_IO_QUEUES 128U /* We need to queues for each IO (on for Tx and one for Rx) */ -#define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES)) +#define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES)) #define ENA_MAX_HANDLERS 256 @@ -33,9 +33,9 @@ #define ENA_HASH_KEY_SIZE 40 -#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF +#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF -#define ENA_FEATURE_MAX_QUEUE_EXT_VER 1 +#define ENA_FEATURE_MAX_QUEUE_EXT_VER 1 struct ena_llq_configurations { enum ena_admin_llq_header_location llq_header_location; From patchwork Wed Apr 1 14:21:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67599 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8ECD1A057B; Wed, 1 Apr 2020 16:24:15 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 99FEF1C0B6; Wed, 1 Apr 2020 16:21:59 +0200 (CEST) Received: from mail-lj1-f194.google.com (mail-lj1-f194.google.com [209.85.208.194]) by dpdk.org (Postfix) with ESMTP id 1665F1C033 for ; Wed, 1 Apr 2020 16:21:57 +0200 (CEST) Received: by mail-lj1-f194.google.com with SMTP id v16so1900594ljg.5 for ; Wed, 01 Apr 2020 07:21:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DfaLBBbYjRF7htP2pF0UB7UukHBPNOpfSKfixX1KGzY=; b=RLu/C4Abrd001t7fQrLSVvOwQMDpYFahJO+uc/KzV+tPi8G1qU5Ab2zSDPe+HN8Y+Z rU5FqK8EKFhrbe62NbjxI3a85QdnMw/lJyjHgZ3THjkhwIFeq32qozWucg1KGs0P5sfH 1GE7fmEStrnZcDhWq28yCn3cDBTeC9s6d3M91l9rxN8HFiuh5UVGxD3SsI6WwUVQq4LF gn7NQdJYp2YqJJhWcTunDIX6lgFGu7h3PQ/NkmADXA1oB9CKpZaN6IL7wYNuI6hVQ0qC qvBcv4Hf/FiunqWt2ULtMoAjqx6ojvXZzKBPQCWA4wOGKCWOGKlpWNK4kVKBUEnQ+XKS nyxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DfaLBBbYjRF7htP2pF0UB7UukHBPNOpfSKfixX1KGzY=; b=YiNQo9Dflbflh1Ufhl7WCKYiiL7wQ4q/qoG9d4iyx3DzIsdPvtN2IUSeVEodrWPZzK cDaoHWWeg7zBGOJ/fT89+KkAGnZ9ud4Cz17H16w9SUYm4RMveGLSsqXTartYjl8Gap3f EhbO4E76vgs5b2AiHDjuGdFmcojidmilFj/HYfmNlWYv1Y8cdWye264fSzoBooVEAO1U +ouKJpIrNsUHn9C70+upv4pzgsw5pfjmq6qqHXWACsJrqnwtH9Efli9v0P/9pHULrYQC U0sxkOtfvhH9LqGEIcZEEAplTyMhOg+udxUDeBxjUdwLXI6m79GjPZWPI+Rls7p1UDR1 C9fA== X-Gm-Message-State: AGi0PuaVSG7E5bgB8HwQ1aeGCPJA3011p/u08oydfQw9EunCyiLI4pGR w1h8PdKE6nbBi5Ood64ulh6lHgyWe4Q= X-Google-Smtp-Source: APiQypJyaiXzihy8wb712q9MtHqOqNh6BoCYKbIZBQvu3qD4TXEdoqaztxx8g+JBjE53fTL7EYGkzA== X-Received: by 2002:a05:651c:310:: with SMTP id a16mr12340346ljp.275.1585750916446; Wed, 01 Apr 2020 07:21:56 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:55 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:12 +0200 Message-Id: <20200401142127.13715-15-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 14/29] net/ena/base: update gen date and commit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The current ena_com version was generated on 25.09.2019. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_defs/ena_gen_info.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ena/base/ena_defs/ena_gen_info.h b/drivers/net/ena/base/ena_defs/ena_gen_info.h index 019b1fdb79..f486e9fe6e 100644 --- a/drivers/net/ena/base/ena_defs/ena_gen_info.h +++ b/drivers/net/ena/base/ena_defs/ena_gen_info.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates. + * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. * All rights reserved. */ -#define ENA_GEN_DATE "Wed Mar 20 10:40:42 STD 2019" -#define ENA_GEN_COMMIT "1476830" +#define ENA_GEN_DATE "Wed Sep 25 11:32:57 UTC 2019" +#define ENA_GEN_COMMIT "952697a9e0d3" From patchwork Wed Apr 1 14:21:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67600 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5453CA057B; Wed, 1 Apr 2020 16:24:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1F85D1C0C2; Wed, 1 Apr 2020 16:22:01 +0200 (CEST) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by dpdk.org (Postfix) with ESMTP id 688A51C08C for ; Wed, 1 Apr 2020 16:21:58 +0200 (CEST) Received: by mail-lj1-f193.google.com with SMTP id q19so25895199ljp.9 for ; Wed, 01 Apr 2020 07:21:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NF11IBWIaOn2+GIileSyCNBvfLqcWt+j6mIcrSCXPh8=; b=x7aRfjxwSUTC7KWPmQoeDzez34weBkmZkfO3fiUxjyQvsNx5T7K9PhBiAGdMsAXUR5 N/Kgzc9egKWCdFr65FYrojcWw2VrYyvud1Wjw5YkW7m91xD1uHmzjkF09UlOcZMfhHKe k08vQOxQKk4wkpTPKqpxNYCF0RYvijXTzPzgQSiDCIsj117i4HsFN3XMZqWq4BnDJ3tE qsxjAcffwLJewHMRTm8IvCb+JdUW2mV9l6IGXuzFjF6Uz0v8owLIGPgnJrPbclgv8DS7 JNZXNv4cAEae3YMA3aae08SRgYEoPa9zS65D4KFKUXaKQNYWf8E1ojp6h/E8oqLo6h/2 +7SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NF11IBWIaOn2+GIileSyCNBvfLqcWt+j6mIcrSCXPh8=; b=UonotkyAQ5C0IEoL5Eeu08jFN7wACa1miH9KmImAop+4Lg+/1Z7X/J9arZKo9d2eYo Agw9CbN9Ls7h3ACIBwPwHQwTHt6Lgn9tPZnl4JdN6Nh6//lO9cnPN8K5MqY6z+OS4yhD 1bxK00vhccdaXNp+hJM4msZVS3K0xbE6xzjKzbpMuSO24iCTkulujJQ8MbMSb5yz3wuv O2WNFuvkJCdiKXj8wMKvOmAuwxzuWI6rJIK7C/33mNbFbgv03lWW7ImiI9xNMXVKABmV NM8G9LBy8lhQ9K6dZ3kikaiLp580tjH+jxUQgagaY7ZG6ELnLPqWk/Znsy9f+Vgmr5Jt klng== X-Gm-Message-State: AGi0Puahd0X/01RlgJYYRGNfkuZfJAHfukU3HrDCcg09diIxhanh0yuq ZQxo8ZNKkoV4jU474oqXgP4oqk+D4Wo= X-Google-Smtp-Source: APiQypJQ6jCzQr7sD9cdQavCLmWQhRQulyg/b2JJh7AwxckfU7UFz9tuRlycsILEX5vyKeqj9sx4LA== X-Received: by 2002:a2e:b80a:: with SMTP id u10mr1151233ljo.109.1585750917735; Wed, 01 Apr 2020 07:21:57 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:57 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk , stable@dpdk.org Date: Wed, 1 Apr 2020 16:21:13 +0200 Message-Id: <20200401142127.13715-16-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 15/29] net/ena: set IO ring size to the valid value X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" IO rings were configured with the maximum allowed size for the Tx/Rx rings. However, the application could decide to create smaller rings. This patch is using value stored in the ring instead of the value from the adapter which is indicating the maximum allowed value. Fixes: df238f84c0a2 ("net/ena: recreate HW IO rings on start and stop") Cc: stable@dpdk.org Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/ena_ethdev.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 21c25b21b1..13a016227c 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -1099,16 +1099,15 @@ static int ena_create_io_queue(struct ena_ring *ring) ena_qid = ENA_IO_TXQ_IDX(ring->id); ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; ctx.mem_queue_type = ena_dev->tx_mem_queue_type; - ctx.queue_size = adapter->tx_ring_size; for (i = 0; i < ring->ring_size; i++) ring->empty_tx_reqs[i] = i; } else { ena_qid = ENA_IO_RXQ_IDX(ring->id); ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; - ctx.queue_size = adapter->rx_ring_size; for (i = 0; i < ring->ring_size; i++) ring->empty_rx_reqs[i] = i; } + ctx.queue_size = ring->ring_size; ctx.qid = ena_qid; ctx.msix_vector = -1; /* interrupts not used */ ctx.numa_node = ring->numa_socket_id; From patchwork Wed Apr 1 14:21:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67601 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C2D06A057B; Wed, 1 Apr 2020 16:24:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7B2231C0C6; Wed, 1 Apr 2020 16:22:02 +0200 (CEST) Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) by dpdk.org (Postfix) with ESMTP id E62981C0B9 for ; Wed, 1 Apr 2020 16:21:59 +0200 (CEST) Received: by mail-lj1-f177.google.com with SMTP id i20so25942555ljn.6 for ; Wed, 01 Apr 2020 07:21:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hDGCzM1oIFg1NlFR5A9HCpLpVF6z8RS+UEWSJ0JRBNw=; b=lq5avyxo3HObBCPiD9QUlmKNVcN+lhcLntqGZkPY3zwiWn+3dzzd9bUObio7rYBLvm 9qMbGR6QVKr7MdXsIZNSREETbTT9ie0tb4VQlRBxeIQN0Qs/rRvSyxvc3GEbRuXRc3Sb U/BGoSnJJy61UuRAXr9WQ7QBwkxnzVQX8unuGGTCACYmUOpyx2NwfbTWyQft8W9ewKDp 8AR6UItJSWRxEuKc0ljdBm3BW5exk5IeBvCl/KIu2M5hK93xh6gbaQpuotuE8jYq1OaW AM4gja0B8UYmvnrLK7/vKaGgvCdPrWjw3esIDy/+k86ZVX9CfvHXbdcJDn15wW3bVLFW AP9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hDGCzM1oIFg1NlFR5A9HCpLpVF6z8RS+UEWSJ0JRBNw=; b=GU2h8z0/GvioeilLayxaGRuVwnU4mpXLs+oVMxAgj7UmdmUosmwcyxiAPK4y7Sfd6I AFw76pf4yMGl3nHdcHJsiYAI4Zz/lZmtMp8xUAviuF8mMx09sP6L63fFyI+2xsjwgGKY f2yA66IGdCsf8tMf/uLZWX/fUMC5DzBq9MsMXJeMUiQUjkQOIUfoRX3HfeSIA277y4mR fjIq5bCM6aK/3MGmLhv1CV2NtIgxPk37MqoxYgO5gOaf8nF8zJgOh0qXBoJ54kPIXFes Bll8NYEOBZJo1axP14lpV+5JhuHjhoDRErOa3IP8VkI+eYnztE1PNPn2YwbivytJvWfN akLQ== X-Gm-Message-State: AGi0PuZAlWOcM/CZOb9LHnu4cQv7pWh+CSCci6kRVWudBNucVqp9ZTRD XzvlqqsbFY+IJMuGZmLDVlibcw3SQ4o= X-Google-Smtp-Source: APiQypIw9B0VCPTkz0hTrg9puswikCGFqnS/iRNgufimT2Dm2WkkBoCR5QapkmDmhgW6xMrtlX1SqQ== X-Received: by 2002:a2e:6809:: with SMTP id c9mr13013120lja.251.1585750919069; Wed, 01 Apr 2020 07:21:59 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:58 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:14 +0200 Message-Id: <20200401142127.13715-17-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 16/29] net/ena: refactor getting IO queues capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Reading values from the device is about the maximum capabilities of the device. Because of that, the names of the fields storing those values, functions and temporary variables, should be more descriptive in order to improve self documentation fo the code. In connection with this, the way of getting maximum queue size could be simplified - no hardcoded values are needed, as the device is going to send it's capabilities anyway. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/ena_ethdev.c | 101 ++++++++++++++++------------------- drivers/net/ena/ena_ethdev.h | 11 ++-- 2 files changed, 52 insertions(+), 60 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 13a016227c..d5f700093f 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -82,9 +82,6 @@ struct ena_stats { #define ENA_STAT_GLOBAL_ENTRY(stat) \ ENA_STAT_ENTRY(stat, dev) -#define ENA_MAX_RING_SIZE_RX 8192 -#define ENA_MAX_RING_SIZE_TX 1024 - /* * Each rte_memzone should have unique name. * To satisfy it, count number of allocation and add it to name. @@ -845,29 +842,26 @@ static int ena_check_valid_conf(struct ena_adapter *adapter) } static int -ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx) +ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx) { struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; struct ena_com_dev *ena_dev = ctx->ena_dev; - uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX; - uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX; + uint32_t max_tx_queue_size; + uint32_t max_rx_queue_size; if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { struct ena_admin_queue_ext_feature_fields *max_queue_ext = &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; - rx_queue_size = RTE_MIN(rx_queue_size, - max_queue_ext->max_rx_cq_depth); - rx_queue_size = RTE_MIN(rx_queue_size, + max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth, max_queue_ext->max_rx_sq_depth); - tx_queue_size = RTE_MIN(tx_queue_size, - max_queue_ext->max_tx_cq_depth); + max_tx_queue_size = max_queue_ext->max_tx_cq_depth; if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { - tx_queue_size = RTE_MIN(tx_queue_size, + max_tx_queue_size = RTE_MIN(max_tx_queue_size, llq->max_llq_depth); } else { - tx_queue_size = RTE_MIN(tx_queue_size, + max_tx_queue_size = RTE_MIN(max_tx_queue_size, max_queue_ext->max_tx_sq_depth); } @@ -878,39 +872,36 @@ ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx) } else { struct ena_admin_queue_feature_desc *max_queues = &ctx->get_feat_ctx->max_queues; - rx_queue_size = RTE_MIN(rx_queue_size, - max_queues->max_cq_depth); - rx_queue_size = RTE_MIN(rx_queue_size, + max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth, max_queues->max_sq_depth); - tx_queue_size = RTE_MIN(tx_queue_size, - max_queues->max_cq_depth); + max_tx_queue_size = max_queues->max_cq_depth; if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { - tx_queue_size = RTE_MIN(tx_queue_size, + max_tx_queue_size = RTE_MIN(max_tx_queue_size, llq->max_llq_depth); } else { - tx_queue_size = RTE_MIN(tx_queue_size, + max_tx_queue_size = RTE_MIN(max_tx_queue_size, max_queues->max_sq_depth); } ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, - max_queues->max_packet_tx_descs); - ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, max_queues->max_packet_rx_descs); + ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, + max_queues->max_packet_tx_descs); } /* Round down to the nearest power of 2 */ - rx_queue_size = rte_align32prevpow2(rx_queue_size); - tx_queue_size = rte_align32prevpow2(tx_queue_size); + max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size); + max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size); - if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) { + if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) { PMD_INIT_LOG(ERR, "Invalid queue size"); return -EFAULT; } - ctx->rx_queue_size = rx_queue_size; - ctx->tx_queue_size = tx_queue_size; + ctx->max_tx_queue_size = max_tx_queue_size; + ctx->max_rx_queue_size = max_rx_queue_size; return 0; } @@ -1230,15 +1221,15 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev, return -EINVAL; } - if (nb_desc > adapter->tx_ring_size) { + if (nb_desc > adapter->max_tx_ring_size) { PMD_DRV_LOG(ERR, "Unsupported size of TX queue (max size: %d)\n", - adapter->tx_ring_size); + adapter->max_tx_ring_size); return -EINVAL; } if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) - nb_desc = adapter->tx_ring_size; + nb_desc = adapter->max_tx_ring_size; txq->port_id = dev->data->port_id; txq->next_to_clean = 0; @@ -1310,7 +1301,7 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, } if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) - nb_desc = adapter->rx_ring_size; + nb_desc = adapter->max_rx_ring_size; if (!rte_is_power_of_2(nb_desc)) { PMD_DRV_LOG(ERR, @@ -1319,10 +1310,10 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, return -EINVAL; } - if (nb_desc > adapter->rx_ring_size) { + if (nb_desc > adapter->max_rx_ring_size) { PMD_DRV_LOG(ERR, "Unsupported size of RX queue (max size: %d)\n", - adapter->rx_ring_size); + adapter->max_rx_ring_size); return -EINVAL; } @@ -1654,10 +1645,10 @@ ena_set_queues_placement_policy(struct ena_adapter *adapter, return 0; } -static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev, - struct ena_com_dev_get_features_ctx *get_feat_ctx) +static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, + struct ena_com_dev_get_features_ctx *get_feat_ctx) { - uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num; + uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues; /* Regular queues capabilities */ if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { @@ -1679,16 +1670,16 @@ static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev, if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) io_tx_sq_num = get_feat_ctx->llq.max_llq_num; - io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); - io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num); - io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num); + max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); + max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num); + max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num); - if (unlikely(io_queue_num == 0)) { + if (unlikely(max_num_io_queues == 0)) { PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n"); return -EFAULT; } - return io_queue_num; + return max_num_io_queues; } static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) @@ -1701,6 +1692,7 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) struct ena_com_dev_get_features_ctx get_feat_ctx; struct ena_llq_configurations llq_config; const char *queue_type_str; + uint32_t max_num_io_queues; int rc; static int adapters_found; @@ -1772,20 +1764,19 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) calc_queue_ctx.ena_dev = ena_dev; calc_queue_ctx.get_feat_ctx = &get_feat_ctx; - adapter->num_queues = ena_calc_io_queue_num(ena_dev, - &get_feat_ctx); - rc = ena_calc_queue_size(&calc_queue_ctx); - if (unlikely((rc != 0) || (adapter->num_queues <= 0))) { + max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx); + rc = ena_calc_io_queue_size(&calc_queue_ctx); + if (unlikely((rc != 0) || (max_num_io_queues == 0))) { rc = -EFAULT; goto err_device_destroy; } - adapter->tx_ring_size = calc_queue_ctx.tx_queue_size; - adapter->rx_ring_size = calc_queue_ctx.rx_queue_size; - + adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size; + adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size; adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; + adapter->max_num_io_queues = max_num_io_queues; /* prepare ring structures */ ena_init_rings(adapter); @@ -1904,9 +1895,9 @@ static int ena_dev_configure(struct rte_eth_dev *dev) static void ena_init_rings(struct ena_adapter *adapter) { - int i; + size_t i; - for (i = 0; i < adapter->num_queues; i++) { + for (i = 0; i < adapter->max_num_io_queues; i++) { struct ena_ring *ring = &adapter->tx_ring[i]; ring->configured = 0; @@ -1918,7 +1909,7 @@ static void ena_init_rings(struct ena_adapter *adapter) ring->sgl_size = adapter->max_tx_sgl_size; } - for (i = 0; i < adapter->num_queues; i++) { + for (i = 0; i < adapter->max_num_io_queues; i++) { struct ena_ring *ring = &adapter->rx_ring[i]; ring->configured = 0; @@ -1982,21 +1973,21 @@ static int ena_infos_get(struct rte_eth_dev *dev, dev_info->max_rx_pktlen = adapter->max_mtu; dev_info->max_mac_addrs = 1; - dev_info->max_rx_queues = adapter->num_queues; - dev_info->max_tx_queues = adapter->num_queues; + dev_info->max_rx_queues = adapter->max_num_io_queues; + dev_info->max_tx_queues = adapter->max_num_io_queues; dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; adapter->tx_supported_offloads = tx_feat; adapter->rx_supported_offloads = rx_feat; - dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size; + dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size; dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, adapter->max_rx_sgl_size); dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, adapter->max_rx_sgl_size); - dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size; + dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size; dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, adapter->max_tx_sgl_size); diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index c1457defeb..99d1fba64d 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -21,6 +21,7 @@ #define ENA_NAME_MAX_LEN 20 #define ENA_PKT_MAX_BUFS 17 #define ENA_RX_BUF_MIN_SIZE 1400 +#define ENA_DEFAULT_RING_SIZE 1024 #define ENA_MIN_MTU 128 @@ -46,8 +47,8 @@ struct ena_tx_buffer { struct ena_calc_queue_size_ctx { struct ena_com_dev_get_features_ctx *get_feat_ctx; struct ena_com_dev *ena_dev; - u16 rx_queue_size; - u16 tx_queue_size; + u32 max_rx_queue_size; + u32 max_tx_queue_size; u16 max_tx_sgl_size; u16 max_rx_sgl_size; }; @@ -159,15 +160,15 @@ struct ena_adapter { /* TX */ struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; - int tx_ring_size; + u32 max_tx_ring_size; u16 max_tx_sgl_size; /* RX */ struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; - int rx_ring_size; + u32 max_rx_ring_size; u16 max_rx_sgl_size; - u16 num_queues; + u32 max_num_io_queues; u16 max_mtu; struct ena_offloads offloads; From patchwork Wed Apr 1 14:21:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67602 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BC809A057B; Wed, 1 Apr 2020 16:24:46 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E390F1BF3C; Wed, 1 Apr 2020 16:22:04 +0200 (CEST) Received: from mail-lf1-f66.google.com (mail-lf1-f66.google.com [209.85.167.66]) by dpdk.org (Postfix) with ESMTP id 426FE1C0C4 for ; Wed, 1 Apr 2020 16:22:01 +0200 (CEST) Received: by mail-lf1-f66.google.com with SMTP id z23so20664827lfh.8 for ; Wed, 01 Apr 2020 07:22:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qBHkCw9e1fePcIJAtEjstphm7hWxoxovMDilapUPYnc=; b=Wj2OVgRbUN67LZygJQno80tWEm/mPqoFHGzHj8rsSsH8z0MeUw+jeJFUOcq37G0rDJ veUVeM0YrpDDxljSYn1/asn+sQwLRUy6g4LiIGcNygVFY/k2P6vQxXcyZ8rPuLxAzXFm MmUC+jJZpcFZuUZLQece0Cl8JcHKxMMVT/yorExOlqynjcfDzoN62jIGgmxGiG1rJh/j 8YZeA3uSxMGjOnNhOoTVpLtA8tKKOpLJkFddiDMH9MSUKRdlrVcQrJFn7umnHNNxmA6d LgbNKjS363aZiCfCXNBPOSmo6Y3kIfdk8W6Jc42RI+ZWQObpESxLgCUvUhWVTGmaWF5O YNtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qBHkCw9e1fePcIJAtEjstphm7hWxoxovMDilapUPYnc=; b=K39y3LWswQ6UJF6LWHjYa7kUa4GAx2+5sRCPs0O/b9NeWjFXVwMvLfxkFKaGjJzDVL aGIX6vNjhu7T+kFEyx1dp2R2B5BRkDHcO+i2xLuU464BEC3WlpzpOeBeWI40ui5Uek4Z 9VaCCLwmiU9FmfhanjNlpAiZHTQ9J/yqs6bdJoqdt8GPEmdIhiNbq1jCt4BRrIgT6UT2 2wrkiahqkAdYUgVVFeXmyzU1jH050GvYTuHmhiWkOO+tqnD0IGR8wKDQl9uD+hniv75v eAn41WGndNFcQswmbIAGJat63gF2do+9bTXLbw92h62VbDJkdVl71qHqqwSGt11af1P7 VlKg== X-Gm-Message-State: AGi0Pub9XvfCiAAeSn7G9qWghVn3/Y+rrwkB6juoXPu3NP1FY2Tt07ao Y+48qnbjWJGbv5+DIxu+PMQMFJBGhvg= X-Google-Smtp-Source: APiQypIkMm7dYhYOi+YXujunLtG+AGtuqWXNyMYZy7pf21GB2B/3gxlyjI0gfFrzwE8MhejiOCNxcQ== X-Received: by 2002:ac2:4426:: with SMTP id w6mr1032215lfl.8.1585750920409; Wed, 01 Apr 2020 07:22:00 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:59 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:15 +0200 Message-Id: <20200401142127.13715-18-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 17/29] net/ena: add support for large LLQ headers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" If the device supports larger LLQ (Low Latency Queue) headers, the user can activate them by enabling CONFIG_RTE_LIBRTE_ENA_LARGE_LLQ_HEADERS flag in the configuration file. If the device isn't supporting this feature, the default value will be used. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- v2: * Use devargs instead of compilation options doc/guides/nics/ena.rst | 8 +++ drivers/net/ena/ena_ethdev.c | 110 +++++++++++++++++++++++++++++++++-- drivers/net/ena/ena_ethdev.h | 2 + 3 files changed, 114 insertions(+), 6 deletions(-) diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst index bbf27f235a..d5081e91e5 100644 --- a/doc/guides/nics/ena.rst +++ b/doc/guides/nics/ena.rst @@ -95,6 +95,14 @@ Configuration information * **CONFIG_RTE_LIBRTE_ENA_COM_DEBUG** (default n): Enables or disables debug logging of low level tx/rx logic in ena_com(base) within the ENA PMD driver. +**Runtime Configuration Parameters** + + * **large_llq_hdr** (default 0) + + Enables or disables usage of large LLQ headers. This option will have + effect only if the device also supports large LLQ headers. Otherwise, the + default value will be used. + **ENA Configuration Parameters** * **Number of Queues** diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index d5f700093f..f23efbe464 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "ena_ethdev.h" #include "ena_logs.h" @@ -82,6 +83,9 @@ struct ena_stats { #define ENA_STAT_GLOBAL_ENTRY(stat) \ ENA_STAT_ENTRY(stat, dev) +/* Device arguments */ +#define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr" + /* * Each rte_memzone should have unique name. * To satisfy it, count number of allocation and add it to name. @@ -231,6 +235,11 @@ static int ena_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, uint64_t *values, unsigned int n); +static int ena_process_bool_devarg(const char *key, + const char *value, + void *opaque); +static int ena_parse_devargs(struct ena_adapter *adapter, + struct rte_devargs *devargs); static const struct eth_dev_ops ena_dev_ops = { .dev_configure = ena_dev_configure, @@ -842,7 +851,8 @@ static int ena_check_valid_conf(struct ena_adapter *adapter) } static int -ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx) +ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, + bool use_large_llq_hdr) { struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; struct ena_com_dev *ena_dev = ctx->ena_dev; @@ -895,6 +905,21 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx) max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size); max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size); + if (use_large_llq_hdr) { + if ((llq->entry_size_ctrl_supported & + ENA_ADMIN_LIST_ENTRY_SIZE_256B) && + (ena_dev->tx_mem_queue_type == + ENA_ADMIN_PLACEMENT_POLICY_DEV)) { + max_tx_queue_size /= 2; + PMD_INIT_LOG(INFO, + "Forcing large headers and decreasing maximum TX queue size to %d\n", + max_tx_queue_size); + } else { + PMD_INIT_LOG(ERR, + "Forcing large headers failed: LLQ is disabled or device does not support large headers\n"); + } + } + if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) { PMD_INIT_LOG(ERR, "Invalid queue size"); return -EFAULT; @@ -1594,14 +1619,25 @@ static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, } static inline void -set_default_llq_configurations(struct ena_llq_configurations *llq_config) +set_default_llq_configurations(struct ena_llq_configurations *llq_config, + struct ena_admin_feature_llq_desc *llq, + bool use_large_llq_hdr) { llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; - llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B; llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; llq_config->llq_num_decs_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; - llq_config->llq_ring_entry_size_value = 128; + + if (use_large_llq_hdr && + (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) { + llq_config->llq_ring_entry_size = + ENA_ADMIN_LIST_ENTRY_SIZE_256B; + llq_config->llq_ring_entry_size_value = 256; + } else { + llq_config->llq_ring_entry_size = + ENA_ADMIN_LIST_ENTRY_SIZE_128B; + llq_config->llq_ring_entry_size_value = 128; + } } static int @@ -1740,6 +1776,12 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", adapter->id_number); + rc = ena_parse_devargs(adapter, pci_dev->device.devargs); + if (rc != 0) { + PMD_INIT_LOG(CRIT, "Failed to parse devargs\n"); + goto err; + } + /* device specific initialization routine */ rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); if (rc) { @@ -1748,7 +1790,8 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) } adapter->wd_state = wd_state; - set_default_llq_configurations(&llq_config); + set_default_llq_configurations(&llq_config, &get_feat_ctx.llq, + adapter->use_large_llq_hdr); rc = ena_set_queues_placement_policy(adapter, ena_dev, &get_feat_ctx.llq, &llq_config); if (unlikely(rc)) { @@ -1766,7 +1809,8 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) calc_queue_ctx.get_feat_ctx = &get_feat_ctx; max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx); - rc = ena_calc_io_queue_size(&calc_queue_ctx); + rc = ena_calc_io_queue_size(&calc_queue_ctx, + adapter->use_large_llq_hdr); if (unlikely((rc != 0) || (max_num_io_queues == 0))) { rc = -EFAULT; goto err_device_destroy; @@ -2582,6 +2626,59 @@ static int ena_xstats_get_by_id(struct rte_eth_dev *dev, return valid; } +static int ena_process_bool_devarg(const char *key, + const char *value, + void *opaque) +{ + struct ena_adapter *adapter = opaque; + bool bool_value; + + /* Parse the value. */ + if (strcmp(value, "1") == 0) { + bool_value = true; + } else if (strcmp(value, "0") == 0) { + bool_value = false; + } else { + PMD_INIT_LOG(ERR, + "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n", + value, key); + return -EINVAL; + } + + /* Now, assign it to the proper adapter field. */ + if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0) + adapter->use_large_llq_hdr = bool_value; + + return 0; +} + +static int ena_parse_devargs(struct ena_adapter *adapter, + struct rte_devargs *devargs) +{ + static const char * const allowed_args[] = { + ENA_DEVARG_LARGE_LLQ_HDR, + }; + struct rte_kvargs *kvlist; + int rc; + + if (devargs == NULL) + return 0; + + kvlist = rte_kvargs_parse(devargs->args, allowed_args); + if (kvlist == NULL) { + PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n", + devargs->args); + return -EINVAL; + } + + rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR, + ena_process_bool_devarg, adapter); + + rte_kvargs_free(kvlist); + + return rc; +} + /********************************************************************* * PMD configuration *********************************************************************/ @@ -2608,6 +2705,7 @@ static struct rte_pci_driver rte_ena_pmd = { RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>"); RTE_INIT(ena_init_log) { diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 99d1fba64d..0e82c894f4 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -200,6 +200,8 @@ struct ena_adapter { bool trigger_reset; bool wd_state; + + bool use_large_llq_hdr; }; #endif /* _ENA_ETHDEV_H_ */ From patchwork Wed Apr 1 14:21:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67603 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9E178A057B; Wed, 1 Apr 2020 16:24:56 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 101B51C0CC; Wed, 1 Apr 2020 16:22:06 +0200 (CEST) Received: from mail-lf1-f68.google.com (mail-lf1-f68.google.com [209.85.167.68]) by dpdk.org (Postfix) with ESMTP id A90681C0C9 for ; Wed, 1 Apr 2020 16:22:02 +0200 (CEST) Received: by mail-lf1-f68.google.com with SMTP id c5so20629099lfp.5 for ; Wed, 01 Apr 2020 07:22:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7e/G8SwLdNk53EZwud8jbWyb19eYNdidQ7LgI7XLSm8=; b=u5WLzScYkN+BkS9LvzeWvJ4YKfszq0sWiAYGefqpLARW/HyhZK9LBC4TI5jGeTGCfZ CNC6kIIS7nLYoS5/qTokdcoapS4h4hDk0FQ0lRyGTDHAZUEHsXKc4HeE9HXw1W4K/GSD 0g1RcUuwvvufGxBrqahHd8XmgmvXN+8RG6rYoO1iT3twgHFmrrRo36xZ6qofUeyGwzDW 8AQy+Oz8cOUghw1YzyTZdBcBgExsGd6sYfZ+XvKewmBHmHmUC6cA5vUzsVSSzZInjn1I N1+Ygq8aWsOeYUM+VLrk79tVmibIclEAd3dgs2LSKLYoY3b1NU2acjYDmyP2UpCwNJqs vTjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7e/G8SwLdNk53EZwud8jbWyb19eYNdidQ7LgI7XLSm8=; b=tgygpDLOMsIMC70g2YLxUKqX7cojw0cOH4REvrTPD4y/XOnhZy/MpQ/wfOvtZsVd7J fRA8kxzxmoyPIiQRC+3ZrtWCrudienDsnVg+wjWteTNHo8k5nU1Rkc7VZQon6KBsHsrG StehN2T9dONbOT+FqgPIzSOVQ/Vi6bH3VNQhoEjKEDBQ7RoftBiEVEm3Gv1FvyfGOeee 6hu9CD/fGrGicMUzqmgAZ/cTDSbyq6Avy/GYx+DGA3DWYK98L1TDF1N5GY2SySHIiw8X wZ+E9VkZeefvOmJu6lg4wDPiw7p5DtBWCNRB0FnMg/E6Lc737bi6lU17X2CB/WVfNzol kPpg== X-Gm-Message-State: AGi0Pua8LV3nNiD7aj93BiJ7GAXLsUraBJ8/GXeBiM5EOzt95SyLits6 fxKCgLyBaKeNhBLFhmp3hJ5xPkPf2lo= X-Google-Smtp-Source: APiQypKEfxnkW4tf8KnByQ16U4KC1Wa59bQsVsKBl+x/oRztzTvWim8t+u6E0H0oYjqRpRpwyA+FpQ== X-Received: by 2002:a05:6512:48e:: with SMTP id v14mr14419549lfq.35.1585750921771; Wed, 01 Apr 2020 07:22:01 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:00 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:16 +0200 Message-Id: <20200401142127.13715-19-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 18/29] net/ena: remove memory barriers before doorbells X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The doorbell code is already issuing the doorbell by using rte_write. Because of that, there is no need to do that before calling the function. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/ena_ethdev.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index f23efbe464..eb97c80660 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -1462,12 +1462,7 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) /* When we submitted free recources to device... */ if (likely(i > 0)) { - /* ...let HW know that it can fill buffers with data - * - * Add memory barrier to make sure the desc were written before - * issue a doorbell - */ - rte_wmb(); + /* ...let HW know that it can fill buffers with data. */ ena_com_write_sq_doorbell(rxq->ena_com_io_sq); rxq->next_to_use = next_to_use; @@ -2405,7 +2400,6 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d" " achieved, writing doorbell to send burst\n", tx_ring->id); - rte_wmb(); ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); } @@ -2428,7 +2422,6 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, /* If there are ready packets to be xmitted... */ if (sent_idx > 0) { /* ...let HW do its best :-) */ - rte_wmb(); ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); tx_ring->tx_stats.doorbells++; tx_ring->next_to_use = next_to_use; From patchwork Wed Apr 1 14:21:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67604 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3BDBEA057B; Wed, 1 Apr 2020 16:25:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5DB991C0D4; Wed, 1 Apr 2020 16:22:07 +0200 (CEST) Received: from mail-lf1-f68.google.com (mail-lf1-f68.google.com [209.85.167.68]) by dpdk.org (Postfix) with ESMTP id E63B61C0CB for ; Wed, 1 Apr 2020 16:22:03 +0200 (CEST) Received: by mail-lf1-f68.google.com with SMTP id x200so13457706lff.0 for ; Wed, 01 Apr 2020 07:22:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dO1Nn0Ir82+T4hZw005gto/tMetTXzKV5ZtZiOGDbSk=; b=iyB37Oljm6vAHU8IT25sNm8UYyJIly+NbOR34x1/5rKgEjEB5tGg/cC85rRQMJHWoq /IbrzWZ93cJOcQIRLtq7uGJt1H0RQX2e2jsqvWKFZsl/2OCVUDIpk8CgpJrpaFSW92uA ZSGoGjsVxrCaOExENKJcycitkuE2hOjut/nYCmwAMVyaNbKjysp98S52oNGPyNf5ruBA 5e4Ryz6BW1RQ9M/1CT/QfLVJQduj2MmZ2Iuq1ng7ZOc3nqC8N/cJD/MbjBacuTuz1Kuf jd00vS4Z9PFNy0g3LgO8YfUQepOQcA0EfTG/IQZXz6Bz+9Vw2QK1uKYV2WNXAyC1NpuL IPHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dO1Nn0Ir82+T4hZw005gto/tMetTXzKV5ZtZiOGDbSk=; b=VqB07AKs1O3jsnEtX9JA6u6OSSt5vY5r8VWvuftuf6WPoJioSDH9nU6TP5o1By/zDN ShYdUq1l+0fqUjltvoANU4z+GwOPmWNyIjiYDtTWmcOwmpcntCLLWsp5y6+Pr4wycaqs WaixmAn1ccbDHRy5fR6uHNUit1ObKeNx3wCZqcNpLNmdQfCQ6G7zJNZN9gXsW8Esvxmn jqSe1nRj/xvRfvi/5hd6TXuOYgVkuL6r31kjij5QtkEPkpNUtBcWyC6D+DT6VX7ewjfF 2KDSR8OE5Fby0o7nQLcL3Q2TXsmx9mIBMGaBqftYMVOzYH2I5HfkmVHLQdeP+m4scd+Z 037w== X-Gm-Message-State: AGi0PuaU0uw3OKJcZCJ+jI39b/XdP3P2r0PXy42qEI+fsNXY0EkTg1mL Zun1inYdAgPVxlXc7+FjLL77oDpe02o= X-Google-Smtp-Source: APiQypKjRA2S6uMStl3kMWt/HdqToXCv+KjaXVNWdySaCr3NT316AKM+VyMZA2bgxYLZ+wK5LpqFRQ== X-Received: by 2002:a19:c304:: with SMTP id t4mr15427810lff.177.1585750923235; Wed, 01 Apr 2020 07:22:03 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:02 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:17 +0200 Message-Id: <20200401142127.13715-20-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 19/29] net/ena: add Tx drops statistic X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" ENA device can report in the AENQ handler amount of Tx packets that were dropped and not sent. This statistic is showing global value for the device and because rte_eth_stats is missing field that could indicate this value (it isn't the Tx error), it is being presented as a extended statistic. As the current design of extended statistics prevents tx_drops from being an atomic variable and both tx_drops and rx_drops are only updated from the AENQ handler, both were set as non-atomic for the alignment. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/ena_ethdev.c | 11 ++++++++--- drivers/net/ena/ena_ethdev.h | 8 +++++++- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index eb97c80660..b7cdc5711c 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -96,6 +96,7 @@ static const struct ena_stats ena_stats_global_strings[] = { ENA_STAT_GLOBAL_ENTRY(wd_expired), ENA_STAT_GLOBAL_ENTRY(dev_start), ENA_STAT_GLOBAL_ENTRY(dev_stop), + ENA_STAT_GLOBAL_ENTRY(tx_drops), }; static const struct ena_stats ena_stats_tx_strings[] = { @@ -938,7 +939,7 @@ static void ena_stats_restart(struct rte_eth_dev *dev) rte_atomic64_init(&adapter->drv_stats->ierrors); rte_atomic64_init(&adapter->drv_stats->oerrors); rte_atomic64_init(&adapter->drv_stats->rx_nombuf); - rte_atomic64_init(&adapter->drv_stats->rx_drops); + adapter->drv_stats->rx_drops = 0; } static int ena_stats_get(struct rte_eth_dev *dev, @@ -972,7 +973,7 @@ static int ena_stats_get(struct rte_eth_dev *dev, ena_stats.tx_bytes_low); /* Driver related stats */ - stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops); + stats->imissed = adapter->drv_stats->rx_drops; stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); @@ -2785,12 +2786,16 @@ static void ena_keep_alive(void *adapter_data, struct ena_adapter *adapter = adapter_data; struct ena_admin_aenq_keep_alive_desc *desc; uint64_t rx_drops; + uint64_t tx_drops; adapter->timestamp_wd = rte_get_timer_cycles(); desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; - rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops); + tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low; + + adapter->drv_stats->rx_drops = rx_drops; + adapter->dev_stats.tx_drops = tx_drops; } /** diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 0e82c894f4..9558ee072f 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -134,13 +134,19 @@ struct ena_driver_stats { rte_atomic64_t ierrors; rte_atomic64_t oerrors; rte_atomic64_t rx_nombuf; - rte_atomic64_t rx_drops; + u64 rx_drops; }; struct ena_stats_dev { u64 wd_expired; u64 dev_start; u64 dev_stop; + /* + * Tx drops cannot be reported as the driver statistic, because DPDK + * rte_eth_stats structure isn't providing appropriate field for that. + * As a workaround it is being published as an extended statistic. + */ + u64 tx_drops; }; struct ena_offloads { From patchwork Wed Apr 1 14:21:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67605 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F01BA057B; Wed, 1 Apr 2020 16:25:21 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 595631C112; Wed, 1 Apr 2020 16:22:09 +0200 (CEST) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by dpdk.org (Postfix) with ESMTP id 34C971C08E for ; Wed, 1 Apr 2020 16:22:05 +0200 (CEST) Received: by mail-lj1-f193.google.com with SMTP id f20so25981061ljm.0 for ; Wed, 01 Apr 2020 07:22:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tvQBM7ntWz2uYqEbW/7EP3JPPwcFl/o0aiMWadMzzcQ=; b=dYo1AsBZIYUm+CRRELofZKkNfIZdVciE88YgL520l4IZPt8e7C+g6kVJfj4rnsImmr hSgQZrkwLtNrvKAtaa6WSUwmft8SGGb9EB4OQrg1ALvqdnOvHs5VnQrR/+QTIpHHvnTC imHIS78+2APFEa/K8yeuMye+BF0FMUSXvwpTaIDYXX+qGLNsPtHYPRKeTO2TmobTjbX/ 9f5NFQE3ve1K/n/W5PwMQRGtM3La2d5rn+SILbplHQ6mr+B97ZuOnIMZK5Ye9vgMbYh7 rR+CMc9emYSYiPVCywR+A5xVnxIhp9P8xkd8W+CIV7wOclMlId1n+P7ARJcS4rmP6THG gKqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tvQBM7ntWz2uYqEbW/7EP3JPPwcFl/o0aiMWadMzzcQ=; b=VkF71MQxcQ1q37VKSVwb1XuwS1rOjEGwZP9EvnpcP6lFtQgx6WC3pD5Fo/V88eW+um u/TrkvAd7zfJQ7XfWSZoRUj+QFFQXpYn0OUPXeiG3lQ82BVpCJbEQWHjfxV4qEt2Zxi8 AdfFWMU2lc7G5iq0DYeR9cSgrCs2YnEgR+Gox4si6i4Ag2TSIOugw6cbVE3vkVkWhkTB lw1gVw8LPQVVVwoVdIxb2bLHpilBCYE3FxDVJbkw4xTipyMp85hQ3PSBjePPSVWHf8dO i2tX9wV0uH/3I0WWON3wSFUNIrGYAwQIBIloLdb1gXkguQlIjf0wR/dBTObhjwPz1XDV kPEA== X-Gm-Message-State: AGi0PubzVg4QASKEiVQAjxRMROneP1Me3EJ/aQbTYFxznCiY6VmZVWgD 5tv7psqe9ghMFK4E2BPS1n9iSZxU+Tk= X-Google-Smtp-Source: APiQypJdhjdBMwwO7i5mcZinfNimDo5nxdSm5UZJv/vY6lOHOOsF+AEgQnYQoLxJBu5BJAVJBUjUew== X-Received: by 2002:a2e:151e:: with SMTP id s30mr13429935ljd.92.1585750924520; Wed, 01 Apr 2020 07:22:04 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:03 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:18 +0200 Message-Id: <20200401142127.13715-21-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 20/29] net/ena: disable meta caching X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In the LLQ mode, the device can indicate that meta data descriptor caching is disabled. In that case the driver should send valid meta descriptor on every Tx packet. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/ena_ethdev.c | 28 ++++++++++++++++++++++------ drivers/net/ena/ena_ethdev.h | 2 ++ 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index b7cdc5711c..64c91531a7 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -191,7 +191,8 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); -static void ena_init_rings(struct ena_adapter *adapter); +static void ena_init_rings(struct ena_adapter *adapter, + bool disable_meta_caching); static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); static int ena_start(struct rte_eth_dev *dev); static void ena_stop(struct rte_eth_dev *dev); @@ -313,7 +314,8 @@ static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, struct ena_com_tx_ctx *ena_tx_ctx, - uint64_t queue_offloads) + uint64_t queue_offloads, + bool disable_meta_caching) { struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; @@ -363,6 +365,9 @@ static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, ena_meta->l3_hdr_len = mbuf->l3_len; ena_meta->l3_hdr_offset = mbuf->l2_len; + ena_tx_ctx->meta_valid = true; + } else if (disable_meta_caching) { + memset(ena_meta, 0, sizeof(*ena_meta)); ena_tx_ctx->meta_valid = true; } else { ena_tx_ctx->meta_valid = false; @@ -1726,8 +1731,8 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) const char *queue_type_str; uint32_t max_num_io_queues; int rc; - static int adapters_found; + bool disable_meta_caching; bool wd_state; eth_dev->dev_ops = &ena_dev_ops; @@ -1818,8 +1823,16 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; adapter->max_num_io_queues = max_num_io_queues; + if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { + disable_meta_caching = + !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags & + BIT(ENA_ADMIN_DISABLE_META_CACHING)); + } else { + disable_meta_caching = false; + } + /* prepare ring structures */ - ena_init_rings(adapter); + ena_init_rings(adapter, disable_meta_caching); ena_config_debug_area(adapter); @@ -1933,7 +1946,8 @@ static int ena_dev_configure(struct rte_eth_dev *dev) return 0; } -static void ena_init_rings(struct ena_adapter *adapter) +static void ena_init_rings(struct ena_adapter *adapter, + bool disable_meta_caching) { size_t i; @@ -1947,6 +1961,7 @@ static void ena_init_rings(struct ena_adapter *adapter) ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; ring->sgl_size = adapter->max_tx_sgl_size; + ring->disable_meta_caching = disable_meta_caching; } for (i = 0; i < adapter->max_num_io_queues; i++) { @@ -2359,7 +2374,8 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, } /* there's no else as we take advantage of memset zeroing */ /* Set TX offloads flags, if applicable */ - ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads); + ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads, + tx_ring->disable_meta_caching); rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]); diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 9558ee072f..99191ac3e7 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -113,6 +113,8 @@ struct ena_ring { uint64_t offloads; u16 sgl_size; + bool disable_meta_caching; + union { struct ena_stats_rx rx_stats; struct ena_stats_tx tx_stats; From patchwork Wed Apr 1 14:21:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67606 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 19E4BA057B; Wed, 1 Apr 2020 16:25:32 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BD26B1C10A; Wed, 1 Apr 2020 16:22:11 +0200 (CEST) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by dpdk.org (Postfix) with ESMTP id CDCF61C0D7 for ; Wed, 1 Apr 2020 16:22:06 +0200 (CEST) Received: by mail-lj1-f193.google.com with SMTP id g27so25878647ljn.10 for ; Wed, 01 Apr 2020 07:22:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hzuw+Q9xcF6a6oNgbJAu90TcvAlAjoQEzzwdgF3k44w=; b=ixEc6CTQ6lYraybUM7Dtwb36UC1A652tQi90m/wJ+Huk6JkeFgTJNdgCVv1pt9x+vf uGm9ZZj71rNWApbxQSrTiGfBvqu7LqjeIifRkire+30mzUe8+nuuHCqrAJ5qN5yGIpjR 8zcNrstMkNutGYAqsByWBLl3l0OSPequYFBBfmMwwskyK0VE3qmqT28kji1F/002T3Vc SwbCCuXvYgn6yG/n5q6IXnYbZzODlwJCWqdDmWE91fFLdFurYw/v//VtTcNid+y8bcpu BmsDTIvL/Q6VugymNw+N2FgwE6d9uV8+eJWFn6VO6+BbaEg3aIbvDI3yjkDfEbW6b23N 0xkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hzuw+Q9xcF6a6oNgbJAu90TcvAlAjoQEzzwdgF3k44w=; b=oBImbzr/qwjOtGfnqUE11GQXudvBTLerEJUAnFm3VbMmQjqCAtUVKqfa8XJT5ZJpXt IEe5wj7zdZv55iZdce3UkEIvQyE/9ze6z3vy43LykYNRqofcKM43vXkEFr/sjyrWg0Ne 1qS1Dh0ufB57gJN4hYAPoHsjL9gu4CP+NGH/6svs7aEYWo4p2UEONRiaeVVce+vKS8Xu TJIuRAqhYMfSFOA8FfKvSVfFFohYnBbGWKCOgt2Ndqb5zP0PLFu1NqWYBQqEBQ+9rbsj xaAwk7qJQWnlQissIYaAJeI0qaLHBxczCmXIvgB8HMJljI+nLRnB4BfB5iM5hyt1U+Bk j+Dw== X-Gm-Message-State: AGi0PubLlNN9THtt51DTSyjBRPBHOtbD2KeY1JhvWOFA60ePXfZjXqPg Z1QBHJcxfnIjhHFjbVrbYBgasLyZGDA= X-Google-Smtp-Source: APiQypITrwnPvpyBZAKrZ0ry+VBd8+suKMU6i3ZSUloYVOdOI2ItSZL5NYyt1gXZar+pOiyl48IBgg== X-Received: by 2002:a2e:9b07:: with SMTP id u7mr12774393lji.110.1585750925933; Wed, 01 Apr 2020 07:22:05 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:05 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:19 +0200 Message-Id: <20200401142127.13715-22-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 21/29] net/ena: refactor Rx path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" * Split main Rx function into multiple ones - the body of the main was very big and further there were 2 nested loops, which were making the code hard to read * Rework how the Rx mbuf chains are being created - Instead of having while loop which has conditional check if it's first segment, handle this segment outside the loop and if more fragments are existing, process them inside. * Initialize Rx mbuf using simple function - it's the common thing for the 1st and next segments. * Create structure for Rx buffer to align it with Tx path, other ENA drivers and to make the variable name more descriptive - on DPDK, Rx buffer must hold only mbuf, so initially array of mbufs was used as the buffers. However, it was misleading, as it was named "rx_buffer_info". To make it more clear, the structure holding mbuf pointer was added and now there is possibility to expand it in the future without reworking the driver. * Remove redundant variables and conditional checks. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/ena_ethdev.c | 182 ++++++++++++++++++++++------------- drivers/net/ena/ena_ethdev.h | 8 +- 2 files changed, 124 insertions(+), 66 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 64c91531a7..1a9c28122b 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -188,6 +188,12 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, uint16_t nb_desc, unsigned int socket_id, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp); +static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len); +static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, + struct ena_com_rx_buf_info *ena_bufs, + uint32_t descs, + uint16_t *next_to_clean, + uint8_t offset); static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); @@ -749,11 +755,13 @@ static void ena_rx_queue_release_bufs(struct ena_ring *ring) { unsigned int i; - for (i = 0; i < ring->ring_size; ++i) - if (ring->rx_buffer_info[i]) { - rte_mbuf_raw_free(ring->rx_buffer_info[i]); - ring->rx_buffer_info[i] = NULL; + for (i = 0; i < ring->ring_size; ++i) { + struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i]; + if (rx_info->mbuf) { + rte_mbuf_raw_free(rx_info->mbuf); + rx_info->mbuf = NULL; } + } } static void ena_tx_queue_release_bufs(struct ena_ring *ring) @@ -1365,8 +1373,8 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, rxq->mb_pool = mp; rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", - sizeof(struct rte_mbuf *) * nb_desc, - RTE_CACHE_LINE_SIZE); + sizeof(struct ena_rx_buffer) * nb_desc, + RTE_CACHE_LINE_SIZE); if (!rxq->rx_buffer_info) { PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n"); return -ENOMEM; @@ -1434,15 +1442,17 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) uint16_t next_to_use_masked = next_to_use & ring_mask; struct rte_mbuf *mbuf = mbufs[i]; struct ena_com_buf ebuf; + struct ena_rx_buffer *rx_info; if (likely((i + 4) < count)) rte_prefetch0(mbufs[i + 4]); req_id = rxq->empty_rx_reqs[next_to_use_masked]; rc = validate_rx_req_id(rxq, req_id); - if (unlikely(rc < 0)) + if (unlikely(rc)) break; - rxq->rx_buffer_info[req_id] = mbuf; + + rx_info = &rxq->rx_buffer_info[req_id]; /* prepare physical address for DMA transaction */ ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; @@ -1452,9 +1462,9 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) &ebuf, req_id); if (unlikely(rc)) { PMD_DRV_LOG(WARNING, "failed adding rx desc\n"); - rxq->rx_buffer_info[req_id] = NULL; break; } + rx_info->mbuf = mbuf; next_to_use++; } @@ -2052,6 +2062,83 @@ static int ena_infos_get(struct rte_eth_dev *dev, return 0; } +static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len) +{ + mbuf->data_len = len; + mbuf->data_off = RTE_PKTMBUF_HEADROOM; + mbuf->refcnt = 1; + mbuf->next = NULL; +} + +static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, + struct ena_com_rx_buf_info *ena_bufs, + uint32_t descs, + uint16_t *next_to_clean, + uint8_t offset) +{ + struct rte_mbuf *mbuf; + struct rte_mbuf *mbuf_head; + struct ena_rx_buffer *rx_info; + unsigned int ring_mask = rx_ring->ring_size - 1; + uint16_t ntc, len, req_id, buf = 0; + + if (unlikely(descs == 0)) + return NULL; + + ntc = *next_to_clean; + + len = ena_bufs[buf].len; + req_id = ena_bufs[buf].req_id; + if (unlikely(validate_rx_req_id(rx_ring, req_id))) + return NULL; + + rx_info = &rx_ring->rx_buffer_info[req_id]; + + mbuf = rx_info->mbuf; + RTE_ASSERT(mbuf != NULL); + + ena_init_rx_mbuf(mbuf, len); + + /* Fill the mbuf head with the data specific for 1st segment. */ + mbuf_head = mbuf; + mbuf_head->nb_segs = descs; + mbuf_head->port = rx_ring->port_id; + mbuf_head->pkt_len = len; + mbuf_head->data_off += offset; + + rx_info->mbuf = NULL; + rx_ring->empty_rx_reqs[ntc & ring_mask] = req_id; + ++ntc; + + while (--descs) { + ++buf; + len = ena_bufs[buf].len; + req_id = ena_bufs[buf].req_id; + if (unlikely(validate_rx_req_id(rx_ring, req_id))) { + rte_mbuf_raw_free(mbuf_head); + return NULL; + } + + rx_info = &rx_ring->rx_buffer_info[req_id]; + RTE_ASSERT(rx_info->mbuf != NULL); + + /* Create an mbuf chain. */ + mbuf->next = rx_info->mbuf; + mbuf = mbuf->next; + + ena_init_rx_mbuf(mbuf, len); + mbuf_head->pkt_len += len; + + rx_info->mbuf = NULL; + rx_ring->empty_rx_reqs[ntc & ring_mask] = req_id; + ++ntc; + } + + *next_to_clean = ntc; + + return mbuf_head; +} + static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) { @@ -2060,16 +2147,10 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, unsigned int ring_mask = ring_size - 1; uint16_t next_to_clean = rx_ring->next_to_clean; uint16_t desc_in_use = 0; - uint16_t req_id; - unsigned int recv_idx = 0; - struct rte_mbuf *mbuf = NULL; - struct rte_mbuf *mbuf_head = NULL; - struct rte_mbuf *mbuf_prev = NULL; - struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info; - unsigned int completed; - + struct rte_mbuf *mbuf; + uint16_t completed; struct ena_com_rx_ctx ena_rx_ctx; - int rc = 0; + int i, rc = 0; /* Check adapter state */ if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { @@ -2083,8 +2164,6 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, nb_pkts = desc_in_use; for (completed = 0; completed < nb_pkts; completed++) { - int segments = 0; - ena_rx_ctx.max_bufs = rx_ring->sgl_size; ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; ena_rx_ctx.descs = 0; @@ -2102,63 +2181,36 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, return 0; } - if (unlikely(ena_rx_ctx.descs == 0)) - break; - - while (segments < ena_rx_ctx.descs) { - req_id = ena_rx_ctx.ena_bufs[segments].req_id; - rc = validate_rx_req_id(rx_ring, req_id); - if (unlikely(rc)) { - if (segments != 0) - rte_mbuf_raw_free(mbuf_head); - break; - } - - mbuf = rx_buff_info[req_id]; - rx_buff_info[req_id] = NULL; - mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len; - mbuf->data_off = RTE_PKTMBUF_HEADROOM; - mbuf->refcnt = 1; - mbuf->next = NULL; - if (unlikely(segments == 0)) { - mbuf->nb_segs = ena_rx_ctx.descs; - mbuf->port = rx_ring->port_id; - mbuf->pkt_len = 0; - mbuf->data_off += ena_rx_ctx.pkt_offset; - mbuf_head = mbuf; - } else { - /* for multi-segment pkts create mbuf chain */ - mbuf_prev->next = mbuf; + mbuf = ena_rx_mbuf(rx_ring, + ena_rx_ctx.ena_bufs, + ena_rx_ctx.descs, + &next_to_clean, + ena_rx_ctx.pkt_offset); + if (unlikely(mbuf == NULL)) { + for (i = 0; i < ena_rx_ctx.descs; ++i) { + rx_ring->empty_rx_reqs[next_to_clean & ring_mask] = + rx_ring->ena_bufs[i].req_id; + ++next_to_clean; } - mbuf_head->pkt_len += mbuf->data_len; - - mbuf_prev = mbuf; - rx_ring->empty_rx_reqs[next_to_clean & ring_mask] = - req_id; - segments++; - next_to_clean++; - } - if (unlikely(rc)) break; + } /* fill mbuf attributes if any */ - ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx); + ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx); - if (unlikely(mbuf_head->ol_flags & + if (unlikely(mbuf->ol_flags & (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); ++rx_ring->rx_stats.bad_csum; } - mbuf_head->hash.rss = ena_rx_ctx.hash; + mbuf->hash.rss = ena_rx_ctx.hash; - /* pass to DPDK application head mbuf */ - rx_pkts[recv_idx] = mbuf_head; - recv_idx++; - rx_ring->rx_stats.bytes += mbuf_head->pkt_len; + rx_pkts[completed] = mbuf; + rx_ring->rx_stats.bytes += mbuf->pkt_len; } - rx_ring->rx_stats.cnt += recv_idx; + rx_ring->rx_stats.cnt += completed; rx_ring->next_to_clean = next_to_clean; desc_in_use = desc_in_use - completed + 1; @@ -2168,7 +2220,7 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, ena_populate_rx_queue(rx_ring, ring_size - desc_in_use); } - return recv_idx; + return completed; } static uint16_t diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 99191ac3e7..9df34136da 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -44,6 +44,12 @@ struct ena_tx_buffer { struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; }; +/* Rx buffer holds only pointer to the mbuf - may be expanded in the future */ +struct ena_rx_buffer { + struct rte_mbuf *mbuf; + struct ena_com_buf ena_buf; +}; + struct ena_calc_queue_size_ctx { struct ena_com_dev_get_features_ctx *get_feat_ctx; struct ena_com_dev *ena_dev; @@ -89,7 +95,7 @@ struct ena_ring { union { struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ - struct rte_mbuf **rx_buffer_info; /* contex of rx packet */ + struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */ }; struct rte_mbuf **rx_refill_buffer; unsigned int ring_size; /* number of tx/rx_buffer_info's entries */ From patchwork Wed Apr 1 14:21:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67607 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 26210A057B; Wed, 1 Apr 2020 16:25:45 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 583901C11D; Wed, 1 Apr 2020 16:22:14 +0200 (CEST) Received: from mail-lj1-f196.google.com (mail-lj1-f196.google.com [209.85.208.196]) by dpdk.org (Postfix) with ESMTP id 3D0F71C0D7 for ; Wed, 1 Apr 2020 16:22:08 +0200 (CEST) Received: by mail-lj1-f196.google.com with SMTP id 19so25905397ljj.7 for ; Wed, 01 Apr 2020 07:22:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u292S0ZQkNHgGfU9MhG7cI7obuqkMTeVbxcTMWXYMXA=; b=R9DetRoCBcgTVazS0KmX1Xhjs9fvIarAQOxdVvjw686qUlBm5MpATtJIWIjImob49m d4a4R70vv5Ws8beghGqMdh0mZJCckGuSc7v3mpYzPTv5s4Gn/H2KSyfqmjWL30X3Z3s2 SZIJRPVX1W1Dq6fDs+HsB2a6JPq5+VxENRj61Ngi2Vs433mMmf0pig4ynVluTz+/pWv7 SU7ifpfyioxlbazKcbxaEKi5vste5DbYB32zFYtoEjFbyNaBGudhIKlEALJIwIKDvOO2 5p1DVhT0s0qcWt3RcQWH5lEjja/mILD/kjq4ANkBh0vW5pFlhhin8HQ86UH7LQ1zsj/r qWIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u292S0ZQkNHgGfU9MhG7cI7obuqkMTeVbxcTMWXYMXA=; b=LnasboIOYcKs8K9y/iXzSZ7+rjouB4x//BgtA2izeYuHrlIeHKs7NWf9Sl8Mx7CbBM +UecOje1rwnL7dq2KekOR5kFPWD5CHIGqX0krRdAqGKFZEfSPV44Sa965oJfLVynSDQU VI7rMj2+bQsZojPEXMAMxP6RR0Rhiy6dEOMNGJMBd/hv1u+biCRH59oRVG20Tozt/hWj ZyRXJZMXNRbsqkcMgSZfv2JPuxk63F9RcGAX/HB+NZR2g++AClmPjZAwUsHST23yeer+ w9u0A3SuI4r7XQwvBBcMee1bRSBKt6+Jbj1TTvzggxIObNg416h+Mm4rnYhJzO4dp6gw ms8w== X-Gm-Message-State: AGi0PuZjR+oFraAPGL3GjJtS0CK3EnjG9TYe4ZDLcpD2B/chsvjGP75q NObd5Nb/+IeBc9zvkyrosYL0wt6Vuhg= X-Google-Smtp-Source: APiQypIuU7b8K1diYpmE+8Suyqmv2VUAe6YLsYCaAMKeDjluP9BWdp9bgYIz8FdaKT+tgTquX05XbQ== X-Received: by 2002:a2e:a16d:: with SMTP id u13mr12958707ljl.140.1585750927380; Wed, 01 Apr 2020 07:22:07 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:06 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:20 +0200 Message-Id: <20200401142127.13715-23-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 22/29] net/ena: rework getting number of available descs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" ena_com API should be preferred for getting number of used/available descriptors unless extra calculation needs to be performed. Some helper variables were added for storing values that are later reused. Moreover, for limiting the value of sent/received packets to the number of available descriptors, the RTE_MIN is used instead of if function, which was doing similar thing but was less descriptive. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/ena_ethdev.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 1a9c28122b..a6375e71c5 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -1426,7 +1426,8 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) if (unlikely(!count)) return 0; - in_use = rxq->next_to_use - rxq->next_to_clean; + in_use = ring_size - ena_com_free_q_entries(rxq->ena_com_io_sq) - 1; + ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n"); /* get resources for incoming packets */ @@ -2145,8 +2146,9 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); unsigned int ring_size = rx_ring->ring_size; unsigned int ring_mask = ring_size - 1; + unsigned int refill_required; uint16_t next_to_clean = rx_ring->next_to_clean; - uint16_t desc_in_use = 0; + uint16_t descs_in_use; struct rte_mbuf *mbuf; uint16_t completed; struct ena_com_rx_ctx ena_rx_ctx; @@ -2159,9 +2161,9 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, return 0; } - desc_in_use = rx_ring->next_to_use - next_to_clean; - if (unlikely(nb_pkts > desc_in_use)) - nb_pkts = desc_in_use; + descs_in_use = ring_size - + ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1; + nb_pkts = RTE_MIN(descs_in_use, nb_pkts); for (completed = 0; completed < nb_pkts; completed++) { ena_rx_ctx.max_bufs = rx_ring->sgl_size; @@ -2213,11 +2215,11 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, rx_ring->rx_stats.cnt += completed; rx_ring->next_to_clean = next_to_clean; - desc_in_use = desc_in_use - completed + 1; + refill_required = ena_com_free_q_entries(rx_ring->ena_com_io_sq); /* Burst refill to save doorbells, memory barriers, const interval */ - if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) { + if (refill_required > ENA_RING_DESCS_RATIO(ring_size)) { ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); - ena_populate_rx_queue(rx_ring, ring_size - desc_in_use); + ena_populate_rx_queue(rx_ring, refill_required); } return completed; @@ -2360,7 +2362,7 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, struct ena_tx_buffer *tx_info; struct ena_com_buf *ebuf; uint16_t rc, req_id, total_tx_descs = 0; - uint16_t sent_idx = 0, empty_tx_reqs; + uint16_t sent_idx = 0; uint16_t push_len = 0; uint16_t delta = 0; int nb_hw_desc; @@ -2373,9 +2375,8 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, return 0; } - empty_tx_reqs = ring_size - (next_to_use - next_to_clean); - if (nb_pkts > empty_tx_reqs) - nb_pkts = empty_tx_reqs; + nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq), + nb_pkts); for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { mbuf = tx_pkts[sent_idx]; From patchwork Wed Apr 1 14:21:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67608 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 09549A057B; Wed, 1 Apr 2020 16:25:56 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AD7351C12A; Wed, 1 Apr 2020 16:22:15 +0200 (CEST) Received: from mail-lf1-f65.google.com (mail-lf1-f65.google.com [209.85.167.65]) by dpdk.org (Postfix) with ESMTP id 8DCAE1C113 for ; Wed, 1 Apr 2020 16:22:09 +0200 (CEST) Received: by mail-lf1-f65.google.com with SMTP id t11so8199845lfe.4 for ; Wed, 01 Apr 2020 07:22:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5A9hsbTp+jjQv9P8DNmXLX5GuSXGtPzKA9NbAJIoZv4=; b=k6chPiwiGvecUN6TrT2fsMF6eDIsfuwdCvcPDN4N6BPhiHmQUl8jGF8buXVn/crluD uEHxur/XYSja74xqMN+NeyeLDpH/49hJbtUIaCbzR92dUbPZxytuVsQNtnsy+E0tuHG8 rnkqISHsCf6BzxHejzJzbHTSGiBnx9gYIoxYCcOkuk1DH0cA1R9zgWyy6rMbFYcoegT4 0+I9u/gtMv23puI11uGvgtIQafZimy9F1sDOZPE/cr05VbEi7Ic89uaJocH1risp3j0n FP32My6jvoKcfpgCkaK5tVTOE3vMnkNxl3YX1N9wxfB8P+jfdTO6aHznMlRa6/49BmGf 0n0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5A9hsbTp+jjQv9P8DNmXLX5GuSXGtPzKA9NbAJIoZv4=; b=jkcAFxe7qPHx2JP2HsV30OBIU1P9+1zDKcqNNmeDda+fiSzokH5Btk6hNRAYrBVE8j rpyuNYf1rQV+2pQH5e5Vnw5WWbbNoOwWbrcIMTMzDFj96hyfEZxI6WRMb1TxZ/2htl8I QZnCpU+CduRqF1QdWgIsI48iArgqmVV0mcMvH1hYp4tAnyCscu/0GjICIouC3i2PKcmq uETNLAKr/Vk/16iOgOtrSW/xdsVgyIY4+Ac5/hR+9N7yJnnz9jjNdayZ1YT+ruMnf87Y vpUTtox8V8jgQzTRxJyiIn+9d2f2+Fox9mSNHN3GQrc2QSKQn1aD6filb0oyTrMLWr14 h45g== X-Gm-Message-State: AGi0PuZOLktBx8Rj42dheXRne1PrNJtjUfFU9tT6hPRc997pubDkowJl QwJK4J/Ph6cLiXbmZkkLx1aqzNJzvI0= X-Google-Smtp-Source: APiQypLdkO9FVHmO3wxi7IOMcWMBjemzLhgEnFJ3ITey29ElR+XE1iILoozh8nhnQx/Ush2a46BCZQ== X-Received: by 2002:ac2:5096:: with SMTP id f22mr15136656lfm.79.1585750928764; Wed, 01 Apr 2020 07:22:08 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:07 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:21 +0200 Message-Id: <20200401142127.13715-24-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 23/29] net/ena: limit refill threshold by fixed value X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Divider used for both Tx and Rx cleanup/refill threshold can cause too big delay in case of the really big rings - for example if the 8k Rx ring will be used, the refill won't trigger unless 1024 threshold will be reached. It will also cause driver to try to allocate that much descriptors. Limiting it by fixed value - 256 in that case, would limit maximum time spent in repopulate function. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/ena_ethdev.c | 27 ++++++++++++++------------- drivers/net/ena/ena_ethdev.h | 10 ++++++++++ 2 files changed, 24 insertions(+), 13 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index a6375e71c5..fc14f1cb32 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -35,14 +35,6 @@ /*reverse version of ENA_IO_RXQ_IDX*/ #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) -/* While processing submitted and completed descriptors (rx and tx path - * respectively) in a loop it is desired to: - * - perform batch submissions while populating sumbissmion queue - * - avoid blocking transmission of other packets during cleanup phase - * Hence the utilization ratio of 1/8 of a queue size. - */ -#define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8) - #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) @@ -2146,7 +2138,8 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); unsigned int ring_size = rx_ring->ring_size; unsigned int ring_mask = ring_size - 1; - unsigned int refill_required; + unsigned int free_queue_entries; + unsigned int refill_threshold; uint16_t next_to_clean = rx_ring->next_to_clean; uint16_t descs_in_use; struct rte_mbuf *mbuf; @@ -2215,11 +2208,15 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, rx_ring->rx_stats.cnt += completed; rx_ring->next_to_clean = next_to_clean; - refill_required = ena_com_free_q_entries(rx_ring->ena_com_io_sq); + free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq); + refill_threshold = + RTE_MIN(ring_size / ENA_REFILL_THRESH_DIVIDER, + (unsigned int)ENA_REFILL_THRESH_PACKET); + /* Burst refill to save doorbells, memory barriers, const interval */ - if (refill_required > ENA_RING_DESCS_RATIO(ring_size)) { + if (free_queue_entries > refill_threshold) { ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); - ena_populate_rx_queue(rx_ring, refill_required); + ena_populate_rx_queue(rx_ring, free_queue_entries); } return completed; @@ -2358,6 +2355,7 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t seg_len; unsigned int ring_size = tx_ring->ring_size; unsigned int ring_mask = ring_size - 1; + unsigned int cleanup_budget; struct ena_com_tx_ctx ena_tx_ctx; struct ena_tx_buffer *tx_info; struct ena_com_buf *ebuf; @@ -2515,9 +2513,12 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, /* Put back descriptor to the ring for reuse */ tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; next_to_clean++; + cleanup_budget = + RTE_MIN(ring_size / ENA_REFILL_THRESH_DIVIDER, + (unsigned int)ENA_REFILL_THRESH_PACKET); /* If too many descs to clean, leave it for another run */ - if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size))) + if (unlikely(total_tx_descs > cleanup_budget)) break; } tx_ring->tx_stats.available_desc = diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 9df34136da..77c405fbdd 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -30,6 +30,16 @@ #define ENA_WD_TIMEOUT_SEC 3 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz()) +/* While processing submitted and completed descriptors (rx and tx path + * respectively) in a loop it is desired to: + * - perform batch submissions while populating sumbissmion queue + * - avoid blocking transmission of other packets during cleanup phase + * Hence the utilization ratio of 1/8 of a queue size or max value if the size + * of the ring is very big - like 8k Rx rings. + */ +#define ENA_REFILL_THRESH_DIVIDER 8 +#define ENA_REFILL_THRESH_PACKET 256 + struct ena_adapter; enum ena_ring_type { From patchwork Wed Apr 1 14:21:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67609 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C4E4A057B; Wed, 1 Apr 2020 16:26:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CAA741C130; Wed, 1 Apr 2020 16:22:16 +0200 (CEST) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by dpdk.org (Postfix) with ESMTP id DE7981C0BE for ; Wed, 1 Apr 2020 16:22:10 +0200 (CEST) Received: by mail-lj1-f193.google.com with SMTP id q19so25895961ljp.9 for ; Wed, 01 Apr 2020 07:22:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EEV4jaCd8a2gCcikdXP4WJZU+K0N7Y58pZgH6pUBHu8=; b=ZUlRlNSLXLzG3aRt3/FtmA875PBE18BeXbIueu+sLLfk+HpEIjScXmT0fDv4UwHdLv 7MdWXFWKLyCmDH78jB8BWhmcvmXbrj3u+LeLSi7M+dYcZfK7MKpgpvHNlaBPPAkaaVep sjkFFVp+8V4+GxCkBljvirnx1VeebC3NTb7giEZ85dDFPv9ICpncnY3WJOK4rX6smrJH 8fw5CfFaz9cwip9BppYkyB+EDdWZIXtyNXMLQUQfX4cbTLC2XZWR5q0RxCi7IOM8v3M/ zwXAMVW2hlCW4bBKw/kIhWNzPXzvtHC7TXQ2hqg2RcvkiR0FPJiVmXvjfjiaz/+gozx6 593g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EEV4jaCd8a2gCcikdXP4WJZU+K0N7Y58pZgH6pUBHu8=; b=nZKfB7tbgZdtq47ZtZMGqhmD4vPJin6YMCNZV1hfKk4wutZXVNWI2HgE4dQ8BOC8Qp hzKJsj4L7OTu7Zpl8CXhZmHLVX/nFH4OxjtunsJji2eVU+JXl/b/Etijck0xA6fcOrYy DwQEE9orfGvzMyVROgeLvXAOTYBisbsB3xlllacVbcZQi1tlr0IUYLe4NZ9zgrGh62AK ueLs7ckGgDeOGR5kZ1zuN/Jr7AzThBZUowuwjNYlUt/f38eKObaiQXcB++sAPUEWxJMm ZGC9LhjH6E6s1IJ2+cGQ1Z5UL+LmmLq1kRnXtDuDKEOeHt49tv4X0oVkH7sWflO8BLHy 4OGg== X-Gm-Message-State: AGi0PuawYejZHGD8HRHaqwjMtM3PGtNxOab6EQiARovfJqbDo/ApPIWs mTiW9DRKOPmeiNXRQ2XJ/uGcLQ1zfaE= X-Google-Smtp-Source: APiQypKPcMOT4uxGh3u/fNsf7T1uSJmOsANNFzNYlbSjhiSon3u4p4E2gkXi9QcC0YLZ1IrvUE65uA== X-Received: by 2002:a05:651c:48a:: with SMTP id s10mr7685835ljc.226.1585750930099; Wed, 01 Apr 2020 07:22:10 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:09 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:22 +0200 Message-Id: <20200401142127.13715-25-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 24/29] net/ena: use macros for ring idx operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To improve code readability, abstraction was added for operating on IO rings indexes. Driver was defining local variable for ring mask in each function that needed to operate on the ring indexes. Now it is being stored in the ring as this value won't change unless size of the ring will change and macros for advancing indexes using the mask has been added. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/ena_ethdev.c | 53 ++++++++++++++++++------------------ drivers/net/ena/ena_ethdev.h | 4 +++ 2 files changed, 30 insertions(+), 27 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index fc14f1cb32..3517c3f97d 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -1266,6 +1266,7 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev, txq->next_to_clean = 0; txq->next_to_use = 0; txq->ring_size = nb_desc; + txq->size_mask = nb_desc - 1; txq->numa_socket_id = socket_id; txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", @@ -1361,6 +1362,7 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, rxq->next_to_clean = 0; rxq->next_to_use = 0; rxq->ring_size = nb_desc; + rxq->size_mask = nb_desc - 1; rxq->numa_socket_id = socket_id; rxq->mb_pool = mp; @@ -1409,8 +1411,6 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) { unsigned int i; int rc; - uint16_t ring_size = rxq->ring_size; - uint16_t ring_mask = ring_size - 1; uint16_t next_to_use = rxq->next_to_use; uint16_t in_use, req_id; struct rte_mbuf **mbufs = rxq->rx_refill_buffer; @@ -1418,9 +1418,10 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) if (unlikely(!count)) return 0; - in_use = ring_size - ena_com_free_q_entries(rxq->ena_com_io_sq) - 1; - - ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n"); + in_use = rxq->ring_size - 1 - + ena_com_free_q_entries(rxq->ena_com_io_sq); + ena_assert_msg(((in_use + count) < rxq->ring_size), + "bad ring state\n"); /* get resources for incoming packets */ rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); @@ -1432,7 +1433,6 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) } for (i = 0; i < count; i++) { - uint16_t next_to_use_masked = next_to_use & ring_mask; struct rte_mbuf *mbuf = mbufs[i]; struct ena_com_buf ebuf; struct ena_rx_buffer *rx_info; @@ -1440,7 +1440,7 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) if (likely((i + 4) < count)) rte_prefetch0(mbufs[i + 4]); - req_id = rxq->empty_rx_reqs[next_to_use_masked]; + req_id = rxq->empty_rx_reqs[next_to_use]; rc = validate_rx_req_id(rxq, req_id); if (unlikely(rc)) break; @@ -1458,7 +1458,7 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) break; } rx_info->mbuf = mbuf; - next_to_use++; + next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask); } if (unlikely(i < count)) { @@ -2072,7 +2072,6 @@ static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, struct rte_mbuf *mbuf; struct rte_mbuf *mbuf_head; struct ena_rx_buffer *rx_info; - unsigned int ring_mask = rx_ring->ring_size - 1; uint16_t ntc, len, req_id, buf = 0; if (unlikely(descs == 0)) @@ -2100,8 +2099,8 @@ static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, mbuf_head->data_off += offset; rx_info->mbuf = NULL; - rx_ring->empty_rx_reqs[ntc & ring_mask] = req_id; - ++ntc; + rx_ring->empty_rx_reqs[ntc] = req_id; + ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); while (--descs) { ++buf; @@ -2123,8 +2122,8 @@ static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, mbuf_head->pkt_len += len; rx_info->mbuf = NULL; - rx_ring->empty_rx_reqs[ntc & ring_mask] = req_id; - ++ntc; + rx_ring->empty_rx_reqs[ntc] = req_id; + ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); } *next_to_clean = ntc; @@ -2136,8 +2135,6 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) { struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); - unsigned int ring_size = rx_ring->ring_size; - unsigned int ring_mask = ring_size - 1; unsigned int free_queue_entries; unsigned int refill_threshold; uint16_t next_to_clean = rx_ring->next_to_clean; @@ -2154,7 +2151,7 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, return 0; } - descs_in_use = ring_size - + descs_in_use = rx_ring->ring_size - ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1; nb_pkts = RTE_MIN(descs_in_use, nb_pkts); @@ -2183,9 +2180,10 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, ena_rx_ctx.pkt_offset); if (unlikely(mbuf == NULL)) { for (i = 0; i < ena_rx_ctx.descs; ++i) { - rx_ring->empty_rx_reqs[next_to_clean & ring_mask] = + rx_ring->empty_rx_reqs[next_to_clean] = rx_ring->ena_bufs[i].req_id; - ++next_to_clean; + next_to_clean = ENA_IDX_NEXT_MASKED( + next_to_clean, rx_ring->size_mask); } break; } @@ -2210,7 +2208,7 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq); refill_threshold = - RTE_MIN(ring_size / ENA_REFILL_THRESH_DIVIDER, + RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, (unsigned int)ENA_REFILL_THRESH_PACKET); /* Burst refill to save doorbells, memory barriers, const interval */ @@ -2353,8 +2351,6 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t next_to_clean = tx_ring->next_to_clean; struct rte_mbuf *mbuf; uint16_t seg_len; - unsigned int ring_size = tx_ring->ring_size; - unsigned int ring_mask = ring_size - 1; unsigned int cleanup_budget; struct ena_com_tx_ctx ena_tx_ctx; struct ena_tx_buffer *tx_info; @@ -2384,7 +2380,7 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, if (unlikely(rc)) break; - req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask]; + req_id = tx_ring->empty_tx_reqs[next_to_use]; tx_info = &tx_ring->tx_buffer_info[req_id]; tx_info->mbuf = mbuf; tx_info->num_of_bufs = 0; @@ -2428,7 +2424,8 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads, tx_ring->disable_meta_caching); - rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]); + rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED( + sent_idx, 4, tx_ring->size_mask)]); /* Process first segment taking into * consideration pushed header @@ -2480,7 +2477,8 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, } tx_info->tx_descs = nb_hw_desc; - next_to_use++; + next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, + tx_ring->size_mask); tx_ring->tx_stats.cnt++; tx_ring->tx_stats.bytes += total_length; } @@ -2511,10 +2509,11 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, tx_info->mbuf = NULL; /* Put back descriptor to the ring for reuse */ - tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; - next_to_clean++; + tx_ring->empty_tx_reqs[next_to_clean] = req_id; + next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean, + tx_ring->size_mask); cleanup_budget = - RTE_MIN(ring_size / ENA_REFILL_THRESH_DIVIDER, + RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, (unsigned int)ENA_REFILL_THRESH_PACKET); /* If too many descs to clean, leave it for another run */ diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 77c405fbdd..77d40d5a1e 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -40,6 +40,9 @@ #define ENA_REFILL_THRESH_DIVIDER 8 #define ENA_REFILL_THRESH_PACKET 256 +#define ENA_IDX_NEXT_MASKED(idx, mask) (((idx) + 1) & (mask)) +#define ENA_IDX_ADD_MASKED(idx, n, mask) (((idx) + (n)) & (mask)) + struct ena_adapter; enum ena_ring_type { @@ -109,6 +112,7 @@ struct ena_ring { }; struct rte_mbuf **rx_refill_buffer; unsigned int ring_size; /* number of tx/rx_buffer_info's entries */ + unsigned int size_mask; struct ena_com_io_cq *ena_com_io_cq; struct ena_com_io_sq *ena_com_io_sq; From patchwork Wed Apr 1 14:21:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67610 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D532A057B; Wed, 1 Apr 2020 16:26:19 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DAF621C138; Wed, 1 Apr 2020 16:22:17 +0200 (CEST) Received: from mail-lj1-f196.google.com (mail-lj1-f196.google.com [209.85.208.196]) by dpdk.org (Postfix) with ESMTP id 015D51C117 for ; Wed, 1 Apr 2020 16:22:13 +0200 (CEST) Received: by mail-lj1-f196.google.com with SMTP id i20so25943294ljn.6 for ; Wed, 01 Apr 2020 07:22:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZULBjz9Tz3RSn5ILlnnGMCzLr37Q8vq5U4I1eZChBe4=; b=FSN4ZXs+jI2BjgNNhVWurVxIHlvfhCOZjh/JQEnTbNc89iBii4VggA+cX8leFz5rsw I9fAsTb+ggG9w/eRdqfRR72uZvrrbNmmmkoGaoRqEH7z2t8GSTdwIeqDdq6wzUxG2PBS rNzXe7D+k9wpz3VXe/NMcB25bMfBj4BQoHGIq740v5IknHR+64iWeAhZpLK6Qrjd2y4n 2FIqy7bDi1n3hLrsW4tXTFBxWMmnhnE7xiBNv4/KfbPcnbAihSn4/qTEYtL8GL64iawA X+UN5BcvBlzhPJMMquIwKe2mxDvOtS0QjUInFLvokKuBTFIJ16B9E7wKoN03466H4aKO Pldg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZULBjz9Tz3RSn5ILlnnGMCzLr37Q8vq5U4I1eZChBe4=; b=GZKHVO80xAYNvl8aPNZS5Vh4JhzcideMI9HoxRXH1/qd+guT1BltqH+9qtW0Qbl6g2 LTBb5Wx8NAN3zdvZ6D5ltumf6Glq5gpbnzVOkFbonEUCNHRxh1/500mLktBc94y+genf IgT7rvie3VeCyzmEMhwbwVbd43fRSmLHaDXp7j9clBj1dmyfvbKmahxynw4R7mvyLL5G UV2Sn8xKN9b+w0YSpt36JeWU8bZ/b65JQXYOlAZW4fgpZpI7lNAaEN6VZMSCJ+R8Jw3F K5Ken6u/LJEt22zW8206LDVzke9tJIH3r9T56oEX9I3qivUAiICIpBdu7v9TSeCjomt9 9yeQ== X-Gm-Message-State: AGi0PuZdURKfcJl6g8AjwtJfn3QXbbg5b7tjCWIsuSRFhqfFLa0kUJ4N Ipz25EtdpbPbAdltORFkuRyXfozQibw= X-Google-Smtp-Source: APiQypItB/rCtlnUtWXlzqnoUZu/OP+dCSV995diVcMalHn/eq6TphQiti9q/zTIEhHDnpzMnbpalQ== X-Received: by 2002:a2e:b175:: with SMTP id a21mr13385500ljm.213.1585750931416; Wed, 01 Apr 2020 07:22:11 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:10 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:23 +0200 Message-Id: <20200401142127.13715-26-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 25/29] net/ena: refactor Tx path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The original Tx function was very long and was containing both cleanup and the sending sections. Because of that it was having a lot of local variables, big indentation and was hard to read. This function was split into 2 sections: * Sending - which is responsible for preparing the mbuf, mapping it to the device descriptors and finally, sending packet to the HW * Cleanup - which is releasing packets sent by the HW. Loop which was releasing packets was reworked a bit, to make intention more visible and aligned with other parts of the driver. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- v2: * Fix compilation error on icc by adding braces around 0 drivers/net/ena/ena_ethdev.c | 323 +++++++++++++++++++---------------- 1 file changed, 179 insertions(+), 144 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 3517c3f97d..601b4cb831 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -169,6 +169,13 @@ static int ena_device_init(struct ena_com_dev *ena_dev, struct ena_com_dev_get_features_ctx *get_feat_ctx, bool *wd_state); static int ena_dev_configure(struct rte_eth_dev *dev); +static void ena_tx_map_mbuf(struct ena_ring *tx_ring, + struct ena_tx_buffer *tx_info, + struct rte_mbuf *mbuf, + void **push_header, + uint16_t *header_len); +static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf); +static void ena_tx_cleanup(struct ena_ring *tx_ring); static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts); static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, @@ -2343,193 +2350,221 @@ static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, return rc; } -static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, - uint16_t nb_pkts) +static void ena_tx_map_mbuf(struct ena_ring *tx_ring, + struct ena_tx_buffer *tx_info, + struct rte_mbuf *mbuf, + void **push_header, + uint16_t *header_len) { - struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); - uint16_t next_to_use = tx_ring->next_to_use; - uint16_t next_to_clean = tx_ring->next_to_clean; - struct rte_mbuf *mbuf; - uint16_t seg_len; - unsigned int cleanup_budget; - struct ena_com_tx_ctx ena_tx_ctx; - struct ena_tx_buffer *tx_info; - struct ena_com_buf *ebuf; - uint16_t rc, req_id, total_tx_descs = 0; - uint16_t sent_idx = 0; - uint16_t push_len = 0; - uint16_t delta = 0; - int nb_hw_desc; - uint32_t total_length; - - /* Check adapter state */ - if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { - PMD_DRV_LOG(ALERT, - "Trying to xmit pkts while device is NOT running\n"); - return 0; - } + struct ena_com_buf *ena_buf; + uint16_t delta, seg_len, push_len; - nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq), - nb_pkts); + delta = 0; + seg_len = mbuf->data_len; - for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { - mbuf = tx_pkts[sent_idx]; - total_length = 0; + tx_info->mbuf = mbuf; + ena_buf = tx_info->bufs; - rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); - if (unlikely(rc)) - break; + if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { + /* + * Tx header might be (and will be in most cases) smaller than + * tx_max_header_size. But it's not an issue to send more data + * to the device, than actually needed if the mbuf size is + * greater than tx_max_header_size. + */ + push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size); + *header_len = push_len; - req_id = tx_ring->empty_tx_reqs[next_to_use]; - tx_info = &tx_ring->tx_buffer_info[req_id]; - tx_info->mbuf = mbuf; - tx_info->num_of_bufs = 0; - ebuf = tx_info->bufs; + if (likely(push_len <= seg_len)) { + /* If the push header is in the single segment, then + * just point it to the 1st mbuf data. + */ + *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *); + } else { + /* If the push header lays in the several segments, copy + * it to the intermediate buffer. + */ + rte_pktmbuf_read(mbuf, 0, push_len, + tx_ring->push_buf_intermediate_buf); + *push_header = tx_ring->push_buf_intermediate_buf; + delta = push_len - seg_len; + } + } else { + *push_header = NULL; + *header_len = 0; + push_len = 0; + } - /* Prepare TX context */ - memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); - memset(&ena_tx_ctx.ena_meta, 0x0, - sizeof(struct ena_com_tx_meta)); - ena_tx_ctx.ena_bufs = ebuf; - ena_tx_ctx.req_id = req_id; + /* Process first segment taking into consideration pushed header */ + if (seg_len > push_len) { + ena_buf->paddr = mbuf->buf_iova + + mbuf->data_off + + push_len; + ena_buf->len = seg_len - push_len; + ena_buf++; + tx_info->num_of_bufs++; + } - delta = 0; + while ((mbuf = mbuf->next) != NULL) { seg_len = mbuf->data_len; - if (tx_ring->tx_mem_queue_type == - ENA_ADMIN_PLACEMENT_POLICY_DEV) { - push_len = RTE_MIN(mbuf->pkt_len, - tx_ring->tx_max_header_size); - ena_tx_ctx.header_len = push_len; - - if (likely(push_len <= seg_len)) { - /* If the push header is in the single segment, - * then just point it to the 1st mbuf data. - */ - ena_tx_ctx.push_header = - rte_pktmbuf_mtod(mbuf, uint8_t *); - } else { - /* If the push header lays in the several - * segments, copy it to the intermediate buffer. - */ - rte_pktmbuf_read(mbuf, 0, push_len, - tx_ring->push_buf_intermediate_buf); - ena_tx_ctx.push_header = - tx_ring->push_buf_intermediate_buf; - delta = push_len - seg_len; - } - } /* there's no else as we take advantage of memset zeroing */ + /* Skip mbufs if whole data is pushed as a header */ + if (unlikely(delta > seg_len)) { + delta -= seg_len; + continue; + } - /* Set TX offloads flags, if applicable */ - ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads, - tx_ring->disable_meta_caching); + ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta; + ena_buf->len = seg_len - delta; + ena_buf++; + tx_info->num_of_bufs++; - rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED( - sent_idx, 4, tx_ring->size_mask)]); + delta = 0; + } +} - /* Process first segment taking into - * consideration pushed header - */ - if (seg_len > push_len) { - ebuf->paddr = mbuf->buf_iova + - mbuf->data_off + - push_len; - ebuf->len = seg_len - push_len; - ebuf++; - tx_info->num_of_bufs++; - } - total_length += mbuf->data_len; +static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf) +{ + struct ena_tx_buffer *tx_info; + struct ena_com_tx_ctx ena_tx_ctx = { { 0 } }; + uint16_t next_to_use; + uint16_t header_len; + uint16_t req_id; + void *push_header; + int nb_hw_desc; + int rc; - while ((mbuf = mbuf->next) != NULL) { - seg_len = mbuf->data_len; + rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); + if (unlikely(rc)) + return rc; - /* Skip mbufs if whole data is pushed as a header */ - if (unlikely(delta > seg_len)) { - delta -= seg_len; - continue; - } + next_to_use = tx_ring->next_to_use; - ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta; - ebuf->len = seg_len - delta; - total_length += ebuf->len; - ebuf++; - tx_info->num_of_bufs++; + req_id = tx_ring->empty_tx_reqs[next_to_use]; + tx_info = &tx_ring->tx_buffer_info[req_id]; + tx_info->num_of_bufs = 0; - delta = 0; - } + ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len); - ena_tx_ctx.num_bufs = tx_info->num_of_bufs; + ena_tx_ctx.ena_bufs = tx_info->bufs; + ena_tx_ctx.push_header = push_header; + ena_tx_ctx.num_bufs = tx_info->num_of_bufs; + ena_tx_ctx.req_id = req_id; + ena_tx_ctx.header_len = header_len; - if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, - &ena_tx_ctx)) { - PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d" - " achieved, writing doorbell to send burst\n", - tx_ring->id); - ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); - } - - /* prepare the packet's descriptors to dma engine */ - rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, - &ena_tx_ctx, &nb_hw_desc); - if (unlikely(rc)) { - ++tx_ring->tx_stats.prepare_ctx_err; - break; - } - tx_info->tx_descs = nb_hw_desc; + /* Set Tx offloads flags, if applicable */ + ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads, + tx_ring->disable_meta_caching); - next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, - tx_ring->size_mask); - tx_ring->tx_stats.cnt++; - tx_ring->tx_stats.bytes += total_length; + if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, + &ena_tx_ctx))) { + PMD_DRV_LOG(DEBUG, + "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n", + tx_ring->id); + ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); } - tx_ring->tx_stats.available_desc = - ena_com_free_q_entries(tx_ring->ena_com_io_sq); - /* If there are ready packets to be xmitted... */ - if (sent_idx > 0) { - /* ...let HW do its best :-) */ - ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); - tx_ring->tx_stats.doorbells++; - tx_ring->next_to_use = next_to_use; + /* prepare the packet's descriptors to dma engine */ + rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx, + &nb_hw_desc); + if (unlikely(rc)) { + ++tx_ring->tx_stats.prepare_ctx_err; + return rc; } - /* Clear complete packets */ - while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) { - rc = validate_tx_req_id(tx_ring, req_id); - if (rc) + tx_info->tx_descs = nb_hw_desc; + + tx_ring->tx_stats.cnt++; + tx_ring->tx_stats.bytes += mbuf->pkt_len; + + tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, + tx_ring->size_mask); + + return 0; +} + +static void ena_tx_cleanup(struct ena_ring *tx_ring) +{ + unsigned int cleanup_budget; + unsigned int total_tx_descs = 0; + uint16_t next_to_clean = tx_ring->next_to_clean; + + cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, + (unsigned int)ENA_REFILL_THRESH_PACKET); + + while (likely(total_tx_descs < cleanup_budget)) { + struct rte_mbuf *mbuf; + struct ena_tx_buffer *tx_info; + uint16_t req_id; + + if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0) + break; + + if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0)) break; /* Get Tx info & store how many descs were processed */ tx_info = &tx_ring->tx_buffer_info[req_id]; - total_tx_descs += tx_info->tx_descs; - /* Free whole mbuf chain */ mbuf = tx_info->mbuf; rte_pktmbuf_free(mbuf); + tx_info->mbuf = NULL; + tx_ring->empty_tx_reqs[next_to_clean] = req_id; + + total_tx_descs += tx_info->tx_descs; /* Put back descriptor to the ring for reuse */ - tx_ring->empty_tx_reqs[next_to_clean] = req_id; next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean, tx_ring->size_mask); - cleanup_budget = - RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, - (unsigned int)ENA_REFILL_THRESH_PACKET); - - /* If too many descs to clean, leave it for another run */ - if (unlikely(total_tx_descs > cleanup_budget)) - break; } - tx_ring->tx_stats.available_desc = - ena_com_free_q_entries(tx_ring->ena_com_io_sq); - if (total_tx_descs > 0) { + if (likely(total_tx_descs > 0)) { /* acknowledge completion of sent packets */ tx_ring->next_to_clean = next_to_clean; ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); } +} + +static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts) +{ + struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); + uint16_t sent_idx = 0; + + /* Check adapter state */ + if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { + PMD_DRV_LOG(ALERT, + "Trying to xmit pkts while device is NOT running\n"); + return 0; + } + + nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq), + nb_pkts); + + for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { + if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx])) + break; + rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4, + tx_ring->size_mask)]); + } + + tx_ring->tx_stats.available_desc = + ena_com_free_q_entries(tx_ring->ena_com_io_sq); + + /* If there are ready packets to be xmitted... */ + if (sent_idx > 0) { + /* ...let HW do its best :-) */ + ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); + tx_ring->tx_stats.doorbells++; + } + + ena_tx_cleanup(tx_ring); + + tx_ring->tx_stats.available_desc = + ena_com_free_q_entries(tx_ring->ena_com_io_sq); tx_ring->tx_stats.tx_poll++; return sent_idx; From patchwork Wed Apr 1 14:21:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67613 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 801BCA057B; Wed, 1 Apr 2020 16:26:55 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D0CA01C193; Wed, 1 Apr 2020 16:22:21 +0200 (CEST) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by dpdk.org (Postfix) with ESMTP id 564E71C12E for ; Wed, 1 Apr 2020 16:22:16 +0200 (CEST) Received: by mail-lj1-f193.google.com with SMTP id 19so25905889ljj.7 for ; Wed, 01 Apr 2020 07:22:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rXaMrzpNnk0KTsARxMl3YcIExiKi66/ob640h+Ml6Do=; b=XWkvYg3fPQ7F3yEoOPWNO/cVeCnhNug94T5N052lXKjmlYgLcWwS82/RZPJiafRvWI CUjlRfLqNvUenaSkvNLD0UiJNeJcx1HGHgcAoAJBeup+ymjDgvjyZV0OmRP6FBj8LWUN pvWqqulki/l+fm/1DomzkvdkyUeVYYMgfIugzy0JTdHBk5im8dJUssso8Ry0ocD9+gGQ 720DY+USh9+zw0kS4UgrCyUQNUhl3vPIXKtk6DYDpLycmAv7dTBR9IQmL5t6dmx55Szp 8dehq68nit3/nKckDVZRez9C7HeRnrfPNB0KlHGYSySgBqRrV+wIwNsGoumaLOXDBkub Xohw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rXaMrzpNnk0KTsARxMl3YcIExiKi66/ob640h+Ml6Do=; b=C3CYnljOtIaS99nQTTaQbvMR6U18JDpGSyo+gxoSxmhkIsBGqnHavswYtsMBY62YH4 U670h2DMas5zrEGjcHShF3Pg6SkLJztdN1jPiZ6QLLhVo51XPqrKEuuDZZ5VtiZ0AdPn 1zjzr9RUjkr8a16WfyIfvgB1vn9yuiP94jpANsFXo6RJwfWXGluxgAUPPg+Bs7MV+lqc spoNbBZCYavDYoXiBl8uPM5mYWjWPvTPl5cF8ahePCb+W+fXNH0aAQrrMXmjXke7QrDY eIq9cAB2AjulRePd6mcu8h405MWh/m+WMuDk13p85ZbGXKt2pijK45O+LqnJIdq2dkjq sjeQ== X-Gm-Message-State: AGi0PuaG/Mo1WnCTJdz//Cq/303tc0Wc1RV0BN5TT1g8rt4xt3hO0p2l 2UquPRcWsIr3x45iPYKc895TyV03Kzg= X-Google-Smtp-Source: APiQypJTKjn5Tz+k27QOn2vVdlKo+1O6IWpKlTfQkVEeHyqUyl5YnHGQnhDH2SoCtsbPLPVmmWnBmg== X-Received: by 2002:a2e:9585:: with SMTP id w5mr13776041ljh.178.1585750932561; Wed, 01 Apr 2020 07:22:12 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:11 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:24 +0200 Message-Id: <20200401142127.13715-27-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 26/29] net/ena: reuse 0 length Rx descriptor X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Some ENA devices can pass to the driver descriptor with length 0. To avoid extra allocation, the descriptor can be reused by simply putting it back to the device. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- v2: * Compare rc (error code) to 0 value explicitely drivers/net/ena/ena_ethdev.c | 75 ++++++++++++++++++++++++++++-------- 1 file changed, 60 insertions(+), 15 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 601b4cb831..34f910c9c4 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -195,6 +195,8 @@ static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, uint8_t offset); static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); +static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, + struct rte_mbuf *mbuf, uint16_t id); static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); static void ena_init_rings(struct ena_adapter *adapter, bool disable_meta_caching); @@ -1414,6 +1416,24 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, return 0; } +static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, + struct rte_mbuf *mbuf, uint16_t id) +{ + struct ena_com_buf ebuf; + int rc; + + /* prepare physical address for DMA transaction */ + ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; + ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; + + /* pass resource to device */ + rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id); + if (unlikely(rc != 0)) + PMD_DRV_LOG(WARNING, "failed adding rx desc\n"); + + return rc; +} + static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) { unsigned int i; @@ -1441,7 +1461,6 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) for (i = 0; i < count; i++) { struct rte_mbuf *mbuf = mbufs[i]; - struct ena_com_buf ebuf; struct ena_rx_buffer *rx_info; if (likely((i + 4) < count)) @@ -1454,16 +1473,10 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) rx_info = &rxq->rx_buffer_info[req_id]; - /* prepare physical address for DMA transaction */ - ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; - ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; - /* pass resource to device */ - rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq, - &ebuf, req_id); - if (unlikely(rc)) { - PMD_DRV_LOG(WARNING, "failed adding rx desc\n"); + rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id); + if (unlikely(rc != 0)) break; - } + rx_info->mbuf = mbuf; next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask); } @@ -2079,6 +2092,7 @@ static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, struct rte_mbuf *mbuf; struct rte_mbuf *mbuf_head; struct ena_rx_buffer *rx_info; + int rc; uint16_t ntc, len, req_id, buf = 0; if (unlikely(descs == 0)) @@ -2121,13 +2135,44 @@ static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, rx_info = &rx_ring->rx_buffer_info[req_id]; RTE_ASSERT(rx_info->mbuf != NULL); - /* Create an mbuf chain. */ - mbuf->next = rx_info->mbuf; - mbuf = mbuf->next; + if (unlikely(len == 0)) { + /* + * Some devices can pass descriptor with the length 0. + * To avoid confusion, the PMD is simply putting the + * descriptor back, as it was never used. We'll avoid + * mbuf allocation that way. + */ + rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq, + rx_info->mbuf, req_id); + if (unlikely(rc != 0)) { + /* Free the mbuf in case of an error. */ + rte_mbuf_raw_free(rx_info->mbuf); + } else { + /* + * If there was no error, just exit the loop as + * 0 length descriptor is always the last one. + */ + break; + } + } else { + /* Create an mbuf chain. */ + mbuf->next = rx_info->mbuf; + mbuf = mbuf->next; - ena_init_rx_mbuf(mbuf, len); - mbuf_head->pkt_len += len; + ena_init_rx_mbuf(mbuf, len); + mbuf_head->pkt_len += len; + } + /* + * Mark the descriptor as depleted and perform necessary + * cleanup. + * This code will execute in two cases: + * 1. Descriptor len was greater than 0 - normal situation. + * 2. Descriptor len was 0 and we failed to add the descriptor + * to the device. In that situation, we should try to add + * the mbuf again in the populate routine and mark the + * descriptor as used up by the device. + */ rx_info->mbuf = NULL; rx_ring->empty_rx_reqs[ntc] = req_id; ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); From patchwork Wed Apr 1 14:21:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67611 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2D3D8A057B; Wed, 1 Apr 2020 16:26:35 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 612261C195; Wed, 1 Apr 2020 16:22:19 +0200 (CEST) Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) by dpdk.org (Postfix) with ESMTP id 77F761C120 for ; Wed, 1 Apr 2020 16:22:14 +0200 (CEST) Received: by mail-lj1-f180.google.com with SMTP id t17so25993482ljc.12 for ; Wed, 01 Apr 2020 07:22:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BALMCJDiCDdxZYtv7NXs5mHsYjFuyMuI5FYst6tEYko=; b=kJ1iA/BkD5mHny4q3YtMB7wTcTt4yAwygaTAHa/7ovfNTP2QGtDnUaTTspPrKsXOxi wfz7BpYE77QlVs+calzi5FixecRG/OLf3hh8VgvLQXWog6Y8787X97PITUm6xKNRZKZd sTN+szW0i5wb8zBRxw1Dc5I9jUkeMt1VN4lzsbYoT517tIY0IBQzzOANUlUeXEkx3afb wukfW5UgFdIEdf++FqudvET1NzexpyVrmu7YUiCVHxxSsN1LcSDQe2P76i0rHR9MFx8Z ft69RhU+xrPd+Nk7Q9+jgD9VkzbQd4/8vg9tmj0G+PJWD3YygciCD5XfV0HSIwC3YQ+3 v9dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BALMCJDiCDdxZYtv7NXs5mHsYjFuyMuI5FYst6tEYko=; b=APaGbND6mbsHeTei0LJFt3ZKhxcpAncchQV3q/tK2CGX8XgaAXNt4ApZJ137VcNcXZ GZVQPXWtbal0hhI8KixUa4rteGJBbwGp3tIFV0rtPyp7y4pX7lLNCn+1cSlfCuPqheT6 aG1jocVNTpaEQpri66qFjXw5z3IwmtWDQEvaSHqLy8CnSKDrOZe6cy9pjKU588cgcomi rGcfhZNFkUR1n785yuebyu6GdT6noZgexLSfzj4nbaA8r/pDOTyp9sf0zkpTzvpf2juH NiRQy4MmKsSlRBZaunhvj8RhEfpTgqxSDvn3oaBdcRBAeTO+WHzJkTGefHgyjM+wrjZ5 eqZQ== X-Gm-Message-State: AGi0PubScSGyiz2acjalVr/FAx4n1Pp+O4iHuyc+jkpAu+UWOzw6bNQ/ mjirvfLDGCwzvPzWO5tYC6tinOoggkU= X-Google-Smtp-Source: APiQypK/5QfyZw6a6nxhMSbOQcDyB2AK0F3aSAxwlqUOBz9VT/Fr45deSTIyznn/Cmhg1DFqjQJ4uQ== X-Received: by 2002:a05:651c:383:: with SMTP id e3mr12687103ljp.271.1585750933681; Wed, 01 Apr 2020 07:22:13 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:13 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:25 +0200 Message-Id: <20200401142127.13715-28-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 27/29] doc: add notes on ENA usage on metal instances X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As AWS metal instances are supporting IOMMU, the usage of igb_uio or vfio-pci can lead to a problems (when to use which module), especially that the vfio-pci isn't supporting SMMU on arm64. To clear up the problem of using those modules in various setup conditions (with or without IOMMU) on metal instances, more detailed explanation was added. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- doc/guides/nics/ena.rst | 48 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst index d5081e91e5..57749eb736 100644 --- a/doc/guides/nics/ena.rst +++ b/doc/guides/nics/ena.rst @@ -187,11 +187,55 @@ Prerequisites echo 1 > /sys/module/vfio/parameters/enable_unsafe_noiommu_mode -#. Bind the intended ENA device to ``vfio-pci`` or ``igb_uio`` module. + To use ``noiommu`` mode, the ``vfio-pci`` must be built with flag + ``CONFIG_VFIO_NOIOMMU``. +#. Bind the intended ENA device to ``vfio-pci`` or ``igb_uio`` module. At this point the system should be ready to run DPDK applications. Once the -application runs to completion, the ENA can be detached from igb_uio if necessary. +application runs to completion, the ENA can be detached from attached module if +necessary. + +**Note about usage on \*.metal instances** + +On AWS, the metal instances are supporting IOMMU for both arm64 and x86_64 +hosts. + +* x86_64 (e.g. c5.metal, i3.metal): + IOMMU should be disabled by default. In that situation, the ``igb_uio`` can + be used as it is but ``vfio-pci`` should be working in no-IOMMU mode (please + see above). + + When IOMMU is enabled, ``igb_uio`` cannot be used as it's not supporting this + feature, while ``vfio-pci`` should work without any changes. + To enable IOMMU on those hosts, please update ``GRUB_CMDLINE_LINUX`` in file + ``/etc/default/grub`` with the below extra boot arguments:: + + iommu=1 intel_iommu=on + + Then, make the changes live by executing as a root:: + + # grub2-mkconfig > /boot/grub2/grub.cfg + + Finally, reboot should result in IOMMU being enabled. + +* arm64 (a1.metal): + IOMMU should be enabled by default. Unfortunately, ``vfio-pci`` isn't + supporting SMMU, which is implementation of IOMMU for arm64 architecture and + ``igb_uio`` isn't supporting IOMMU at all, so to use DPDK with ENA on those + hosts, one must disable IOMMU. This can be done by updating + ``GRUB_CMDLINE_LINUX`` in file ``/etc/default/grub`` with the extra boot + argument:: + + iommu.passthrough=1 + + Then, make the changes live by executing as a root:: + + # grub2-mkconfig > /boot/grub2/grub.cfg + + Finally, reboot should result in IOMMU being disabled. + Without IOMMU, ``igb_uio`` can be used as it is but ``vfio-pci`` should be + working in no-IOMMU mode (please see above). Usage example ------------- From patchwork Wed Apr 1 14:21:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67612 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2008FA057B; Wed, 1 Apr 2020 16:26:45 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9D6981C19A; Wed, 1 Apr 2020 16:22:20 +0200 (CEST) Received: from mail-lj1-f194.google.com (mail-lj1-f194.google.com [209.85.208.194]) by dpdk.org (Postfix) with ESMTP id BEBFC1C12C for ; Wed, 1 Apr 2020 16:22:15 +0200 (CEST) Received: by mail-lj1-f194.google.com with SMTP id t17so25993563ljc.12 for ; Wed, 01 Apr 2020 07:22:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xa/3OgtfENC1bcpjwJVSO8Q2qR3xitL1t+wthzuB/AU=; b=ReoqrbovMI8ooQijGI0T8ahTjv1dmi9mvJrTYhCUb6tCaNlwehu1O3baD8hLvtg7Bl Q8vA60g/rFGe84WhZbKw0gkeHNR72jC2gYmecqfPammH63vD2vHiK2Y47TE86K18cuaD qSy/iP55vOwgeA3xSBsOPh7u66JjD0rvST6YvfE0SolFv4Bk7svTeJSiP8FakpSHEnzY 4yjOX+kE4k9wQyZcSDT8Kn1LL9NEiIv33X1KTyatbY56XxJrJffiJ6sCQI0nBjRZVpxc xtsn8u5AE4ywvJIO+rgE0FWxgzwu6Hg5+CDtAl3FriWSt+Ka2k6uKOdD+5nHseChDopd 2SVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xa/3OgtfENC1bcpjwJVSO8Q2qR3xitL1t+wthzuB/AU=; b=XvsAtFSJ/pfNRxtoLk05Dt/LJ0LXNByBwzoGrream7Mv/NnjD9WWB43r8GpRpivHzy KsxecwKdckJM+fkcV2EQBgeSLvWSXMa086VplZ0JbZjep3veALJ8Lt+lFFY2TzLSoT4S TI6BwiMMfyteuMcX8OAAzhRCTa7vFRmTkSMDNli4omDfo+DQ+/LiCIE8QfRfCZSt6SjY tHCq9OAf1hWgaOXN8116IGwFbWg3txqVu7eO3IZuRXZaXodEdP7XAY/4pnDYuocZJ4GK cspKMTV/bDozdKAtpfSDtbbjbWVzZ2HGVm8s1nUO6IpBRdvi3W186iSUWlh1zOm11rQP KuqQ== X-Gm-Message-State: AGi0PuZFyIcoIkNX4tmjd35Ap8lQZZZeX8ildFDrPUN/3mpVz419RayH 9+76hfx/q60rU4Wtbh9WGxnvMq0oJk4= X-Google-Smtp-Source: APiQypLCQXVmeOoaQjoswyuvhVheWCpDBulNQiOKlJCLTmqs1e4ocLjPEzYaYA7ljzsjvqkXJ4im4g== X-Received: by 2002:a2e:9752:: with SMTP id f18mr13438931ljj.181.1585750935082; Wed, 01 Apr 2020 07:22:15 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:14 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:26 +0200 Message-Id: <20200401142127.13715-29-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 28/29] net/ena: update copyright date X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The v2.1.0 making changes in the ena_ethdev files were done this year, so the copyright notice should be updated. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_plat_dpdk.h | 2 +- drivers/net/ena/ena_ethdev.c | 2 +- drivers/net/ena/ena_ethdev.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index c69426a062..595967e6e3 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates. + * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. * All rights reserved. */ diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 34f910c9c4..53798b8af4 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates. + * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. * All rights reserved. */ diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 77d40d5a1e..6e24a4e582 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates. + * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. * All rights reserved. */ From patchwork Wed Apr 1 14:21:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67614 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 471A7A057B; Wed, 1 Apr 2020 16:27:05 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F1C281C1A3; Wed, 1 Apr 2020 16:22:22 +0200 (CEST) Received: from mail-lf1-f65.google.com (mail-lf1-f65.google.com [209.85.167.65]) by dpdk.org (Postfix) with ESMTP id 654341BFD4 for ; Wed, 1 Apr 2020 16:22:17 +0200 (CEST) Received: by mail-lf1-f65.google.com with SMTP id j17so20587797lfe.7 for ; Wed, 01 Apr 2020 07:22:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B9n2qm3fzdKRt9OZjJ64PleCkBVKgZt8QXVxlV1hiaA=; b=SRBZEF+xn8fTaKZVvcXqMq4LPvUWztxyQzLJCbVuoiEkPDJswhEcM4/+18wQFCqoJw rZrS0yKJ563CUI+lw/JmEnRmQOFZ6+z13g+mOE0xr3tUbJJD1oZ9TiK4u+r1QJurW1Qg J6oBeF3mlwhmcbODxHddYaxn6V5k1a0AdZchfRROw6skWm1kPVfOmkDxi24O9rvI9pBK pmm6yBaECc35EU0sjHLrYSxeHILxjNC2w6uyEmJvHO5jtuhEkc+EIa1a41et1mSadRrq pnS2OHaAo+APvmuQEi6LIhHW2mf0DNvzCIsgXRb2mxFWnOoWXKaKrfwOnClaBw7+EDnk mZkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B9n2qm3fzdKRt9OZjJ64PleCkBVKgZt8QXVxlV1hiaA=; b=MWCXmq0xCvCWpeDiXAMI2LsSR4qxqcMyqd/ahwp3hYAYXVoUCuPPH0hEUR/gFx/3eo 9eXw/q3WkxQT2WBNARivs3DwfzrE5Z/rgDjUUkqKuuUT2gJxON/bYvBagN7/BPx+x8MU WriJcrs02+PkZEzg+W4UfZuidT8hAOvy10zt63j+ApE+f7EwxjMSU+uW15txCnGaO3bP GO0K5D9oN7fvsqOgDfi0g8jwAV3nTYwq57UQvK5h3kiNs/WvtVuNGBVm0mpv/uqLTFX/ tgsPkynYBgojMqwl6gzreqLQNIgpLcAaTV6NU5HzBK+T769LPgpB54+9ohMUpwzVUzp7 ARUw== X-Gm-Message-State: AGi0PuZ6gUlvlqbUoNS7gSQPGwDgex1qeXcBhuFh+b+hjxzrHXr7+g5r 2O/+GS+kZ7HjgiURYJPEeGx1BSPNJj8= X-Google-Smtp-Source: APiQypIuC49nUT+lV19NCENEG7zkLS1TtEFenQutL4H/15NSlYlePHPo0hg66WkGcQL8frc1u9QhRw== X-Received: by 2002:a19:c781:: with SMTP id x123mr14655229lff.140.1585750936436; Wed, 01 Apr 2020 07:22:16 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:15 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:27 +0200 Message-Id: <20200401142127.13715-30-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 29/29] net/ena: update version of the driver to v2.1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The v2.1.0 is refactoring Tx and Rx paths, including few bug fixes and is also adding a new features which are going to be available with the newest hardware: * Accelerated LLQ mode * Disabling meta descriptor caching is required for that * Handling Rx descriptor which length is 0 * Tx drops are now being reported as extended statistic * Support LLQ headers higher than 96B Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/ena_ethdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 53798b8af4..b467489cc2 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -27,8 +27,8 @@ #include #define DRV_MODULE_VER_MAJOR 2 -#define DRV_MODULE_VER_MINOR 0 -#define DRV_MODULE_VER_SUBMINOR 3 +#define DRV_MODULE_VER_MINOR 1 +#define DRV_MODULE_VER_SUBMINOR 0 #define ENA_IO_TXQ_IDX(q) (2 * (q)) #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)