From patchwork Mon Mar 30 11:45:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67422 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id ED446A057B; Mon, 30 Mar 2020 13:42:20 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 668F21C031; Mon, 30 Mar 2020 13:42:15 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id BBADB2B8B for ; Mon, 30 Mar 2020 13:42:12 +0200 (CEST) IronPort-SDR: HD2dq/baCSttpac/UYP5RGQgkxEEjEIk8d/Go2ZEwW7ravgHLlkGNZldJPEv2OM8iOuRayViAv Upuj26ztl1ow== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:12 -0700 IronPort-SDR: DiPBLK36brGT4jTuNILCdHZySEwp/Oz+lbyFAFQyVJxL+Wj/g9OlZQFwwSUWo59XDsdIsFewiP 2axQ2BV8q9Qw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769833" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:11 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Beilei Xing , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:23 +0800 Message-Id: <20200330114538.43275-2-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 01/16] net/ice/base: add more macro for FDID priority X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add macro for FDID priroty 0 and 3, also adjust the fdid_prio position to sync with kernel driver. Signed-off-by: Beilei Xing Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.h | 2 +- drivers/net/ice/base/ice_lan_tx_rx.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index 86b532b73..6f11195f6 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -202,8 +202,8 @@ struct ice_fdir_fltr { u8 cnt_ena; u8 fltr_status; u16 cnt_index; - u8 fdid_prio; u32 fltr_id; + u8 fdid_prio; /* Set to true for an ACL filter */ bool acl_fltr; }; diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index 331297462..d904385cb 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -162,7 +162,9 @@ struct ice_fltr_desc { #define ICE_FXD_FLTR_QW1_FDID_PRI_S 25 #define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S) +#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO 0x0ULL #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL +#define ICE_FXD_FLTR_QW1_FDID_PRI_THREE 0x3ULL #define ICE_FXD_FLTR_QW1_FDID_MDID_S 28 #define ICE_FXD_FLTR_QW1_FDID_MDID_M (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S) From patchwork Mon Mar 30 11:45:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67423 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8FDB7A057B; Mon, 30 Mar 2020 13:42:29 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id ADEFA1C05C; Mon, 30 Mar 2020 13:42:16 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 6497A1C02D for ; Mon, 30 Mar 2020 13:42:14 +0200 (CEST) IronPort-SDR: N3By7W2EPiZFX9i5aPOoN0xSEHvwZqqoTzNonNgQQLn3M4IgKE8PVzCYFVF7lSzx/2T0ShT7WJ buJUAttA4KKQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:14 -0700 IronPort-SDR: t/9cn/FB2lWUY/nnswzBqeEkxwDaC6P646M7/oeU1snkXgsBCE5LQ9XV/onKN1bYW80p35Y6z3 mmzLoTAz+pCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769839" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:12 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Tony Nguyen , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:24 +0800 Message-Id: <20200330114538.43275-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 02/16] net/ice/base: reduce scope of variables X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The scope of these variables can be reduced, so do so. This also eliminates the need for the extra wrapping/braces. Also, compact a line since it can fit within 80 columns Signed-off-by: Tony Nguyen Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 5 +---- drivers/net/ice/base/ice_fdir.c | 3 +-- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 0cf578c34..1acac8640 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1840,9 +1840,6 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, caps->msix_vector_first_id); break; case ICE_AQC_CAPS_FD: - { - u32 reg_val, val; - if (dev_p) { dev_p->num_flow_director_fltr = number; ice_debug(hw, ICE_DBG_INIT, @@ -1851,6 +1848,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, dev_p->num_flow_director_fltr); } if (func_p) { + u32 reg_val, val; if (hw->dcf_enabled) break; reg_val = rd32(hw, GLQF_FD_SIZE); @@ -1869,7 +1867,6 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, prefix, func_p->fd_fltr_best_effort); } break; - } case ICE_AQC_CAPS_MAX_MTU: caps->max_mtu = number; ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 6dc8d54da..df754dc74 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -581,8 +581,7 @@ ice_free_fd_shrd_item(struct ice_hw *hw, u16 cntr_id, u16 num_fltr) */ int ice_get_fdir_cnt_all(struct ice_hw *hw) { - return hw->func_caps.fd_fltr_guar + - hw->func_caps.fd_fltr_best_effort; + return hw->func_caps.fd_fltr_guar + hw->func_caps.fd_fltr_best_effort; } /** From patchwork Mon Mar 30 11:45:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67424 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41113A057B; Mon, 30 Mar 2020 13:42:39 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 234DC1C07B; Mon, 30 Mar 2020 13:42:19 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 390711C068 for ; Mon, 30 Mar 2020 13:42:17 +0200 (CEST) IronPort-SDR: E9GypxZfT4wQidHDbyBwAdL/+3u/uJlQlQBVqaGCfKGHylixI0NRV3HkPQplQCf60+HJJ5ppmO 98W5X466HyCQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:16 -0700 IronPort-SDR: 175u6aZNVYRqq79gItDyAHlWXNnCcNpY3TxNEOma+aV1cMsEi2FWFLn1fpupaBUynntxLQhV3w AsAcPpVOKG+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769846" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:14 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Chinh T Cao , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:25 +0800 Message-Id: <20200330114538.43275-4-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 03/16] net/ice/base: ignore EMODE when setting PHY config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When setting the PHY cfg (CQ cmd 0x0601), if the firmware responds with an EMODE error, software will ignore the error as it simply means that manageability (ex: BMC) is in control of the link and that the new setting may not be applied. Signed-off-by: Chinh T Cao Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 1acac8640..c48a8926a 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2334,6 +2334,9 @@ ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); + if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) + status = ICE_SUCCESS; + if (!status) pi->phy.curr_user_phy_cfg = *cfg; From patchwork Mon Mar 30 11:45:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67425 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5D034A057B; Mon, 30 Mar 2020 13:42:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 791711C0AA; Mon, 30 Mar 2020 13:42:21 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 3C3071C06D for ; Mon, 30 Mar 2020 13:42:18 +0200 (CEST) IronPort-SDR: Ui61FOeYBuqekdE9gab35+7gJ/tqdVbj2QXN1/t7NalAMPPheWYeSLP82Qb8hPl6C9P6+bvj8T aJRNhVvB0cAw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:17 -0700 IronPort-SDR: faZuo9jbSw2sJMEVy/TFHCOLsXpowQc9Z6AmukZz/4pUM2wChTMeSngQ1yvxj1hJAurOWmF1by dkInTGZF/u4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769850" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:16 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , wei zhao , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:26 +0800 Message-Id: <20200330114538.43275-5-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 04/16] net/ice/base: add ethertype check for dummy packet X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In order to support switch rule for ethertype filter with ipv6 ethertype id, it has to check ethertype then find a proper dummy packet. Signed-off-by: wei zhao Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_switch.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 3d83ded6e..9c4fc0f0b 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -12,6 +12,7 @@ #define ICE_MAX_VLAN_ID 0xFFF #define ICE_IPV4_NVGRE_PROTO_ID 0x002F #define ICE_PPP_IPV6_PROTO_ID 0x0057 +#define ICE_IPV6_ETHER_ID 0x86DD /* Dummy ethernet header needed in the ice_aqc_sw_rules_elem * struct to configure any switch filter rules. @@ -5962,6 +5963,12 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, lkups[i].m_u.pppoe_hdr.ppp_prot_id == 0xFFFF) ipv6 = true; + else if (lkups[i].type == ICE_ETYPE_OL && + lkups[i].h_u.ethertype.ethtype_id == + CPU_TO_BE16(ICE_IPV6_ETHER_ID) && + lkups[i].m_u.ethertype.ethtype_id == + 0xFFFF) + ipv6 = true; } if (tun_type == ICE_SW_TUN_GTP) { From patchwork Mon Mar 30 11:45:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67426 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C1BDA057B; Mon, 30 Mar 2020 13:42:57 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D3C0B1C06D; Mon, 30 Mar 2020 13:42:23 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id E56B21C08D for ; Mon, 30 Mar 2020 13:42:19 +0200 (CEST) IronPort-SDR: VMZJ3KZajV4Ng0T0j6SSSEG8butVYN0m7sf+T9uOGtj53vxVjYw5bZ58MKy8fDAkCaKMVikHrs VJwA5EZVoIHA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:19 -0700 IronPort-SDR: 4/pXR5jE4fUeu6zDx+qd+3b5bMFz9mor9LPcG6Wy+zaMPJ8jwL1Z2VeJSC3QQe1GA6UwDEMuMb DHAEi7BOjm3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769854" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:17 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Chinh T Cao , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:27 +0800 Message-Id: <20200330114538.43275-6-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 05/16] net/ice/base: refactor function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" We will remove the logic of configuring the flow control out of the ice_set_fc(...) function. The goal is to enable any driver to combine all PHY related flow logic, without repeatedly call ice_aq_set_phy_cfg. Signed-off-by: Chinh T Cao Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 93 +++++++++++++++++++++++++-------------- 1 file changed, 59 insertions(+), 34 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index c48a8926a..dc9e54197 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2463,50 +2463,36 @@ enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) return ICE_FEC_NONE; } -/** - * ice_set_fc - * @pi: port information structure - * @aq_failures: pointer to status code, specific to ice_set_fc routine - * @ena_auto_link_update: enable automatic link update - * - * Set the requested flow control mode. - */ -enum ice_status -ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) +static enum ice_status +ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, + enum ice_fc_mode req_mode) { - struct ice_aqc_set_phy_cfg_data cfg = { 0 }; + struct ice_aqc_get_phy_caps_data *pcaps = NULL; struct ice_phy_cache_mode_data cache_data; - struct ice_aqc_get_phy_caps_data *pcaps; - enum ice_status status; + enum ice_status status = ICE_SUCCESS; u8 pause_mask = 0x0; - struct ice_hw *hw; - - if (!pi || !aq_failures) - return ICE_ERR_PARAM; - hw = pi->hw; - *aq_failures = ICE_SET_FC_AQ_FAIL_NONE; - - /* Cache user FC request */ - cache_data.data.curr_user_fc_req = pi->fc.req_mode; - ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); + if (!pi || !cfg) + return ICE_ERR_BAD_PTR; pcaps = (struct ice_aqc_get_phy_caps_data *) - ice_malloc(hw, sizeof(*pcaps)); + ice_malloc(pi->hw, sizeof(*pcaps)); if (!pcaps) return ICE_ERR_NO_MEMORY; - switch (pi->fc.req_mode) { + /* Cache user FC request */ + cache_data.data.curr_user_fc_req = req_mode; + ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); + + switch (req_mode) { case ICE_FC_AUTO: /* Query the value of FC that both the NIC and attached media * can do. */ status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); - if (status) { - *aq_failures = ICE_SET_FC_AQ_FAIL_GET; + if (status) goto out; - } pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE; pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE; @@ -2525,8 +2511,45 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) break; } + /* clear the old pause settings */ + cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | + ICE_AQC_PHY_EN_RX_LINK_PAUSE); + + /* set the new capabilities */ + cfg->caps |= pause_mask; + +out: + ice_free(pi->hw, pcaps); + return status; +} + +/** + * ice_set_fc + * @pi: port information structure + * @aq_failures: pointer to status code, specific to ice_set_fc routine + * @ena_auto_link_update: enable automatic link update + * + * Set the requested flow control mode. + */ +enum ice_status +ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) +{ + struct ice_aqc_set_phy_cfg_data cfg = { 0 }; + struct ice_aqc_get_phy_caps_data *pcaps; + enum ice_status status; + struct ice_hw *hw; + + if (!pi || !aq_failures) + return ICE_ERR_BAD_PTR; + + hw = pi->hw; + + pcaps = (struct ice_aqc_get_phy_caps_data *) + ice_malloc(hw, sizeof(*pcaps)); + if (!pcaps) + return ICE_ERR_NO_MEMORY; + /* Get the current PHY config */ - ice_memset(pcaps, 0, sizeof(*pcaps), ICE_NONDMA_MEM); status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, NULL); if (status) { @@ -2536,12 +2559,14 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); - /* clear the old pause settings */ - cfg.caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | - ICE_AQC_PHY_EN_RX_LINK_PAUSE); + /* Configure the set phy data */ + status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); + if (status) { + if (status != ICE_ERR_BAD_PTR) + *aq_failures = ICE_SET_FC_AQ_FAIL_GET; - /* set the new capabilities */ - cfg.caps |= pause_mask; + goto out; + } /* If the capabilities have changed, then set the new config */ if (cfg.caps != pcaps->caps) { From patchwork Mon Mar 30 11:45:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67427 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 59F7AA057B; Mon, 30 Mar 2020 13:43:04 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 46B741C0B2; Mon, 30 Mar 2020 13:42:25 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id C73EC1C0AE for ; Mon, 30 Mar 2020 13:42:21 +0200 (CEST) IronPort-SDR: QgEb3ZgDtkZ7fEbbLz0DJXcEw2bGFeFPTBVZ53oaa0Y5mHhvuGUhxksOJ7sTveM/xA6UuE8314 W1kpPyKpf4zA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:21 -0700 IronPort-SDR: im9NWge6MDU03y4oVUpIJGLArXAhP6wy06n81IpZRVuolPJpYc0oa11W2fEWLVoCQzOhVbw+Gq J8g4q1Zge65Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769858" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:19 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Michal Swiatkowski , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:28 +0800 Message-Id: <20200330114538.43275-7-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 06/16] net/ice/base: allow adding MAC VLAN filter on the port X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add new API function to allow user to choose port on which mac vlan rule going to be added. Signed-off-by: Michal Swiatkowski Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_switch.c | 58 +++++++++++++++++++++++++++++++-------- 1 file changed, 46 insertions(+), 12 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 9c4fc0f0b..103894f65 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -3510,14 +3510,17 @@ ice_add_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list) * ice_add_mac_vlan - Add MAC and VLAN pair based filter rule * @hw: pointer to the hardware structure * @mv_list: list of MAC and VLAN filters + * @sw: pointer to switch info struct for which function add rule + * @lport: logic port number on which function add rule * * If the VSI on which the MAC-VLAN pair has to be added has Rx and Tx VLAN * pruning bits enabled, then it is the responsibility of the caller to make * sure to add a VLAN only filter on the same VSI. Packets belonging to that * VLAN won't be received on that VSI otherwise. */ -enum ice_status -ice_add_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *mv_list) +static enum ice_status +ice_add_mac_vlan_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *mv_list, + struct ice_switch_info *sw, u8 lport) { struct ice_fltr_list_entry *mv_list_itr; struct ice_sw_recipe *recp_list; @@ -3525,7 +3528,7 @@ ice_add_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *mv_list) if (!mv_list || !hw) return ICE_ERR_PARAM; - recp_list = &hw->switch_info->recp_list[ICE_SW_LKUP_MAC_VLAN]; + recp_list = &sw->recp_list[ICE_SW_LKUP_MAC_VLAN]; LIST_FOR_EACH_ENTRY(mv_list_itr, mv_list, ice_fltr_list_entry, list_entry) { enum ice_sw_lkup_type l_type = @@ -3535,8 +3538,7 @@ ice_add_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *mv_list) return ICE_ERR_PARAM; mv_list_itr->fltr_info.flag = ICE_FLTR_TX; mv_list_itr->status = - ice_add_rule_internal(hw, recp_list, - hw->port_info->lport, + ice_add_rule_internal(hw, recp_list, lport, mv_list_itr); if (mv_list_itr->status) return mv_list_itr->status; @@ -3545,6 +3547,23 @@ ice_add_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *mv_list) } /** + * ice_add_mac_vlan - Add a MAC VLAN address based filter rule + * @hw: pointer to the hardware structure + * @mv_list: list of MAC VLAN addresses and forwarding information + * + * Function add MAC VLAN rule for logical port from HW struct + */ +enum ice_status +ice_add_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *mv_list) +{ + if (!mv_list || !hw) + return ICE_ERR_PARAM; + + return ice_add_mac_vlan_rule(hw, mv_list, hw->switch_info, + hw->port_info->lport); +} + +/** * ice_add_eth_mac_rule - Add ethertype and MAC based filter rule * @hw: pointer to the hardware structure * @em_list: list of ether type MAC filter, MAC is optional @@ -3946,18 +3965,16 @@ ice_remove_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list) } /** - * ice_remove_mac_vlan - Remove MAC VLAN based filter rule + * ice_remove_mac_vlan_rule - Remove MAC VLAN based filter rule * @hw: pointer to the hardware structure * @v_list: list of MAC VLAN entries and forwarding information + * @recp_list: list from which function remove MAC VLAN */ -enum ice_status -ice_remove_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list) +static enum ice_status +ice_remove_mac_vlan_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list, + struct ice_sw_recipe *recp_list) { struct ice_fltr_list_entry *v_list_itr, *tmp; - struct ice_sw_recipe *recp_list; - - if (!v_list || !hw) - return ICE_ERR_PARAM; recp_list = &hw->switch_info->recp_list[ICE_SW_LKUP_MAC_VLAN]; LIST_FOR_EACH_ENTRY_SAFE(v_list_itr, tmp, v_list, ice_fltr_list_entry, @@ -3976,6 +3993,23 @@ ice_remove_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list) } /** + * ice_remove_mac_vlan - remove a MAC VLAN address based filter rule + * @hw: pointer to the hardware structure + * @mv_list: list of MAC VLAN and forwarding information + */ +enum ice_status +ice_remove_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *mv_list) +{ + struct ice_sw_recipe *recp_list; + + if (!mv_list || !hw) + return ICE_ERR_PARAM; + + recp_list = &hw->switch_info->recp_list[ICE_SW_LKUP_MAC_VLAN]; + return ice_remove_mac_vlan_rule(hw, mv_list, recp_list); +} + +/** * ice_vsi_uses_fltr - Determine if given VSI uses specified filter * @fm_entry: filter entry to inspect * @vsi_handle: VSI handle to compare with filter info From patchwork Mon Mar 30 11:45:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67428 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B867EA057B; Mon, 30 Mar 2020 13:43:14 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B7D1C1C0B6; Mon, 30 Mar 2020 13:42:26 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 6141B1C02D for ; Mon, 30 Mar 2020 13:42:23 +0200 (CEST) IronPort-SDR: GRd3M7mKJ7qPMTG4RMF5JEbygDGZSOWYiusXUL7XE9Vo+o+UwChNFf+I2OaXDBlu8nh0B3n9GO 9f+m4slFroKA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:23 -0700 IronPort-SDR: PtVUW1cViRBHMYZs44jS4eBQqlpSFXelXDc1nuRhEp0gPCSkmX47wwnGDWFF5Q04hSWdPcrACB Qa34IyUCfEwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769862" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:21 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Sharon Haroni Date: Mon, 30 Mar 2020 19:45:29 +0800 Message-Id: <20200330114538.43275-8-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 07/16] net/ice/base: default DCB Parameters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added new value for cmd_flag: Persistently set the DCB configuration mode for the current port. Added new value for valid_flags: represent bit#1 of command flag Signed-off-by: Sharon Haroni Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 3344481d6..4e280f413 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -976,8 +976,10 @@ struct ice_aqc_set_query_pfc_mode { struct ice_aqc_set_dcb_params { u8 cmd_flags; /* unused in response */ #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) +#define ICE_AQC_PERSIST_DCB_CFG BIT(1) u8 valid_flags; /* unused in response */ #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) +#define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) u8 rsvd[14]; }; From patchwork Mon Mar 30 11:45:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67429 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 10D98A057B; Mon, 30 Mar 2020 13:43:25 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BAA851C0C1; Mon, 30 Mar 2020 13:42:28 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 6DE601C0B4 for ; Mon, 30 Mar 2020 13:42:25 +0200 (CEST) IronPort-SDR: /enIP5VoBrwqfhEI9qEXZ/uxEZDaUzvBCU+uT1FWN4/d5EM1VUYlFrUJWhg8tOOaNOh4Xhadyj z5FQkaZ6b5Jg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:25 -0700 IronPort-SDR: uBkAh0f6mNhrJM+rOPGPXXTrxzg6GxxLM4iFbiByyE+NKQYJgcsOCeoT7l1j0o7L62bMdfNTyK aEsAKl1y/WLA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769874" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:23 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Dan Nowlin , Wei Zhao , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:30 +0800 Message-Id: <20200330114538.43275-9-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 08/16] net/ice/base: allow profile based switch rules X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Switch rules usually match packet fields to take actions. Add capability to add a switch rule that does not match any packet fields, but instead matches the profile that the packet hits in the switch block. Signed-off-by: Dan Nowlin Signed-off-by: Wei Zhao Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_protocol_type.h | 3 ++ drivers/net/ice/base/ice_switch.c | 86 ++++++++++++++++++++++++++++++-- drivers/net/ice/base/ice_switch.h | 5 ++ 3 files changed, 89 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index eda71722d..a63ef0c96 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -61,6 +61,9 @@ enum ice_sw_tunnel_type { */ ICE_SW_TUN_GTP, ICE_SW_TUN_PPPOE, + ICE_SW_TUN_PROFID_IPV6_ESP, + ICE_SW_TUN_PROFID_IPV6_AH, + ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3, ICE_ALL_TUNNELS /* All tunnel types including NVGRE */ }; diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 103894f65..83fb40f7a 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -5147,6 +5147,19 @@ ice_create_first_fit_recp_def(struct ice_hw *hw, *recp_cnt = 0; + if (!lkup_exts->n_val_words) { + struct ice_recp_grp_entry *entry; + + entry = (struct ice_recp_grp_entry *) + ice_malloc(hw, sizeof(*entry)); + if (!entry) + return ICE_ERR_NO_MEMORY; + LIST_ADD(&entry->l_entry, rg_list); + grp = &entry->r_group; + (*recp_cnt)++; + grp->n_val_pairs = 0; + } + /* Walk through every word in the rule to check if it is not done. If so * then this word needs to be part of a new recipe. */ @@ -5679,6 +5692,9 @@ ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, u8 *prot_ids; u16 i; + if (!lkups_cnt) + return ICE_SUCCESS; + prot_ids = (u8 *)ice_calloc(hw, lkups_cnt, sizeof(*prot_ids)); if (!prot_ids) return ICE_ERR_NO_MEMORY; @@ -5736,6 +5752,8 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo, { enum ice_prof_type prof_type; + ice_zero_bitmap(bm, ICE_MAX_NUM_PROFILES); + switch (rinfo->tun_type) { case ICE_NON_TUN: prof_type = ICE_PROF_NON_TUN; @@ -5756,6 +5774,15 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo, case ICE_SW_TUN_PPPOE: prof_type = ICE_PROF_TUN_PPPOE; break; + case ICE_SW_TUN_PROFID_IPV6_ESP: + ice_set_bit(ICE_PROFID_IPV6_ESP, bm); + return; + case ICE_SW_TUN_PROFID_IPV6_AH: + ice_set_bit(ICE_PROFID_IPV6_AH, bm); + return; + case ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3: + ice_set_bit(ICE_PROFID_MAC_IPV6_L2TPV3, bm); + return; case ICE_SW_TUN_AND_NON_TUN: default: prof_type = ICE_PROF_ALL; @@ -5766,6 +5793,27 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo, } /** + * ice_is_prof_rule - determine if rule type is a profile rule + * @type: the rule type + * + * if the rule type is a profile rule, that means that there no field value + * match required, in this case just a profile hit is required. + */ +static bool ice_is_prof_rule(enum ice_sw_tunnel_type type) +{ + switch (type) { + case ICE_SW_TUN_PROFID_IPV6_ESP: + case ICE_SW_TUN_PROFID_IPV6_AH: + case ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3: + return true; + default: + break; + } + + return false; +} + +/** * ice_add_adv_recipe - Add an advanced recipe that is not part of the default * @hw: pointer to hardware structure * @lkups: lookup elements or match criteria for the advanced recipe, one @@ -5790,7 +5838,7 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, bool match_tun = false; u8 i; - if (!lkups_cnt) + if (!ice_is_prof_rule(rinfo->tun_type) && !lkups_cnt) return ICE_ERR_PARAM; lkup_exts = (struct ice_prot_lkup_ext *) @@ -5864,6 +5912,26 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, if (status) goto err_unroll; + /* An empty FV list means to use all the profiles returned in the + * profile bitmap + */ + if (LIST_EMPTY(&rm->fv_list)) { + u16 j; + + for (j = 0; j < ICE_MAX_NUM_PROFILES; j++) + if (ice_is_bit_set(fv_bitmap, j)) { + struct ice_sw_fv_list_entry *fvl; + + fvl = (struct ice_sw_fv_list_entry *) + ice_malloc(hw, sizeof(*fvl)); + if (!fvl) + goto err_unroll; + fvl->fv_ptr = NULL; + fvl->profile_id = j; + LIST_ADD(&fvl->list_entry, &rm->fv_list); + } + } + /* get bitmap of all profiles the recipe will be associated with */ ice_zero_bitmap(profiles, ICE_MAX_NUM_PROFILES); LIST_FOR_EACH_ENTRY(fvit, &rm->fv_list, ice_sw_fv_list_entry, @@ -6453,6 +6521,7 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, struct ice_switch_info *sw; enum ice_status status; const u8 *pkt = NULL; + bool prof_rule; u16 word_cnt; u32 act = 0; u8 q_rgn; @@ -6463,7 +6532,8 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, ice_init_prof_result_bm(hw); } - if (!lkups_cnt) + prof_rule = ice_is_prof_rule(rinfo->tun_type); + if (!prof_rule && !lkups_cnt) return ICE_ERR_PARAM; /* get # of words we need to match */ @@ -6476,8 +6546,14 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, if (ptr[j] != 0) word_cnt++; } - if (!word_cnt || word_cnt > ICE_MAX_CHAIN_WORDS) - return ICE_ERR_PARAM; + + if (prof_rule) { + if (word_cnt > ICE_MAX_CHAIN_WORDS) + return ICE_ERR_PARAM; + } else { + if (!word_cnt || word_cnt > ICE_MAX_CHAIN_WORDS) + return ICE_ERR_PARAM; + } /* make sure that we can locate a dummy packet */ ice_find_dummy_packet(lkups, lkups_cnt, rinfo->tun_type, &pkt, &pkt_len, @@ -6608,7 +6684,7 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, adv_fltr->lkups = (struct ice_adv_lkup_elem *) ice_memdup(hw, lkups, lkups_cnt * sizeof(*lkups), ICE_NONDMA_TO_NONDMA); - if (!adv_fltr->lkups) { + if (!adv_fltr->lkups && !prof_rule) { status = ICE_ERR_NO_MEMORY; goto err_ice_add_adv_rule; } diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index c01fa8a6d..30f3746dc 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -15,6 +15,11 @@ #define ICE_FLTR_TX BIT(1) #define ICE_FLTR_TX_RX (ICE_FLTR_RX | ICE_FLTR_TX) +/* Switch Profile IDs for Profile related switch rules */ +#define ICE_PROFID_IPV6_ESP 72 +#define ICE_PROFID_IPV6_AH 74 +#define ICE_PROFID_MAC_IPV6_L2TPV3 78 + /* Worst case buffer length for ice_aqc_opc_get_res_alloc */ #define ICE_MAX_RES_TYPES 0x80 #define ICE_AQ_GET_RES_ALLOC_BUF_LEN \ From patchwork Mon Mar 30 11:45:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67430 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CEC17A057B; Mon, 30 Mar 2020 13:43:31 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5F6AA1C0C6; Mon, 30 Mar 2020 13:42:30 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id DC7401C0B9 for ; Mon, 30 Mar 2020 13:42:26 +0200 (CEST) IronPort-SDR: BMDxTaRbtnKptAm8bjpAwWMSTFiYopzDKh6+kjPkqUlCld6iWir3I3YQsl1/EAj9dDUhYbwKRn fRI8WkWHsVHg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:26 -0700 IronPort-SDR: ZVhRHT6cEUk17BtlHEpLj83O4t6lUmuFa9DOl6TPrGLqi3IoMR9A9/FB97+vHh50QgLS7v00LU avjZJvcS4lvw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769884" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:25 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:31 +0800 Message-Id: <20200330114538.43275-10-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 09/16] net/ice/base: improve GTPU extend header handle X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" A GTPU header can stack with a extend header or not, while current implementation does not allow HDR bit sets like below: ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_GTPU_EH ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_GTPU_UP ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_GTPU_DWN Which is not convenient for upper layer flow parser to generate correct HDR bit. but it could be if we have below assumptions: ICE_FLOW_SEG_HDR_GTPU_DWN -- for GTPU with extend header down link ICE_FLOW_SEG_HDR_GTPU_UP -- for GTPU with extend header up link ICE_FLOW_SEG_HDR_GTPU_EH -- for GTPU with any extend header ICE_FLOW_SEG_HDR_GTPU_IP -- for any GTPU header, but when it combined with any above it downgrade to a dummy one. And handle from specific case to generic case will hit all the cases as expected. if else (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN) { ... } else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP) { ... } else if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) { ... } else if (hdr & ICE_FLOW_SEG_HDR_GTPU_IP { ... } Signed-off-by: Qi Zhang Signed-off-by: Paul M Stillwell Jr --- drivers/net/ice/base/ice_flow.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index e523b8f45..466fa83d6 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -656,8 +656,7 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params) /* Attributes for GTP packet with Extension Header */ params->attr = ice_attr_gtpu_eh; params->attr_cnt = ARRAY_SIZE(ice_attr_gtpu_eh); - } else if ((hdrs & ICE_FLOW_SEG_HDR_GTPU) == - ICE_FLOW_SEG_HDR_GTPU) { + } else if (hdrs & ICE_FLOW_SEG_HDR_GTPU_IP) { src = (const ice_bitmap_t *)ice_ptypes_gtpu; ice_and_bitmap(params->ptypes, params->ptypes, src, ICE_FLOW_PTYPE_MAX); From patchwork Mon Mar 30 11:45:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67431 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D0563A057B; Mon, 30 Mar 2020 13:43:40 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0D7B31C0CD; Mon, 30 Mar 2020 13:42:32 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id B5A4D1C0BF for ; Mon, 30 Mar 2020 13:42:28 +0200 (CEST) IronPort-SDR: xFjGD5KSxJKWX+/jDmMTL1corEo0H7WZfyWyPDRuZXOipz2Q01zJaZHnp1m9a/LcWfW5Vfk6V6 p0cjOxocJ/rQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:28 -0700 IronPort-SDR: GCe7x3PExGR0uIsQxJMybfHDuZuTYzIXNKf4D25WDlg9OwTdZh+5IVIVKhp+2hs7Pj2R0kHWux v1FA40ikbrMA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769892" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:26 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Evan Swanson , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:32 +0800 Message-Id: <20200330114538.43275-11-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 10/16] net/ice/base: handle critical FW error X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" A race condition between FW and SW can occur between admin queue setup and the first command sent. A link event may occur and FW attempts to notify a non-existent queue. FW will set the critical error bit and disable the queue. When this happens retry queue setup. Signed-off-by: Evan Swanson Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_controlq.c | 128 +++++++++++++++++++++--------------- drivers/net/ice/base/ice_controlq.h | 3 + drivers/net/ice/base/ice_status.h | 1 + 3 files changed, 78 insertions(+), 54 deletions(-) diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c index 0fcf62e20..41c8c7e05 100644 --- a/drivers/net/ice/base/ice_controlq.c +++ b/drivers/net/ice/base/ice_controlq.c @@ -13,6 +13,7 @@ do { \ (qinfo)->sq.bal = prefix##_ATQBAL; \ (qinfo)->sq.len_mask = prefix##_ATQLEN_ATQLEN_M; \ (qinfo)->sq.len_ena_mask = prefix##_ATQLEN_ATQENABLE_M; \ + (qinfo)->sq.len_crit_mask = prefix##_ATQLEN_ATQCRIT_M; \ (qinfo)->sq.head_mask = prefix##_ATQH_ATQH_M; \ (qinfo)->rq.head = prefix##_ARQH; \ (qinfo)->rq.tail = prefix##_ARQT; \ @@ -21,6 +22,7 @@ do { \ (qinfo)->rq.bal = prefix##_ARQBAL; \ (qinfo)->rq.len_mask = prefix##_ARQLEN_ARQLEN_M; \ (qinfo)->rq.len_ena_mask = prefix##_ARQLEN_ARQENABLE_M; \ + (qinfo)->rq.len_crit_mask = prefix##_ARQLEN_ARQCRIT_M; \ (qinfo)->rq.head_mask = prefix##_ARQH_ARQH_M; \ } while (0) @@ -610,6 +612,53 @@ static enum ice_status ice_init_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type) } /** + * ice_shutdown_ctrlq - shutdown routine for any control queue + * @hw: pointer to the hardware structure + * @q_type: specific Control queue type + * + * NOTE: this function does not destroy the control queue locks. + */ +static void ice_shutdown_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type) +{ + struct ice_ctl_q_info *cq; + + ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); + + switch (q_type) { + case ICE_CTL_Q_ADMIN: + cq = &hw->adminq; + if (ice_check_sq_alive(hw, cq)) + ice_aq_q_shutdown(hw, true); + break; + case ICE_CTL_Q_MAILBOX: + cq = &hw->mailboxq; + break; + default: + return; + } + + ice_shutdown_sq(hw, cq); + ice_shutdown_rq(hw, cq); +} + +/** + * ice_shutdown_all_ctrlq - shutdown routine for all control queues + * @hw: pointer to the hardware structure + * + * NOTE: this function does not destroy the control queue locks. The driver + * may call this at runtime to shutdown and later restart control queues, such + * as in response to a reset event. + */ +void ice_shutdown_all_ctrlq(struct ice_hw *hw) +{ + ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); + /* Shutdown FW admin queue */ + ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN); + /* Shutdown PF-VF Mailbox */ + ice_shutdown_ctrlq(hw, ICE_CTL_Q_MAILBOX); +} + +/** * ice_init_all_ctrlq - main initialization routine for all control queues * @hw: pointer to the hardware structure * @@ -625,15 +674,26 @@ static enum ice_status ice_init_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type) enum ice_status ice_init_all_ctrlq(struct ice_hw *hw) { enum ice_status status; + u32 retry = 0; ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); /* Init FW admin queue */ - status = ice_init_ctrlq(hw, ICE_CTL_Q_ADMIN); - if (status) - return status; + do { + status = ice_init_ctrlq(hw, ICE_CTL_Q_ADMIN); + if (status) + return status; + + status = ice_init_check_adminq(hw); + if (status != ICE_ERR_AQ_FW_CRITICAL) + break; + + ice_debug(hw, ICE_DBG_AQ_MSG, + "Retry Admin Queue init due to FW critical error\n"); + ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN); + ice_msec_delay(ICE_CTL_Q_ADMIN_INIT_MSEC, true); + } while (retry++ < ICE_CTL_Q_ADMIN_INIT_TIMEOUT); - status = ice_init_check_adminq(hw); if (status) return status; /* Init Mailbox queue */ @@ -677,53 +737,6 @@ enum ice_status ice_create_all_ctrlq(struct ice_hw *hw) } /** - * ice_shutdown_ctrlq - shutdown routine for any control queue - * @hw: pointer to the hardware structure - * @q_type: specific Control queue type - * - * NOTE: this function does not destroy the control queue locks. - */ -static void ice_shutdown_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type) -{ - struct ice_ctl_q_info *cq; - - ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); - - switch (q_type) { - case ICE_CTL_Q_ADMIN: - cq = &hw->adminq; - if (ice_check_sq_alive(hw, cq)) - ice_aq_q_shutdown(hw, true); - break; - case ICE_CTL_Q_MAILBOX: - cq = &hw->mailboxq; - break; - default: - return; - } - - ice_shutdown_sq(hw, cq); - ice_shutdown_rq(hw, cq); -} - -/** - * ice_shutdown_all_ctrlq - shutdown routine for all control queues - * @hw: pointer to the hardware structure - * - * NOTE: this function does not destroy the control queue locks. The driver - * may call this at runtime to shutdown and later restart control queues, such - * as in response to a reset event. - */ -void ice_shutdown_all_ctrlq(struct ice_hw *hw) -{ - ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); - /* Shutdown FW admin queue */ - ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN); - /* Shutdown PF-VF Mailbox */ - ice_shutdown_ctrlq(hw, ICE_CTL_Q_MAILBOX); -} - -/** * ice_destroy_ctrlq_locks - Destroy locks for a control queue * @cq: pointer to the control queue * @@ -1025,9 +1038,16 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, /* update the error if time out occurred */ if (!cmd_completed) { - ice_debug(hw, ICE_DBG_AQ_MSG, - "Control Send Queue Writeback timeout.\n"); - status = ICE_ERR_AQ_TIMEOUT; + if (rd32(hw, cq->rq.len) & cq->rq.len_crit_mask || + rd32(hw, cq->sq.len) & cq->sq.len_crit_mask) { + ice_debug(hw, ICE_DBG_AQ_MSG, + "Critical FW error.\n"); + status = ICE_ERR_AQ_FW_CRITICAL; + } else { + ice_debug(hw, ICE_DBG_AQ_MSG, + "Control Send Queue Writeback timeout.\n"); + status = ICE_ERR_AQ_TIMEOUT; + } } sq_send_command_error: diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h index 464a2adb7..f47fd4346 100644 --- a/drivers/net/ice/base/ice_controlq.h +++ b/drivers/net/ice/base/ice_controlq.h @@ -35,6 +35,8 @@ enum ice_ctl_q { /* Control Queue timeout settings - max delay 250ms */ #define ICE_CTL_Q_SQ_CMD_TIMEOUT 2500 /* Count 2500 times */ #define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */ +#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */ +#define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */ struct ice_ctl_q_ring { void *dma_head; /* Virtual address to DMA head */ @@ -60,6 +62,7 @@ struct ice_ctl_q_ring { u32 bal; u32 len_mask; u32 len_ena_mask; + u32 len_crit_mask; u32 head_mask; }; diff --git a/drivers/net/ice/base/ice_status.h b/drivers/net/ice/base/ice_status.h index 7bcccd39a..446702f9a 100644 --- a/drivers/net/ice/base/ice_status.h +++ b/drivers/net/ice/base/ice_status.h @@ -42,6 +42,7 @@ enum ice_status { ICE_ERR_AQ_FULL = -102, ICE_ERR_AQ_NO_WORK = -103, ICE_ERR_AQ_EMPTY = -104, + ICE_ERR_AQ_FW_CRITICAL = -105, }; #endif /* _ICE_STATUS_H_ */ From patchwork Mon Mar 30 11:45:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67432 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 137E8A057B; Mon, 30 Mar 2020 13:43:52 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 93CCE1C0D4; Mon, 30 Mar 2020 13:42:33 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 5E2AD1C0C5 for ; Mon, 30 Mar 2020 13:42:30 +0200 (CEST) IronPort-SDR: U1K4O3pCmbFKS02OWeBOh/bKKHP40rtBEmX4N5aAnRw2pNNoQzg0q8HwwPo1HodmAALTR/tWnH nTaivD1dSgNw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:30 -0700 IronPort-SDR: yOtR01pWbTMgvGc4eGZ50iQgveHmwxfAaqVIX1pPqJdDzYgT/q7bU7hBoiuFWE9gMMajtOjLij nTSKiWX4skbw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769898" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:28 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Tony Nguyen , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:33 +0800 Message-Id: <20200330114538.43275-12-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 11/16] net/ice/base: group case statements X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" ICE_BLK_FD and ICE_BLK_RSS are executing the same code so group the case statements together instead of duplicating code for each block. Signed-off-by: Tony Nguyen Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 466fa83d6..c369aae84 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -1161,10 +1161,8 @@ ice_flow_proc_segs(struct ice_hw *hw, struct ice_flow_prof_params *params) return status; switch (params->blk) { + case ICE_BLK_FD: case ICE_BLK_RSS: - /* Only header information is provided for RSS configuration. - * No further processing is needed. - */ status = ICE_SUCCESS; break; case ICE_BLK_ACL: @@ -1175,9 +1173,6 @@ ice_flow_proc_segs(struct ice_hw *hw, struct ice_flow_prof_params *params) if (status) return status; break; - case ICE_BLK_FD: - status = ICE_SUCCESS; - break; case ICE_BLK_SW: default: return ICE_ERR_NOT_IMPL; @@ -2696,8 +2691,8 @@ ice_flow_add_entry(struct ice_hw *hw, enum ice_block blk, u64 prof_id, e->priority = prio; switch (blk) { + case ICE_BLK_FD: case ICE_BLK_RSS: - /* RSS will add only one entry per VSI per profile */ break; case ICE_BLK_ACL: /* ACL will handle the entry management */ @@ -2711,8 +2706,6 @@ ice_flow_add_entry(struct ice_hw *hw, enum ice_block blk, u64 prof_id, goto out; break; - case ICE_BLK_FD: - break; case ICE_BLK_SW: case ICE_BLK_PE: default: From patchwork Mon Mar 30 11:45:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67433 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C9C49A057B; Mon, 30 Mar 2020 13:43:58 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 15E201C0D8; Mon, 30 Mar 2020 13:42:36 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 3578A1C0D0 for ; Mon, 30 Mar 2020 13:42:32 +0200 (CEST) IronPort-SDR: 2acWA1srXelfPE9J3xe+YwJX3gMtLIlf0NjWkD93rsdxaqPpfnjxU56zbepCMFPBePe/z/leom UE7U2GbxJksw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:31 -0700 IronPort-SDR: I1wOFuUO9PFD2/PeoV/rxOBsQsm2j8GwAJnY2/jgwqaSHUO0vLUSK8guCiQLrlzRE53c2/xqQI j8TgpWfaku7w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769904" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:30 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Xiao Zhang , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:34 +0800 Message-Id: <20200330114538.43275-13-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 12/16] net/ice/base: move some macro X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Move some macro from ice_switch.c to ice_switch.h. Currently this is only required by kernel driver, DPDK just to sync the code. Signed-off-by: Xiao Zhang Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_switch.c | 22 ---------------------- drivers/net/ice/base/ice_switch.h | 22 ++++++++++++++++++++++ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 83fb40f7a..ff479cdd2 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -29,32 +29,10 @@ * In case of Ether type filter it is treated as header without VLAN tag * and byte 12 and 13 is used to program a given Ether type instead */ -#define DUMMY_ETH_HDR_LEN 16 static const u8 dummy_eth_header[DUMMY_ETH_HDR_LEN] = { 0x2, 0, 0, 0, 0, 0, 0x2, 0, 0, 0, 0, 0, 0x81, 0, 0, 0}; -#define ICE_SW_RULE_RX_TX_ETH_HDR_SIZE \ - (sizeof(struct ice_aqc_sw_rules_elem) - \ - sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \ - sizeof(struct ice_sw_rule_lkup_rx_tx) + DUMMY_ETH_HDR_LEN - 1) -#define ICE_SW_RULE_RX_TX_NO_HDR_SIZE \ - (sizeof(struct ice_aqc_sw_rules_elem) - \ - sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \ - sizeof(struct ice_sw_rule_lkup_rx_tx) - 1) -#define ICE_SW_RULE_LG_ACT_SIZE(n) \ - (sizeof(struct ice_aqc_sw_rules_elem) - \ - sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \ - sizeof(struct ice_sw_rule_lg_act) - \ - sizeof(((struct ice_sw_rule_lg_act *)0)->act) + \ - ((n) * sizeof(((struct ice_sw_rule_lg_act *)0)->act))) -#define ICE_SW_RULE_VSI_LIST_SIZE(n) \ - (sizeof(struct ice_aqc_sw_rules_elem) - \ - sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \ - sizeof(struct ice_sw_rule_vsi_list) - \ - sizeof(((struct ice_sw_rule_vsi_list *)0)->vsi) + \ - ((n) * sizeof(((struct ice_sw_rule_vsi_list *)0)->vsi))) - struct ice_dummy_pkt_offsets { enum ice_protocol_type type; u16 offset; /* ICE_PROTOCOL_LAST indicates end of list */ diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index 30f3746dc..cf9f6fd73 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -20,6 +20,28 @@ #define ICE_PROFID_IPV6_AH 74 #define ICE_PROFID_MAC_IPV6_L2TPV3 78 +#define DUMMY_ETH_HDR_LEN 16 +#define ICE_SW_RULE_RX_TX_ETH_HDR_SIZE \ + (sizeof(struct ice_aqc_sw_rules_elem) - \ + sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \ + sizeof(struct ice_sw_rule_lkup_rx_tx) + DUMMY_ETH_HDR_LEN - 1) +#define ICE_SW_RULE_RX_TX_NO_HDR_SIZE \ + (sizeof(struct ice_aqc_sw_rules_elem) - \ + sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \ + sizeof(struct ice_sw_rule_lkup_rx_tx) - 1) +#define ICE_SW_RULE_LG_ACT_SIZE(n) \ + (sizeof(struct ice_aqc_sw_rules_elem) - \ + sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \ + sizeof(struct ice_sw_rule_lg_act) - \ + sizeof(((struct ice_sw_rule_lg_act *)0)->act) + \ + ((n) * sizeof(((struct ice_sw_rule_lg_act *)0)->act))) +#define ICE_SW_RULE_VSI_LIST_SIZE(n) \ + (sizeof(struct ice_aqc_sw_rules_elem) - \ + sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \ + sizeof(struct ice_sw_rule_vsi_list) - \ + sizeof(((struct ice_sw_rule_vsi_list *)0)->vsi) + \ + ((n) * sizeof(((struct ice_sw_rule_vsi_list *)0)->vsi))) + /* Worst case buffer length for ice_aqc_opc_get_res_alloc */ #define ICE_MAX_RES_TYPES 0x80 #define ICE_AQ_GET_RES_ALLOC_BUF_LEN \ From patchwork Mon Mar 30 11:45:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67434 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 923E6A057B; Mon, 30 Mar 2020 13:44:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 376061C10B; Mon, 30 Mar 2020 13:42:37 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 130381C0D0 for ; Mon, 30 Mar 2020 13:42:33 +0200 (CEST) IronPort-SDR: uHHS9SpgX93vIGOyyecizGmIBiSL3dUFKqAoCZOVi/BPQaAPgbumKB6NATJFQ2FpotbbzCnNx7 lc+MVIUoSNWA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:33 -0700 IronPort-SDR: rpQEHhC5pF+O3k0iqTbVD9h51z5JZZR2fYZZHOjBSW2t5lkod8iJyxnK9/nKPiIlucMovoz+q4 lypQiOeL83dA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769910" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:32 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Wei Zhao , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:35 +0800 Message-Id: <20200330114538.43275-14-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 13/16] net/ice/base: add support for PFCP and NAT-T of switch X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch add support switch rule for PFCP and NAT-T packet base on profile rule, PFCP and NAT-T packet will not be matched on any packet fields, but instead matches the profile that the packet hits in the switch block. Signed-off-by: Wei Zhao Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_protocol_type.h | 5 +++++ drivers/net/ice/base/ice_switch.c | 20 ++++++++++++++++++++ drivers/net/ice/base/ice_switch.h | 5 +++++ 3 files changed, 30 insertions(+) diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index a63ef0c96..3588be0ca 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -64,6 +64,11 @@ enum ice_sw_tunnel_type { ICE_SW_TUN_PROFID_IPV6_ESP, ICE_SW_TUN_PROFID_IPV6_AH, ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3, + ICE_SW_TUN_PROFID_IPV6_NAT_T, + ICE_SW_TUN_PROFID_IPV4_PFCP_NODE, + ICE_SW_TUN_PROFID_IPV4_PFCP_SESSION, + ICE_SW_TUN_PROFID_IPV6_PFCP_NODE, + ICE_SW_TUN_PROFID_IPV6_PFCP_SESSION, ICE_ALL_TUNNELS /* All tunnel types including NVGRE */ }; diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index ff479cdd2..b5aa5abd9 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -5761,6 +5761,21 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo, case ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3: ice_set_bit(ICE_PROFID_MAC_IPV6_L2TPV3, bm); return; + case ICE_SW_TUN_PROFID_IPV6_NAT_T: + ice_set_bit(ICE_PROFID_IPV6_NAT_T, bm); + return; + case ICE_SW_TUN_PROFID_IPV4_PFCP_NODE: + ice_set_bit(ICE_PROFID_IPV4_PFCP_NODE, bm); + return; + case ICE_SW_TUN_PROFID_IPV4_PFCP_SESSION: + ice_set_bit(ICE_PROFID_IPV4_PFCP_SESSION, bm); + return; + case ICE_SW_TUN_PROFID_IPV6_PFCP_NODE: + ice_set_bit(ICE_PROFID_IPV6_PFCP_NODE, bm); + return; + case ICE_SW_TUN_PROFID_IPV6_PFCP_SESSION: + ice_set_bit(ICE_PROFID_IPV6_PFCP_SESSION, bm); + return; case ICE_SW_TUN_AND_NON_TUN: default: prof_type = ICE_PROF_ALL; @@ -5783,6 +5798,11 @@ static bool ice_is_prof_rule(enum ice_sw_tunnel_type type) case ICE_SW_TUN_PROFID_IPV6_ESP: case ICE_SW_TUN_PROFID_IPV6_AH: case ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3: + case ICE_SW_TUN_PROFID_IPV6_NAT_T: + case ICE_SW_TUN_PROFID_IPV4_PFCP_NODE: + case ICE_SW_TUN_PROFID_IPV4_PFCP_SESSION: + case ICE_SW_TUN_PROFID_IPV6_PFCP_NODE: + case ICE_SW_TUN_PROFID_IPV6_PFCP_SESSION: return true; default: break; diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index cf9f6fd73..f7ae5c741 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -18,7 +18,12 @@ /* Switch Profile IDs for Profile related switch rules */ #define ICE_PROFID_IPV6_ESP 72 #define ICE_PROFID_IPV6_AH 74 +#define ICE_PROFID_IPV6_NAT_T 76 #define ICE_PROFID_MAC_IPV6_L2TPV3 78 +#define ICE_PROFID_IPV4_PFCP_NODE 79 +#define ICE_PROFID_IPV4_PFCP_SESSION 80 +#define ICE_PROFID_IPV6_PFCP_NODE 81 +#define ICE_PROFID_IPV6_PFCP_SESSION 82 #define DUMMY_ETH_HDR_LEN 16 #define ICE_SW_RULE_RX_TX_ETH_HDR_SIZE \ From patchwork Mon Mar 30 11:45:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67435 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 959AEA057B; Mon, 30 Mar 2020 13:44:17 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 37CDE1C118; Mon, 30 Mar 2020 13:42:40 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id DDC431C0D0 for ; Mon, 30 Mar 2020 13:42:35 +0200 (CEST) IronPort-SDR: udn+HSZeiM0ZGKwblgWunhbh+xznWW1crc2rhSPDwvs/QUD8TUnZsGE5PlK3ERPrQhvQTaOlKk t0kMDbGYVKrA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:35 -0700 IronPort-SDR: wyZ5MTW6dOil/KcXkuoXyleyoS1xq7oC4KfrV3mI5XOsv12HUvquz4ZFj7+qrovX9/w3B/A3OX h/hLg0r4TEQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769918" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:33 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Tony Nguyen , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:36 +0800 Message-Id: <20200330114538.43275-15-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 14/16] net/ice/base: change function to static X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Change ice_set_fd_desc_val to static, since it only be used internally. Signed-off-by: Tony Nguyen Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 97 +++++++++++++++++++---------------------- drivers/net/ice/base/ice_fdir.h | 3 -- 2 files changed, 45 insertions(+), 55 deletions(-) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index df754dc74..c703a7c6b 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -381,62 +381,11 @@ ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx) } /** - * ice_fdir_get_prgm_desc - set a fdir descriptor from a fdir filter struct - * @hw: pointer to the hardware structure - * @input: filter - * @fdesc: filter descriptor - * @add: if add is true, this is an add operation, false implies delete - */ -void -ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input, - struct ice_fltr_desc *fdesc, bool add) -{ - struct ice_fd_fltr_desc_ctx fdir_fltr_ctx = { 0 }; - - /* set default context info */ - ice_set_dflt_val_fd_desc(&fdir_fltr_ctx); - - /* change sideband filtering values */ - fdir_fltr_ctx.fdid = input->fltr_id; - if (input->dest_ctl == ICE_FLTR_PRGM_DESC_DEST_DROP_PKT) { - fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_YES; - fdir_fltr_ctx.qindex = 0; - } else if (input->dest_ctl == - ICE_FLTR_PRGM_DESC_DEST_DIRECT_PKT_OTHER) { - fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_NO; - fdir_fltr_ctx.qindex = 0; - } else { - if (input->dest_ctl == - ICE_FLTR_PRGM_DESC_DEST_DIRECT_PKT_QGROUP) - fdir_fltr_ctx.toq = input->q_region; - fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_NO; - fdir_fltr_ctx.qindex = input->q_index; - } - fdir_fltr_ctx.cnt_ena = input->cnt_ena; - fdir_fltr_ctx.cnt_index = input->cnt_index; - fdir_fltr_ctx.fd_vsi = ice_get_hw_vsi_num(hw, input->dest_vsi); - fdir_fltr_ctx.evict_ena = ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE; - if (input->dest_ctl == ICE_FLTR_PRGM_DESC_DEST_DIRECT_PKT_OTHER) - fdir_fltr_ctx.toq_prio = 0; - else - fdir_fltr_ctx.toq_prio = 3; - fdir_fltr_ctx.pcmd = (add) ? ICE_FXD_FLTR_QW1_PCMD_ADD : - ICE_FXD_FLTR_QW1_PCMD_REMOVE; - fdir_fltr_ctx.swap = ICE_FXD_FLTR_QW1_SWAP_NOT_SET; - fdir_fltr_ctx.comp_q = ICE_FXD_FLTR_QW0_COMP_Q_ZERO; - fdir_fltr_ctx.comp_report = ICE_FXD_FLTR_QW0_COMP_REPORT_SW; - fdir_fltr_ctx.fdid_prio = input->fdid_prio; - fdir_fltr_ctx.desc_prof = 1; - fdir_fltr_ctx.desc_prof_prio = 3; - ice_set_fd_desc_val(&fdir_fltr_ctx, fdesc); -} - -/** * ice_set_fd_desc_val * @ctx: pointer to fd filter descriptor context * @fdir_desc: populated with fd filter descriptor values */ -void +static void ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *ctx, struct ice_fltr_desc *fdir_desc) { @@ -496,6 +445,50 @@ ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *ctx, } /** + * ice_fdir_get_prgm_desc - set a fdir descriptor from a fdir filter struct + * @hw: pointer to the hardware structure + * @input: filter + * @fdesc: filter descriptor + * @add: if add is true, this is an add operation, false implies delete + */ +void +ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input, + struct ice_fltr_desc *fdesc, bool add) +{ + struct ice_fd_fltr_desc_ctx fdir_fltr_ctx = { 0 }; + + /* set default context info */ + ice_set_dflt_val_fd_desc(&fdir_fltr_ctx); + + /* change sideband filtering values */ + fdir_fltr_ctx.fdid = input->fltr_id; + if (input->dest_ctl == ICE_FLTR_PRGM_DESC_DEST_DROP_PKT) { + fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_YES; + fdir_fltr_ctx.qindex = 0; + } else { + if (input->dest_ctl == + ICE_FLTR_PRGM_DESC_DEST_DIRECT_PKT_QGROUP) + fdir_fltr_ctx.toq = input->q_region; + fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_NO; + fdir_fltr_ctx.qindex = input->q_index; + } + fdir_fltr_ctx.cnt_ena = input->cnt_ena; + fdir_fltr_ctx.cnt_index = input->cnt_index; + fdir_fltr_ctx.fd_vsi = ice_get_hw_vsi_num(hw, input->dest_vsi); + fdir_fltr_ctx.evict_ena = ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE; + fdir_fltr_ctx.toq_prio = 3; + fdir_fltr_ctx.pcmd = (add) ? ICE_FXD_FLTR_QW1_PCMD_ADD : + ICE_FXD_FLTR_QW1_PCMD_REMOVE; + fdir_fltr_ctx.swap = ICE_FXD_FLTR_QW1_SWAP_NOT_SET; + fdir_fltr_ctx.comp_q = ICE_FXD_FLTR_QW0_COMP_Q_ZERO; + fdir_fltr_ctx.comp_report = ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL; + fdir_fltr_ctx.fdid_prio = input->fdid_prio; + fdir_fltr_ctx.desc_prof = 1; + fdir_fltr_ctx.desc_prof_prio = 3; + ice_set_fd_desc_val(&fdir_fltr_ctx, fdesc); +} + +/** * ice_alloc_fd_res_cntr - obtain counter resource for FD type * @hw: pointer to the hardware structure * @cntr_id: returns counter index diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index 6f11195f6..21a83fd6c 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -36,9 +36,6 @@ struct ice_fd_fltr_desc_ctx { enum ice_status ice_alloc_fd_res_cntr(struct ice_hw *hw, u16 *cntr_id); enum ice_status ice_free_fd_res_cntr(struct ice_hw *hw, u16 cntr_id); -void -ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx, - struct ice_fltr_desc *fdir_desc); void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx); enum ice_status ice_alloc_fd_guar_item(struct ice_hw *hw, u16 *cntr_id, u16 num_fltr); From patchwork Mon Mar 30 11:45:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67436 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9D314A057B; Mon, 30 Mar 2020 13:44:26 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8EEB61C116; Mon, 30 Mar 2020 13:42:41 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id DFD712B8B; Mon, 30 Mar 2020 13:42:37 +0200 (CEST) IronPort-SDR: 1TGCCbTpgABm4v4xa3ZHAAQCsf03fgxoLkXmHWMYMyY73VnFrte/DsquyyfABjt/dPWTHXNA6b +tDwAE58cFXw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:37 -0700 IronPort-SDR: YPmotwQsJMXoAwET9hTY3Pj9mzMgvrzQXGytxiSDmo5UfRZp6zWTPzm72miuFYZKS4BtSXXn2Y LyW2fj9y2Eyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769924" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:35 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , stable@dpdk.org, Ting Xu , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:37 +0800 Message-Id: <20200330114538.43275-16-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 15/16] net/ice/base: fix binary order for gtpu FDIR filter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Take network order for gtpu fdir filter. Fixes: b5c274f4e2ad ("net/ice/base: support FDIR for GTPU QFI field") Cc: stable@dpdk.org Signed-off-by: Ting Xu Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index 21a83fd6c..e52104e9a 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -148,9 +148,9 @@ struct ice_fdir_v6 { struct ice_fdir_udp_gtp { u8 flags; u8 msg_type; - u16 rsrvd_len; - u32 teid; - u16 rsrvd_seq_nbr; + __be16 rsrvd_len; + __be32 teid; + __be16 rsrvd_seq_nbr; u8 rsrvd_n_pdu_nbr; u8 rsrvd_next_ext_type; u8 rsvrd_ext_len; From patchwork Mon Mar 30 11:45:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 67437 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5847DA057B; Mon, 30 Mar 2020 13:44:35 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 021741C123; Mon, 30 Mar 2020 13:42:43 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id F37291C116 for ; Mon, 30 Mar 2020 13:42:39 +0200 (CEST) IronPort-SDR: PHUNcbzHI9Fh7DZdhEHccu12ecw5IGqzJOARsRBzuouwUktNT/Rxih8rg0q3hCoxadzutyumb2 4jzqNLYunFCw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 04:42:39 -0700 IronPort-SDR: 2To+DkTyCwadyNC/X7vpaskzGFyah8S3u6HyU2sphW+GivVC9sQcNTEuJCvg0EAvU4SMdTRldI Tk5uurt3Dd3Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="449769932" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga006.fm.intel.com with ESMTP; 30 Mar 2020 04:42:37 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Ting Xu , Paul M Stillwell Jr Date: Mon, 30 Mar 2020 19:45:38 +0800 Message-Id: <20200330114538.43275-17-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200330114538.43275-1-qi.z.zhang@intel.com> References: <20200330114538.43275-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 16/16] net/ice/base: enable RSS support for PFCP L2TP ESP and AH X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for PFCP, L2TP, ESP and AH RSS enabling. Signed-off-by: Ting Xu Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_bitops.h | 31 ++++++ drivers/net/ice/base/ice_flow.c | 163 +++++++++++++++++++++++++++++-- drivers/net/ice/base/ice_flow.h | 53 ++++++++++ drivers/net/ice/base/ice_protocol_type.h | 41 +++++++- 4 files changed, 280 insertions(+), 8 deletions(-) diff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h index bcdee63c0..0643904db 100644 --- a/drivers/net/ice/base/ice_bitops.h +++ b/drivers/net/ice/base/ice_bitops.h @@ -259,6 +259,37 @@ ice_xor_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1, } /** + * ice_andnot_bitmap - bitwise ANDNOT 2 bitmaps and result in dst bitmap + * @dst: Destination bitmap that receive the result of the operation + * @bmp1: The first bitmap of ANDNOT operation + * @bmp2: The second bitmap to ANDNOT operation + * @size: Size of the bitmaps in bits + * + * This function performs a bitwise ANDNOT on two "source" bitmaps of the same + * size, and stores the result to "dst" bitmap. The "dst" bitmap must be of the + * same size as the "source" bitmaps to avoid buffer overflows. + */ +static inline void +ice_andnot_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1, + const ice_bitmap_t *bmp2, u16 size) +{ + ice_bitmap_t mask; + u16 i; + + /* Handle all but last chunk*/ + for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++) + dst[i] = bmp1[i] & ~bmp2[i]; + + /* We want to only clear bits within the size. Furthermore, we also do + * not want to modify destination bits which are beyond the specified + * size. Use a bitmask to ensure that we only modify the bits that are + * within the specified size. + */ + mask = LAST_CHUNK_MASK(size); + dst[i] = (dst[i] & ~mask) | ((bmp1[i] & ~bmp2[i]) & mask); +} + +/** * ice_find_next_bit - Find the index of the next set bit of a bitmap * @bitmap: the bitmap to scan * @size: the size in bits of the bitmap diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index c369aae84..c876377ed 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -22,6 +22,11 @@ #define ICE_FLOW_FLD_SZ_GTP_TEID 4 #define ICE_FLOW_FLD_SZ_GTP_QFI 2 #define ICE_FLOW_FLD_SZ_PPPOE_SESS_ID 2 +#define ICE_FLOW_FLD_SZ_PFCP_SEID 8 +#define ICE_FLOW_FLD_SZ_L2TPV3_SESS_ID 4 +#define ICE_FLOW_FLD_SZ_ESP_SPI 4 +#define ICE_FLOW_FLD_SZ_AH_SPI 4 +#define ICE_FLOW_FLD_SZ_NAT_T_ESP_SPI 4 /* Describe properties of a protocol header field */ struct ice_flow_field_info { @@ -143,6 +148,26 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { /* ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_PPPOE, 2, ICE_FLOW_FLD_SZ_PPPOE_SESS_ID), + /* PFCP */ + /* ICE_FLOW_FIELD_IDX_PFCP_SEID */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_PFCP_SESSION, 12, + ICE_FLOW_FLD_SZ_PFCP_SEID), + /* L2TPV3 */ + /* ICE_FLOW_FIELD_IDX_L2TPV3_SESS_ID */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_L2TPV3, 0, + ICE_FLOW_FLD_SZ_L2TPV3_SESS_ID), + /* ESP */ + /* ICE_FLOW_FIELD_IDX_ESP_SPI */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ESP, 0, + ICE_FLOW_FLD_SZ_ESP_SPI), + /* AH */ + /* ICE_FLOW_FIELD_IDX_AH_SPI */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_AH, 4, + ICE_FLOW_FLD_SZ_AH_SPI), + /* NAT_T_ESP */ + /* ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_NAT_T_ESP, 8, + ICE_FLOW_FLD_SZ_NAT_T_ESP_SPI), }; /* Bitmaps indicating relevant packet types for a particular protocol header @@ -175,8 +200,8 @@ static const u32 ice_ptypes_macvlan_il[] = { /* Packet types for packets with an Outer/First/Single IPv4 header */ static const u32 ice_ptypes_ipv4_ofos[] = { 0x1DC00000, 0x04000800, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x0003000F, 0x000FC000, 0x03E0F800, 0x00000000, + 0x00000000, 0x00000155, 0x00000000, 0x00000000, + 0x0003000F, 0x000FC000, 0x83E0F800, 0x00000101, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -199,8 +224,8 @@ static const u32 ice_ptypes_ipv4_il[] = { /* Packet types for packets with an Outer/First/Single IPv6 header */ static const u32 ice_ptypes_ipv6_ofos[] = { 0x00000000, 0x00000000, 0x77000000, 0x10002000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00080F00, 0x03F00000, 0x7C1F0000, 0x00000000, + 0x00000000, 0x000002AA, 0x00000000, 0x00000000, + 0x00080F00, 0x03F00000, 0x7C1F0000, 0x00000206, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -238,7 +263,7 @@ static const u32 ice_ptypes_arp_of[] = { static const u32 ice_ptypes_udp_il[] = { 0x81000000, 0x20204040, 0x04000010, 0x80810102, 0x00000040, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00410000, 0x10842000, 0x00000000, + 0x00000000, 0x00410000, 0x90842000, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -435,6 +460,78 @@ static const u32 ice_ptypes_pppoe[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; +/* Packet types for packets with PFCP NODE header */ +static const u32 ice_ptypes_pfcp_node[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x80000000, 0x00000002, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +/* Packet types for packets with PFCP SESSION header */ +static const u32 ice_ptypes_pfcp_session[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000005, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +/* Packet types for l2tpv3 */ +static const u32 ice_ptypes_l2tpv3[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000300, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +/* Packet types for esp */ +static const u32 ice_ptypes_esp[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000003, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +/* Packet types for ah */ +static const u32 ice_ptypes_ah[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x0000000C, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +/* Packet types for packets with NAT_T ESP header */ +static const u32 ice_ptypes_nat_t_esp[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000030, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + /* Manage parameters and info. used during the creation of a flow profile */ struct ice_flow_prof_params { enum ice_block blk; @@ -456,7 +553,10 @@ struct ice_flow_prof_params { #define ICE_FLOW_RSS_HDRS_INNER_MASK \ (ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_GTPC | \ - ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU) + ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU | \ + ICE_FLOW_SEG_HDR_PFCP_SESSION | ICE_FLOW_SEG_HDR_L2TPV3 | \ + ICE_FLOW_SEG_HDR_ESP | ICE_FLOW_SEG_HDR_AH | \ + ICE_FLOW_SEG_HDR_NAT_T_ESP) #define ICE_FLOW_SEG_HDRS_L2_MASK \ (ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN) @@ -660,6 +760,42 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params) src = (const ice_bitmap_t *)ice_ptypes_gtpu; ice_and_bitmap(params->ptypes, params->ptypes, src, ICE_FLOW_PTYPE_MAX); + } else if (hdrs & ICE_FLOW_SEG_HDR_L2TPV3) { + src = (const ice_bitmap_t *)ice_ptypes_l2tpv3; + ice_and_bitmap(params->ptypes, params->ptypes, + src, ICE_FLOW_PTYPE_MAX); + } else if (hdrs & ICE_FLOW_SEG_HDR_ESP) { + src = (const ice_bitmap_t *)ice_ptypes_esp; + ice_and_bitmap(params->ptypes, params->ptypes, + src, ICE_FLOW_PTYPE_MAX); + } else if (hdrs & ICE_FLOW_SEG_HDR_AH) { + src = (const ice_bitmap_t *)ice_ptypes_ah; + ice_and_bitmap(params->ptypes, params->ptypes, + src, ICE_FLOW_PTYPE_MAX); + } else if (hdrs & ICE_FLOW_SEG_HDR_NAT_T_ESP) { + src = (const ice_bitmap_t *)ice_ptypes_nat_t_esp; + ice_and_bitmap(params->ptypes, params->ptypes, + src, ICE_FLOW_PTYPE_MAX); + } + + if (hdrs & ICE_FLOW_SEG_HDR_PFCP) { + if (hdrs & ICE_FLOW_SEG_HDR_PFCP_NODE) + src = + (const ice_bitmap_t *)ice_ptypes_pfcp_node; + else + src = + (const ice_bitmap_t *)ice_ptypes_pfcp_session; + + ice_and_bitmap(params->ptypes, params->ptypes, + src, ICE_FLOW_PTYPE_MAX); + } else { + src = (const ice_bitmap_t *)ice_ptypes_pfcp_node; + ice_andnot_bitmap(params->ptypes, params->ptypes, + src, ICE_FLOW_PTYPE_MAX); + + src = (const ice_bitmap_t *)ice_ptypes_pfcp_session; + ice_andnot_bitmap(params->ptypes, params->ptypes, + src, ICE_FLOW_PTYPE_MAX); } } @@ -817,6 +953,21 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, case ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID: prot_id = ICE_PROT_PPPOE; break; + case ICE_FLOW_FIELD_IDX_PFCP_SEID: + prot_id = ICE_PROT_UDP_IL_OR_S; + break; + case ICE_FLOW_FIELD_IDX_L2TPV3_SESS_ID: + prot_id = ICE_PROT_L2TPV3; + break; + case ICE_FLOW_FIELD_IDX_ESP_SPI: + prot_id = ICE_PROT_ESP_F; + break; + case ICE_FLOW_FIELD_IDX_AH_SPI: + prot_id = ICE_PROT_ESP_2; + break; + case ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI: + prot_id = ICE_PROT_UDP_IL_OR_S; + break; case ICE_FLOW_FIELD_IDX_ARP_SIP: case ICE_FLOW_FIELD_IDX_ARP_DIP: case ICE_FLOW_FIELD_IDX_ARP_SHA: diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index fd30b1a68..37f1c76ae 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -82,6 +82,41 @@ #define ICE_FLOW_HASH_PPPOE_UDP_ID \ (ICE_FLOW_HASH_UDP_PORT | ICE_FLOW_HASH_PPPOE_SESS_ID) +#define ICE_FLOW_HASH_PFCP_SEID \ + (BIT_ULL(ICE_FLOW_FIELD_IDX_PFCP_SEID)) +#define ICE_FLOW_HASH_PFCP_IPV4_SEID \ + (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_PFCP_SEID) +#define ICE_FLOW_HASH_PFCP_IPV6_SEID \ + (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_PFCP_SEID) + +#define ICE_FLOW_HASH_L2TPV3_SESS_ID \ + (BIT_ULL(ICE_FLOW_FIELD_IDX_L2TPV3_SESS_ID)) +#define ICE_FLOW_HASH_L2TPV3_IPV4_SESS_ID \ + (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_L2TPV3_SESS_ID) +#define ICE_FLOW_HASH_L2TPV3_IPV6_SESS_ID \ + (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_L2TPV3_SESS_ID) + +#define ICE_FLOW_HASH_ESP_SPI \ + (BIT_ULL(ICE_FLOW_FIELD_IDX_ESP_SPI)) +#define ICE_FLOW_HASH_ESP_IPV4_SPI \ + (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_ESP_SPI) +#define ICE_FLOW_HASH_ESP_IPV6_SPI \ + (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_ESP_SPI) + +#define ICE_FLOW_HASH_AH_SPI \ + (BIT_ULL(ICE_FLOW_FIELD_IDX_AH_SPI)) +#define ICE_FLOW_HASH_AH_IPV4_SPI \ + (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_AH_SPI) +#define ICE_FLOW_HASH_AH_IPV6_SPI \ + (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_AH_SPI) + +#define ICE_FLOW_HASH_NAT_T_ESP_SPI \ + (BIT_ULL(ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI)) +#define ICE_FLOW_HASH_NAT_T_ESP_IPV4_SPI \ + (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_NAT_T_ESP_SPI) +#define ICE_FLOW_HASH_NAT_T_ESP_IPV6_SPI \ + (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_NAT_T_ESP_SPI) + /* Protocol header fields within a packet segment. A segment consists of one or * more protocol headers that make up a logical group of protocol headers. Each * logical group of protocol headers encapsulates or is encapsulated using/by @@ -107,6 +142,12 @@ enum ice_flow_seg_hdr { ICE_FLOW_SEG_HDR_GTPU_DWN = 0x00004000, ICE_FLOW_SEG_HDR_GTPU_UP = 0x00008000, ICE_FLOW_SEG_HDR_PPPOE = 0x00010000, + ICE_FLOW_SEG_HDR_PFCP_NODE = 0x00020000, + ICE_FLOW_SEG_HDR_PFCP_SESSION = 0x00040000, + ICE_FLOW_SEG_HDR_L2TPV3 = 0x00080000, + ICE_FLOW_SEG_HDR_ESP = 0x00100000, + ICE_FLOW_SEG_HDR_AH = 0x00200000, + ICE_FLOW_SEG_HDR_NAT_T_ESP = 0x00400000, }; /* These segements all have the same PTYPES, but are otherwise distinguished by @@ -121,6 +162,8 @@ enum ice_flow_seg_hdr { #define ICE_FLOW_SEG_HDR_GTPU (ICE_FLOW_SEG_HDR_GTPU_IP | \ ICE_FLOW_SEG_HDR_GTPU_DWN | \ ICE_FLOW_SEG_HDR_GTPU_UP) +#define ICE_FLOW_SEG_HDR_PFCP (ICE_FLOW_SEG_HDR_PFCP_NODE | \ + ICE_FLOW_SEG_HDR_PFCP_SESSION) enum ice_flow_field { /* L2 */ @@ -172,6 +215,16 @@ enum ice_flow_field { ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID, /* PPPOE */ ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID, + /* PFCP */ + ICE_FLOW_FIELD_IDX_PFCP_SEID, + /* L2TPV3 */ + ICE_FLOW_FIELD_IDX_L2TPV3_SESS_ID, + /* ESP */ + ICE_FLOW_FIELD_IDX_ESP_SPI, + /* AH */ + ICE_FLOW_FIELD_IDX_AH_SPI, + /* NAT_T ESP */ + ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI, /* The total number of enums must not exceed 64 */ ICE_FLOW_FIELD_IDX_MAX }; diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index 3588be0ca..3fb065169 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -46,6 +46,10 @@ enum ice_protocol_type { ICE_NVGRE, ICE_GTP, ICE_PPPOE, + ICE_PFCP, + ICE_L2TPV3, + ICE_ESP, + ICE_AH, ICE_PROTOCOL_LAST }; @@ -112,6 +116,7 @@ enum ice_prot_id { ICE_PROT_VRRP_F = 101, ICE_PROT_OSPF = 102, ICE_PROT_PPPOE = 103, + ICE_PROT_L2TPV3 = 104, ICE_PROT_ATAOE_OF = 114, ICE_PROT_CTRL_OF = 116, ICE_PROT_LLDP_OF = 117, @@ -133,8 +138,11 @@ enum ice_prot_id { #define ICE_IPV6_IL_HW 41 #define ICE_TCP_IL_HW 49 #define ICE_UDP_ILOS_HW 53 +#define ICE_ESP_HW 88 +#define ICE_AH_HW 89 #define ICE_SCTP_IL_HW 96 #define ICE_PPPOE_HW 103 +#define ICE_L2TPV3_HW 104 /* ICE_UDP_OF is used to identify all 3 tunnel types * VXLAN, GENEVE and VXLAN_GPE. To differentiate further @@ -230,7 +238,6 @@ struct ice_udp_tnl_hdr { __be32 vni; /* only use lower 24-bits */ }; -#pragma pack(1) struct ice_udp_gtp_hdr { u8 flags; u8 msg_type; @@ -252,7 +259,33 @@ struct ice_pppoe_hdr { __be16 length; __be16 ppp_prot_id; /* control and data only */ }; -#pragma pack() + +struct ice_pfcp_hdr { + u8 flags; + u8 msg_type; + __be16 length; + __be64 seid; + __be32 seq; + u8 spare; +}; + +struct ice_l2tpv3_sess_hdr { + __be32 session_id; + __be64 cookie; +}; + +struct ice_esp_hdr { + __be32 spi; + __be32 seq; +}; + +struct ice_ah_hdr { + u8 next_hdr; + u8 paylen; + __be16 rsrvd; + __be32 spi; + __be32 seq; +}; struct ice_nvgre { __be16 flags; @@ -272,6 +305,10 @@ union ice_prot_hdr { struct ice_nvgre nvgre_hdr; struct ice_udp_gtp_hdr gtp_hdr; struct ice_pppoe_hdr pppoe_hdr; + struct ice_pfcp_hdr pfcp_hdr; + struct ice_l2tpv3_sess_hdr l2tpv3_sess_hdr; + struct ice_esp_hdr esp_hdr; + struct ice_ah_hdr ah_hdr; }; /* This is mapping table entry that maps every word within a given protocol