From patchwork Wed Mar 11 07:24:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linhaifeng X-Patchwork-Id: 66528 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2F629A0567; Wed, 11 Mar 2020 08:24:22 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 096231BF7F; Wed, 11 Mar 2020 08:24:22 +0100 (CET) Received: from huawei.com (szxga01-in.huawei.com [45.249.212.187]) by dpdk.org (Postfix) with ESMTP id 4D8192BE6 for ; Wed, 11 Mar 2020 08:24:20 +0100 (CET) Received: from DGGEML403-HUB.china.huawei.com (unknown [172.30.72.55]) by Forcepoint Email with ESMTP id 64531E785FB50157234E; Wed, 11 Mar 2020 15:24:17 +0800 (CST) Received: from DGGEML502-MBX.china.huawei.com ([169.254.2.18]) by DGGEML403-HUB.china.huawei.com ([fe80::74d9:c659:fbec:21fa%31]) with mapi id 14.03.0439.000; Wed, 11 Mar 2020 15:24:10 +0800 From: Linhaifeng To: Jerin Jacob CC: Gavin Hu , "dev@dpdk.org" , "thomas@monjalon.net" , chenchanghu , xudingke , "Lilijun (Jerry)" , Honnappa Nagarahalli , Steve Capper , nd Thread-Topic: [PATCH v6] eal/arm64: fix rdtsc precise version Thread-Index: AdX3dgKBGjygbzr3Sk+6Pwftac7sGQ== Date: Wed, 11 Mar 2020 07:24:10 +0000 Message-ID: <4099DE2E54AFAD489356C6C9161D53339729FAD0@DGGEML502-MBX.china.huawei.com> Accept-Language: en-GB, zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.133.215.248] MIME-Version: 1.0 X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v6] eal/arm64: fix rdtsc precise version X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In order to get more accurate the cntvct_el0 reading, SW must invoke isb and arch_counter_enforce_ordering. Reference of linux kernel: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/ linux.git/tree/arch/arm64/include/asm/arch_timer.h?h=v5.5#n220 Fixes: ccad39ea0712 ("eal/arm: add cpu cycle operations for ARMv8") Cc: stable@dpdk.org Reviewed-by: Jerin Jacob Reviewed-by: Gavin Hu Signed-off-by: Haifeng Lin --- .../common/include/arch/arm/rte_cycles_64.h | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h index 68e7c7338..6b0df5b0a 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h @@ -59,11 +59,33 @@ rte_rdtsc(void) } #endif +static inline void +isb(void) +{ + asm volatile("isb" : : : "memory"); +} + +static inline void +__rte_arm64_cntvct_el0_enforce_ordering(uint64_t val) +{ + uint64_t tmp; + + asm volatile( + " eor %0, %1, %1\n" + " add %0, sp, %0\n" + " ldr xzr, [%0]" + : "=r" (tmp) : "r" (val)); +} + static inline uint64_t rte_rdtsc_precise(void) { - rte_mb(); - return rte_rdtsc(); + uint64_t tsc; + + isb(); + tsc = rte_rdtsc(); + __rte_arm64_cntvct_el0_enforce_ordering(tsc); + return tsc; } static inline uint64_t