From patchwork Mon Mar 9 09:54:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 66407 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BD514A052E; Mon, 9 Mar 2020 10:54:40 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 08E141C0AA; Mon, 9 Mar 2020 10:54:37 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id D64173B5 for ; Mon, 9 Mar 2020 10:54:35 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 56E747FA; Mon, 9 Mar 2020 02:54:35 -0700 (PDT) Received: from net-arm-thunderx2-03.shanghai.arm.com (net-arm-thunderx2-03.shanghai.arm.com [10.169.41.185]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1968D3F67D; Mon, 9 Mar 2020 02:54:29 -0700 (PDT) From: Joyce Kong To: thomas@monjalon.net, stephen@networkplumber.org, david.marchand@redhat.com, mb@smartsharesystems.com, jerinj@marvell.com, bruce.richardson@intel.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com, honnappa.nagarahalli@arm.com, phil.yang@arm.com, gavin.hu@arm.com Cc: nd@arm.com, dev@dpdk.org Date: Mon, 9 Mar 2020 17:54:05 +0800 Message-Id: <20200309095410.28983-2-joyce.kong@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200309095410.28983-1-joyce.kong@arm.com> References: <20200309095410.28983-1-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 1/6] lib/eal: implement the family of PMD bit operation APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Bitwise operation APIs are defined and used in a lot of PMDs, which caused a huge code duplication. To reduce duplication, this patch consolidates them into a common API family. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu Reviewed-by: Phil Yang Acked-by: Morten Brørup --- MAINTAINERS | 4 + doc/api/doxy-api-index.md | 5 +- drivers/net/Makefile | 1 + lib/librte_eal/common/Makefile | 1 + .../common/include/rte_pmd_bitops.h | 257 ++++++++++++++++++ lib/librte_eal/common/meson.build | 3 +- 6 files changed, 268 insertions(+), 3 deletions(-) create mode 100644 lib/librte_eal/common/include/rte_pmd_bitops.h diff --git a/MAINTAINERS b/MAINTAINERS index f4e0ed8e0..071daf887 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -244,6 +244,10 @@ M: Cristian Dumitrescu F: lib/librte_eal/common/include/rte_bitmap.h F: app/test/test_bitmap.c +PMD Bitops +M: Joyce Kong +F: lib/librte_eal/common/include/rte_pmd_bitops.h + MCSlock - EXPERIMENTAL M: Phil Yang F: lib/librte_eal/common/include/generic/rte_mcslock.h diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md index dff496be0..64ab142f3 100644 --- a/doc/api/doxy-api-index.md +++ b/doc/api/doxy-api-index.md @@ -35,6 +35,7 @@ The public API headers are grouped by topics: [vfio] (@ref rte_vfio.h) - **device specific**: + [pmd_bitops] (@ref rte_pmd_bitops.h), [softnic] (@ref rte_eth_softnic.h), [bond] (@ref rte_eth_bond.h), [vhost] (@ref rte_vhost.h), @@ -133,12 +134,12 @@ The public API headers are grouped by topics: [BPF] (@ref rte_bpf.h) - **containers**: + [bitmap] (@ref rte_bitmap.h), [mbuf] (@ref rte_mbuf.h), [mbuf pool ops] (@ref rte_mbuf_pool_ops.h), [ring] (@ref rte_ring.h), [stack] (@ref rte_stack.h), - [tailq] (@ref rte_tailq.h), - [bitmap] (@ref rte_bitmap.h) + [tailq] (@ref rte_tailq.h) - **packet framework**: * [port] (@ref rte_port.h): diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 4a7f155fc..1a3202d1c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -3,6 +3,7 @@ include $(RTE_SDK)/mk/rte.vars.mk +INC := rte_pmd_bitops.h # set in mk/toolchain/xxx/rte.toolchain-compat.mk ifeq ($(CONFIG_RTE_LIBRTE_THUNDERX_NICVF_PMD),d) $(warning thunderx pmd is not supported by old compilers) diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile index c2c6d92cd..24a5ae94f 100644 --- a/lib/librte_eal/common/Makefile +++ b/lib/librte_eal/common/Makefile @@ -19,6 +19,7 @@ INC += rte_malloc.h rte_keepalive.h rte_time.h INC += rte_service.h rte_service_component.h INC += rte_bitmap.h rte_vfio.h rte_hypervisor.h rte_test.h INC += rte_reciprocal.h rte_fbarray.h rte_uuid.h +INC += rte_pmd_bitops.h GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h GENERIC_INC += rte_memcpy.h rte_cpuflags.h diff --git a/lib/librte_eal/common/include/rte_pmd_bitops.h b/lib/librte_eal/common/include/rte_pmd_bitops.h new file mode 100644 index 000000000..b7801e01e --- /dev/null +++ b/lib/librte_eal/common/include/rte_pmd_bitops.h @@ -0,0 +1,257 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2020 Arm Limited + */ + +#ifndef _RTE_PMD_BITOPS_H_ +#define _RTE_PMD_BITOPS_H_ + +/** + * @file + * Bit Operations + * + * This file defines a API for bit operations without/with memory ordering. + */ + +#include +#include +#include + +/*---------------------------- 32 bit operations ----------------------------*/ + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 32-bit value without memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint32_t +rte_get_bit32_relaxed(unsigned int nr, volatile uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return (*addr) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 32-bit value to 1 without memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit32_relaxed(unsigned int nr, volatile uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + *addr = (*addr) | mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 32-bit value to 0 without memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit32_relaxed(unsigned int nr, volatile uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + *addr = (*addr) & (~mask); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then set it to 1 without + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_set_bit32_relaxed(unsigned int nr, volatile uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + uint32_t val = *addr; + *addr = (*addr) | mask; + return val & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then clear it to 0 without + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_clear_bit32_relaxed(unsigned int nr, volatile uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + uint32_t val = *addr; + *addr = (*addr) & (~mask); + return val & mask; +} + +/*---------------------------- 64 bit operations ----------------------------*/ + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 64-bit value without memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint64_t +rte_get_bit64_relaxed(unsigned int nr, volatile uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return (*addr) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 64-bit value to 1 without memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit64_relaxed(unsigned int nr, volatile uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + (*addr) = (*addr) | mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 64-bit value to 0 without memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit64_relaxed(unsigned int nr, volatile uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + *addr = (*addr) & (~mask); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then set it to 1 without + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_set_bit64_relaxed(unsigned int nr, volatile uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + uint64_t val = *addr; + *addr = (*addr) | mask; + return val; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then clear it to 0 without + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_clear_bit64_relaxed(unsigned int nr, volatile uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + uint64_t val = *addr; + *addr = (*addr) & (~mask); + return val & mask; +} + +#endif /* _RTE_PMD_BITOPS_H_ */ diff --git a/lib/librte_eal/common/meson.build b/lib/librte_eal/common/meson.build index 2b97715a2..0862ae64c 100644 --- a/lib/librte_eal/common/meson.build +++ b/lib/librte_eal/common/meson.build @@ -50,9 +50,9 @@ common_objs += eal_common_arch_objs common_headers = files( 'include/rte_alarm.h', + 'include/rte_bitmap.h', 'include/rte_branch_prediction.h', 'include/rte_bus.h', - 'include/rte_bitmap.h', 'include/rte_class.h', 'include/rte_common.h', 'include/rte_compat.h', @@ -78,6 +78,7 @@ common_headers = files( 'include/rte_pci_dev_feature_defs.h', 'include/rte_pci_dev_features.h', 'include/rte_per_lcore.h', + 'include/rte_pmd_bitops.h', 'include/rte_random.h', 'include/rte_reciprocal.h', 'include/rte_service.h', From patchwork Mon Mar 9 09:54:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 66408 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6AC65A052E; Mon, 9 Mar 2020 10:54:50 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 94AEF1C0C5; Mon, 9 Mar 2020 10:54:43 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 170E31C0C5 for ; Mon, 9 Mar 2020 10:54:42 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8F2C3101E; Mon, 9 Mar 2020 02:54:41 -0700 (PDT) Received: from net-arm-thunderx2-03.shanghai.arm.com (net-arm-thunderx2-03.shanghai.arm.com [10.169.41.185]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E163F3F67D; Mon, 9 Mar 2020 02:54:35 -0700 (PDT) From: Joyce Kong To: thomas@monjalon.net, stephen@networkplumber.org, david.marchand@redhat.com, mb@smartsharesystems.com, jerinj@marvell.com, bruce.richardson@intel.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com, honnappa.nagarahalli@arm.com, phil.yang@arm.com, gavin.hu@arm.com Cc: nd@arm.com, dev@dpdk.org Date: Mon, 9 Mar 2020 17:54:06 +0800 Message-Id: <20200309095410.28983-3-joyce.kong@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200309095410.28983-1-joyce.kong@arm.com> References: <20200309095410.28983-1-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v7 2/6] test/pmdbitops: add PMD bit operation test case X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add test cases of bit operations which used by PMDs. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu Reviewed-by: Phil Yang --- MAINTAINERS | 1 + app/test/Makefile | 1 + app/test/autotest_data.py | 6 ++ app/test/meson.build | 2 + app/test/test_pmd_bitops.c | 137 +++++++++++++++++++++++++++++++++++++ 5 files changed, 147 insertions(+) create mode 100644 app/test/test_pmd_bitops.c diff --git a/MAINTAINERS b/MAINTAINERS index 071daf887..876cb2bfd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -247,6 +247,7 @@ F: app/test/test_bitmap.c PMD Bitops M: Joyce Kong F: lib/librte_eal/common/include/rte_pmd_bitops.h +F: app/test/test_pmd_bitops.c MCSlock - EXPERIMENTAL M: Phil Yang diff --git a/app/test/Makefile b/app/test/Makefile index 1f080d162..3bdcbfdcf 100644 --- a/app/test/Makefile +++ b/app/test/Makefile @@ -78,6 +78,7 @@ SRCS-y += test_rand_perf.c SRCS-y += test_ring.c SRCS-y += test_ring_perf.c +SRCS-y += test_pmd_bitops.c SRCS-y += test_pmd_perf.c ifeq ($(CONFIG_RTE_LIBRTE_TABLE),y) diff --git a/app/test/autotest_data.py b/app/test/autotest_data.py index 7b1d01389..143b59097 100644 --- a/app/test/autotest_data.py +++ b/app/test/autotest_data.py @@ -284,6 +284,12 @@ "Func": default_autotest, "Report": None, }, + { + "Name": "PMD bitops autotest", + "Command": "pmd_bitops_autotest", + "Func": default_autotest, + "Report": None, + } { "Name": "PMD ring autotest", "Command": "ring_pmd_autotest", diff --git a/app/test/meson.build b/app/test/meson.build index 0a2ce710f..5567b9d1c 100644 --- a/app/test/meson.build +++ b/app/test/meson.build @@ -84,6 +84,7 @@ test_sources = files('commands.c', 'test_mcslock.c', 'test_mp_secondary.c', 'test_per_lcore.c', + 'test_pmd_bitops.c', 'test_pmd_perf.c', 'test_power.c', 'test_power_cpufreq.c', @@ -198,6 +199,7 @@ fast_test_names = [ 'meter_autotest', 'multiprocess_autotest', 'per_lcore_autotest', + 'pmd_bitops_autotest', 'prefetch_autotest', 'rcu_qsbr_autotest', 'red_autotest', diff --git a/app/test/test_pmd_bitops.c b/app/test/test_pmd_bitops.c new file mode 100644 index 000000000..f84c582be --- /dev/null +++ b/app/test/test_pmd_bitops.c @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Arm Limited + */ + +#include +#include +#include "test.h" + +uint32_t val32; +uint64_t val64; + +#define MAX_BITS_32 32 +#define MAX_BITS_64 64 +/* + * Bitops functions + * ================ + * + * - The main test function performs several subtests. + * - For relaxed version, check bit operations on one core. + * - Initialize valXX to specified values, then set each bit of valXX + * to 1 one by one in "test_bitops_set_relaxed". + * + * - Clear each bit of valXX to 0 one by one in "test_bitops_clear_relaxed". + * + * - Function "test_bitops_test_set_clear_relaxed" checks whether each bit + * of valXX can do "test and set" and "test and clear" correctly. + */ + +static int +test_bitops_set_relaxed(void) +{ + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + rte_set_bit32_relaxed(i, &val32); + + for (i = 0; i < MAX_BITS_32; i++) + if (!rte_get_bit32_relaxed(i, &val32)) { + printf("Failed to set bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + rte_set_bit64_relaxed(i, &val64); + + for (i = 0; i < MAX_BITS_64; i++) + if (!rte_get_bit64_relaxed(i, &val64)) { + printf("Failed to set bit in relaxed version.\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; +} + +static int +test_bitops_clear_relaxed(void) +{ + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + rte_clear_bit32_relaxed(i, &val32); + + for (i = 0; i < MAX_BITS_32; i++) + if (rte_get_bit32_relaxed(i, &val32)) { + printf("Failed to clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + rte_clear_bit64_relaxed(i, &val64); + + for (i = 0; i < MAX_BITS_64; i++) + if (rte_get_bit64_relaxed(i, &val64)) { + printf("Failed to clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; +} + +static int +test_bitops_test_set_clear_relaxed(void) +{ + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + rte_test_and_set_bit32_relaxed(i, &val32); + + for (i = 0; i < MAX_BITS_32; i++) + if (!rte_test_and_clear_bit32_relaxed(i, &val32)) { + printf("Failed to set and test bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_32; i++) + if (rte_get_bit32_relaxed(i, &val32)) { + printf("Failed to test and clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + rte_test_and_set_bit64_relaxed(i, &val64); + + for (i = 0; i < MAX_BITS_64; i++) + if (!rte_test_and_clear_bit64_relaxed(i, &val64)) { + printf("Failed to set and test bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + if (rte_get_bit64_relaxed(i, &val64)) { + printf("Failed to test and clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; +} + +static int +test_bitops(void) +{ + val32 = 0; + val64 = 0; + + if (test_bitops_set_relaxed() < 0) + return TEST_FAILED; + + if (test_bitops_clear_relaxed() < 0) + return TEST_FAILED; + + if (test_bitops_test_set_clear_relaxed() < 0) + return TEST_FAILED; + + return TEST_SUCCESS; +} + +REGISTER_TEST_COMMAND(bitops_autotest, test_bitops); From patchwork Mon Mar 9 09:54:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 66409 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DDB61A052E; Mon, 9 Mar 2020 10:55:01 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0DD6B1C0BC; Mon, 9 Mar 2020 10:54:49 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 814C43B5 for ; Mon, 9 Mar 2020 10:54:47 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0A62E1FB; Mon, 9 Mar 2020 02:54:47 -0700 (PDT) Received: from net-arm-thunderx2-03.shanghai.arm.com (net-arm-thunderx2-03.shanghai.arm.com [10.169.41.185]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 179153F67D; Mon, 9 Mar 2020 02:54:41 -0700 (PDT) From: Joyce Kong To: thomas@monjalon.net, stephen@networkplumber.org, david.marchand@redhat.com, mb@smartsharesystems.com, jerinj@marvell.com, bruce.richardson@intel.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com, honnappa.nagarahalli@arm.com, phil.yang@arm.com, gavin.hu@arm.com Cc: nd@arm.com, dev@dpdk.org Date: Mon, 9 Mar 2020 17:54:07 +0800 Message-Id: <20200309095410.28983-4-joyce.kong@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200309095410.28983-1-joyce.kong@arm.com> References: <20200309095410.28983-1-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v7 3/6] net/axgbe: use common rte bit operation APIs instead X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove its own bit operation APIs and use the common one, this can reduce the code duplication largely. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu --- drivers/net/axgbe/axgbe_common.h | 29 +---------------------------- drivers/net/axgbe/axgbe_ethdev.c | 14 +++++++------- drivers/net/axgbe/axgbe_ethdev.h | 2 +- drivers/net/axgbe/axgbe_mdio.c | 15 ++++++++------- 4 files changed, 17 insertions(+), 43 deletions(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index fdb037dd5..a4a685181 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -38,6 +38,7 @@ #include #include #include +#include #define BIT(nr) (1 << (nr)) #ifndef ARRAY_SIZE @@ -1677,34 +1678,6 @@ do { \ #define time_after_eq(a, b) ((long)((a) - (b)) >= 0) #define time_before_eq(a, b) time_after_eq(b, a) -/*---bitmap support apis---*/ -static inline int axgbe_test_bit(int nr, volatile unsigned long *addr) -{ - int res; - - rte_mb(); - res = ((*addr) & (1UL << nr)) != 0; - rte_mb(); - return res; -} - -static inline void axgbe_set_bit(unsigned int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_or(addr, (1UL << nr)); -} - -static inline void axgbe_clear_bit(int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_and(addr, ~(1UL << nr)); -} - -static inline int axgbe_test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = (1UL << nr); - - return __sync_fetch_and_and(addr, ~mask) & mask; -} - static inline unsigned long msecs_to_timer_cycles(unsigned int m) { return rte_get_timer_hz() * (m / 1000); diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c index d0b6f091f..fe1f92843 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -277,8 +277,8 @@ axgbe_dev_start(struct rte_eth_dev *dev) axgbe_dev_enable_tx(dev); axgbe_dev_enable_rx(dev); - axgbe_clear_bit(AXGBE_STOPPED, &pdata->dev_state); - axgbe_clear_bit(AXGBE_DOWN, &pdata->dev_state); + rte_clear_bit32_relaxed(AXGBE_STOPPED, &pdata->dev_state); + rte_clear_bit32_relaxed(AXGBE_DOWN, &pdata->dev_state); return 0; } @@ -292,17 +292,17 @@ axgbe_dev_stop(struct rte_eth_dev *dev) rte_intr_disable(&pdata->pci_dev->intr_handle); - if (axgbe_test_bit(AXGBE_STOPPED, &pdata->dev_state)) + if (rte_get_bit32_relaxed(AXGBE_STOPPED, &pdata->dev_state)) return; - axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state); + rte_set_bit32_relaxed(AXGBE_STOPPED, &pdata->dev_state); axgbe_dev_disable_tx(dev); axgbe_dev_disable_rx(dev); pdata->phy_if.phy_stop(pdata); pdata->hw_if.exit(pdata); memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); - axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state); + rte_set_bit32_relaxed(AXGBE_DOWN, &pdata->dev_state); } /* Clear all resources like TX/RX queues. */ @@ -1031,8 +1031,8 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) pdata = eth_dev->data->dev_private; /* initial state */ - axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state); - axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state); + rte_set_bit32_relaxed(AXGBE_DOWN, &pdata->dev_state); + rte_set_bit32_relaxed(AXGBE_STOPPED, &pdata->dev_state); pdata->eth_dev = eth_dev; pci_dev = RTE_DEV_TO_PCI(eth_dev->device); diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index a1083b17b..259221964 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -511,7 +511,7 @@ struct axgbe_port { unsigned int xpcs_window_mask; /* Flags representing axgbe_state */ - unsigned long dev_state; + uint32_t dev_state; struct axgbe_hw_if hw_if; struct axgbe_phy_if phy_if; diff --git a/drivers/net/axgbe/axgbe_mdio.c b/drivers/net/axgbe/axgbe_mdio.c index 4b280b72d..2bb7f5263 100644 --- a/drivers/net/axgbe/axgbe_mdio.c +++ b/drivers/net/axgbe/axgbe_mdio.c @@ -875,7 +875,7 @@ static int __axgbe_phy_config_aneg(struct axgbe_port *pdata) { int ret; - axgbe_set_bit(AXGBE_LINK_INIT, &pdata->dev_state); + rte_set_bit32_relaxed(AXGBE_LINK_INIT, &pdata->dev_state); pdata->link_check = rte_get_timer_cycles(); ret = pdata->phy_if.phy_impl.an_config(pdata); @@ -937,9 +937,9 @@ static int axgbe_phy_config_aneg(struct axgbe_port *pdata) ret = __axgbe_phy_config_aneg(pdata); if (ret) - axgbe_set_bit(AXGBE_LINK_ERR, &pdata->dev_state); + rte_set_bit32_relaxed(AXGBE_LINK_ERR, &pdata->dev_state); else - axgbe_clear_bit(AXGBE_LINK_ERR, &pdata->dev_state); + rte_clear_bit32_relaxed(AXGBE_LINK_ERR, &pdata->dev_state); pthread_mutex_unlock(&pdata->an_mutex); @@ -1026,7 +1026,7 @@ static void axgbe_phy_status(struct axgbe_port *pdata) unsigned int reg = 0; unsigned long autoneg_start_time; - if (axgbe_test_bit(AXGBE_LINK_ERR, &pdata->dev_state)) { + if (rte_get_bit32_relaxed(AXGBE_LINK_ERR, &pdata->dev_state)) { pdata->phy.link = 0; goto adjust_link; } @@ -1070,10 +1070,11 @@ static void axgbe_phy_status(struct axgbe_port *pdata) } } axgbe_phy_status_result(pdata); - if (axgbe_test_bit(AXGBE_LINK_INIT, &pdata->dev_state)) - axgbe_clear_bit(AXGBE_LINK_INIT, &pdata->dev_state); + if (rte_get_bit32_relaxed(AXGBE_LINK_INIT, &pdata->dev_state)) + rte_clear_bit32_relaxed(AXGBE_LINK_INIT, + &pdata->dev_state); } else { - if (axgbe_test_bit(AXGBE_LINK_INIT, &pdata->dev_state)) { + if (rte_get_bit32_relaxed(AXGBE_LINK_INIT, &pdata->dev_state)) { axgbe_check_link_timeout(pdata); if (link_aneg) From patchwork Mon Mar 9 09:54:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 66410 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 42AA3A052E; Mon, 9 Mar 2020 10:55:14 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 658A41C0D9; Mon, 9 Mar 2020 10:54:54 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 588FE1C0D9 for ; Mon, 9 Mar 2020 10:54:53 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C4D257FA; Mon, 9 Mar 2020 02:54:52 -0700 (PDT) Received: from net-arm-thunderx2-03.shanghai.arm.com (net-arm-thunderx2-03.shanghai.arm.com [10.169.41.185]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 943673F67D; Mon, 9 Mar 2020 02:54:47 -0700 (PDT) From: Joyce Kong To: thomas@monjalon.net, stephen@networkplumber.org, david.marchand@redhat.com, mb@smartsharesystems.com, jerinj@marvell.com, bruce.richardson@intel.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com, honnappa.nagarahalli@arm.com, phil.yang@arm.com, gavin.hu@arm.com Cc: nd@arm.com, dev@dpdk.org Date: Mon, 9 Mar 2020 17:54:08 +0800 Message-Id: <20200309095410.28983-5-joyce.kong@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200309095410.28983-1-joyce.kong@arm.com> References: <20200309095410.28983-1-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v7 4/6] net/bnx2x: use common rte bit operation APIs instead X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove its own bit operation APIs and use the common one, this can reduce the code duplication largely. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu --- drivers/net/bnx2x/bnx2x.c | 253 +++++++++++++++++------------------ drivers/net/bnx2x/bnx2x.h | 10 +- drivers/net/bnx2x/ecore_sp.h | 48 +++---- 3 files changed, 150 insertions(+), 161 deletions(-) diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c index 0b4030e2b..2ea23b2eb 100644 --- a/drivers/net/bnx2x/bnx2x.c +++ b/drivers/net/bnx2x/bnx2x.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #define BNX2X_PMD_VER_PREFIX "BNX2X PMD" @@ -129,32 +130,6 @@ static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm, uint16_t index, uint8_t op, uint8_t update); -int bnx2x_test_bit(int nr, volatile unsigned long *addr) -{ - int res; - - mb(); - res = ((*addr) & (1UL << nr)) != 0; - mb(); - return res; -} - -void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_or(addr, (1UL << nr)); -} - -void bnx2x_clear_bit(int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_and(addr, ~(1UL << nr)); -} - -int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = (1UL << nr); - return __sync_fetch_and_and(addr, ~mask) & mask; -} - int bnx2x_cmpxchg(volatile int *addr, int old, int new) { return __sync_val_compare_and_swap(addr, old, new); @@ -1434,16 +1409,16 @@ static int bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj, int mac_type, uint8_t wait_for_comp) { - unsigned long ramrod_flags = 0, vlan_mac_flags = 0; + uint32_t ramrod_flags = 0, vlan_mac_flags = 0; int rc; /* wait for completion of requested */ if (wait_for_comp) { - bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); + rte_set_bit32_relaxed(RAMROD_COMP_WAIT, &ramrod_flags); } /* Set the mac type of addresses we want to clear */ - bnx2x_set_bit(mac_type, &vlan_mac_flags); + rte_set_bit32_relaxed(mac_type, &vlan_mac_flags); rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags); if (rc < 0) @@ -1454,8 +1429,7 @@ bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj, static int bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode, - unsigned long *rx_accept_flags, - unsigned long *tx_accept_flags) + uint32_t *rx_accept_flags, uint32_t *tx_accept_flags) { /* Clear the flags first */ *rx_accept_flags = 0; @@ -1470,26 +1444,28 @@ bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode, break; case BNX2X_RX_MODE_NORMAL: - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST, rx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_MULTICAST, rx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, rx_accept_flags); /* internal switching mode */ - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST, tx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_MULTICAST, tx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, tx_accept_flags); break; case BNX2X_RX_MODE_ALLMULTI: - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST, rx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_ALL_MULTICAST, + rx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, rx_accept_flags); /* internal switching mode */ - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST, tx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_ALL_MULTICAST, + tx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, tx_accept_flags); break; @@ -1500,19 +1476,23 @@ bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode, * should receive matched and unmatched (in resolution of port) * unicast packets. */ - bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_UNMATCHED, rx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST, rx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_ALL_MULTICAST, + rx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, rx_accept_flags); /* internal switching mode */ - bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_ALL_MULTICAST, + tx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, tx_accept_flags); if (IS_MF_SI(sc)) { - bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_ALL_UNICAST, + tx_accept_flags); } else { - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST, + tx_accept_flags); } break; @@ -1524,8 +1504,8 @@ bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode, /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */ if (rx_mode != BNX2X_RX_MODE_NONE) { - bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags); + rte_set_bit32_relaxed(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags); } return 0; @@ -1554,7 +1534,7 @@ bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id, ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata); ramrod_param.rdata_mapping = (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata), - bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); + rte_set_bit32_relaxed(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); ramrod_param.ramrod_flags = ramrod_flags; ramrod_param.rx_mode_flags = rx_mode_flags; @@ -1573,8 +1553,8 @@ bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id, int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc) { - unsigned long rx_mode_flags = 0, ramrod_flags = 0; - unsigned long rx_accept_flags = 0, tx_accept_flags = 0; + uint32_t rx_mode_flags = 0, ramrod_flags = 0; + uint32_t rx_accept_flags = 0, tx_accept_flags = 0; int rc; rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags, @@ -1583,9 +1563,9 @@ int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc) return rc; } - bnx2x_set_bit(RAMROD_RX, &ramrod_flags); - bnx2x_set_bit(RAMROD_TX, &ramrod_flags); - bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); + rte_set_bit32_relaxed(RAMROD_RX, &ramrod_flags); + rte_set_bit32_relaxed(RAMROD_TX, &ramrod_flags); + rte_set_bit32_relaxed(RAMROD_COMP_WAIT, &ramrod_flags); return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags, rx_accept_flags, tx_accept_flags, @@ -1710,7 +1690,8 @@ static int bnx2x_func_wait_started(struct bnx2x_softc *sc) "Forcing STARTED-->TX_STOPPED-->STARTED"); func_params.f_obj = &sc->func_obj; - bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); + rte_set_bit32_relaxed(RAMROD_DRV_CLR_ONLY, + &func_params.ramrod_flags); /* STARTED-->TX_STOPPED */ func_params.cmd = ECORE_F_CMD_TX_STOP; @@ -1734,7 +1715,7 @@ static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index) q_params.q_obj = &sc->sp_objs[fp->index].q_obj; /* We want to wait for completion in this context */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); + rte_set_bit32_relaxed(RAMROD_COMP_WAIT, &q_params.ramrod_flags); /* Stop the primary connection: */ @@ -1795,7 +1776,7 @@ static int bnx2x_func_stop(struct bnx2x_softc *sc) int rc; /* prepare parameters for function state transitions */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); + rte_set_bit32_relaxed(RAMROD_COMP_WAIT, &func_params.ramrod_flags); func_params.f_obj = &sc->func_obj; func_params.cmd = ECORE_F_CMD_STOP; @@ -1809,7 +1790,8 @@ static int bnx2x_func_stop(struct bnx2x_softc *sc) if (rc) { PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. " "Running a dry transaction"); - bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); + rte_set_bit32_relaxed(RAMROD_DRV_CLR_ONLY, + &func_params.ramrod_flags); return ecore_func_state_change(sc, &func_params); } @@ -1821,7 +1803,7 @@ static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code) struct ecore_func_state_params func_params = { NULL }; /* Prepare parameters for function state transitions */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); + rte_set_bit32_relaxed(RAMROD_COMP_WAIT, &func_params.ramrod_flags); func_params.f_obj = &sc->func_obj; func_params.cmd = ECORE_F_CMD_HW_RESET; @@ -1878,11 +1860,12 @@ bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_li * a race between the completion code and this code. */ - if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) { - bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state); - } else { + if (rte_get_bit32_relaxed(ECORE_FILTER_RX_MODE_PENDING, + &sc->sp_state)) + rte_set_bit32_relaxed(ECORE_FILTER_RX_MODE_SCHED, + &sc->sp_state); + else bnx2x_set_storm_rx_mode(sc); - } /* Clean up multicast configuration */ rparam.mcast_obj = &sc->mcast_obj; @@ -1964,7 +1947,7 @@ static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc) */ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc) { - unsigned long ramrod_flags = 0, vlan_mac_flags = 0; + uint32_t ramrod_flags = 0, vlan_mac_flags = 0; struct ecore_mcast_ramrod_params rparam = { NULL }; struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj; int rc; @@ -1972,12 +1955,12 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc) /* Cleanup MACs' object first... */ /* Wait for completion of requested */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); + rte_set_bit32_relaxed(RAMROD_COMP_WAIT, &ramrod_flags); /* Perform a dry cleanup */ - bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags); + rte_set_bit32_relaxed(RAMROD_DRV_CLR_ONLY, &ramrod_flags); /* Clean ETH primary MAC */ - bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags); + rte_set_bit32_relaxed(ECORE_ETH_MAC, &vlan_mac_flags); rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags, &ramrod_flags); if (rc != 0) { @@ -1986,7 +1969,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc) /* Cleanup UC list */ vlan_mac_flags = 0; - bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags); + rte_set_bit32_relaxed(ECORE_UC_LIST_MAC, &vlan_mac_flags); rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags); if (rc != 0) { PMD_DRV_LOG(NOTICE, sc, @@ -1996,7 +1979,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc) /* Now clean mcast object... */ rparam.mcast_obj = &sc->mcast_obj; - bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags); + rte_set_bit32_relaxed(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags); /* Add a DEL command... */ rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); @@ -4294,13 +4277,13 @@ static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc) static void bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem) { - unsigned long ramrod_flags = 0; + uint32_t ramrod_flags = 0; int rc = 0; uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; struct ecore_vlan_mac_obj *vlan_mac_obj; /* always push next commands out, don't wait here */ - bnx2x_set_bit(RAMROD_CONT, &ramrod_flags); + rte_set_bit32_relaxed(RAMROD_CONT, &ramrod_flags); switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) { case ECORE_FILTER_MAC_PENDING: @@ -4331,12 +4314,12 @@ bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *e static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc) { - bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); + rte_clear_bit32_relaxed(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); /* send rx_mode command again if was requested */ - if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) { + if (rte_test_and_clear_bit32_relaxed(ECORE_FILTER_RX_MODE_SCHED, + &sc->sp_state)) bnx2x_set_storm_rx_mode(sc); - } } static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod) @@ -4705,7 +4688,7 @@ static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code) PMD_INIT_FUNC_TRACE(sc); /* prepare the parameters for function state transitions */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); + rte_set_bit32_relaxed(RAMROD_COMP_WAIT, &func_params.ramrod_flags); func_params.f_obj = &sc->func_obj; func_params.cmd = ECORE_F_CMD_HW_INIT; @@ -4953,7 +4936,7 @@ static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx) { struct bnx2x_fastpath *fp = &sc->fp[idx]; uint32_t cids[ECORE_MULTI_TX_COS] = { 0 }; - unsigned long q_type = 0; + uint32_t q_type = 0; int cos; fp->sc = sc; @@ -5000,8 +4983,8 @@ static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx) bnx2x_update_fp_sb_idx(fp); /* Configure Queue State object */ - bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type); - bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type); + rte_set_bit32_relaxed(ECORE_Q_TYPE_HAS_RX, &q_type); + rte_set_bit32_relaxed(ECORE_Q_TYPE_HAS_TX, &q_type); ecore_init_queue_obj(sc, &sc->sp_objs[idx].q_obj, @@ -5815,7 +5798,7 @@ static int bnx2x_func_start(struct bnx2x_softc *sc) &func_params.params.start; /* Prepare parameters for function state transitions */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); + rte_set_bit32_relaxed(RAMROD_COMP_WAIT, &func_params.ramrod_flags); func_params.f_obj = &sc->func_obj; func_params.cmd = ECORE_F_CMD_START; @@ -6391,11 +6374,11 @@ bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t cos; int cxt_index, cxt_offset; - bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags); - bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_HC, &init_params->rx.flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_HC, &init_params->tx.flags); - bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags); - bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_HC_EN, &init_params->rx.flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_HC_EN, &init_params->tx.flags); /* HC rate */ init_params->rx.hc_rate = @@ -6426,10 +6409,10 @@ bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, static unsigned long bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats) { - unsigned long flags = 0; + uint32_t flags = 0; /* PF driver will always initialize the Queue to an ACTIVE state */ - bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_ACTIVE, &flags); /* * tx only connections collect statistics (on the same index as the @@ -6437,9 +6420,9 @@ bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats) * connection is initialized. */ - bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_STATS, &flags); if (zero_stats) { - bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_ZERO_STATS, &flags); } /* @@ -6447,28 +6430,28 @@ bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats) * CoS-ness doesn't survive the loopback */ if (sc->flags & BNX2X_TX_SWITCHING) { - bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_TX_SWITCH, &flags); } - bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_PCSUM_ON_PKT, &flags); return flags; } static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading) { - unsigned long flags = 0; + uint32_t flags = 0; if (IS_MF_SD(sc)) { - bnx2x_set_bit(ECORE_Q_FLG_OV, &flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_OV, &flags); } if (leading) { - bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags); - bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_LEADING_RSS, &flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_MCAST, &flags); } - bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags); + rte_set_bit32_relaxed(ECORE_Q_FLG_VLAN, &flags); /* merge with common flags */ return flags | bnx2x_get_common_flags(sc, TRUE); @@ -6589,7 +6572,7 @@ bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t lea q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj; /* we want to wait for completion in this context */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); + rte_set_bit32_relaxed(RAMROD_COMP_WAIT, &q_params.ramrod_flags); /* prepare the INIT parameters */ bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init); @@ -6657,20 +6640,20 @@ bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj params.rss_obj = rss_obj; - bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); + rte_set_bit32_relaxed(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); - bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags); + rte_set_bit32_relaxed(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags); /* RSS configuration */ - bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags); - bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags); - bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags); - bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags); + rte_set_bit32_relaxed(ECORE_RSS_IPV4, ¶ms.rss_flags); + rte_set_bit32_relaxed(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags); + rte_set_bit32_relaxed(ECORE_RSS_IPV6, ¶ms.rss_flags); + rte_set_bit32_relaxed(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags); if (rss_obj->udp_rss_v4) { - bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags); + rte_set_bit32_relaxed(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags); } if (rss_obj->udp_rss_v6) { - bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags); + rte_set_bit32_relaxed(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags); } /* Hash bits */ @@ -6685,7 +6668,7 @@ bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj params.rss_key[i] = (uint32_t) rte_rand(); } - bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags); + rte_set_bit32_relaxed(ECORE_RSS_SET_SRCH, ¶ms.rss_flags); } if (IS_PF(sc)) @@ -6730,7 +6713,7 @@ static int bnx2x_init_rss_pf(struct bnx2x_softc *sc) static int bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac, struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type, - unsigned long *ramrod_flags) + uint32_t *ramrod_flags) { struct ecore_vlan_mac_ramrod_params ramrod_param; int rc; @@ -6742,11 +6725,12 @@ bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac, ramrod_param.ramrod_flags = *ramrod_flags; /* fill a user request section if needed */ - if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) { + if (!rte_get_bit32_relaxed(RAMROD_CONT, ramrod_flags)) { rte_memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); - bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); + rte_set_bit32_relaxed(mac_type, + &ramrod_param.user_req.vlan_mac_flags); /* Set the command: ADD or DEL */ ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD : @@ -6769,11 +6753,11 @@ bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac, static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set) { - unsigned long ramrod_flags = 0; + uint32_t ramrod_flags = 0; PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC"); - bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); + rte_set_bit32_relaxed(RAMROD_COMP_WAIT, &ramrod_flags); /* Eth MAC is set on RSS leading client (fp[0]) */ return bnx2x_set_mac_one(sc, sc->link_params.mac_addr, @@ -6905,24 +6889,26 @@ bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *da /* Link is down */ if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) { - bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN, + rte_set_bit32_relaxed(BNX2X_LINK_REPORT_LINK_DOWN, &data->link_report_flags); } /* Full DUPLEX */ if (sc->link_vars.duplex == DUPLEX_FULL) { - bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX, + rte_set_bit32_relaxed(BNX2X_LINK_REPORT_FULL_DUPLEX, &data->link_report_flags); } /* Rx Flow Control is ON */ if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) { - bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags); + rte_set_bit32_relaxed(BNX2X_LINK_REPORT_RX_FC_ON, + &data->link_report_flags); } /* Tx Flow Control is ON */ if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) { - bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags); + rte_set_bit32_relaxed(BNX2X_LINK_REPORT_TX_FC_ON, + &data->link_report_flags); } } @@ -6941,9 +6927,9 @@ static void bnx2x_link_report_locked(struct bnx2x_softc *sc) /* Don't report link down or exactly the same link status twice */ if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) || - (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN, + (rte_get_bit32_relaxed(BNX2X_LINK_REPORT_LINK_DOWN, &sc->last_reported_link.link_report_flags) && - bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN, + rte_get_bit32_relaxed(BNX2X_LINK_REPORT_LINK_DOWN, &cur_data.link_report_flags))) { return; } @@ -6958,15 +6944,16 @@ static void bnx2x_link_report_locked(struct bnx2x_softc *sc) /* report new link params and remember the state for the next time */ rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data)); - if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN, + if (rte_get_bit32_relaxed(BNX2X_LINK_REPORT_LINK_DOWN, &cur_data.link_report_flags)) { ELINK_DEBUG_P0(sc, "NIC Link is Down"); } else { __rte_unused const char *duplex; __rte_unused const char *flow; - if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX, - &cur_data.link_report_flags)) { + if (rte_test_and_clear_bit32_relaxed + (BNX2X_LINK_REPORT_FULL_DUPLEX, + &cur_data.link_report_flags)) { duplex = "full"; ELINK_DEBUG_P0(sc, "link set to full duplex"); } else { @@ -6980,20 +6967,24 @@ static void bnx2x_link_report_locked(struct bnx2x_softc *sc) * enabled. */ if (cur_data.link_report_flags) { - if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON, + if (rte_get_bit32_relaxed(BNX2X_LINK_REPORT_RX_FC_ON, &cur_data.link_report_flags) && - bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON, + rte_get_bit32_relaxed(BNX2X_LINK_REPORT_TX_FC_ON, &cur_data.link_report_flags)) { flow = "ON - receive & transmit"; - } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON, - &cur_data.link_report_flags) && - !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON, + } else if (rte_get_bit32_relaxed + (BNX2X_LINK_REPORT_RX_FC_ON, + &cur_data.link_report_flags) && + !rte_get_bit32_relaxed + (BNX2X_LINK_REPORT_TX_FC_ON, &cur_data.link_report_flags)) { flow = "ON - receive"; - } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON, + } else if (!rte_get_bit32_relaxed + (BNX2X_LINK_REPORT_RX_FC_ON, &cur_data.link_report_flags) && - bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON, - &cur_data.link_report_flags)) { + rte_get_bit32_relaxed + (BNX2X_LINK_REPORT_TX_FC_ON, + &cur_data.link_report_flags)) { flow = "ON - transmit"; } else { flow = "none"; /* possible? */ diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index 1dbc98197..63be72a5b 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -1000,8 +1000,8 @@ struct bnx2x_sp_objs { * link parameters twice. */ struct bnx2x_link_report_data { - uint16_t line_speed; /* Effective line speed */ - unsigned long link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */ + uint16_t line_speed; /* Effective line speed */ + uint32_t link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */ }; enum { @@ -1232,7 +1232,7 @@ struct bnx2x_softc { /* slow path */ struct bnx2x_dma sp_dma; struct bnx2x_slowpath *sp; - unsigned long sp_state; + uint32_t sp_state; /* slow path queue */ struct bnx2x_dma spq_dma; @@ -1812,10 +1812,6 @@ static const uint32_t dmae_reg_go_c[] = { #define PCI_PM_D0 1 #define PCI_PM_D3hot 2 -int bnx2x_test_bit(int nr, volatile unsigned long * addr); -void bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr); -void bnx2x_clear_bit(int nr, volatile unsigned long * addr); -int bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr); int bnx2x_cmpxchg(volatile int *addr, int old, int new); int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, diff --git a/drivers/net/bnx2x/ecore_sp.h b/drivers/net/bnx2x/ecore_sp.h index cc1db377a..d3f1dac36 100644 --- a/drivers/net/bnx2x/ecore_sp.h +++ b/drivers/net/bnx2x/ecore_sp.h @@ -15,6 +15,7 @@ #define ECORE_SP_H #include +#include #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN #ifndef __LITTLE_ENDIAN @@ -73,10 +74,11 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN; #define ECORE_SET_BIT_NA(bit, var) (*var |= (1 << bit)) #define ECORE_CLEAR_BIT_NA(bit, var) (*var &= ~(1 << bit)) -#define ECORE_TEST_BIT(bit, var) bnx2x_test_bit(bit, var) -#define ECORE_SET_BIT(bit, var) bnx2x_set_bit(bit, var) -#define ECORE_CLEAR_BIT(bit, var) bnx2x_clear_bit(bit, var) -#define ECORE_TEST_AND_CLEAR_BIT(bit, var) bnx2x_test_and_clear_bit(bit, var) +#define ECORE_TEST_BIT(bit, var) rte_get_bit32_relaxed(bit, var) +#define ECORE_SET_BIT(bit, var) rte_set_bit32_relaxed(bit, var) +#define ECORE_CLEAR_BIT(bit, var) rte_clear_bit32_relaxed(bit, var) +#define ECORE_TEST_AND_CLEAR_BIT(bit, var) \ + rte_test_and_clear_bit32_relaxed(bit, var) #define atomic_load_acq_int (int)* #define atomic_store_rel_int(a, v) (*a = v) @@ -538,7 +540,7 @@ struct ecore_vlan_mac_data { /* used to contain the data related vlan_mac_flags bits from * ramrod parameters. */ - unsigned long vlan_mac_flags; + uint32_t vlan_mac_flags; /* Needed for MOVE command */ struct ecore_vlan_mac_obj *target_obj; @@ -688,7 +690,7 @@ struct ecore_vlan_mac_ramrod_params { struct ecore_vlan_mac_obj *vlan_mac_obj; /* General command flags: COMP_WAIT, etc. */ - unsigned long ramrod_flags; + uint32_t ramrod_flags; /* Command specific configuration request */ struct ecore_vlan_mac_data user_req; @@ -928,7 +930,7 @@ struct ecore_mcast_ramrod_params { struct ecore_mcast_obj *mcast_obj; /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ - unsigned long ramrod_flags; + uint32_t ramrod_flags; ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */ /** TODO: @@ -1144,22 +1146,22 @@ struct ecore_config_rss_params { struct ecore_rss_config_obj *rss_obj; /* may have RAMROD_COMP_WAIT set only */ - unsigned long ramrod_flags; + uint32_t ramrod_flags; /* ECORE_RSS_X bits */ - unsigned long rss_flags; + uint32_t rss_flags; /* Number hash bits to take into an account */ - uint8_t rss_result_mask; + uint8_t rss_result_mask; /* Indirection table */ - uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; + uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; /* RSS hash values */ - uint32_t rss_key[10]; + uint32_t rss_key[10]; /* valid only if ECORE_RSS_UPDATE_TOE is set */ - uint16_t toe_rss_bitmap; + uint16_t toe_rss_bitmap; }; struct ecore_rss_config_obj { @@ -1290,17 +1292,17 @@ enum ecore_q_type { struct ecore_queue_init_params { struct { - unsigned long flags; - uint16_t hc_rate; - uint8_t fw_sb_id; - uint8_t sb_cq_index; + uint32_t flags; + uint16_t hc_rate; + uint8_t fw_sb_id; + uint8_t sb_cq_index; } tx; struct { - unsigned long flags; - uint16_t hc_rate; - uint8_t fw_sb_id; - uint8_t sb_cq_index; + uint32_t flags; + uint16_t hc_rate; + uint8_t fw_sb_id; + uint8_t sb_cq_index; } rx; /* CID context in the host memory */ @@ -1440,7 +1442,7 @@ struct ecore_queue_state_params { enum ecore_queue_cmd cmd; /* may have RAMROD_COMP_WAIT set only */ - unsigned long ramrod_flags; + uint32_t ramrod_flags; /* Params according to the current command */ union { @@ -1704,7 +1706,7 @@ struct ecore_func_state_params { enum ecore_func_cmd cmd; /* may have RAMROD_COMP_WAIT set only */ - unsigned long ramrod_flags; + uint32_t ramrod_flags; /* Params according to the current command */ union { From patchwork Mon Mar 9 09:54:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 66411 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1338BA052E; Mon, 9 Mar 2020 10:55:29 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4809F1C10C; Mon, 9 Mar 2020 10:55:00 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 832191C117 for ; Mon, 9 Mar 2020 10:54:59 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1D01A1FB; Mon, 9 Mar 2020 02:54:59 -0700 (PDT) Received: from net-arm-thunderx2-03.shanghai.arm.com (net-arm-thunderx2-03.shanghai.arm.com [10.169.41.185]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 488EE3F67D; Mon, 9 Mar 2020 02:54:53 -0700 (PDT) From: Joyce Kong To: thomas@monjalon.net, stephen@networkplumber.org, david.marchand@redhat.com, mb@smartsharesystems.com, jerinj@marvell.com, bruce.richardson@intel.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com, honnappa.nagarahalli@arm.com, phil.yang@arm.com, gavin.hu@arm.com Cc: nd@arm.com, dev@dpdk.org Date: Mon, 9 Mar 2020 17:54:09 +0800 Message-Id: <20200309095410.28983-6-joyce.kong@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200309095410.28983-1-joyce.kong@arm.com> References: <20200309095410.28983-1-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v7 5/6] net/qede: use common rte bit operation APIs instead X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove its own bit operation APIs and use the common one, this can reduce the code duplication largely. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu --- drivers/net/qede/base/bcm_osal.c | 22 +------------ drivers/net/qede/base/bcm_osal.h | 14 ++++----- drivers/net/qede/base/ecore.h | 6 ++-- drivers/net/qede/base/ecore_cxt.c | 6 ++-- drivers/net/qede/base/ecore_dcbx.c | 8 ++--- drivers/net/qede/base/ecore_dev.c | 38 +++++++++++------------ drivers/net/qede/base/ecore_dev_api.h | 2 +- drivers/net/qede/base/ecore_l2.c | 6 ++-- drivers/net/qede/base/ecore_mcp.c | 4 +-- drivers/net/qede/base/ecore_sp_commands.c | 12 +++---- drivers/net/qede/base/ecore_spq.c | 2 +- drivers/net/qede/base/ecore_spq.h | 10 +++--- drivers/net/qede/qede_main.c | 4 +-- 13 files changed, 56 insertions(+), 78 deletions(-) diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c index 48d016e24..54e5e4f98 100644 --- a/drivers/net/qede/base/bcm_osal.c +++ b/drivers/net/qede/base/bcm_osal.c @@ -46,26 +46,6 @@ u32 qede_osal_log2(u32 val) return log; } -inline void qede_set_bit(u32 nr, unsigned long *addr) -{ - __sync_fetch_and_or(addr, (1UL << nr)); -} - -inline void qede_clr_bit(u32 nr, unsigned long *addr) -{ - __sync_fetch_and_and(addr, ~(1UL << nr)); -} - -inline bool qede_test_bit(u32 nr, unsigned long *addr) -{ - bool res; - - rte_mb(); - res = ((*addr) & (1UL << nr)) != 0; - rte_mb(); - return res; -} - static inline u32 qede_ffb(unsigned long word) { unsigned long first_bit; @@ -95,7 +75,7 @@ static inline u32 qede_ffz(unsigned long word) return first_zero ? (first_zero - 1) : OSAL_BITS_PER_UL; } -inline u32 qede_find_first_zero_bit(unsigned long *addr, u32 limit) +inline u32 qede_find_first_zero_bit(u32 *addr, u32 limit) { u32 i; u32 nwords = 0; diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index 513f6a8b4..51598a62b 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -18,6 +18,7 @@ #include #include #include +#include /* Forward declaration */ struct ecore_dev; @@ -308,23 +309,20 @@ typedef struct osal_list_t { #define OSAL_BITS_PER_UL_MASK (OSAL_BITS_PER_UL - 1) /* Bitops */ -void qede_set_bit(u32, unsigned long *); #define OSAL_SET_BIT(bit, bitmap) \ - qede_set_bit(bit, bitmap) + rte_set_bit32_relaxed(bit, bitmap) -void qede_clr_bit(u32, unsigned long *); #define OSAL_CLEAR_BIT(bit, bitmap) \ - qede_clr_bit(bit, bitmap) + rte_clear_bit32_relaxed(bit, bitmap) -bool qede_test_bit(u32, unsigned long *); -#define OSAL_TEST_BIT(bit, bitmap) \ - qede_test_bit(bit, bitmap) +#define OSAL_GET_BIT(bit, bitmap) \ + rte_get_bit32_relaxed(bit, bitmap) u32 qede_find_first_bit(unsigned long *, u32); #define OSAL_FIND_FIRST_BIT(bitmap, length) \ qede_find_first_bit(bitmap, length) -u32 qede_find_first_zero_bit(unsigned long *, u32); +u32 qede_find_first_zero_bit(u32 *bitmap, u32 length); #define OSAL_FIND_FIRST_ZERO_BIT(bitmap, length) \ qede_find_first_zero_bit(bitmap, length) diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h index b2077bc46..498bb6f09 100644 --- a/drivers/net/qede/base/ecore.h +++ b/drivers/net/qede/base/ecore.h @@ -422,8 +422,8 @@ struct ecore_hw_info { u8 max_chains_per_vf; u32 port_mode; - u32 hw_mode; - unsigned long device_capabilities; + u32 hw_mode; + u32 device_capabilities; /* Default DCBX mode */ u8 dcbx_mode; @@ -807,7 +807,7 @@ struct ecore_dev { u8 path_id; - unsigned long mf_bits; + u32 mf_bits; enum ecore_mf_mode mf_mode; #define IS_MF_DEFAULT(_p_hwfn) \ (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) diff --git a/drivers/net/qede/base/ecore_cxt.c b/drivers/net/qede/base/ecore_cxt.c index 773b75ecd..dda47ea67 100644 --- a/drivers/net/qede/base/ecore_cxt.c +++ b/drivers/net/qede/base/ecore_cxt.c @@ -154,7 +154,7 @@ struct ecore_ilt_client_cfg { struct ecore_cid_acquired_map { u32 start_cid; u32 max_count; - unsigned long *cid_map; + u32 *cid_map; }; struct ecore_src_t2 { @@ -1991,7 +1991,7 @@ static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn, } rel_cid = cid - (*pp_map)->start_cid; - if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) { + if (!OSAL_GET_BIT(rel_cid, (*pp_map)->cid_map)) { DP_NOTICE(p_hwfn, true, "CID %d [vifd %02x] not acquired", cid, vfid); goto fail; @@ -2102,7 +2102,7 @@ enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn) count = p_params->num_arfs_filters; - if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, + if (!OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS, &p_hwfn->p_dev->mf_bits)) p_hwfn->p_cxt_mngr->arfs_count = count; diff --git a/drivers/net/qede/base/ecore_dcbx.c b/drivers/net/qede/base/ecore_dcbx.c index ccd4383bb..31234f18c 100644 --- a/drivers/net/qede/base/ecore_dcbx.c +++ b/drivers/net/qede/base/ecore_dcbx.c @@ -148,7 +148,7 @@ ecore_dcbx_set_params(struct ecore_dcbx_results *p_data, p_data->arr[type].update = UPDATE_DCB_DSCP; /* Do not add valn tag 0 when DCB is enabled and port is in UFP mode */ - if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) + if (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) p_data->arr[type].dont_add_vlan0 = true; /* QM reconf data */ @@ -156,8 +156,8 @@ ecore_dcbx_set_params(struct ecore_dcbx_results *p_data, p_hwfn->hw_info.offload_tc = tc; /* Configure dcbx vlan priority in doorbell block for roce EDPM */ - if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits) && - (type == DCBX_PROTOCOL_ROCE)) { + if (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits) && + type == DCBX_PROTOCOL_ROCE) { ecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1); ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_PCP, prio << 1); } @@ -293,7 +293,7 @@ ecore_dcbx_process_tlv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, } /* If Eth TLV is not detected, use UFP TC as default TC */ - if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, + if (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits) && !eth_tlv) p_data->arr[DCBX_PROTOCOL_ETH].tc = p_hwfn->ufp_info.tc; diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index 86ecfb269..e18c2fa89 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -805,7 +805,7 @@ static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn, ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id); } - if (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) && + if (OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) && !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) { rc = ecore_llh_add_mac_filter(p_dev, 0, p_hwfn->hw_info.hw_mac_addr); @@ -1044,7 +1044,7 @@ ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, filter_details.enable = 1; filter_details.value = ((u64)high << 32) | low; filter_details.hdr_sel = - OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ? + OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ? 1 : /* inner/encapsulated header */ 0; /* outer/tunnel header */ filter_details.protocol_type = filter_prot_type; @@ -1083,7 +1083,7 @@ enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid, if (p_ptt == OSAL_NULL) return ECORE_AGAIN; - if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) + if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) goto out; OSAL_MEM_ZERO(&filter, sizeof(filter)); @@ -1220,7 +1220,7 @@ ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid, if (p_ptt == OSAL_NULL) return ECORE_AGAIN; - if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits)) + if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits)) goto out; rc = ecore_llh_protocol_filter_stringify(p_dev, type, @@ -1287,7 +1287,7 @@ void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid, if (p_ptt == OSAL_NULL) return; - if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) + if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) goto out; OSAL_MEM_ZERO(&filter, sizeof(filter)); @@ -1342,7 +1342,7 @@ void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid, if (p_ptt == OSAL_NULL) return; - if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits)) + if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits)) goto out; rc = ecore_llh_protocol_filter_stringify(p_dev, type, @@ -1396,8 +1396,8 @@ void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid) if (p_ptt == OSAL_NULL) return; - if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) && - !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) + if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) && + !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) goto out; rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid); @@ -1423,8 +1423,8 @@ void ecore_llh_clear_all_filters(struct ecore_dev *p_dev) { u8 ppfid; - if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) && - !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) + if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) && + !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) return; for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) @@ -2674,7 +2674,7 @@ static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn) return ECORE_INVAL; } - if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) + if (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) hw_mode |= 1 << MODE_MF_SD; else hw_mode |= 1 << MODE_MF_SI; @@ -3382,7 +3382,7 @@ static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn, * The ppfid should be set in the vector, except in BB which has * a bug in the LLH where the ppfid is actually engine based. */ - if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) { + if (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) { u8 pf_id = p_hwfn->rel_pf_id; if (!ECORE_IS_BB(p_dev)) @@ -3715,11 +3715,11 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, if (rc != ECORE_SUCCESS) return rc; - if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, + if (IS_PF(p_dev) && (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING, &p_dev->mf_bits) || - OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING, + OSAL_GET_BIT(ECORE_MF_8021AD_TAGGING, &p_dev->mf_bits))) { - if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, + if (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING, &p_dev->mf_bits)) ether_type = ETHER_TYPE_VLAN; else @@ -4119,7 +4119,7 @@ enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev) OSAL_MSLEEP(1); if (IS_LEAD_HWFN(p_hwfn) && - OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) && + OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) && !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) ecore_llh_remove_mac_filter(p_dev, 0, p_hwfn->hw_info.hw_mac_addr); @@ -5113,7 +5113,7 @@ ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn, p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF; break; } - DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", + DP_INFO(p_hwfn, "Multi function mode is 0x%x\n", p_hwfn->p_dev->mf_bits); if (ECORE_IS_CMT(p_hwfn->p_dev)) @@ -6218,7 +6218,7 @@ enum _ecore_status_t ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) { - if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) { + if (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) { ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << p_hwfn->abs_pf_id / 2); @@ -6795,5 +6795,5 @@ void ecore_set_fw_mac_addr(__le16 *fw_msb, bool ecore_is_mf_fip_special(struct ecore_dev *p_dev) { - return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits); + return !!OSAL_GET_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits); } diff --git a/drivers/net/qede/base/ecore_dev_api.h b/drivers/net/qede/base/ecore_dev_api.h index 5ea8427a0..9ddf502eb 100644 --- a/drivers/net/qede/base/ecore_dev_api.h +++ b/drivers/net/qede/base/ecore_dev_api.h @@ -212,7 +212,7 @@ enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev, static OSAL_INLINE bool ecore_is_mf_ufp(struct ecore_hwfn *p_hwfn) { - return !!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits); + return !!OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits); } #endif diff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c index b20d83762..af234dec8 100644 --- a/drivers/net/qede/base/ecore_l2.c +++ b/drivers/net/qede/base/ecore_l2.c @@ -29,7 +29,7 @@ struct ecore_l2_info { u32 queues; - unsigned long **pp_qid_usage; + u32 **pp_qid_usage; /* The lock is meant to synchronize access to the qid usage */ osal_mutex_t lock; @@ -38,7 +38,7 @@ struct ecore_l2_info { enum _ecore_status_t ecore_l2_alloc(struct ecore_hwfn *p_hwfn) { struct ecore_l2_info *p_l2_info; - unsigned long **pp_qids; + u32 **pp_qids; u32 i; if (!ECORE_IS_L2_PERSONALITY(p_hwfn)) @@ -2116,7 +2116,7 @@ void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, struct ecore_arfs_config_params *p_cfg_params) { - if (OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &p_hwfn->p_dev->mf_bits)) + if (OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS, &p_hwfn->p_dev->mf_bits)) return; if (p_cfg_params->mode != ECORE_FILTER_CONFIG_MODE_DISABLE) { diff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c index 7518765a0..a7485967b 100644 --- a/drivers/net/qede/base/ecore_mcp.c +++ b/drivers/net/qede/base/ecore_mcp.c @@ -1732,7 +1732,7 @@ static void ecore_mcp_update_stag(struct ecore_hwfn *p_hwfn, p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK; p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; - if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) { + if (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) { if (p_hwfn->hw_info.ovlan != ECORE_MCP_VLAN_UNSET) { ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, p_hwfn->hw_info.ovlan); @@ -2026,7 +2026,7 @@ ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) struct public_func shmem_info; u32 port_cfg, val; - if (!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) + if (!OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) return; OSAL_MEMSET(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); diff --git a/drivers/net/qede/base/ecore_sp_commands.c b/drivers/net/qede/base/ecore_sp_commands.c index 9860a62b5..44ced135d 100644 --- a/drivers/net/qede/base/ecore_sp_commands.c +++ b/drivers/net/qede/base/ecore_sp_commands.c @@ -335,16 +335,16 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn, p_ramrod->dont_log_ramrods = 0; p_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0x8f); - if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) + if (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) p_ramrod->mf_mode = MF_OVLAN; else p_ramrod->mf_mode = MF_NPAR; p_ramrod->outer_tag_config.outer_tag.tci = OSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan); - if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, &p_hwfn->p_dev->mf_bits)) { + if (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING, &p_hwfn->p_dev->mf_bits)) { p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021Q; - } else if (OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING, + } else if (OSAL_GET_BIT(ECORE_MF_8021AD_TAGGING, &p_hwfn->p_dev->mf_bits)) { p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021AD; p_ramrod->outer_tag_config.enable_stag_pri_change = 1; @@ -357,7 +357,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn, /* enable_stag_pri_change should be set if port is in BD mode or, * UFP with Host Control mode. */ - if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) { + if (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) { if (p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS) p_ramrod->outer_tag_config.enable_stag_pri_change = 1; else @@ -378,7 +378,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn, ecore_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config); - if (OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH, + if (OSAL_GET_BIT(ECORE_MF_INTER_PF_SWITCH, &p_hwfn->p_dev->mf_bits)) p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch; @@ -638,7 +638,7 @@ enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn) if (rc != ECORE_SUCCESS) return rc; - if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) + if (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) p_ent->ramrod.pf_update.mf_vlan |= OSAL_CPU_TO_LE16(((u16)p_hwfn->ufp_info.tc << 13)); diff --git a/drivers/net/qede/base/ecore_spq.c b/drivers/net/qede/base/ecore_spq.c index 6c386821f..02f613688 100644 --- a/drivers/net/qede/base/ecore_spq.c +++ b/drivers/net/qede/base/ecore_spq.c @@ -977,7 +977,7 @@ enum _ecore_status_t ecore_spq_completion(struct ecore_hwfn *p_hwfn, * for the first successive completed entries. */ SPQ_COMP_BMAP_SET_BIT(p_spq, echo); - while (SPQ_COMP_BMAP_TEST_BIT(p_spq, + while (SPQ_COMP_BMAP_GET_BIT(p_spq, p_spq->comp_bitmap_idx)) { SPQ_COMP_BMAP_CLEAR_BIT(p_spq, p_spq->comp_bitmap_idx); diff --git a/drivers/net/qede/base/ecore_spq.h b/drivers/net/qede/base/ecore_spq.h index 6142c399a..0958e5a0a 100644 --- a/drivers/net/qede/base/ecore_spq.h +++ b/drivers/net/qede/base/ecore_spq.h @@ -121,17 +121,17 @@ struct ecore_spq { #define SPQ_RING_SIZE \ (CORE_SPQE_PAGE_SIZE_BYTES / sizeof(struct slow_path_element)) /* BITS_PER_LONG */ -#define SPQ_COMP_BMAP_SIZE (SPQ_RING_SIZE / (sizeof(unsigned long) * 8)) - unsigned long p_comp_bitmap[SPQ_COMP_BMAP_SIZE]; - u8 comp_bitmap_idx; +#define SPQ_COMP_BMAP_SIZE (SPQ_RING_SIZE / (sizeof(u32) * 8)) + u32 p_comp_bitmap[SPQ_COMP_BMAP_SIZE]; + u8 comp_bitmap_idx; #define SPQ_COMP_BMAP_SET_BIT(p_spq, idx) \ (OSAL_SET_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap)) #define SPQ_COMP_BMAP_CLEAR_BIT(p_spq, idx) \ (OSAL_CLEAR_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap)) -#define SPQ_COMP_BMAP_TEST_BIT(p_spq, idx) \ - (OSAL_TEST_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap)) +#define SPQ_COMP_BMAP_GET_BIT(p_spq, idx) \ + (OSAL_GET_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap)) /* Statistics */ u32 unlimited_pending_count; diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c index 8580cbcd7..bd63c0ac7 100644 --- a/drivers/net/qede/qede_main.c +++ b/drivers/net/qede/qede_main.c @@ -382,8 +382,8 @@ qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info) if (IS_PF(edev)) { dev_info->b_inter_pf_switch = - OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits); - if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits)) + OSAL_GET_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits); + if (!OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits)) dev_info->b_arfs_capable = true; dev_info->tx_switching = false; From patchwork Mon Mar 9 09:54:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 66412 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DCF17A052E; Mon, 9 Mar 2020 10:55:42 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C0DF21C11F; Mon, 9 Mar 2020 10:55:06 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 3BD8E1C11E for ; Mon, 9 Mar 2020 10:55:05 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BA9BE101E; Mon, 9 Mar 2020 02:55:04 -0700 (PDT) Received: from net-arm-thunderx2-03.shanghai.arm.com (net-arm-thunderx2-03.shanghai.arm.com [10.169.41.185]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A0B1C3F67D; Mon, 9 Mar 2020 02:54:59 -0700 (PDT) From: Joyce Kong To: thomas@monjalon.net, stephen@networkplumber.org, david.marchand@redhat.com, mb@smartsharesystems.com, jerinj@marvell.com, bruce.richardson@intel.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com, honnappa.nagarahalli@arm.com, phil.yang@arm.com, gavin.hu@arm.com Cc: nd@arm.com, dev@dpdk.org Date: Mon, 9 Mar 2020 17:54:10 +0800 Message-Id: <20200309095410.28983-7-joyce.kong@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200309095410.28983-1-joyce.kong@arm.com> References: <20200309095410.28983-1-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v7 6/6] net/hinic: use common rte bit operation APIs instead X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove its own bit operation APIs and use the common one, this can reduce the code duplication largely. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu --- drivers/net/hinic/Makefile | 1 + drivers/net/hinic/base/hinic_compat.h | 33 +-------------------------- drivers/net/hinic/hinic_pmd_ethdev.c | 18 ++++++++------- drivers/net/hinic/hinic_pmd_ethdev.h | 2 +- drivers/net/hinic/meson.build | 2 ++ 5 files changed, 15 insertions(+), 41 deletions(-) diff --git a/drivers/net/hinic/Makefile b/drivers/net/hinic/Makefile index 87fd843e4..f087baac5 100644 --- a/drivers/net/hinic/Makefile +++ b/drivers/net/hinic/Makefile @@ -9,6 +9,7 @@ include $(RTE_SDK)/mk/rte.vars.mk LIB = librte_pmd_hinic.a CFLAGS += -O3 +CFLAGS += -DALLOW_EXPERIMENTAL_API CFLAGS += $(WERROR_FLAGS) ifeq ($(CONFIG_RTE_ARCH_ARM64),y) diff --git a/drivers/net/hinic/base/hinic_compat.h b/drivers/net/hinic/base/hinic_compat.h index b72e8cfe2..7fab6dc29 100644 --- a/drivers/net/hinic/base/hinic_compat.h +++ b/drivers/net/hinic/base/hinic_compat.h @@ -18,6 +18,7 @@ #include #include #include +#include typedef uint8_t u8; typedef int8_t s8; @@ -116,38 +117,6 @@ extern int hinic_logtype; #define HINIC_PAGE_SIZE_DPDK 6 -static inline int hinic_test_bit(int nr, volatile unsigned long *addr) -{ - int res; - - res = ((*addr) & (1UL << nr)) != 0; - return res; -} - -static inline void hinic_set_bit(unsigned int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_or(addr, (1UL << nr)); -} - -static inline void hinic_clear_bit(int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_and(addr, ~(1UL << nr)); -} - -static inline int hinic_test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = (1UL << nr); - - return __sync_fetch_and_and(addr, ~mask) & mask; -} - -static inline int hinic_test_and_set_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = (1UL << nr); - - return __sync_fetch_and_or(addr, mask) & mask; -} - void *dma_zalloc_coherent(void *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag); void *dma_zalloc_coherent_aligned(void *dev, size_t size, diff --git a/drivers/net/hinic/hinic_pmd_ethdev.c b/drivers/net/hinic/hinic_pmd_ethdev.c index 803a39e2d..c53980f44 100644 --- a/drivers/net/hinic/hinic_pmd_ethdev.c +++ b/drivers/net/hinic/hinic_pmd_ethdev.c @@ -269,7 +269,7 @@ static void hinic_dev_interrupt_handler(void *param) struct rte_eth_dev *dev = param; struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); - if (!hinic_test_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status)) { + if (!rte_get_bit32_relaxed(HINIC_DEV_INTR_EN, &nic_dev->dev_status)) { PMD_DRV_LOG(WARNING, "Device's interrupt is disabled, ignore interrupt event, dev_name: %s, port_id: %d", nic_dev->proc_dev_name, dev->data->port_id); return; @@ -1076,7 +1076,7 @@ static int hinic_dev_start(struct rte_eth_dev *dev) if (dev->data->dev_conf.intr_conf.lsc != 0) (void)hinic_link_update(dev, 0); - hinic_set_bit(HINIC_DEV_START, &nic_dev->dev_status); + rte_set_bit32_relaxed(HINIC_DEV_START, &nic_dev->dev_status); return 0; @@ -1201,7 +1201,8 @@ static void hinic_dev_stop(struct rte_eth_dev *dev) name = dev->data->name; port_id = dev->data->port_id; - if (!hinic_test_and_clear_bit(HINIC_DEV_START, &nic_dev->dev_status)) { + if (!rte_test_and_clear_bit32_relaxed(HINIC_DEV_START, + &nic_dev->dev_status)) { PMD_DRV_LOG(INFO, "Device %s already stopped", name); return; } @@ -1246,7 +1247,7 @@ static void hinic_disable_interrupt(struct rte_eth_dev *dev) struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); int ret, retries = 0; - hinic_clear_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status); + rte_clear_bit32_relaxed(HINIC_DEV_INTR_EN, &nic_dev->dev_status); /* disable msix interrupt in hardware */ hinic_set_msix_state(nic_dev->hwdev, 0, HINIC_MSIX_DISABLE); @@ -2845,7 +2846,8 @@ static void hinic_dev_close(struct rte_eth_dev *dev) { struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); - if (hinic_test_and_set_bit(HINIC_DEV_CLOSE, &nic_dev->dev_status)) { + if (rte_test_and_set_bit32_relaxed(HINIC_DEV_CLOSE, + &nic_dev->dev_status)) { PMD_DRV_LOG(WARNING, "Device %s already closed", dev->data->name); return; @@ -3042,7 +3044,7 @@ static int hinic_func_init(struct rte_eth_dev *eth_dev) eth_dev->data->name); goto enable_intr_fail; } - hinic_set_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status); + rte_set_bit32_relaxed(HINIC_DEV_INTR_EN, &nic_dev->dev_status); /* initialize filter info */ filter_info = &nic_dev->filter; @@ -3054,7 +3056,7 @@ static int hinic_func_init(struct rte_eth_dev *eth_dev) TAILQ_INIT(&nic_dev->filter_fdir_rule_list); TAILQ_INIT(&nic_dev->hinic_flow_list); - hinic_set_bit(HINIC_DEV_INIT, &nic_dev->dev_status); + rte_set_bit32_relaxed(HINIC_DEV_INIT, &nic_dev->dev_status); PMD_DRV_LOG(INFO, "Initialize %s in primary successfully", eth_dev->data->name); @@ -3110,7 +3112,7 @@ static int hinic_dev_uninit(struct rte_eth_dev *dev) struct hinic_nic_dev *nic_dev; nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); - hinic_clear_bit(HINIC_DEV_INIT, &nic_dev->dev_status); + rte_clear_bit32_relaxed(HINIC_DEV_INIT, &nic_dev->dev_status); if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; diff --git a/drivers/net/hinic/hinic_pmd_ethdev.h b/drivers/net/hinic/hinic_pmd_ethdev.h index 3e3f3b360..114f1df92 100644 --- a/drivers/net/hinic/hinic_pmd_ethdev.h +++ b/drivers/net/hinic/hinic_pmd_ethdev.h @@ -171,7 +171,7 @@ struct hinic_nic_dev { unsigned int flags; struct nic_service_cap nic_cap; u32 rx_mode_status; /* promisc or allmulticast */ - unsigned long dev_status; + u32 dev_status; char proc_dev_name[HINIC_DEV_NAME_LEN]; /* PF0->COS4, PF1->COS5, PF2->COS6, PF3->COS7, diff --git a/drivers/net/hinic/meson.build b/drivers/net/hinic/meson.build index bc7e24639..8c7ee9dfc 100644 --- a/drivers/net/hinic/meson.build +++ b/drivers/net/hinic/meson.build @@ -1,6 +1,8 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Huawei Technologies Co., Ltd +allow_experimental_apis = true + subdir('base') objs = [base_objs]