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X-Microsoft-Antispam-Message-Info: hzXO/4SEcZChgrLnS9O6RvbjbIedU5L7XHZOnDIvndFR85HRS20V6v391erUJAEf8c0o6sF9WkYKxdugyg7Obpggjy5QVsR2evaHOHSJq32jZus03vtWTtJcTI8/avJnUwMvPuM8QorGoZV2vS021+5uV04hG2ZI8epNiVMxSeWc3RO2pJoGlkCtgnl35zQ/5nzcJ1X+tjKsFgaeO3Wy2sH4jknQv96U66w+9wolgTlZga4wBqTwR6v6nvq3+/ei204qTUqsVVcPIjg1DsZmAmUEzpvPWj0tD8xFBT/MKR4OAnjsmXcRJAWm1u5hrDSNqkvVLsNRoonjnL5w4upfaqFOAqgo3enchhWgj9sqiLDkFTPTsEJvor5p4r2tSahyjFR00eCEJWkbpmSw7EhbktGcKizURewxFp6sh2wB4rAiOchq/ItsuxEnNlqY21n/ X-MS-Exchange-AntiSpam-MessageData: WVuAXhjhq/j1K/YwoOseeIr5lUwUEA/xUui6FafYIxBRA8OmDzr6lcqxQHwm1uFLD0Fcirx2wQ93Vs/ejohCP9TpNYu4Ru/EwpPJnofDrT/yKxCJIZ0h/x5jXPbJBmzDbzvxZuzKUD0VZkcL8mSfTg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0f4476a2-cc1f-48ae-e772-08d7a867051f X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2020 05:07:52.1417 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6Z4/g09DyJUgwp61vKj8iwy1k9U4413lAAXVU/NpBTwoyv5YK7X/wTIAk8ziSgjU2USvau4p26bG34N4zy+8IQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0123 Subject: [dpdk-dev] [PATCH v3 1/2] net/axgbe: support flow control API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Amaranath Somalapuram Adding api for flow_ctrl_get and flow_ctrl_set. By default axgbe driver flow control is disabled. Adding dpdk flow control to set water high and low. Cc: stable@dpdk.org Signed-off-by: Amaranath Somalapuram --- drivers/net/axgbe/axgbe_ethdev.c | 85 +++++++++++++++++++++++++++++++- drivers/net/axgbe/axgbe_ethdev.h | 10 ++++ 2 files changed, 94 insertions(+), 1 deletion(-) diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c index d0b6f091f..b88ad55ac 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -43,7 +43,11 @@ axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, unsigned int size); static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev); static int axgbe_dev_info_get(struct rte_eth_dev *dev, - struct rte_eth_dev_info *dev_info); + struct rte_eth_dev_info *dev_info); +static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, + struct rte_eth_fc_conf *fc_conf); +static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, + struct rte_eth_fc_conf *fc_conf); struct axgbe_xstats { char name[RTE_ETH_XSTATS_NAME_SIZE]; @@ -170,6 +174,8 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = { .rx_queue_release = axgbe_dev_rx_queue_release, .tx_queue_setup = axgbe_dev_tx_queue_setup, .tx_queue_release = axgbe_dev_tx_queue_release, + .flow_ctrl_get = axgbe_flow_ctrl_get, + .flow_ctrl_set = axgbe_flow_ctrl_set, }; static int axgbe_phy_reset(struct axgbe_port *pdata) @@ -815,6 +821,83 @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) return 0; } +static int +axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) +{ + struct axgbe_port *pdata = dev->data->dev_private; + struct xgbe_fc_info fc = pdata->fc; + unsigned int reg, reg_val = 0; + + reg = MAC_Q0TFCR; + reg_val = AXGMAC_IOREAD(pdata, reg); + fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA); + fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD); + fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT); + fc.autoneg = pdata->pause_autoneg; + + if (pdata->rx_pause && pdata->tx_pause) + fc.mode = RTE_FC_FULL; + else if (pdata->rx_pause) + fc.mode = RTE_FC_RX_PAUSE; + else if (pdata->tx_pause) + fc.mode = RTE_FC_TX_PAUSE; + else + fc.mode = RTE_FC_NONE; + + fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024; + fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024; + fc_conf->pause_time = fc.pause_time[0]; + fc_conf->send_xon = fc.send_xon; + fc_conf->mode = fc.mode; + + return 0; +} + +static int +axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) +{ + struct axgbe_port *pdata = dev->data->dev_private; + struct xgbe_fc_info fc = pdata->fc; + unsigned int reg, reg_val = 0; + reg = MAC_Q0TFCR; + + pdata->pause_autoneg = fc_conf->autoneg; + pdata->phy.pause_autoneg = pdata->pause_autoneg; + fc.send_xon = fc_conf->send_xon; + AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA, + AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water)); + AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD, + AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water)); + AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time); + AXGMAC_IOWRITE(pdata, reg, reg_val); + fc.mode = fc_conf->mode; + + if (fc.mode == RTE_FC_FULL) { + pdata->tx_pause = 1; + pdata->rx_pause = 1; + } else if (fc.mode == RTE_FC_RX_PAUSE) { + pdata->tx_pause = 0; + pdata->rx_pause = 1; + } else if (fc.mode == RTE_FC_TX_PAUSE) { + pdata->tx_pause = 1; + pdata->rx_pause = 0; + } else { + pdata->tx_pause = 0; + pdata->rx_pause = 0; + } + + if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) + pdata->hw_if.config_tx_flow_control(pdata); + + if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) + pdata->hw_if.config_rx_flow_control(pdata); + + pdata->hw_if.config_flow_control(pdata); + pdata->phy.tx_pause = pdata->tx_pause; + pdata->phy.rx_pause = pdata->rx_pause; + + return 0; +} static void axgbe_get_all_hw_features(struct axgbe_port *pdata) { diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index a1083b17b..746fb2f15 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -485,6 +485,15 @@ struct axgbe_mmc_stats { uint64_t rxwatchdogerror; }; +/* Flow control parameters */ +struct xgbe_fc_info { + uint32_t high_water[AXGBE_PRIORITY_QUEUES]; + uint32_t low_water[AXGBE_PRIORITY_QUEUES]; + uint16_t pause_time[AXGBE_PRIORITY_QUEUES]; + uint16_t send_xon; + enum rte_eth_fc_mode mode; + uint8_t autoneg; +}; /* * Structure to store private data for each port. */ @@ -625,6 +634,7 @@ struct axgbe_port { uint32_t rx_csum_enable; struct axgbe_mmc_stats mmc_stats; + struct xgbe_fc_info fc; }; void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); From patchwork Mon Feb 3 05:04:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AMARANATH SOMALAPURAM X-Patchwork-Id: 65483 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8FF7EA04B3; Mon, 3 Feb 2020 06:08:22 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 740441BFEF; Mon, 3 Feb 2020 06:08:22 +0100 (CET) Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-eopbgr770083.outbound.protection.outlook.com [40.107.77.83]) by dpdk.org (Postfix) with ESMTP id BDE581BFE0; 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SFS:(10009020)(4636009)(376002)(39860400002)(346002)(136003)(396003)(366004)(189003)(199004)(6916009)(2616005)(36756003)(7696005)(52116002)(956004)(5660300002)(450100002)(316002)(4326008)(66556008)(16526019)(66476007)(26005)(478600001)(8936002)(186003)(81156014)(81166006)(66946007)(8676002)(1076003)(9686003)(6486002)(2906002)(6666004); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR1201MB0123; H:DM5PR1201MB2474.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AOma7JYYcvWE5PVnWzdhw3uNJYj/nIK1AeWNVbgLHGvhGwoCXk7rePN3lVrW1yi7AnS5XMeuFhO10Edx30PJL0r3Wen46IBOEf/41VE3T39jTjoytyqMDB/d/Q14pxKpi2XFScJufQASaz/8MmbeDRXJeSprMfdcyJ0p7hpwUfCNoAe64pRaVep1hGVXJbODhRpzwl13INKmUBmeMwMAxMLfHVZC7kIycT/S9DZrp3r1sudqvT5D9rrYZE2Jl2EPYFA9bHcpUe2GJRLz4rfD0NmUkHtKASKf+V9M2qvLvUZzfSHbOjaIxUSExKq99utOSCJ73xmf/GxkV+rWbCr+SvD4O8a2Pt3GzAwBU0PwHzs6Y+s8w6K6JLyg+PsfB6xfPtO3wwIuDOYTEyR0zsyGYjmFFEQ9I7jjaaSWp3uiSX7xupz0asznenupbEgAzvLX X-MS-Exchange-AntiSpam-MessageData: g7GzrtR2+buXrYUlmCxE5fO52LOczG/Op3QqfnPRADx5s1eGgnWNP2r4VRvpSd4Bw74UTjUCqcuDZDhqNH0lXLIgcoCmQSRushououy7YS2lHktYGbPvTS4WWGZzutN2tUanJBxPx/T3+taH+DR0CA== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: f4d3ea0e-50e8-440c-e7e7-08d7a8671591 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2020 05:08:19.4775 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Sg0O2yEjLB6Otomn5i7ST3/9GYCNUUZIRHJNtSY/vbdaHe2zFot1hnE15eZkFm693NmlMIhEFCjeZ72PG4UELQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0123 Subject: [dpdk-dev] [PATCH v3 2/2] net/axgbe: support priority flow control API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Amaranath Somalapuram Adding API for priority_flow_ctrl_set. Priority flow control to set water high and low, pause_time and priority. Cc: stable@dpdk.org Signed-off-by: Amaranath Somalapuram --- drivers/net/axgbe/axgbe_common.h | 17 ++++++ drivers/net/axgbe/axgbe_dev.c | 1 + drivers/net/axgbe/axgbe_ethdev.c | 96 ++++++++++++++++++++++++++++++++ drivers/net/axgbe/axgbe_ethdev.h | 1 + 4 files changed, 115 insertions(+) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index fdb037dd5..bc7bc6af5 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -833,6 +833,23 @@ #define MTL_TC_QWR_QW_INDEX 0 #define MTL_TC_QWR_QW_WIDTH 21 +#define MTL_TCPM0R_PSTC0_INDEX 0 +#define MTL_TCPM0R_PSTC0_WIDTH 8 +#define MTL_TCPM0R_PSTC1_INDEX 8 +#define MTL_TCPM0R_PSTC1_WIDTH 8 +#define MTL_TCPM0R_PSTC2_INDEX 16 +#define MTL_TCPM0R_PSTC2_WIDTH 8 +#define MTL_TCPM0R_PSTC3_INDEX 24 +#define MTL_TCPM0R_PSTC3_WIDTH 8 +#define MTL_TCPM1R_PSTC4_INDEX 0 +#define MTL_TCPM1R_PSTC4_WIDTH 8 +#define MTL_TCPM1R_PSTC5_INDEX 8 +#define MTL_TCPM1R_PSTC5_WIDTH 8 +#define MTL_TCPM1R_PSTC6_INDEX 16 +#define MTL_TCPM1R_PSTC6_WIDTH 8 +#define MTL_TCPM1R_PSTC7_INDEX 24 +#define MTL_TCPM1R_PSTC7_WIDTH 8 + /* MTL traffic class register value */ #define MTL_TSA_SP 0x00 #define MTL_TSA_ETS 0x02 diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c index 83089f20d..9a68bea63 100644 --- a/drivers/net/axgbe/axgbe_dev.c +++ b/drivers/net/axgbe/axgbe_dev.c @@ -958,6 +958,7 @@ static void axgbe_config_queue_mapping(struct axgbe_port *pdata) if (i < qptc_extra) AXGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, Q2TCMAP, i); + pdata->pfc_map[queue++] = i; } if (pdata->rss_enable) { diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c index b88ad55ac..686a9a20d 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -48,6 +48,8 @@ static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); +static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, + struct rte_eth_pfc_conf *pfc_conf); struct axgbe_xstats { char name[RTE_ETH_XSTATS_NAME_SIZE]; @@ -176,6 +178,7 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = { .tx_queue_release = axgbe_dev_tx_queue_release, .flow_ctrl_get = axgbe_flow_ctrl_get, .flow_ctrl_set = axgbe_flow_ctrl_set, + .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set, }; static int axgbe_phy_reset(struct axgbe_port *pdata) @@ -899,6 +902,99 @@ axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) return 0; } +static int +axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, + struct rte_eth_pfc_conf *pfc_conf) +{ + struct axgbe_port *pdata = dev->data->dev_private; + struct xgbe_fc_info fc = pdata->fc; + uint8_t tc_num; + + tc_num = pdata->pfc_map[pfc_conf->priority]; + + if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) { + PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n", + pdata->hw_feat.tc_cnt); + return -EINVAL; + } + + pdata->pause_autoneg = pfc_conf->fc.autoneg; + pdata->phy.pause_autoneg = pdata->pause_autoneg; + fc.send_xon = pfc_conf->fc.send_xon; + AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, + AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); + AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, + AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water)); + + switch (tc_num) { + case 0: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC0, pfc_conf->fc.pause_time); + break; + case 1: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC1, pfc_conf->fc.pause_time); + break; + case 2: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC2, pfc_conf->fc.pause_time); + break; + case 3: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC3, pfc_conf->fc.pause_time); + break; + case 4: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC4, pfc_conf->fc.pause_time); + break; + case 5: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC5, pfc_conf->fc.pause_time); + break; + case 7: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC6, pfc_conf->fc.pause_time); + break; + case 6: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC7, pfc_conf->fc.pause_time); + break; + } + + fc.mode = pfc_conf->fc.mode; + + if (fc.mode == RTE_FC_FULL) { + pdata->tx_pause = 1; + pdata->rx_pause = 1; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); + } else if (fc.mode == RTE_FC_RX_PAUSE) { + pdata->tx_pause = 0; + pdata->rx_pause = 1; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); + } else if (fc.mode == RTE_FC_TX_PAUSE) { + pdata->tx_pause = 1; + pdata->rx_pause = 0; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); + } else { + pdata->tx_pause = 0; + pdata->rx_pause = 0; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); + } + + if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) + pdata->hw_if.config_tx_flow_control(pdata); + + if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) + pdata->hw_if.config_rx_flow_control(pdata); + pdata->hw_if.config_flow_control(pdata); + pdata->phy.tx_pause = pdata->tx_pause; + pdata->phy.rx_pause = pdata->rx_pause; + + return 0; +} + + + static void axgbe_get_all_hw_features(struct axgbe_port *pdata) { unsigned int mac_hfr0, mac_hfr1, mac_hfr2; diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index 746fb2f15..c884f5642 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -585,6 +585,7 @@ struct axgbe_port { unsigned int rx_rfa[AXGBE_MAX_QUEUES]; unsigned int rx_rfd[AXGBE_MAX_QUEUES]; unsigned int fifo; + unsigned int pfc_map[AXGBE_MAX_QUEUES]; /* Receive Side Scaling settings */ u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];