From patchwork Sat Dec 21 01:34:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasesh Mody X-Patchwork-Id: 64086 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2BA82A04F7; Sat, 21 Dec 2019 02:35:11 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 453D91F1C; Sat, 21 Dec 2019 02:35:10 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 7808B1252 for ; Sat, 21 Dec 2019 02:35:08 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBL1WAne025916; Fri, 20 Dec 2019 17:35:07 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0818; bh=Ww+8KzWnZmF0JPk/1Of7IrjrYHSh6PQfr9xa6G7QdOQ=; b=wGwm8rqrjpug21D3d+I7mBEwLxm3N/zm0GWOz2SG0K2TQ3vBByvKwHznJkbyvERL/fwE yS26ONURlHn4ZdknwxYi+3z5YvYEfIUaDJXouCfn/OvfKkCM6+t+AbZ667MnvjRZWEIo MnjRf5gAQaepDoS6Ah6HBR8ms1U8eYKdWeZnDDfQq5Ix+moqv4eku9DjAdOSITrlHirY yuXlL1u8lJsitJLAvsjB9ImfMNLupy2xDGhgDwLGJyl4SK1wsCIfrxT3LpgGWpZIiuJ0 Iigbb17Qd9u42BekAqIWpvZnR2RTYh1nY0lvnFU3rIWrgWyq53RkWGx50pWbM7xdNKWF lg== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2x0sfy30g4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 20 Dec 2019 17:35:07 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 20 Dec 2019 17:35:04 -0800 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 20 Dec 2019 17:35:05 -0800 Received: from irv1user08.caveonetworks.com (unknown [10.104.116.105]) by maili.marvell.com (Postfix) with ESMTP id 3B0BE3F703F; Fri, 20 Dec 2019 17:35:05 -0800 (PST) Received: (from rmody@localhost) by irv1user08.caveonetworks.com (8.14.4/8.14.4/Submit) id xBL1Z3dg028652; Fri, 20 Dec 2019 17:35:03 -0800 X-Authentication-Warning: irv1user08.caveonetworks.com: rmody set sender to rmody@marvell.com using -f From: Rasesh Mody To: , , CC: Rasesh Mody , , Date: Fri, 20 Dec 2019 17:34:51 -0800 Message-ID: <20191221013451.28588-1-rmody@marvell.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-20_07:2019-12-17,2019-12-20 signatures=0 Subject: [dpdk-dev] [PATCH] net/qede/base: fix number of ports per engine X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fix the way in which the number of ports per engine of an adapter is determined by reading port mode register. Set default value to 1. Fixes: 3b307c55f2ac ("net/qede/base: update FW to 8.40.25.0") Cc: stable@dpdk.com Signed-off-by: Rasesh Mody --- drivers/net/qede/base/ecore_dev.c | 38 ++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index 9d1db14590..f33b9910c0 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -5253,7 +5253,6 @@ static void ecore_emul_hw_info_port_num(struct ecore_hwfn *p_hwfn, /* MISCS_REG_ECO_RESERVED[15:12]: num of ports in an engine */ eco_reserved = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED); - switch ((eco_reserved & 0xf000) >> 12) { case 1: p_dev->num_ports_in_engine = 1; @@ -5268,7 +5267,7 @@ static void ecore_emul_hw_info_port_num(struct ecore_hwfn *p_hwfn, DP_NOTICE(p_hwfn, false, "Emulation: Unknown port mode [ECO_RESERVED 0x%08x]\n", eco_reserved); - p_dev->num_ports_in_engine = 2; /* Default to something */ + p_dev->num_ports_in_engine = 1; /* Default to something */ break; } @@ -5281,8 +5280,8 @@ static void ecore_emul_hw_info_port_num(struct ecore_hwfn *p_hwfn, static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) { + u32 addr, global_offsize, global_addr, port_mode; struct ecore_dev *p_dev = p_hwfn->p_dev; - u32 addr, global_offsize, global_addr; #ifndef ASIC_ONLY if (CHIP_REV_IS_TEDIBEAR(p_dev)) { @@ -5304,15 +5303,32 @@ static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn, return; } - addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, - PUBLIC_GLOBAL); - global_offsize = ecore_rd(p_hwfn, p_ptt, addr); - global_addr = SECTION_ADDR(global_offsize, 0); - addr = global_addr + OFFSETOF(struct public_global, max_ports); - p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr); + /* Determine the number of ports per engine */ + port_mode = ecore_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE); + switch (port_mode) { + case 0x0: + p_dev->num_ports_in_engine = 1; + break; + case 0x1: + p_dev->num_ports_in_engine = 2; + break; + case 0x2: + p_dev->num_ports_in_engine = 4; + break; + default: + DP_NOTICE(p_hwfn, false, "Unknown port mode 0x%08x\n", + port_mode); + p_dev->num_ports_in_engine = 1; /* Default to something */ + break; + } - p_dev->num_ports_in_engine = p_dev->num_ports >> - (ecore_device_num_engines(p_dev) - 1); + /* Get the total number of ports of the device */ + addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, + PUBLIC_GLOBAL); + global_offsize = ecore_rd(p_hwfn, p_ptt, addr); + global_addr = SECTION_ADDR(global_offsize, 0); + addr = global_addr + OFFSETOF(struct public_global, max_ports); + p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr); } static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,