From patchwork Sun Oct 27 12:52:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 62059 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3742C1BF1F; Sun, 27 Oct 2019 13:53:03 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 75F921BEF4; Sun, 27 Oct 2019 13:53:01 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D384D1F1; Sun, 27 Oct 2019 05:53:00 -0700 (PDT) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 560D83F71F; Sun, 27 Oct 2019 05:52:57 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, konstantin.ananyev@intel.com, thomas@monjalon.net, stephen@networkplumber.org, hemant.agrawal@nxp.com, jerinj@marvell.com, pbhagavatula@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, steve.capper@arm.com, stable@dpdk.org Date: Sun, 27 Oct 2019 20:52:41 +0800 Message-Id: <1572180765-49767-2-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572180765-49767-1-git-send-email-gavin.hu@arm.com> References: <1572180765-49767-1-git-send-email-gavin.hu@arm.com> In-Reply-To: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH v11 1/5] bus/fslmc: fix the conflicting dmb function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" There are two definitions conflicting each other, for more details, refer to [1]. include/rte_atomic_64.h:19: error: "dmb" redefined [-Werror] drivers/bus/fslmc/mc/fsl_mc_sys.h:36: note: this is the location of the previous definition #define dmb() {__asm__ __volatile__("" : : : "memory"); } The fix is to reuse the EAL definition to avoid conflicts. [1] http://inbox.dpdk.org/users/VI1PR08MB537631AB25F41B8880DCCA988FDF0@ VI1PR08MB5376.eurprd08.prod.outlook.com/T/#u Fixes: 3af733ba8da8 ("bus/fslmc: introduce MC object functions") Cc: stable@dpdk.org Signed-off-by: Gavin Hu Reviewed-by: Phil Yang Acked-by: Hemant Agrawal --- drivers/bus/fslmc/mc/fsl_mc_sys.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/bus/fslmc/mc/fsl_mc_sys.h b/drivers/bus/fslmc/mc/fsl_mc_sys.h index d0c7b39..68ce38b 100644 --- a/drivers/bus/fslmc/mc/fsl_mc_sys.h +++ b/drivers/bus/fslmc/mc/fsl_mc_sys.h @@ -31,12 +31,10 @@ struct fsl_mc_io { #include #include #include +#include -#ifndef dmb -#define dmb() {__asm__ __volatile__("" : : : "memory"); } -#endif -#define __iormb() dmb() -#define __iowmb() dmb() +#define __iormb() rte_io_rmb() +#define __iowmb() rte_io_wmb() #define __arch_getq(a) (*(volatile uint64_t *)(a)) #define __arch_putq(v, a) (*(volatile uint64_t *)(a) = (v)) #define __arch_putq32(v, a) (*(volatile uint32_t *)(a) = (v)) From patchwork Sun Oct 27 12:52:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 62060 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D064C1BF3C; Sun, 27 Oct 2019 13:53:06 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 166841BF2B for ; Sun, 27 Oct 2019 13:53:05 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 91CEA1F1; Sun, 27 Oct 2019 05:53:04 -0700 (PDT) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 49CCC3F71F; Sun, 27 Oct 2019 05:53:01 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, konstantin.ananyev@intel.com, thomas@monjalon.net, stephen@networkplumber.org, hemant.agrawal@nxp.com, jerinj@marvell.com, pbhagavatula@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, steve.capper@arm.com Date: Sun, 27 Oct 2019 20:52:42 +0800 Message-Id: <1572180765-49767-3-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572180765-49767-1-git-send-email-gavin.hu@arm.com> References: <1572180765-49767-1-git-send-email-gavin.hu@arm.com> In-Reply-To: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH v11 2/5] eal: add the APIs to wait until equal X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The rte_wait_until_equal_xx APIs abstract the functionality of 'polling for a memory location to become equal to a given value'. Add the RTE_ARM_USE_WFE configuration entry for aarch64, disabled by default. When it is enabled, the above APIs will call WFE instruction to save CPU cycles and power. From a VM, when calling this API on aarch64, it may trap in and out to release vCPUs whereas cause high exit latency. Since kernel 4.18.20 an adaptive trapping mechanism is introduced to balance the latency and workload. Signed-off-by: Gavin Hu Reviewed-by: Ruifeng Wang Reviewed-by: Steve Capper Reviewed-by: Ola Liljedahl Reviewed-by: Honnappa Nagarahalli Reviewed-by: Phil Yang Acked-by: Pavan Nikhilesh Acked-by: Jerin Jacob --- config/arm/meson.build | 1 + config/common_base | 5 + .../common/include/arch/arm/rte_pause_64.h | 188 +++++++++++++++++++++ lib/librte_eal/common/include/generic/rte_pause.h | 99 +++++++++++ 4 files changed, 293 insertions(+) diff --git a/config/arm/meson.build b/config/arm/meson.build index 979018e..b4b4cac 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -26,6 +26,7 @@ flags_common_default = [ ['RTE_LIBRTE_AVP_PMD', false], ['RTE_SCHED_VECTOR', false], + ['RTE_ARM_USE_WFE', false], ] flags_generic = [ diff --git a/config/common_base b/config/common_base index e843a21..c812156 100644 --- a/config/common_base +++ b/config/common_base @@ -111,6 +111,11 @@ CONFIG_RTE_MAX_VFIO_CONTAINERS=64 CONFIG_RTE_MALLOC_DEBUG=n CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n CONFIG_RTE_USE_LIBBSD=n +# Use WFE instructions to implement the rte_wait_for_equal_xxx APIs, +# calling these APIs put the cores in low power state while waiting +# for the memory address to become equal to the expected value. +# This is supported only by aarch64. +CONFIG_RTE_ARM_USE_WFE=n # # Recognize/ignore the AVX/AVX512 CPU flags for performance/power testing. diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h index 93895d3..1680d7a 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2017 Cavium, Inc + * Copyright(c) 2019 Arm Limited */ #ifndef _RTE_PAUSE_ARM64_H_ @@ -10,6 +11,11 @@ extern "C" { #endif #include + +#ifdef RTE_ARM_USE_WFE +#define RTE_WAIT_UNTIL_EQUAL_ARCH_DEFINED +#endif + #include "generic/rte_pause.h" static inline void rte_pause(void) @@ -17,6 +23,188 @@ static inline void rte_pause(void) asm volatile("yield" ::: "memory"); } +/** + * Send an event to quit WFE. + */ +static inline void rte_sevl(void); + +/** + * Put processor into low power WFE(Wait For Event) state + */ +static inline void rte_wfe(void); + +#ifdef RTE_ARM_USE_WFE +static inline void rte_sevl(void) +{ + asm volatile("sevl" : : : "memory"); +} + +static inline void rte_wfe(void) +{ + asm volatile("wfe" : : : "memory"); +} +#else +static inline void rte_sevl(void) +{ +} +static inline void rte_wfe(void) +{ + rte_pause(); +} +#endif + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Atomic exclusive load from addr, it returns the 16-bit content of *addr + * while making it 'monitored',when it is written by someone else, the + * 'monitored' state is cleared and a event is generated implicitly to exit + * WFE. + * + * @param addr + * A pointer to the memory location. + * @param memorder + * The valid memory order variants are __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. + * These map to C++11 memory orders with the same names, see the C++11 standard + * the GCC wiki on atomic synchronization for detailed definitions. + */ +static __rte_always_inline uint16_t +rte_atomic_load_ex_16(volatile uint16_t *addr, int memorder); + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Atomic exclusive load from addr, it returns the 32-bit content of *addr + * while making it 'monitored',when it is written by someone else, the + * 'monitored' state is cleared and a event is generated implicitly to exit + * WFE. + * + * @param addr + * A pointer to the memory location. + * @param memorder + * The valid memory order variants are __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. + * These map to C++11 memory orders with the same names, see the C++11 standard + * the GCC wiki on atomic synchronization for detailed definitions. + */ +static __rte_always_inline uint32_t +rte_atomic_load_ex_32(volatile uint32_t *addr, int memorder); + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Atomic exclusive load from addr, it returns the 64-bit content of *addr + * while making it 'monitored',when it is written by someone else, the + * 'monitored' state is cleared and a event is generated implicitly to exit + * WFE. + * + * @param addr + * A pointer to the memory location. + * @param memorder + * The valid memory order variants are __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. + * These map to C++11 memory orders with the same names, see the C++11 standard + * the GCC wiki on atomic synchronization for detailed definitions. + */ +static __rte_always_inline uint64_t +rte_atomic_load_ex_64(volatile uint64_t *addr, int memorder); + +static __rte_always_inline uint16_t +rte_atomic_load_ex_16(volatile uint16_t *addr, int memorder) +{ + uint16_t tmp; + assert((memorder == __ATOMIC_ACQUIRE) + || (memorder == __ATOMIC_RELAXED)); + if (memorder == __ATOMIC_ACQUIRE) + asm volatile("ldaxrh %w[tmp], [%x[addr]]" + : [tmp] "=&r" (tmp) + : [addr] "r"(addr) + : "memory"); + else if (memorder == __ATOMIC_RELAXED) + asm volatile("ldxrh %w[tmp], [%x[addr]]" + : [tmp] "=&r" (tmp) + : [addr] "r"(addr) + : "memory"); + return tmp; +} + +static __rte_always_inline uint32_t +rte_atomic_load_ex_32(volatile uint32_t *addr, int memorder) +{ + uint32_t tmp; + assert((memorder == __ATOMIC_ACQUIRE) + || (memorder == __ATOMIC_RELAXED)); + if (memorder == __ATOMIC_ACQUIRE) + asm volatile("ldaxr %w[tmp], [%x[addr]]" + : [tmp] "=&r" (tmp) + : [addr] "r"(addr) + : "memory"); + else if (memorder == __ATOMIC_RELAXED) + asm volatile("ldxr %w[tmp], [%x[addr]]" + : [tmp] "=&r" (tmp) + : [addr] "r"(addr) + : "memory"); + return tmp; +} + +static __rte_always_inline uint64_t +rte_atomic_load_ex_64(volatile uint64_t *addr, int memorder) +{ + uint64_t tmp; + assert((memorder == __ATOMIC_ACQUIRE) + || (memorder == __ATOMIC_RELAXED)); + if (memorder == __ATOMIC_ACQUIRE) + asm volatile("ldaxr %x[tmp], [%x[addr]]" + : [tmp] "=&r" (tmp) + : [addr] "r"(addr) + : "memory"); + else if (memorder == __ATOMIC_RELAXED) + asm volatile("ldxr %x[tmp], [%x[addr]]" + : [tmp] "=&r" (tmp) + : [addr] "r"(addr) + : "memory"); + return tmp; +} + +#ifdef RTE_WAIT_UNTIL_EQUAL_ARCH_DEFINED +static __rte_always_inline void +rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, +int memorder) +{ + if (__atomic_load_n(addr, memorder) != expected) { + rte_sevl(); + do { + rte_wfe(); + } while (rte_atomic_load_ex_16(addr, memorder) != expected); + } +} + +static __rte_always_inline void +rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected, +int memorder) +{ + if (__atomic_load_n(addr, memorder) != expected) { + rte_sevl(); + do { + rte_wfe(); + } while (__atomic_load_n(addr, memorder) != expected); + } +} + +static __rte_always_inline void +rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, +int memorder) +{ + if (__atomic_load_n(addr, memorder) != expected) { + rte_sevl(); + do { + rte_wfe(); + } while (__atomic_load_n(addr, memorder) != expected); + } +} +#endif + #ifdef __cplusplus } #endif diff --git a/lib/librte_eal/common/include/generic/rte_pause.h b/lib/librte_eal/common/include/generic/rte_pause.h index 52bd4db..9d42e32 100644 --- a/lib/librte_eal/common/include/generic/rte_pause.h +++ b/lib/librte_eal/common/include/generic/rte_pause.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2017 Cavium, Inc + * Copyright(c) 2019 Arm Limited */ #ifndef _RTE_PAUSE_H_ @@ -12,6 +13,12 @@ * */ +#include +#include +#include +#include +#include + /** * Pause CPU execution for a short while * @@ -20,4 +27,96 @@ */ static inline void rte_pause(void); +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Wait for *addr to be updated with a 16-bit expected value, with a relaxed + * memory ordering model meaning the loads around this API can be reordered. + * + * @param addr + * A pointer to the memory location. + * @param expected + * A 16-bit expected value to be in the memory location. + * @param memorder + * Two different memory orders that can be specified: + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to + * C++11 memory orders with the same names, see the C++11 standard or + * the GCC wiki on atomic synchronization for detailed definition. + */ +__rte_experimental +static __rte_always_inline void +rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, +int memorder); + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Wait for *addr to be updated with a 32-bit expected value, with a relaxed + * memory ordering model meaning the loads around this API can be reordered. + * + * @param addr + * A pointer to the memory location. + * @param expected + * A 32-bit expected value to be in the memory location. + * @param memorder + * Two different memory orders that can be specified: + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to + * C++11 memory orders with the same names, see the C++11 standard or + * the GCC wiki on atomic synchronization for detailed definition. + */ +__rte_experimental +static __rte_always_inline void +rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected, +int memorder); + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Wait for *addr to be updated with a 64-bit expected value, with a relaxed + * memory ordering model meaning the loads around this API can be reordered. + * + * @param addr + * A pointer to the memory location. + * @param expected + * A 64-bit expected value to be in the memory location. + * @param memorder + * Two different memory orders that can be specified: + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to + * C++11 memory orders with the same names, see the C++11 standard or + * the GCC wiki on atomic synchronization for detailed definition. + */ +__rte_experimental +static __rte_always_inline void +rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, +int memorder); + +#ifndef RTE_WAIT_UNTIL_EQUAL_ARCH_DEFINED +static __rte_always_inline void +rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, +int memorder) +{ + while (__atomic_load_n(addr, memorder) != expected) + rte_pause(); +} + +static __rte_always_inline void +rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected, +int memorder) +{ + while (__atomic_load_n(addr, memorder) != expected) + rte_pause(); +} + +static __rte_always_inline void +rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, +int memorder) +{ + while (__atomic_load_n(addr, memorder) != expected) + rte_pause(); +} +#endif + #endif /* _RTE_PAUSE_H_ */ From patchwork Sun Oct 27 12:52:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 62061 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AF4421BF48; Sun, 27 Oct 2019 13:53:10 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id BEACA1BF40 for ; Sun, 27 Oct 2019 13:53:08 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 50170337; Sun, 27 Oct 2019 05:53:08 -0700 (PDT) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0827B3F71F; Sun, 27 Oct 2019 05:53:04 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, konstantin.ananyev@intel.com, thomas@monjalon.net, stephen@networkplumber.org, hemant.agrawal@nxp.com, jerinj@marvell.com, pbhagavatula@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, steve.capper@arm.com Date: Sun, 27 Oct 2019 20:52:43 +0800 Message-Id: <1572180765-49767-4-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572180765-49767-1-git-send-email-gavin.hu@arm.com> References: <1572180765-49767-1-git-send-email-gavin.hu@arm.com> In-Reply-To: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH v11 3/5] ticketlock: use new API to reduce contention on aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" While using ticket lock, cores repeatedly poll the lock variable. This is replaced by rte_wait_until_equal API. Running ticketlock_autotest on ThunderX2, Ampere eMAG80, and Arm N1SDP[1], there were variances between runs, but no notable performance gain or degradation were seen with and without this patch. [1] https://community.arm.com/developer/tools-software/oss-platforms/w/\ docs/440/neoverse-n1-sdp Signed-off-by: Gavin Hu Reviewed-by: Honnappa Nagarahalli Tested-by: Phil Yang Tested-by: Pavan Nikhilesh Reviewed-by: Jerin Jacob --- lib/librte_eal/common/include/generic/rte_ticketlock.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/lib/librte_eal/common/include/generic/rte_ticketlock.h b/lib/librte_eal/common/include/generic/rte_ticketlock.h index d9bec87..c295ae7 100644 --- a/lib/librte_eal/common/include/generic/rte_ticketlock.h +++ b/lib/librte_eal/common/include/generic/rte_ticketlock.h @@ -66,8 +66,7 @@ static inline void rte_ticketlock_lock(rte_ticketlock_t *tl) { uint16_t me = __atomic_fetch_add(&tl->s.next, 1, __ATOMIC_RELAXED); - while (__atomic_load_n(&tl->s.current, __ATOMIC_ACQUIRE) != me) - rte_pause(); + rte_wait_until_equal_16(&tl->s.current, me, __ATOMIC_ACQUIRE); } /** From patchwork Sun Oct 27 12:52:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 62062 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 72E301BF4F; Sun, 27 Oct 2019 13:53:14 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 8DCF91BF4E for ; Sun, 27 Oct 2019 13:53:12 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0E7BC1F1; Sun, 27 Oct 2019 05:53:12 -0700 (PDT) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BA5F73F71F; Sun, 27 Oct 2019 05:53:08 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, konstantin.ananyev@intel.com, thomas@monjalon.net, stephen@networkplumber.org, hemant.agrawal@nxp.com, jerinj@marvell.com, pbhagavatula@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, steve.capper@arm.com Date: Sun, 27 Oct 2019 20:52:44 +0800 Message-Id: <1572180765-49767-5-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572180765-49767-1-git-send-email-gavin.hu@arm.com> References: <1572180765-49767-1-git-send-email-gavin.hu@arm.com> In-Reply-To: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH v11 4/5] net/thunderx: use new API to save cycles on aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Use the new API to wait in low power state instead of continuous polling to save CPU cycles and power. Signed-off-by: Gavin Hu Reviewed-by: Ruifeng Wang Acked-by: Jerin Jacob --- drivers/net/thunderx/Makefile | 1 + drivers/net/thunderx/meson.build | 1 + drivers/net/thunderx/nicvf_rxtx.c | 3 +-- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/thunderx/Makefile b/drivers/net/thunderx/Makefile index e6bf497..9e0de10 100644 --- a/drivers/net/thunderx/Makefile +++ b/drivers/net/thunderx/Makefile @@ -10,6 +10,7 @@ include $(RTE_SDK)/mk/rte.vars.mk LIB = librte_pmd_thunderx_nicvf.a CFLAGS += $(WERROR_FLAGS) +CFLAGS += -DALLOW_EXPERIMENTAL_API LDLIBS += -lm LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring diff --git a/drivers/net/thunderx/meson.build b/drivers/net/thunderx/meson.build index 69819a9..23d9458 100644 --- a/drivers/net/thunderx/meson.build +++ b/drivers/net/thunderx/meson.build @@ -4,6 +4,7 @@ subdir('base') objs = [base_objs] +allow_experimental_apis = true sources = files('nicvf_rxtx.c', 'nicvf_ethdev.c', 'nicvf_svf.c' diff --git a/drivers/net/thunderx/nicvf_rxtx.c b/drivers/net/thunderx/nicvf_rxtx.c index 1c42874..90a6098 100644 --- a/drivers/net/thunderx/nicvf_rxtx.c +++ b/drivers/net/thunderx/nicvf_rxtx.c @@ -385,8 +385,7 @@ nicvf_fill_rbdr(struct nicvf_rxq *rxq, int to_fill) ltail++; } - while (__atomic_load_n(&rbdr->tail, __ATOMIC_RELAXED) != next_tail) - rte_pause(); + rte_wait_until_equal_32(&rbdr->tail, next_tail, __ATOMIC_RELAXED); __atomic_store_n(&rbdr->tail, ltail, __ATOMIC_RELEASE); nicvf_addr_write(door, to_fill); From patchwork Sun Oct 27 12:52:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 62063 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 321141BF5B; Sun, 27 Oct 2019 13:53:17 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 399411BF55 for ; Sun, 27 Oct 2019 13:53:16 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C0F141F1; Sun, 27 Oct 2019 05:53:15 -0700 (PDT) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 78CDE3F71F; Sun, 27 Oct 2019 05:53:12 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, konstantin.ananyev@intel.com, thomas@monjalon.net, stephen@networkplumber.org, hemant.agrawal@nxp.com, jerinj@marvell.com, pbhagavatula@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, steve.capper@arm.com Date: Sun, 27 Oct 2019 20:52:45 +0800 Message-Id: <1572180765-49767-6-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572180765-49767-1-git-send-email-gavin.hu@arm.com> References: <1572180765-49767-1-git-send-email-gavin.hu@arm.com> In-Reply-To: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH v11 5/5] event/opdl: use new API to save cycles on aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Use the new API to wait in low power state instead of continuous polling to save CPU cycles and power. Signed-off-by: Gavin Hu Reviewed-by: Ruifeng Wang Reviewed-by: Jerin Jacob --- drivers/event/opdl/Makefile | 1 + drivers/event/opdl/meson.build | 1 + drivers/event/opdl/opdl_ring.c | 5 ++--- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/event/opdl/Makefile b/drivers/event/opdl/Makefile index bf50a60..72ef07d 100644 --- a/drivers/event/opdl/Makefile +++ b/drivers/event/opdl/Makefile @@ -9,6 +9,7 @@ LIB = librte_pmd_opdl_event.a # build flags CFLAGS += -O3 CFLAGS += $(WERROR_FLAGS) +CFLAGS += -DALLOW_EXPERIMENTAL_API # for older GCC versions, allow us to initialize an event using # designated initializers. ifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y) diff --git a/drivers/event/opdl/meson.build b/drivers/event/opdl/meson.build index 1fe034e..e67b164 100644 --- a/drivers/event/opdl/meson.build +++ b/drivers/event/opdl/meson.build @@ -1,6 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Luca Boccassi +allow_experimental_apis = true sources = files( 'opdl_evdev.c', 'opdl_evdev_init.c', diff --git a/drivers/event/opdl/opdl_ring.c b/drivers/event/opdl/opdl_ring.c index 06fb5b3..c8d19fe 100644 --- a/drivers/event/opdl/opdl_ring.c +++ b/drivers/event/opdl/opdl_ring.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "opdl_ring.h" #include "opdl_log.h" @@ -474,9 +475,7 @@ opdl_ring_input_multithread(struct opdl_ring *t, const void *entries, /* If another thread started inputting before this one, but hasn't * finished, we need to wait for it to complete to update the tail. */ - while (unlikely(__atomic_load_n(&s->shared.tail, __ATOMIC_ACQUIRE) != - old_head)) - rte_pause(); + rte_wait_until_equal_32(&s->shared.tail, old_head, __ATOMIC_ACQUIRE); __atomic_store_n(&s->shared.tail, old_head + num_entries, __ATOMIC_RELEASE);