From patchwork Sun Oct 20 05:20:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasesh Mody X-Patchwork-Id: 61482 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2542B1BF1F; Sun, 20 Oct 2019 07:21:01 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 2084E1BF1D for ; Sun, 20 Oct 2019 07:21:00 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9K5Kj3k015824; Sat, 19 Oct 2019 22:20:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0818; bh=TvF4r5ZjOaCAPN9Phf+TU/o88ql4jFczlWlgwToHhKY=; b=wgCNyzIVDt9O1JWckbsFIyW1wtzUczC8UjOOgEhqhG5S6bHIV3BmlNOpo2oeDf/aMd9D my1fWBHfyjnTRfvOXW/HFoD9p0mOe1Np2//Sa7k8rIg5L2mVBGOfjSKX9F6OPo1gX1rn idt5A+2HM2AeJwy94M4GazXcvh0qZnGNJdUNox21iSeTy+WQfarlexy60BecHhq6rNWl GHKB5GOj9lk7o+COeTsxB8yUPD/qaRUJ+jpEc3Kh5JRxaP4Bl2S+lh+jmhYu2mGBQd7O KUdbZ6M+wMcyL0vXjyBsc+a4d+/GA/G4fQIlhQZGR1PnNoROj6P6z1Y185Bi0b+iyFC3 rQ== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2vr20mhvqf-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 19 Oct 2019 22:20:58 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 19 Oct 2019 22:20:57 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 19 Oct 2019 22:20:56 -0700 Received: from irv1user08.caveonetworks.com (unknown [10.104.116.105]) by maili.marvell.com (Postfix) with ESMTP id CBF663F703F; Sat, 19 Oct 2019 22:20:56 -0700 (PDT) Received: (from rmody@localhost) by irv1user08.caveonetworks.com (8.14.4/8.14.4/Submit) id x9K5KtNm009960; Sat, 19 Oct 2019 22:20:56 -0700 X-Authentication-Warning: irv1user08.caveonetworks.com: rmody set sender to rmody@marvell.com using -f From: Rasesh Mody To: , , CC: Rasesh Mody , Date: Sat, 19 Oct 2019 22:20:49 -0700 Message-ID: <20191020052051.9905-1-rmody@marvell.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-20_02:2019-10-18,2019-10-20 signatures=0 Subject: [dpdk-dev] [PATCH 1/3] net/qede/base: fix for FW bug X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In our testing we have identified a critical FW bug. Performance is degraded significantly for certain packet sizes with 8.40.25.0 FW. This patch updates the FW to version 8.40.33.0. The updated FW has a fix to performance issue. The patch also adds initialization for FW overlay RAM as part of hardware initialization which is required by the new FW. Fixes: 066f0d380a2f ("net/qede/base: update FW to 8.40.25.0") Signed-off-by: Rasesh Mody --- doc/guides/nics/qede.rst | 4 +- drivers/net/qede/base/common_hsi.h | 6 +- drivers/net/qede/base/ecore.h | 4 +- drivers/net/qede/base/ecore_dev.c | 19 ++- drivers/net/qede/base/ecore_hsi_debug_tools.h | 3 + drivers/net/qede/base/ecore_hw.c | 4 +- drivers/net/qede/base/ecore_init_fw_funcs.c | 138 ++++++++++++++++++ drivers/net/qede/base/ecore_init_fw_funcs.h | 35 +++++ drivers/net/qede/base/ecore_int.c | 14 +- drivers/net/qede/base/ecore_iro_values.h | 122 ++++++++-------- drivers/net/qede/qede_ethdev.h | 2 +- drivers/net/qede/qede_main.c | 2 +- 12 files changed, 274 insertions(+), 79 deletions(-) diff --git a/doc/guides/nics/qede.rst b/doc/guides/nics/qede.rst index 471d98014..2f4045795 100644 --- a/doc/guides/nics/qede.rst +++ b/doc/guides/nics/qede.rst @@ -78,9 +78,9 @@ Supported QLogic Adapters Prerequisites ------------- -- Requires storm firmware version **8.37.7.0**. Firmware may be available +- Requires storm firmware version **8.40.33.0**. Firmware may be available inbox in certain newer Linux distros under the standard directory - ``E.g. /lib/firmware/qed/qed_init_values-8.37.7.0.bin``. + ``E.g. /lib/firmware/qed/qed_init_values-8.40.33.0.bin``. If the required firmware files are not available then download it from `linux-firmware git repository `_ or `QLogic Driver Download Center `_. diff --git a/drivers/net/qede/base/common_hsi.h b/drivers/net/qede/base/common_hsi.h index 74afed1ec..e230fe5ac 100644 --- a/drivers/net/qede/base/common_hsi.h +++ b/drivers/net/qede/base/common_hsi.h @@ -92,10 +92,10 @@ /****************************************************************************/ -#define FW_MAJOR_VERSION 8 +#define FW_MAJOR_VERSION 8 #define FW_MINOR_VERSION 40 -#define FW_REVISION_VERSION 25 -#define FW_ENGINEERING_VERSION 0 +#define FW_REVISION_VERSION 33 +#define FW_ENGINEERING_VERSION 0 /***********************/ /* COMMON HW CONSTANTS */ diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h index 925b75cb9..b2077bc46 100644 --- a/drivers/net/qede/base/ecore.h +++ b/drivers/net/qede/base/ecore.h @@ -29,7 +29,7 @@ #define ECORE_MAJOR_VERSION 8 #define ECORE_MINOR_VERSION 40 -#define ECORE_REVISION_VERSION 18 +#define ECORE_REVISION_VERSION 26 #define ECORE_ENGINEERING_VERSION 0 #define ECORE_VERSION \ @@ -699,6 +699,8 @@ struct ecore_hwfn { */ bool b_en_pacing; + struct phys_mem_desc *fw_overlay_mem; + /* @DPDK */ struct ecore_ptt *p_arfs_ptt; }; diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index 2c47aba48..9d1db1459 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -1653,6 +1653,7 @@ void ecore_resc_free(struct ecore_dev *p_dev) ecore_dmae_info_free(p_hwfn); ecore_dcbx_info_free(p_hwfn); ecore_dbg_user_data_free(p_hwfn); + ecore_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem); /* @@@TBD Flush work-queue ? */ /* destroy doorbell recovery mechanism */ @@ -3467,6 +3468,8 @@ ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, if (rc) return rc; + ecore_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem); + /* Pure runtime initializations - directly to the HW */ ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); @@ -3494,7 +3497,7 @@ ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, if (IS_LEAD_HWFN(p_hwfn)) { rc = ecore_llh_hw_init_pf(p_hwfn, p_ptt, p_params->avoid_eng_affin); - if (rc) + if (rc != ECORE_SUCCESS) return rc; } @@ -3510,7 +3513,6 @@ ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, if (rc) { DP_NOTICE(p_hwfn, true, "Function start ramrod failed\n"); - } else { return rc; } prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1); @@ -3677,6 +3679,8 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, u32 load_code, resp, param, drv_mb_param; bool b_default_mtu = true; struct ecore_hwfn *p_hwfn; + const u32 *fw_overlays; + u32 fw_overlays_len; enum _ecore_status_t rc = ECORE_SUCCESS; u16 ether_type; int i; @@ -3815,6 +3819,17 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, */ ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); + fw_overlays = p_dev->fw_data->fw_overlays; + fw_overlays_len = p_dev->fw_data->fw_overlays_len; + p_hwfn->fw_overlay_mem = + ecore_fw_overlay_mem_alloc(p_hwfn, fw_overlays, + fw_overlays_len); + if (!p_hwfn->fw_overlay_mem) { + DP_NOTICE(p_hwfn, false, + "Failed to allocate fw overlay memory\n"); + goto load_err; + } + switch (load_code) { case FW_MSG_CODE_DRV_LOAD_ENGINE: rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, diff --git a/drivers/net/qede/base/ecore_hsi_debug_tools.h b/drivers/net/qede/base/ecore_hsi_debug_tools.h index a959aeea7..eb72e93cf 100644 --- a/drivers/net/qede/base/ecore_hsi_debug_tools.h +++ b/drivers/net/qede/base/ecore_hsi_debug_tools.h @@ -917,6 +917,9 @@ enum dbg_grc_params { DBG_GRC_PARAM_NO_FW_VER /* dont read FW/MFW version (0/1) */, DBG_GRC_PARAM_RESERVED3 /* reserved */, DBG_GRC_PARAM_DUMP_MCP_HW_DUMP /* dump MCP HW Dump (0/1) */, + DBG_GRC_PARAM_DUMP_ILT_CDUC /* dump ILT CDUC client (0/1) */, + DBG_GRC_PARAM_DUMP_ILT_CDUT /* dump ILT CDUT client (0/1) */, + DBG_GRC_PARAM_DUMP_CAU_EXT /* dump CAU extended memories (0/1) */, MAX_DBG_GRC_PARAMS }; diff --git a/drivers/net/qede/base/ecore_hw.c b/drivers/net/qede/base/ecore_hw.c index 0aed043bb..1db39d6a3 100644 --- a/drivers/net/qede/base/ecore_hw.c +++ b/drivers/net/qede/base/ecore_hw.c @@ -712,7 +712,7 @@ static enum _ecore_status_t ecore_dmae_operation_wait(struct ecore_hwfn *p_hwfn) while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) { OSAL_UDELAY(DMAE_MIN_WAIT_TIME); if (++wait_cnt > wait_cnt_limit) { - DP_NOTICE(p_hwfn->p_dev, ECORE_MSG_HW, + DP_NOTICE(p_hwfn->p_dev, false, "Timed-out waiting for operation to" " complete. Completion word is 0x%08x" " expected 0x%08x.\n", @@ -805,7 +805,7 @@ ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn, length_dw * sizeof(u32), true); if (ecore_status != ECORE_SUCCESS) { - DP_NOTICE(p_hwfn, ECORE_MSG_HW, + DP_NOTICE(p_hwfn, false, "Wait Failed. source_addr 0x%lx, grc_addr 0x%lx, size_in_dwords 0x%x, intermediate buffer 0x%lx.\n", (unsigned long)src_addr, (unsigned long)dst_addr, length_dw, diff --git a/drivers/net/qede/base/ecore_init_fw_funcs.c b/drivers/net/qede/base/ecore_init_fw_funcs.c index fa1e89a86..6a52f32cc 100644 --- a/drivers/net/qede/base/ecore_init_fw_funcs.c +++ b/drivers/net/qede/base/ecore_init_fw_funcs.c @@ -2058,3 +2058,141 @@ void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn, ctx_validation = CDU_CONTEXT_VALIDATION_DEFAULT_CFG << 8; ecore_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation); } + +#define PHYS_ADDR_DWORDS DIV_ROUND_UP(sizeof(dma_addr_t), 4) +#define OVERLAY_HDR_SIZE_DWORDS (sizeof(struct fw_overlay_buf_hdr) / 4) + +static u32 ecore_get_overlay_addr_ram_addr(struct ecore_hwfn *p_hwfn, + u8 storm_id) +{ + switch (storm_id) { + case 0: return TSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + TSTORM_OVERLAY_BUF_ADDR_OFFSET; + case 1: return MSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + MSTORM_OVERLAY_BUF_ADDR_OFFSET; + case 2: return USEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + USTORM_OVERLAY_BUF_ADDR_OFFSET; + case 3: return XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + XSTORM_OVERLAY_BUF_ADDR_OFFSET; + case 4: return YSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + YSTORM_OVERLAY_BUF_ADDR_OFFSET; + case 5: return PSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + PSTORM_OVERLAY_BUF_ADDR_OFFSET; + + default: return 0; + } +} + +struct phys_mem_desc *ecore_fw_overlay_mem_alloc(struct ecore_hwfn *p_hwfn, + const u32 *const fw_overlay_in_buf, + u32 buf_size_in_bytes) +{ + u32 buf_size = buf_size_in_bytes / sizeof(u32), buf_offset = 0; + struct phys_mem_desc *allocated_mem; + + if (!buf_size) + return OSAL_NULL; + + allocated_mem = (struct phys_mem_desc *)OSAL_ZALLOC(p_hwfn->p_dev, + GFP_KERNEL, + NUM_STORMS * + sizeof(struct phys_mem_desc)); + if (!allocated_mem) + return OSAL_NULL; + + OSAL_MEMSET(allocated_mem, 0, NUM_STORMS * + sizeof(struct phys_mem_desc)); + + /* For each Storm, set physical address in RAM */ + while (buf_offset < buf_size) { + struct phys_mem_desc *storm_mem_desc; + struct fw_overlay_buf_hdr *hdr; + u32 storm_buf_size; + u8 storm_id; + + hdr = + (struct fw_overlay_buf_hdr *)&fw_overlay_in_buf[buf_offset]; + storm_buf_size = GET_FIELD(hdr->data, + FW_OVERLAY_BUF_HDR_BUF_SIZE); + storm_id = GET_FIELD(hdr->data, FW_OVERLAY_BUF_HDR_STORM_ID); + storm_mem_desc = allocated_mem + storm_id; + storm_mem_desc->size = storm_buf_size * sizeof(u32); + + /* Allocate physical memory for Storm's overlays buffer */ + storm_mem_desc->virt_addr = + OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, + &storm_mem_desc->phys_addr, + storm_mem_desc->size); + if (!storm_mem_desc->virt_addr) + break; + + /* Skip overlays buffer header */ + buf_offset += OVERLAY_HDR_SIZE_DWORDS; + + /* Copy Storm's overlays buffer to allocated memory */ + OSAL_MEMCPY(storm_mem_desc->virt_addr, + &fw_overlay_in_buf[buf_offset], + storm_mem_desc->size); + + /* Advance to next Storm */ + buf_offset += storm_buf_size; + } + + /* If memory allocation has failed, free all allocated memory */ + if (buf_offset < buf_size) { + ecore_fw_overlay_mem_free(p_hwfn, allocated_mem); + return OSAL_NULL; + } + + return allocated_mem; +} + +void ecore_fw_overlay_init_ram(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + struct phys_mem_desc *fw_overlay_mem) +{ + u8 storm_id; + + for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) { + struct phys_mem_desc *storm_mem_desc = + (struct phys_mem_desc *)fw_overlay_mem + storm_id; + u32 ram_addr, i; + + /* Skip Storms with no FW overlays */ + if (!storm_mem_desc->virt_addr) + continue; + + /* Calculate overlay RAM GRC address of current PF */ + ram_addr = ecore_get_overlay_addr_ram_addr(p_hwfn, storm_id) + + sizeof(dma_addr_t) * p_hwfn->rel_pf_id; + + /* Write Storm's overlay physical address to RAM */ + for (i = 0; i < PHYS_ADDR_DWORDS; i++, ram_addr += sizeof(u32)) + ecore_wr(p_hwfn, p_ptt, ram_addr, + ((u32 *)&storm_mem_desc->phys_addr)[i]); + } +} + +void ecore_fw_overlay_mem_free(struct ecore_hwfn *p_hwfn, + struct phys_mem_desc *fw_overlay_mem) +{ + u8 storm_id; + + if (!fw_overlay_mem) + return; + + for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) { + struct phys_mem_desc *storm_mem_desc = + (struct phys_mem_desc *)fw_overlay_mem + storm_id; + + /* Free Storm's physical memory */ + if (storm_mem_desc->virt_addr) + OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, + storm_mem_desc->virt_addr, + storm_mem_desc->phys_addr, + storm_mem_desc->size); + } + + /* Free allocated virtual memory */ + OSAL_FREE(p_hwfn->p_dev, fw_overlay_mem); +} diff --git a/drivers/net/qede/base/ecore_init_fw_funcs.h b/drivers/net/qede/base/ecore_init_fw_funcs.h index 1d1b107c4..912451662 100644 --- a/drivers/net/qede/base/ecore_init_fw_funcs.h +++ b/drivers/net/qede/base/ecore_init_fw_funcs.h @@ -553,5 +553,40 @@ void ecore_set_rdma_error_level(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u8 assert_level[NUM_STORMS]); +/** + * @brief ecore_fw_overlay_mem_alloc - Allocates and fills the FW overlay memory + * + * @param p_hwfn - HW device data + * @param fw_overlay_in_buf - the input FW overlay buffer. + * @param buf_size - the size of the input FW overlay buffer in bytes. + * must be aligned to dwords. + * @param fw_overlay_out_mem - OUT: a pointer to the allocated overlays memory. + * + * @return a pointer to the allocated overlays memory, or OSAL_NULL in case of + * failures. + */ +struct phys_mem_desc *ecore_fw_overlay_mem_alloc(struct ecore_hwfn *p_hwfn, + const u32 *const fw_overlay_in_buf, + u32 buf_size_in_bytes); + +/** + * @brief ecore_fw_overlay_init_ram - Initializes the FW overlay RAM. + * + * @param p_hwfn - HW device data. + * @param p_ptt - ptt window used for writing the registers. + * @param fw_overlay_mem - the allocated FW overlay memory. + */ +void ecore_fw_overlay_init_ram(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + struct phys_mem_desc *fw_overlay_mem); + +/** + * @brief ecore_fw_overlay_mem_free - Frees the FW overlay memory. + * + * @param p_hwfn - HW device data. + * @param fw_overlay_mem - the allocated FW overlay memory to free. + */ +void ecore_fw_overlay_mem_free(struct ecore_hwfn *p_hwfn, + struct phys_mem_desc *fw_overlay_mem); #endif diff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c index b1e127849..4207b1853 100644 --- a/drivers/net/qede/base/ecore_int.c +++ b/drivers/net/qede/base/ecore_int.c @@ -192,7 +192,10 @@ static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn) return ECORE_SUCCESS; } -#define ECORE_GRC_ATTENTION_VALID_BIT (1 << 0) +/* Register GRC_REG_TIMEOUT_ATTN_ACCESS_VALID */ +#define ECORE_GRC_ATTENTION_VALID_BIT_MASK (0x1) +#define ECORE_GRC_ATTENTION_VALID_BIT_SHIFT (0) + #define ECORE_GRC_ATTENTION_ADDRESS_MASK (0x7fffff << 0) #define ECORE_GRC_ATTENTION_RDWR_BIT (1 << 23) #define ECORE_GRC_ATTENTION_MASTER_MASK (0xf << 24) @@ -237,15 +240,14 @@ static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn) u32 tmp, tmp2; /* We've already cleared the timeout interrupt register, so we learn - * of interrupts via the validity register. - * Any attention which is not for a timeout event is treated as fatal. + * of interrupts via the validity register. If it is not a timeout do + * nothing. It is too late at this stage to differentiate spurious + * interrupt from fatal grc attention. */ tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); - if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT)) { - rc = ECORE_INVAL; + if (!(GET_FIELD(tmp, ECORE_GRC_ATTENTION_VALID_BIT))) goto out; - } /* Read the GRC timeout information */ tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, diff --git a/drivers/net/qede/base/ecore_iro_values.h b/drivers/net/qede/base/ecore_iro_values.h index 6442057ac..dd7349778 100644 --- a/drivers/net/qede/base/ecore_iro_values.h +++ b/drivers/net/qede/base/ecore_iro_values.h @@ -17,8 +17,8 @@ static const u32 iro_arr[] = { /* offset=0x0, size=0x8 */ 0x00000000, 0x00000000, 0x00080000, /* TSTORM_PORT_STAT_OFFSET(port_id), */ - /* offset=0x3908, mult1=0x88, size=0x88 */ - 0x00003908, 0x00000088, 0x00880000, + /* offset=0x3288, mult1=0x88, size=0x88 */ + 0x00003288, 0x00000088, 0x00880000, /* TSTORM_LL2_PORT_STAT_OFFSET(port_id), */ /* offset=0x58f0, mult1=0x20, size=0x20 */ 0x000058f0, 0x00000020, 0x00200000, @@ -38,38 +38,38 @@ static const u32 iro_arr[] = { /* offset=0x84, mult1=0x8, size=0x2 */ 0x00000084, 0x00000008, 0x00020000, /* XSTORM_PQ_INFO_OFFSET(pq_id), */ - /* offset=0x5618, mult1=0x4, size=0x4 */ - 0x00005618, 0x00000004, 0x00040000, - /* XSTORM_INTEG_TEST_DATA_OFFSET */ - /* offset=0x4cd0, size=0x78 */ - 0x00004cd0, 0x00000000, 0x00780000, + /* offset=0x5718, mult1=0x4, size=0x4 */ + 0x00005718, 0x00000004, 0x00040000, + /* XSTORM_INTEG_TEST_DATA_OFFSET, */ + /* offset=0x4dd0, size=0x78 */ + 0x00004dd0, 0x00000000, 0x00780000, /* YSTORM_INTEG_TEST_DATA_OFFSET */ /* offset=0x3e40, size=0x78 */ 0x00003e40, 0x00000000, 0x00780000, - /* PSTORM_INTEG_TEST_DATA_OFFSET */ - /* offset=0x3e00, size=0x78 */ - 0x00003e00, 0x00000000, 0x00780000, - /* TSTORM_INTEG_TEST_DATA_OFFSET */ - /* offset=0x3890, size=0x78 */ - 0x00003890, 0x00000000, 0x00780000, + /* PSTORM_INTEG_TEST_DATA_OFFSET, */ + /* offset=0x4480, size=0x78 */ + 0x00004480, 0x00000000, 0x00780000, + /* TSTORM_INTEG_TEST_DATA_OFFSET, */ + /* offset=0x3210, size=0x78 */ + 0x00003210, 0x00000000, 0x00780000, /* MSTORM_INTEG_TEST_DATA_OFFSET */ /* offset=0x3b50, size=0x78 */ 0x00003b50, 0x00000000, 0x00780000, /* USTORM_INTEG_TEST_DATA_OFFSET */ /* offset=0x7f58, size=0x78 */ 0x00007f58, 0x00000000, 0x00780000, - /* XSTORM_OVERLAY_BUF_ADDR_OFFSET */ - /* offset=0x5e58, size=0x8 */ - 0x00005e58, 0x00000000, 0x00080000, + /* XSTORM_OVERLAY_BUF_ADDR_OFFSET, */ + /* offset=0x5f58, size=0x8 */ + 0x00005f58, 0x00000000, 0x00080000, /* YSTORM_OVERLAY_BUF_ADDR_OFFSET */ /* offset=0x7100, size=0x8 */ 0x00007100, 0x00000000, 0x00080000, - /* PSTORM_OVERLAY_BUF_ADDR_OFFSET */ - /* offset=0xa820, size=0x8 */ - 0x0000a820, 0x00000000, 0x00080000, - /* TSTORM_OVERLAY_BUF_ADDR_OFFSET */ - /* offset=0x4a18, size=0x8 */ - 0x00004a18, 0x00000000, 0x00080000, + /* PSTORM_OVERLAY_BUF_ADDR_OFFSET, */ + /* offset=0xaea0, size=0x8 */ + 0x0000aea0, 0x00000000, 0x00080000, + /* TSTORM_OVERLAY_BUF_ADDR_OFFSET, */ + /* offset=0x4398, size=0x8 */ + 0x00004398, 0x00000000, 0x00080000, /* MSTORM_OVERLAY_BUF_ADDR_OFFSET */ /* offset=0xa5a0, size=0x8 */ 0x0000a5a0, 0x00000000, 0x00080000, @@ -86,8 +86,8 @@ static const u32 iro_arr[] = { /* offset=0xc210, mult1=0x30, size=0x30 */ 0x0000c210, 0x00000030, 0x00300000, /* CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id), */ - /* offset=0xaa08, mult1=0x38, size=0x38 */ - 0x0000aa08, 0x00000038, 0x00380000, + /* offset=0xb088, mult1=0x38, size=0x38 */ + 0x0000b088, 0x00000038, 0x00380000, /* MSTORM_QUEUE_STAT_OFFSET(stat_counter_id), */ /* offset=0x3d20, mult1=0x80, size=0x40 */ 0x00003d20, 0x00000080, 0x00400000, @@ -110,20 +110,20 @@ static const u32 iro_arr[] = { /* offset=0xe840, mult1=0x60, size=0x60 */ 0x0000e840, 0x00000060, 0x00600000, /* PSTORM_QUEUE_STAT_OFFSET(stat_counter_id), */ - /* offset=0x3f98, mult1=0x80, size=0x38 */ - 0x00003f98, 0x00000080, 0x00380000, + /* offset=0x4618, mult1=0x80, size=0x38 */ + 0x00004618, 0x00000080, 0x00380000, /* PSTORM_ETH_PF_STAT_OFFSET(pf_id), */ - /* offset=0x100b8, mult1=0xc0, size=0xc0 */ - 0x000100b8, 0x000000c0, 0x00c00000, + /* offset=0x10738, mult1=0xc0, size=0xc0 */ + 0x00010738, 0x000000c0, 0x00c00000, /* PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethType_id), */ /* offset=0x1f8, mult1=0x2, size=0x2 */ 0x000001f8, 0x00000002, 0x00020000, - /* TSTORM_ETH_PRS_INPUT_OFFSET */ - /* offset=0xa2a0, size=0x108 */ - 0x0000a2a0, 0x00000000, 0x01080000, + /* TSTORM_ETH_PRS_INPUT_OFFSET, */ + /* offset=0xa2a8, size=0x108 */ + 0x0000a2a8, 0x00000000, 0x01080000, /* ETH_RX_RATE_LIMIT_OFFSET(pf_id), */ - /* offset=0xa3a8, mult1=0x8, size=0x8 */ - 0x0000a3a8, 0x00000008, 0x00080000, + /* offset=0xa3b0, mult1=0x8, size=0x8 */ + 0x0000a3b0, 0x00000008, 0x00080000, /* TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id), */ /* offset=0x1c0, mult1=0x8, size=0x8 */ 0x000001c0, 0x00000008, 0x00080000, @@ -149,8 +149,8 @@ static const u32 iro_arr[] = { /* offset=0xb78, mult1=0x18, mult2=0x8, size=0x2 */ 0x00000b78, 0x00080018, 0x00020000, /* TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id), */ - /* offset=0xc640, mult1=0x50, size=0x3c */ - 0x0000c640, 0x00000050, 0x003c0000, + /* offset=0xc648, mult1=0x50, size=0x3c */ + 0x0000c648, 0x00000050, 0x003c0000, /* MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id), */ /* offset=0x12038, mult1=0x18, size=0x10 */ 0x00012038, 0x00000018, 0x00100000, @@ -158,38 +158,38 @@ static const u32 iro_arr[] = { /* offset=0x11b00, mult1=0x40, size=0x18 */ 0x00011b00, 0x00000040, 0x00180000, /* XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id), */ - /* offset=0x94d0, mult1=0x50, size=0x20 */ - 0x000094d0, 0x00000050, 0x00200000, + /* offset=0x95d0, mult1=0x50, size=0x20 */ + 0x000095d0, 0x00000050, 0x00200000, /* YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id), */ /* offset=0x8b10, mult1=0x40, size=0x28 */ 0x00008b10, 0x00000040, 0x00280000, /* PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id), */ - /* offset=0x10fc0, mult1=0x18, size=0x10 */ - 0x00010fc0, 0x00000018, 0x00100000, + /* offset=0x11640, mult1=0x18, size=0x10 */ + 0x00011640, 0x00000018, 0x00100000, /* TSTORM_FCOE_RX_STATS_OFFSET(pf_id), */ - /* offset=0xc828, mult1=0x48, size=0x38 */ - 0x0000c828, 0x00000048, 0x00380000, + /* offset=0xc830, mult1=0x48, size=0x38 */ + 0x0000c830, 0x00000048, 0x00380000, /* PSTORM_FCOE_TX_STATS_OFFSET(pf_id), */ - /* offset=0x11090, mult1=0x20, size=0x20 */ - 0x00011090, 0x00000020, 0x00200000, + /* offset=0x11710, mult1=0x20, size=0x20 */ + 0x00011710, 0x00000020, 0x00200000, /* PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id), */ - /* offset=0x3fd0, mult1=0x80, size=0x10 */ - 0x00003fd0, 0x00000080, 0x00100000, + /* offset=0x4650, mult1=0x80, size=0x10 */ + 0x00004650, 0x00000080, 0x00100000, /* TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id), */ - /* offset=0x3c98, mult1=0x10, size=0x10 */ - 0x00003c98, 0x00000010, 0x00100000, + /* offset=0x3618, mult1=0x10, size=0x10 */ + 0x00003618, 0x00000010, 0x00100000, /* XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id), */ - /* offset=0xa868, mult1=0x8, size=0x1 */ - 0x0000a868, 0x00000008, 0x00010000, + /* offset=0xa968, mult1=0x8, size=0x1 */ + 0x0000a968, 0x00000008, 0x00010000, /* YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id), */ /* offset=0x97a0, mult1=0x8, size=0x1 */ 0x000097a0, 0x00000008, 0x00010000, /* PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id), */ - /* offset=0x11310, mult1=0x8, size=0x1 */ - 0x00011310, 0x00000008, 0x00010000, + /* offset=0x11990, mult1=0x8, size=0x1 */ + 0x00011990, 0x00000008, 0x00010000, /* TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id), */ - /* offset=0xf018, mult1=0x8, size=0x1 */ - 0x0000f018, 0x00000008, 0x00010000, + /* offset=0xf020, mult1=0x8, size=0x1 */ + 0x0000f020, 0x00000008, 0x00010000, /* MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id), */ /* offset=0x12628, mult1=0x8, size=0x1 */ 0x00012628, 0x00000008, 0x00010000, @@ -197,11 +197,11 @@ static const u32 iro_arr[] = { /* offset=0x11da8, mult1=0x8, size=0x1 */ 0x00011da8, 0x00000008, 0x00010000, /* XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id), */ - /* offset=0xa978, mult1=0x30, size=0x10 */ - 0x0000a978, 0x00000030, 0x00100000, + /* offset=0xaa78, mult1=0x30, size=0x10 */ + 0x0000aa78, 0x00000030, 0x00100000, /* TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id), */ - /* offset=0xd768, mult1=0x28, size=0x28 */ - 0x0000d768, 0x00000028, 0x00280000, + /* offset=0xd770, mult1=0x28, size=0x28 */ + 0x0000d770, 0x00000028, 0x00280000, /* YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id), */ /* offset=0x9a58, mult1=0x18, size=0x18 */ 0x00009a58, 0x00000018, 0x00180000, @@ -209,14 +209,14 @@ static const u32 iro_arr[] = { /* offset=0x9bd8, mult1=0x8, size=0x8 */ 0x00009bd8, 0x00000008, 0x00080000, /* PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id), */ - /* offset=0x13398, mult1=0x8, size=0x8 */ - 0x00013398, 0x00000008, 0x00080000, + /* offset=0x13a18, mult1=0x8, size=0x8 */ + 0x00013a18, 0x00000008, 0x00080000, /* USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id), */ /* offset=0x126e8, mult1=0x18, size=0x18 */ 0x000126e8, 0x00000018, 0x00180000, /* TSTORM_NVMF_PORT_TASKPOOL_PRODUCER_CONSUMER_OFFSET(port_num_id,taskpool_index), */ - /* offset=0xe608, mult1=0x288, mult2=0x50, size=0x10 */ - 0x0000e608, 0x00500288, 0x00100000, + /* offset=0xe610, mult1=0x288, mult2=0x50, size=0x10 */ + 0x0000e610, 0x00500288, 0x00100000, /* USTORM_NVMF_PORT_COUNTERS_OFFSET(port_num_id), */ /* offset=0x12970, mult1=0x138, size=0x28 */ 0x00012970, 0x00000138, 0x00280000, diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.h index 1ac2d086a..21115a077 100644 --- a/drivers/net/qede/qede_ethdev.h +++ b/drivers/net/qede/qede_ethdev.h @@ -46,7 +46,7 @@ #define QEDE_PMD_VER_PREFIX "QEDE PMD" #define QEDE_PMD_VERSION_MAJOR 2 #define QEDE_PMD_VERSION_MINOR 11 -#define QEDE_PMD_VERSION_REVISION 0 +#define QEDE_PMD_VERSION_REVISION 3 #define QEDE_PMD_VERSION_PATCH 1 #define QEDE_PMD_DRV_VERSION qede_stringify(QEDE_PMD_VERSION_MAJOR) "." \ diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c index c9caec645..4eb79d0fb 100644 --- a/drivers/net/qede/qede_main.c +++ b/drivers/net/qede/qede_main.c @@ -18,7 +18,7 @@ char qede_fw_file[PATH_MAX]; static const char * const QEDE_DEFAULT_FIRMWARE = - "/lib/firmware/qed/qed_init_values-8.40.25.0.bin"; + "/lib/firmware/qed/qed_init_values-8.40.33.0.bin"; static void qed_update_pf_params(struct ecore_dev *edev, struct ecore_pf_params *params) From patchwork Sun Oct 20 05:20:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasesh Mody X-Patchwork-Id: 61483 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BBDF31BF42; Sun, 20 Oct 2019 07:21:04 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id D3CFA1BF23; Sun, 20 Oct 2019 07:21:01 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9K5KuKl005336; Sat, 19 Oct 2019 22:21:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=EgnRb2DzOH0Y5GwWajLTJn9wFuTS0rYrbZi3v/yckvc=; b=iIcHbKQbGZKemyulwuOOgM6QnZ+vPE6zq+De6MjmPZmpyliz9pooLx7A7/G/Iw+maRfc Q6V1dwUNqHQR2VO57KuMHd7GaAd0pNqUIxSS1ym2y73SPNt3qgC15SFfZNyTRPdpLHum j77v9Z3a5+/Vlu28nnIgd0/bxr2fHT4wjvUd5mPNBZKcP8eqZvmoseY+q0r5ycBu6NX+ Ts0JFRFxbmsesUOZFasLSXHs1bMyGcYv9a7v19TupeY0iJ0pj14akbmHedfdEBlrmizz wH0Fs1P+vJxP5P8S4SasBDezk4Zh+mcAjsm3k2hyKZ72+Syf0W0QQr/WRFvdCdN5Y79h KQ== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 2vqyuqacnn-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 19 Oct 2019 22:21:00 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 19 Oct 2019 22:20:59 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 19 Oct 2019 22:20:59 -0700 Received: from irv1user08.caveonetworks.com (unknown [10.104.116.105]) by maili.marvell.com (Postfix) with ESMTP id 35CE83F703F; Sat, 19 Oct 2019 22:20:59 -0700 (PDT) Received: (from rmody@localhost) by irv1user08.caveonetworks.com (8.14.4/8.14.4/Submit) id x9K5KxmX009963; Sat, 19 Oct 2019 22:20:59 -0700 X-Authentication-Warning: irv1user08.caveonetworks.com: rmody set sender to rmody@marvell.com using -f From: Rasesh Mody To: , , CC: Shahed Shaikh , , Date: Sat, 19 Oct 2019 22:20:50 -0700 Message-ID: <20191020052051.9905-2-rmody@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191020052051.9905-1-rmody@marvell.com> References: <20191020052051.9905-1-rmody@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-20_02:2019-10-18,2019-10-20 signatures=0 Subject: [dpdk-dev] [PATCH 2/3] net/qede: fix to modify MTU update flow X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shahed Shaikh New MTU value is not propagated to vport in HW when MTU update request is sent while ports are stopped. This patch fixes the logic error for above mentioned condition. Fixes: d121a6b5f781 ("net/qede: fix VF MTU update") Cc: stable@dpdk.org Signed-off-by: Shahed Shaikh Reviewed-by: Rasesh Mody --- drivers/net/qede/qede_ethdev.c | 8 +++++--- drivers/net/qede/qede_ethdev.h | 1 + 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c index 53fdfde9a..42e2b5083 100644 --- a/drivers/net/qede/qede_ethdev.c +++ b/drivers/net/qede/qede_ethdev.c @@ -1038,9 +1038,11 @@ static int qede_dev_start(struct rte_eth_dev *eth_dev) PMD_INIT_FUNC_TRACE(edev); /* Update MTU only if it has changed */ - if (eth_dev->data->mtu != qdev->mtu) { - if (qede_update_mtu(eth_dev, qdev->mtu)) + if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) { + if (qede_update_mtu(eth_dev, qdev->new_mtu)) goto err; + qdev->mtu = qdev->new_mtu; + qdev->new_mtu = 0; } /* Configure TPA parameters */ @@ -2248,7 +2250,7 @@ static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) restart = true; } rte_delay_ms(1000); - qdev->mtu = mtu; + qdev->new_mtu = mtu; /* Fix up RX buf size for all queues of the port */ for (i = 0; i < qdev->num_rx_queues; i++) { diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.h index 21115a077..b988a73f2 100644 --- a/drivers/net/qede/qede_ethdev.h +++ b/drivers/net/qede/qede_ethdev.h @@ -225,6 +225,7 @@ struct qede_dev { struct qede_fastpath *fp_array; struct qede_fastpath_cmt *fp_array_cmt; uint16_t mtu; + uint16_t new_mtu; bool enable_tx_switching; bool rss_enable; struct rte_eth_rss_conf rss_conf; From patchwork Sun Oct 20 05:20:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasesh Mody X-Patchwork-Id: 61484 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 724EF1BF4B; Sun, 20 Oct 2019 07:21:09 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 3CDB11BF24; Sun, 20 Oct 2019 07:21:03 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9K5KmRR015848; Sat, 19 Oct 2019 22:21:02 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=ZrPi68PUdejsRo7wt2uORwlFHcsKaSpcvfQw0SzfFfQ=; b=RFGMKHNQiuGXmaLSeAYxvsWccJA+N4D9Q/iIqX6dtPOezjzp9ctEbAurIP7EUF1TZm/4 YNBAfp5swygJ9rqsE+wm8zWJn1/9MuDE6C3zqt8zFR/D6fj+fPcYyR6n4z0ga1MkpkN7 F8i8nO6BIAyN4IIF4dYj1fhQ5Q1ZJOpt4n5RKVtpfGfrn62XAjK/h+ZhPErQ3+w3yhU8 Fguc65rYB4UHYPFsI79Mx6Y4h2Rhfy62kHs3WTna58j3LzZItb/kcG3KlWjvOUXbwlUv YjClVZx0jBz8cSdANCz5BW2WQV4kyv2FUYP6Z7w4V+Dt3sUzDNYHmj9RbgaEfK7uO4Pw 3w== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2vr20mhvqm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 19 Oct 2019 22:21:02 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 19 Oct 2019 22:21:00 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 19 Oct 2019 22:21:00 -0700 Received: from irv1user08.caveonetworks.com (unknown [10.104.116.105]) by maili.marvell.com (Postfix) with ESMTP id BC7333F7040; Sat, 19 Oct 2019 22:21:00 -0700 (PDT) Received: (from rmody@localhost) by irv1user08.caveonetworks.com (8.14.4/8.14.4/Submit) id x9K5L0sO009966; Sat, 19 Oct 2019 22:21:00 -0700 X-Authentication-Warning: irv1user08.caveonetworks.com: rmody set sender to rmody@marvell.com using -f From: Rasesh Mody To: , , CC: Shahed Shaikh , , Date: Sat, 19 Oct 2019 22:20:51 -0700 Message-ID: <20191020052051.9905-3-rmody@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191020052051.9905-1-rmody@marvell.com> References: <20191020052051.9905-1-rmody@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-20_02:2019-10-18,2019-10-20 signatures=0 Subject: [dpdk-dev] [PATCH 3/3] net/qede: fix to set VLAN strip mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shahed Shaikh Commit 9a6d30ae6d46 ("net/qede: refactoring vport handling code") deleted the code as part of refactoring which sets vlan strip mode. Revert it back and fix vlan strip feature. Fixes: 9a6d30ae6d46 ("net/qede: refactoring vport handling code") Cc: stable@dpdk.org Signed-off-by: Shahed Shaikh Reviewed-by: Rasesh Mody --- drivers/net/qede/qede_ethdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c index 42e2b5083..575982fd0 100644 --- a/drivers/net/qede/qede_ethdev.c +++ b/drivers/net/qede/qede_ethdev.c @@ -833,6 +833,8 @@ static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg) } } + qdev->vlan_strip_flg = flg; + DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled"); return 0; }