From patchwork Thu Oct 17 16:51:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 61437 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E50841EA3E; Thu, 17 Oct 2019 18:51:54 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id DE5271EA3E for ; Thu, 17 Oct 2019 18:51:53 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9HGncJM032129; Thu, 17 Oct 2019 09:51:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=46uQgehSl33utUAzQ8YaLpNAhm8prT0vqBemLaE3rng=; b=QgjxktNPSGEmyfR2ZARSQh/9u02N5KXBSdje0wM5sE6mrvaZFUyOWyU+Mg6uRSGkB/CL wW2HDQffaSnVAe8d+W4qoECvMHR7X1zvMoWYqRBZzjv4Xv7biYGayg1P1Ncjg0arrfyQ BFZYJRkA4urRlCwtYXmHhvEzx5qwPcxcvQ9gilWdYxoQTBei7Zo6VYUY4bayDWU8oiEU ffWfHir5nONJ7qnK7x0v+TfMllr46y4D+qfnRFMWfQdwTiPmK13UQmupS7pTqPxhj3lk l3P81QntWkTVFXrtCeFliwQI2a7dRM9HulQt9PPVi44mD0uO7LaZyk6Vkm2sYy9U9M1u SQ== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2vpj9bt40b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2019 09:51:53 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 17 Oct 2019 09:51:51 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 17 Oct 2019 09:51:51 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.69]) by maili.marvell.com (Postfix) with ESMTP id 5127B3F703F; Thu, 17 Oct 2019 09:51:48 -0700 (PDT) From: To: , , Nithin Dabilpuram , Kiran Kumar K , "John McNamara" , Marko Kovacevic CC: , Pavan Nikhilesh Date: Thu, 17 Oct 2019 22:21:46 +0530 Message-ID: <20191017165147.7054-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191017122004.5446-1-pbhagavatula@marvell.com> References: <20191017122004.5446-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-17_05:2019-10-17,2019-10-17 signatures=0 Subject: [dpdk-dev] [PATCH v3] net/octeontx2: add set supported types op X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add support to set supported ptypes for octeontx2. Signed-off-by: Pavan Nikhilesh --- v3 Changes: ---------- - Actually update doc file. v2 Changes: ---------- - Update documentation. - Use positive logic. doc/guides/nics/octeontx2.rst | 5 ----- drivers/net/octeontx2/otx2_ethdev.c | 1 + drivers/net/octeontx2/otx2_ethdev.h | 2 ++ drivers/net/octeontx2/otx2_ethdev_devargs.c | 21 --------------------- drivers/net/octeontx2/otx2_lookup.c | 15 +++++++++++++++ 5 files changed, 18 insertions(+), 26 deletions(-) -- 2.17.1 diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst index 9a76567a8..fb468a06b 100644 --- a/doc/guides/nics/octeontx2.rst +++ b/doc/guides/nics/octeontx2.rst @@ -112,11 +112,6 @@ use arm64-octeontx2-linux-gcc as target. Runtime Config Options ---------------------- -- ``HW offload ptype parsing disable`` (default ``0``) - - Packet type parsing is HW offloaded by default and this feature may be toggled - using ``ptype_disable`` ``devargs`` parameter. - - ``Rx&Tx scalar mode enable`` (default ``0``) Ethdev supports both scalar and vector mode, it may be selected at runtime diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index 4a60f9f74..361a3d993 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -1944,6 +1944,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = { .dev_set_link_up = otx2_nix_dev_set_link_up, .dev_set_link_down = otx2_nix_dev_set_link_down, .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get, + .dev_supported_ptypes_set = otx2_nix_supported_ptypes_set, .dev_reset = otx2_nix_dev_reset, .stats_get = otx2_nix_dev_stats_get, .stats_reset = otx2_nix_dev_stats_reset, diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h index 33fa0c60b..a5bf89090 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -506,6 +506,8 @@ void *otx2_nix_fastpath_lookup_mem_get(void); /* PTYPES */ const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev); +int otx2_nix_supported_ptypes_set(struct rte_eth_dev *eth_dev, + uint32_t ptype_mask); /* Mac address handling */ int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev, diff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c index 7dc6e92be..9ad00c6f4 100644 --- a/drivers/net/octeontx2/otx2_ethdev_devargs.c +++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c @@ -63,21 +63,6 @@ parse_reta_size(const char *key, const char *value, void *extra_args) return 0; } -static int -parse_ptype_flag(const char *key, const char *value, void *extra_args) -{ - RTE_SET_USED(key); - uint32_t val; - - val = atoi(value); - if (val) - val = 0; /* Disable NIX_RX_OFFLOAD_PTYPE_F */ - - *(uint16_t *)extra_args = val; - - return 0; -} - static int parse_flag(const char *key, const char *value, void *extra_args) { @@ -105,7 +90,6 @@ parse_sqb_count(const char *key, const char *value, void *extra_args) } #define OTX2_RSS_RETA_SIZE "reta_size" -#define OTX2_PTYPE_DISABLE "ptype_disable" #define OTX2_SCL_ENABLE "scalar_enable" #define OTX2_MAX_SQB_COUNT "max_sqb_count" #define OTX2_FLOW_PREALLOC_SIZE "flow_prealloc_size" @@ -114,7 +98,6 @@ parse_sqb_count(const char *key, const char *value, void *extra_args) int otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) { - uint16_t offload_flag = NIX_RX_OFFLOAD_PTYPE_F; uint16_t rss_size = NIX_RSS_RETA_SIZE; uint16_t sqb_count = NIX_MAX_SQB; uint16_t flow_prealloc_size = 8; @@ -129,8 +112,6 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) if (kvlist == NULL) goto exit; - rte_kvargs_process(kvlist, OTX2_PTYPE_DISABLE, - &parse_ptype_flag, &offload_flag); rte_kvargs_process(kvlist, OTX2_RSS_RETA_SIZE, &parse_reta_size, &rss_size); rte_kvargs_process(kvlist, OTX2_SCL_ENABLE, @@ -144,7 +125,6 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) rte_kvargs_free(kvlist); null_devargs: - dev->rx_offload_flags = offload_flag; dev->scalar_ena = scalar_enable; dev->max_sqb_count = sqb_count; dev->rss_info.rss_size = rss_size; @@ -158,7 +138,6 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2, OTX2_RSS_RETA_SIZE "=<64|128|256>" - OTX2_PTYPE_DISABLE "=1" OTX2_SCL_ENABLE "=1" OTX2_MAX_SQB_COUNT "=<8-512>" OTX2_FLOW_PREALLOC_SIZE "=<1-32>" diff --git a/drivers/net/octeontx2/otx2_lookup.c b/drivers/net/octeontx2/otx2_lookup.c index 3071278fc..8e15b59a0 100644 --- a/drivers/net/octeontx2/otx2_lookup.c +++ b/drivers/net/octeontx2/otx2_lookup.c @@ -62,6 +62,21 @@ otx2_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev) return NULL; } +int +otx2_nix_supported_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask) +{ + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + + if (ptype_mask) + dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F; + else + dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F; + + otx2_eth_set_rx_function(eth_dev); + + return 0; +} + /* * +------------------ +------------------ + * | | IL4 | IL3| IL2 | TU | L4 | L3 | L2 |