From patchwork Mon Oct 14 05:19:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AMARANATH SOMALAPURAM X-Patchwork-Id: 61036 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1CE271C1B1; Mon, 14 Oct 2019 07:19:57 +0200 (CEST) Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-eopbgr760077.outbound.protection.outlook.com [40.107.76.77]) by dpdk.org (Postfix) with ESMTP id C91001C18E; Mon, 14 Oct 2019 07:19:55 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bzT3N7vCdcCbd+yRUYofZWVKuliV5nsFAGbYVbyM0Ivgsy+qEpcPxsVoDjY4Cn1wHxFMQdBvs64HxSQHko3CzCOZyWkpqxJJwAJ/GpLUEHOhwfQS6ZdKmroYyuQ10n4l0B4Drn4LeNa4GhzEpshBQbDyM/ltxfsD39pNzyr4EOXB8zAn0BTIJyTylwUzdVzGtjnIj1wa7AC2gaYVbc3UU3U4mDlJocqXyzjWzzwDomqwV0oEMfaWub7Gwx3Hiw3C4/upmcHSRpFUSW0iWK2HHik9V9gmxwZcGwZ8ILvNLfz/Nd/VOyYYZi7zfa+w78aX+xOCJKThMaWwvasNskE0+w== ARC-Message-Signature: i=1; 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Mon, 14 Oct 2019 05:19:54 +0000 Received: from DM5PR1201MB2474.namprd12.prod.outlook.com ([fe80::f3:94a5:9dbc:1fd5]) by DM5PR1201MB2474.namprd12.prod.outlook.com ([fe80::f3:94a5:9dbc:1fd5%12]) with mapi id 15.20.2347.023; Mon, 14 Oct 2019 05:19:54 +0000 From: To: "dev@dpdk.org" CC: "stable@dpdk.org" Thread-Topic: [PATCH v1 1/6] crypto/ccp: fix documentation updating algo arguments like AES_CBC to aes-cbc, SHA1_HMAC to sha1-hmac Thread-Index: AQHVgk8C4dH1pfJ+YkC3HY33r/4fAA== Date: Mon, 14 Oct 2019 05:19:53 +0000 Message-ID: <20191014051934.11494-1-asomalap@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR01CA0143.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::13) To DM5PR1201MB2474.namprd12.prod.outlook.com (2603:10b6:3:e3::8) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Amaranath.Somalapuram@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.156.251] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a51154b7-9d39-4303-7115-08d75066251f x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: DM5PR1201MB0172: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:751; x-forefront-prvs: 01901B3451 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(396003)(346002)(136003)(39850400004)(376002)(366004)(189003)(199004)(3846002)(7736002)(6116002)(256004)(14444005)(8676002)(14454004)(2501003)(305945005)(478600001)(71200400001)(2906002)(71190400001)(316002)(1730700003)(66946007)(5640700003)(6436002)(50226002)(81166006)(66476007)(66556008)(66446008)(8936002)(81156014)(64756008)(6486002)(25786009)(450100002)(2351001)(6512007)(36756003)(66066001)(6916009)(102836004)(6506007)(1076003)(386003)(99286004)(26005)(486006)(2616005)(476003)(52116002)(5660300002)(4326008)(186003); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR1201MB0172; H:DM5PR1201MB2474.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: Rb5ZNyf5GVzXQSGgcNQ9yw/OFHNoFASk6QPjb8S9Awpwt5Y8G2Ugyw0LjIw/TAp9KSuSLU3lWlWbB0XPmZoGZVvDz64jelWgKT7xmDqRFrKMZYaS6ixKS6Mr+N4G9TrEzJzUT6gA8oX4pXWGf114qr1LB/2JEu9/MuBC1JkcSwTAeSRjdfsgn722syHFB650hofUHTBZ4EEGU1d5XPclKYGUJKoWhfjxiYnxVrkUO22ndatiuFGLEnoWNe4SUf/uzcPi80jFkcaqTLAQoQ1q+zUZQ7OXDwe1FjFGOF13J4KjK+476lIeIzmS/G6+l99puaO0gJDHv1bRmDc8diwz5YZHHMwkL+G4lx6EMhsL0DDTeMwT0Rv1dj5lxNlXiumCSqi9hmUWyagzhFG/5GgI1dgZ3fMeMeStX9GCNlAefPQ= x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a51154b7-9d39-4303-7115-08d75066251f X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2019 05:19:53.9146 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: oFsVIDtcorD0PwXJGaY7cVx+s9s3fiuPOnuDVsUurfFHsT66UJE0AReEHhlPjWCqrkm431SSvckimKtW266XCQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0172 Subject: [dpdk-dev] [PATCH v1 1/6] crypto/ccp: fix documentation updating algo arguments like AES_CBC to aes-cbc, SHA1_HMAC to sha1-hmac X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Amaranath Somalapuram Signed-off-by: Amaranath Somalapuram --- doc/guides/cryptodevs/ccp.rst | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/doc/guides/cryptodevs/ccp.rst b/doc/guides/cryptodevs/ccp.rst index 034d20367..a43fe92de 100644 --- a/doc/guides/cryptodevs/ccp.rst +++ b/doc/guides/cryptodevs/ccp.rst @@ -109,14 +109,14 @@ To validate ccp pmd, l2fwd-crypto example can be used with following command: .. code-block:: console - sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp" -- -p 0x1 - --chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo AES_CBC - --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f - --iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff - --auth_op GENERATE --auth_algo SHA1_HMAC - --auth_key 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 - :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 - :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp" -- -p 0x1 + --chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo aes-cbc + --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f + --cipher_iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff + --auth_op GENERATE --auth_algo sha1-hmac + --auth_key 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 The CCP PMD also supports computing authentication over CPU with cipher offloaded to CCP. To enable this feature, pass an additional argument as ccp_auth_opt=1 to --vdev parameters as @@ -124,14 +124,14 @@ following: .. code-block:: console - sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp,ccp_auth_opt=1" -- -p 0x1 - --chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo AES_CBC - --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f - --iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff - --auth_op GENERATE --auth_algo SHA1_HMAC - --auth_key 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 - :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 - :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp,ccp_auth_opt=1" -- -p 0x1 + --chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo aes-cbc + --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f + --cipher_iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff + --auth_op GENERATE --auth_algo sha1-hmac + --auth_key 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 Limitations ----------- From patchwork Mon Oct 14 05:20:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AMARANATH SOMALAPURAM X-Patchwork-Id: 61037 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D251A1C1C7; Mon, 14 Oct 2019 07:20:26 +0200 (CEST) Received: from NAM01-BY2-obe.outbound.protection.outlook.com (mail-eopbgr810041.outbound.protection.outlook.com [40.107.81.41]) by dpdk.org (Postfix) with ESMTP id 47F731C19E; Mon, 14 Oct 2019 07:20:25 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VoiraSLm8jlgtVTSiwBfJ0VWSlrK9KTtrEfKDJPcNTkiqf4y/p8egkRFEsfLWbav7RmVQyKHj6xYVomkGNTvIE2tA2km23tZnm9GCX3dgETUNrHjEMcD1lIuBCmouJTOiR8UcYqiy+5sRSezu408UIg3L1LCLgJ7sjayvTdyzQLgVQxlC+9TsTGnEcKqn1699Lm2RZv5DRJF6n5/X1e3rZk7f8DeCeRmsZ+QREjZlR627Rhxfbwri1Y3QvtzNuwMFdPlT6n4hFAVNscio/gglZrIQmdu36YjzrsHioq2kLvy8sw9f6aC+AeslEV+PLwdmYbJg1/E6DQrJISnkXKExw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=om34HFQCKDMmescMH9sd63ZDK8BLo1asjdQ2jBgvNJU=; b=YKm0EdMgJMb54zcnWPO3lNYcKK8Pq52W6aXfjHt7MnLZxj58Vwmmmofmih3Zq8StQiFElUqk6xslUkJn3UDCzfCLTZ+OmNdC5ngGUZ8Z0rllP4WKpnAUz7WwdlIlse3SSIwq/+5n8rU1ZqUBfkNAo+ANOSWNecqZXwyIq4jSjgB5RRIkrn/kp3u95sTse31/7c1NesYZyZqn249hac7ss+hOsQ1cnNsQiRSEg2CXAPzJf5ZM18bZBsCoM4LjbWr+rd2XQNvILdld+7/zIJSsqH06v7CgXr7TI+EXdoikYSeXH0QGDYPId50UXJ0U+1M3iJ+ZugIJ7tO4Aqcm7HvHFA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=om34HFQCKDMmescMH9sd63ZDK8BLo1asjdQ2jBgvNJU=; b=V059K/2ywAnBdsLrmYFMS5LoU7iVGxW970eE059ofnHnKbzHainC+FwN8hN54SiGhj1BYfona2/pCJ5dobvcEgrOPnl3y/UK2jS16CrGB9+iifaWWSJN9XG77PSct7epgNB5f825MD+BODWeasOi32bnbUjLMitNJLN+WGPkVZo= Received: from DM5PR1201MB2474.namprd12.prod.outlook.com (10.172.87.136) by DM5PR1201MB0027.namprd12.prod.outlook.com (10.174.108.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2347.19; Mon, 14 Oct 2019 05:20:23 +0000 Received: from DM5PR1201MB2474.namprd12.prod.outlook.com ([fe80::f3:94a5:9dbc:1fd5]) by DM5PR1201MB2474.namprd12.prod.outlook.com ([fe80::f3:94a5:9dbc:1fd5%12]) with mapi id 15.20.2347.023; Mon, 14 Oct 2019 05:20:23 +0000 From: To: "dev@dpdk.org" CC: "stable@dpdk.org" Thread-Topic: [PATCH v1 2/6] crypto/ccp: fix for max queue pair and max burst sizes for ccp drivers fixing crash issue in VPP when ccp used. vpp max burst size is 256, and minimum queue pair required is 3. Thread-Index: AQHVgk8UU1jhGo/ptk+OYl6vcYAw7A== Date: Mon, 14 Oct 2019 05:20:23 +0000 Message-ID: <20191014052002.11712-1-asomalap@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR01CA0158.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::28) To DM5PR1201MB2474.namprd12.prod.outlook.com (2603:10b6:3:e3::8) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Amaranath.Somalapuram@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.156.251] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 86d6a434-3163-482a-5a30-08d7506636a3 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: DM5PR1201MB0027: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:296; x-forefront-prvs: 01901B3451 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(346002)(376002)(39860400002)(136003)(396003)(366004)(199004)(189003)(1076003)(14454004)(5660300002)(2616005)(66066001)(486006)(4326008)(476003)(99286004)(4744005)(256004)(66556008)(71200400001)(66476007)(64756008)(66946007)(66446008)(71190400001)(6436002)(478600001)(6512007)(5640700003)(2906002)(316002)(450100002)(7736002)(25786009)(2351001)(2501003)(6486002)(6916009)(386003)(6506007)(102836004)(26005)(52116002)(186003)(3846002)(6116002)(36756003)(305945005)(8676002)(50226002)(81156014)(1730700003)(8936002)(81166006); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR1201MB0027; H:DM5PR1201MB2474.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: AMlfcuBlXHT/D4AHAqOIWD9vyKvvrDzZ/TyeoV7XIOjx/W/a50Le3j5VkCK+f783nuoOKoYmvsJMnwxdo6Ik3XsNB/SjAyW97eqqJNZOkQd2iiWBMP51UN3sVp9ueugO0PikLJYNqYo7YboclaU6QNrXbtSjyuw961gIskCuxmPwwebCXdKywrqlqB61PFNUWDFLC6AuMlRfARnq4OLJ0f/I0bLoBHIwdgXMsM5YVtuJTy8jH8u37Kgepfd4VgDfciFVCqP7d1A4/bkt2vMW0u3doWBIom6T+PMSl6eY6g3gAdJAQ/SvLoRNodDX3RdrhIfDPn+Sr3nhu04ZUED1a4JN47WUdlihBLJZJm0w5ohqBIBrJPNzthOSmRg/AX8ESnTg1rliJlz1BO/j3fvb9+Tmn2ETaOv1UwcoVMlgCVo= x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 86d6a434-3163-482a-5a30-08d7506636a3 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2019 05:20:23.4853 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7UiGnDWk/jLblI6imMCv7hrof0g20JaL1xY8u7yC3w70JGLcjvPAKBdIQ3NfS0ps6GxdpE97fRtaRvkuCz/5Cg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0027 Subject: [dpdk-dev] [PATCH v1 2/6] crypto/ccp: fix for max queue pair and max burst sizes for ccp drivers fixing crash issue in VPP when ccp used. vpp max burst size is 256, and minimum queue pair required is 3. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Amaranath Somalapuram Signed-off-by: Amaranath Somalapuram --- drivers/crypto/ccp/ccp_pmd_private.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/ccp/ccp_pmd_private.h b/drivers/crypto/ccp/ccp_pmd_private.h index 7f2979e89..781050c31 100644 --- a/drivers/crypto/ccp/ccp_pmd_private.h +++ b/drivers/crypto/ccp/ccp_pmd_private.h @@ -31,9 +31,9 @@ #endif /**< Maximum queue pairs supported by CCP PMD */ -#define CCP_PMD_MAX_QUEUE_PAIRS 1 +#define CCP_PMD_MAX_QUEUE_PAIRS 8 #define CCP_NB_MAX_DESCRIPTORS 1024 -#define CCP_MAX_BURST 64 +#define CCP_MAX_BURST 256 #include "ccp_dev.h" From patchwork Mon Oct 14 05:20:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AMARANATH SOMALAPURAM X-Patchwork-Id: 61038 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 22E841C1B1; Mon, 14 Oct 2019 07:20:55 +0200 (CEST) Received: from NAM01-BY2-obe.outbound.protection.outlook.com (mail-eopbgr810053.outbound.protection.outlook.com [40.107.81.53]) by dpdk.org (Postfix) with ESMTP id 159A21C196; Mon, 14 Oct 2019 07:20:53 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QUuXm3T4ib9Zxm5/gcG24TPAOmYsUrDP8M9cOMW+Etij0kirns2yEGoRmvGSQnVK8lZqLkWizUfuUNuMI8RkfJ0SB815ZGVvhVQ5+CL8UKbiYDYuzQyvao+VWaclYCjIXAQByTvRQuEzRZYyoterQEvBr/VpoUO12XCmhK3ctGRu8ua+6siZ0GvlARqVXZG8k5mYEurlk9A2GjnqDLgFzVLVPj6syERl4r4fop1O1rQs0CvJc/p1DwL4wblGYihMVrpG+ngQhwfowROliMpdqAB/p/XJ5EZ3i8oFaez0xQmiD+vc2HsZm9FC8e+KCil60s1HAgsLZo7pLj93kGPMRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FUfBLAddtpoOR1xmh4/389YO/+ZcqD9NDJh135vSqtc=; b=P3U0kHGkPxiBNrB2BQgeJ2mr9NApSnUVZu7oMaWRkIw40tjdp+ouRCJMqrMKWUpk5rA0qlFL4SrZ1wwo9PV5GJ9VP19DVK+JMjxUnm+eEPPvBBNrRI7RT5xequF1/ckcTVqvKmhtM2fWkZYYQXB/ySeYH/bRjQCm0Wvgj9ibGV7skHoOFUxXAdgcI458xD1FjtHJwgB7T8t77SlQSqmutuMPq4HuTLEC8Bnk1JcvuG1ePJQq5HqPoADstQhnyxkAJ+y4y9fE5XtwcMkrLq+UNQdT1IhkU69odNjssku5qVJtwBxseHvBvCejNfRHGJofs+jDEQvFsQcDVCdlHUOflg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FUfBLAddtpoOR1xmh4/389YO/+ZcqD9NDJh135vSqtc=; b=DxDB9VTUsCNTDWlpi1K43gKONCZ2PGbtEKKM1fSQ7TFywASRDSSOQDkgcddEJVXgnPVBkNVKM5QZntVWbOz3Ak+AStt9L7EZ0G27Os8DiQnJHmsVhVG4S6/X0WSayAS3pdgIilrk8QqScJJeUFX6RpGiro2uF+CyHzI49C2oH8M= Received: from DM5PR1201MB2474.namprd12.prod.outlook.com (10.172.87.136) by DM5PR1201MB0027.namprd12.prod.outlook.com (10.174.108.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2347.19; Mon, 14 Oct 2019 05:20:51 +0000 Received: from DM5PR1201MB2474.namprd12.prod.outlook.com ([fe80::f3:94a5:9dbc:1fd5]) by DM5PR1201MB2474.namprd12.prod.outlook.com ([fe80::f3:94a5:9dbc:1fd5%12]) with mapi id 15.20.2347.023; Mon, 14 Oct 2019 05:20:51 +0000 From: To: "dev@dpdk.org" CC: "stable@dpdk.org" Thread-Topic: [PATCH v1 3/6] crypto/ccp: fix for crash when ccp cpu authentication algorithm fails when ccp_auth_opt=1 is set and authentication error occurred ccp driver crash. Thread-Index: AQHVgk8lPsamxhl7ZUePvVEMgGnQow== Date: Mon, 14 Oct 2019 05:20:51 +0000 Message-ID: <20191014052031.11936-1-asomalap@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MAXPR0101CA0062.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:e::24) To DM5PR1201MB2474.namprd12.prod.outlook.com (2603:10b6:3:e3::8) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Amaranath.Somalapuram@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.156.251] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 22531683-1910-42ef-c76c-08d750664793 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: DM5PR1201MB0027: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:311; x-forefront-prvs: 01901B3451 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(346002)(376002)(39860400002)(136003)(396003)(366004)(199004)(189003)(1076003)(14454004)(5660300002)(2616005)(66066001)(486006)(4326008)(476003)(99286004)(4744005)(14444005)(256004)(66556008)(71200400001)(66476007)(64756008)(66946007)(66446008)(71190400001)(6436002)(478600001)(6512007)(5640700003)(2906002)(316002)(450100002)(7736002)(25786009)(2351001)(2501003)(6486002)(6916009)(386003)(6506007)(102836004)(26005)(52116002)(186003)(3846002)(6116002)(36756003)(305945005)(8676002)(50226002)(81156014)(1730700003)(8936002)(81166006); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR1201MB0027; H:DM5PR1201MB2474.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: APFVCDLx3IbhJTyRjXUjKU4qPe8yytbN7UVE9Lt+VE87oHvV/Ok0ugmAG1HUdo+WCwej4yNrXZu43QBKlUYqm2RyeSnUqOScR/ceXmJSipVGRUfyqGmtgLix4AUKFs7sCN2RigJ2ox0zEAY7p0weYtTGDkMJuvqOlH5W/zDL8Q7yHRhrFoiTycEh4kK82i30kk5Z9l7FvDvSUCOzprQjXTcMBDMjjHOrgcBvKQytrBXy75/07pzTiM2OKwgXdPqADmSWlJFNnVYXRjDHNyCkEglDeY5LMyfuuGjRtk3eY3asWbwlElr++z8p5HnqIhJT3TYMLF4m8zuiwi9FEIPhXSWY0Axr2IHuoF3nvfYmxHSM7kw/Q0mQcGjzhtSSTlOVq+aqUG4PM56fHRlc5KkzrOa33o6iHvHj/vDfA+natFY= x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 22531683-1910-42ef-c76c-08d750664793 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2019 05:20:51.8425 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: xbL3EaX0s7SHra3vuWomyYiwbyYPt4KPGifM+bsNd9pjHQbz7Sb2ErRRhs/gajAoFq5toOMw+nrApDAyFmCw5Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0027 Subject: [dpdk-dev] [PATCH v1 3/6] crypto/ccp: fix for crash when ccp cpu authentication algorithm fails when ccp_auth_opt=1 is set and authentication error occurred ccp driver crash. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Amaranath Somalapuram Signed-off-by: Amaranath Somalapuram --- drivers/crypto/ccp/ccp_crypto.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/ccp/ccp_crypto.c b/drivers/crypto/ccp/ccp_crypto.c index 19ae9153d..1837c8543 100644 --- a/drivers/crypto/ccp/ccp_crypto.c +++ b/drivers/crypto/ccp/ccp_crypto.c @@ -2738,7 +2738,7 @@ process_ops_to_enqueue(struct ccp_qp *qp, session, auth_ctx); if (op[i]->status != RTE_CRYPTO_OP_STATUS_SUCCESS) - continue; + CCP_LOG_ERR("RTE_CRYPTO_OP_STATUS_AUTH_FAILED"); } else result = ccp_crypto_auth(op[i], cmd_q, b_info); From patchwork Mon Oct 14 05:21:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AMARANATH SOMALAPURAM X-Patchwork-Id: 61039 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1628E1B994; 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Mon, 14 Oct 2019 05:21:22 +0000 From: To: "dev@dpdk.org" CC: "stable@dpdk.org" Thread-Topic: [PATCH v1 4/6] crypto/ccp: fix for crypto capabilites ops crypto capabilites ops for ccp initilzed incorrectly. fix the correct values for the capabilites ops Thread-Index: AQHVgk83F4FmqCBKY0OkBgzrb0SF3Q== Date: Mon, 14 Oct 2019 05:21:22 +0000 Message-ID: <20191014052102.12171-1-asomalap@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MAXPR0101CA0070.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:e::32) To DM5PR1201MB2474.namprd12.prod.outlook.com (2603:10b6:3:e3::8) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Amaranath.Somalapuram@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.156.251] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 8a1cd93e-2305-4134-12e9-08d7506659c9 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: DM5PR1201MB0027: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:296; 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charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AMARANATH SOMALAPURAM X-Patchwork-Id: 61040 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D7F7A1C1D3; Mon, 14 Oct 2019 07:21:56 +0200 (CEST) Received: from NAM01-BY2-obe.outbound.protection.outlook.com (mail-eopbgr810070.outbound.protection.outlook.com [40.107.81.70]) by dpdk.org (Postfix) with ESMTP id 20EBA2BAA; Mon, 14 Oct 2019 07:21:55 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Midlas9rWKl+YHkaKRSakdKku+87RBFGXbUj1N+kJEG44AzNbee5hoxeupZQ8QukJmkZvY/NoBF28UmvhlTHmpT4CGx/adJi0O0PfNDyJLRiwtX5cBPFcXTKZ+hRSOFaEL6h8Ocp9JRtvg+NQo+0LBJrFnm9vPRMi/PRo7n0V9JFgEc3alDwUt1MAM/Qy20WKT9aMk3ETISf0rQex6hC322DJ0NVVKJUCo5dM2OhZoAi/pvzwVv0lbk+0Pv+omNi4NuWqIEVYuCjozYOCCMM7W6CS4A5iQk5pySIFy6Hde1D79zDoHUKA/DQiDJ/Qef2+YD8dTuIcCDK3qo97W0seA== ARC-Message-Signature: i=1; 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SFP:1101; SCL:1; SRVR:DM5PR1201MB0027; H:DM5PR1201MB2474.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: F3JtE52o5DN+HnWQqpE14SxnCCpxBjxTthhtO89R7VydsKLbEqClLe/3iY0Lvpn1vDK4liQ0avT9Syu53GY+oCFDmok8F9VXdYwDSKUAxkfXveOh3yL9laEiM/IIrdB/pRpZjfxUJD90arXtQE6My5Qov6JzuqNQtNkH+a7dfATf9Iupxw5Y3jQEy/Oh0LUEgxWecULXgAZnJNprd5GiwnGjFMBgB1qPIoMn7UWQPgzOODWHv2aegoMQDOyIKenTp9M8JczD1ok43rDxiW6QyVlhLt9pW8j4ge8VVDgL2fbWfbLgLVc5y9/4kogSUHtFQw8AVG1aO+mI+Kkz1pwgrRxaGko4ahjdGBGuT3ubmTGsMdMwOkLIrI8/dh10KYTzxDqL19rhdClTkvg9odaTNiv/dxCY7liSTXMQqRTBbtU= x-ms-exchange-transport-forked: True Content-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2ae32afe-a579-4c75-9ceb-08d750666c4c X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2019 05:21:53.4399 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: H3xY0st5XBaXbUlvjOTFk0fXsTO+Q37rVgo26ECjaQOFPtov0TND4+nxtDf3r+1fTs4YqGe0eWeHqlRsyWPkPg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0027 Subject: [dpdk-dev] =?utf-8?q?=5BPATCH_v1_5/6=5D_crypto/ccp=3A_enable_IOMM?= =?utf-8?q?U_for_CCP_CCP_use_vdev_framework=2C_and_vdev_framework_d?= =?utf-8?q?on=E2=80=99t_support_IOMMU=2E_Adding_custom_IOMMU_suppor?= =?utf-8?q?t_for_AMD_CCP_drives=2E?= X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Amaranath Somalapuram Signed-off-by: Amaranath Somalapuram --- drivers/crypto/ccp/ccp_crypto.c | 244 ++++++++++++++++++++++++------- drivers/crypto/ccp/ccp_dev.c | 56 ++----- drivers/crypto/ccp/ccp_dev.h | 2 +- drivers/crypto/ccp/ccp_pci.c | 1 + drivers/crypto/ccp/ccp_pci.h | 1 + drivers/crypto/ccp/rte_ccp_pmd.c | 5 +- 6 files changed, 211 insertions(+), 98 deletions(-) diff --git a/drivers/crypto/ccp/ccp_crypto.c b/drivers/crypto/ccp/ccp_crypto.c index 1837c8543..c0ece4e37 100644 --- a/drivers/crypto/ccp/ccp_crypto.c +++ b/drivers/crypto/ccp/ccp_crypto.c @@ -31,8 +31,11 @@ #include #include +extern int iommu_mode; + /* SHA initial context values */ -static uint32_t ccp_sha1_init[SHA_COMMON_DIGEST_SIZE / sizeof(uint32_t)] = { +void *sha_ctx; +uint32_t ccp_sha1_init[SHA_COMMON_DIGEST_SIZE / sizeof(uint32_t)] = { SHA1_H4, SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0, 0x0U, @@ -744,8 +747,16 @@ ccp_configure_session_cipher(struct ccp_session *sess, CCP_LOG_ERR("Invalid CCP Engine"); return -ENOTSUP; } - sess->cipher.nonce_phys = rte_mem_virt2phy(sess->cipher.nonce); - sess->cipher.key_phys = rte_mem_virt2phy(sess->cipher.key_ccp); + if(iommu_mode == 2) + { + sess->cipher.nonce_phys = rte_mem_virt2iova(sess->cipher.nonce); + sess->cipher.key_phys = rte_mem_virt2iova(sess->cipher.key_ccp); + } + else + { + sess->cipher.nonce_phys = rte_mem_virt2phy(sess->cipher.nonce); + sess->cipher.key_phys = rte_mem_virt2phy(sess->cipher.key_ccp); + } return 0; } @@ -784,6 +795,7 @@ ccp_configure_session_auth(struct ccp_session *sess, sess->auth.ctx = (void *)ccp_sha1_init; sess->auth.ctx_len = CCP_SB_BYTES; sess->auth.offset = CCP_SB_BYTES - SHA1_DIGEST_SIZE; + rte_memcpy(sha_ctx,sess->auth.ctx,SHA_COMMON_DIGEST_SIZE); break; case RTE_CRYPTO_AUTH_SHA1_HMAC: if (sess->auth_opt) { @@ -822,6 +834,7 @@ ccp_configure_session_auth(struct ccp_session *sess, sess->auth.ctx = (void *)ccp_sha224_init; sess->auth.ctx_len = CCP_SB_BYTES; sess->auth.offset = CCP_SB_BYTES - SHA224_DIGEST_SIZE; + rte_memcpy(sha_ctx,sess->auth.ctx,SHA256_DIGEST_SIZE); break; case RTE_CRYPTO_AUTH_SHA224_HMAC: if (sess->auth_opt) { @@ -884,6 +897,7 @@ ccp_configure_session_auth(struct ccp_session *sess, sess->auth.ctx = (void *)ccp_sha256_init; sess->auth.ctx_len = CCP_SB_BYTES; sess->auth.offset = CCP_SB_BYTES - SHA256_DIGEST_SIZE; + rte_memcpy(sha_ctx,sess->auth.ctx,SHA256_DIGEST_SIZE); break; case RTE_CRYPTO_AUTH_SHA256_HMAC: if (sess->auth_opt) { @@ -946,6 +960,7 @@ ccp_configure_session_auth(struct ccp_session *sess, sess->auth.ctx = (void *)ccp_sha384_init; sess->auth.ctx_len = CCP_SB_BYTES << 1; sess->auth.offset = (CCP_SB_BYTES << 1) - SHA384_DIGEST_SIZE; + rte_memcpy(sha_ctx,sess->auth.ctx,SHA512_DIGEST_SIZE); break; case RTE_CRYPTO_AUTH_SHA384_HMAC: if (sess->auth_opt) { @@ -1010,6 +1025,7 @@ ccp_configure_session_auth(struct ccp_session *sess, sess->auth.ctx = (void *)ccp_sha512_init; sess->auth.ctx_len = CCP_SB_BYTES << 1; sess->auth.offset = (CCP_SB_BYTES << 1) - SHA512_DIGEST_SIZE; + rte_memcpy(sha_ctx,sess->auth.ctx,SHA512_DIGEST_SIZE); break; case RTE_CRYPTO_AUTH_SHA512_HMAC: if (sess->auth_opt) { @@ -1159,8 +1175,16 @@ ccp_configure_session_aead(struct ccp_session *sess, CCP_LOG_ERR("Unsupported aead algo"); return -ENOTSUP; } - sess->cipher.nonce_phys = rte_mem_virt2phy(sess->cipher.nonce); - sess->cipher.key_phys = rte_mem_virt2phy(sess->cipher.key_ccp); + if(iommu_mode == 2) + { + sess->cipher.nonce_phys = rte_mem_virt2iova(sess->cipher.nonce); + sess->cipher.key_phys = rte_mem_virt2iova(sess->cipher.key_ccp); + } + else + { + sess->cipher.nonce_phys = rte_mem_virt2phy(sess->cipher.nonce); + sess->cipher.key_phys = rte_mem_virt2phy(sess->cipher.key_ccp); + } return 0; } @@ -1571,15 +1595,27 @@ ccp_perform_hmac(struct rte_crypto_op *op, ccp_cryptodev_driver_id); addr = session->auth.pre_compute; - src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, - op->sym->auth.data.offset); append_ptr = (void *)rte_pktmbuf_append(op->sym->m_src, session->auth.ctx_len); - dest_addr = (phys_addr_t)rte_mem_virt2phy(append_ptr); + if(iommu_mode == 2) + { + src_addr = (phys_addr_t)rte_mem_virt2iova( + rte_pktmbuf_mtod_offset(op->sym->m_src, phys_addr_t*, + op->sym->auth.data.offset)); + dest_addr = (phys_addr_t)rte_mem_virt2iova(append_ptr); + pst.src_addr = (phys_addr_t)rte_mem_virt2iova((void *)addr); + } + else + { + src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, + op->sym->auth.data.offset); + dest_addr = (phys_addr_t)rte_mem_virt2phy(append_ptr); + pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)addr); + } dest_addr_t = dest_addr; /** Load PHash1 to LSB*/ - pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)addr); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES); pst.len = session->auth.ctx_len; pst.dir = 1; @@ -1659,7 +1695,14 @@ ccp_perform_hmac(struct rte_crypto_op *op, /** Load PHash2 to LSB*/ addr += session->auth.ctx_len; - pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)addr); + if(iommu_mode == 2) + { + pst.src_addr = (phys_addr_t)rte_mem_virt2iova((void *)addr); + } + else + { + pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)addr); + } pst.dest_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES); pst.len = session->auth.ctx_len; pst.dir = 1; @@ -1743,17 +1786,26 @@ ccp_perform_sha(struct rte_crypto_op *op, op->sym->session, ccp_cryptodev_driver_id); - src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, - op->sym->auth.data.offset); - append_ptr = (void *)rte_pktmbuf_append(op->sym->m_src, session->auth.ctx_len); - dest_addr = (phys_addr_t)rte_mem_virt2phy(append_ptr); - /** Passthru sha context*/ + if(iommu_mode == 2) + { + src_addr = (phys_addr_t)rte_mem_virt2iova( + rte_pktmbuf_mtod_offset(op->sym->m_src, void*, + op->sym->auth.data.offset)); + dest_addr = (phys_addr_t)rte_mem_virt2iova(append_ptr); + pst.src_addr = (phys_addr_t)sha_ctx; + } + else + { + src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, + op->sym->auth.data.offset); + dest_addr = (phys_addr_t)rte_mem_virt2phy(append_ptr); + pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *) + session->auth.ctx); + } - pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *) - session->auth.ctx); pst.dest_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES); pst.len = session->auth.ctx_len; pst.dir = 1; @@ -1832,18 +1884,32 @@ ccp_perform_sha3_hmac(struct rte_crypto_op *op, op->sym->session, ccp_cryptodev_driver_id); - src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, - op->sym->auth.data.offset); append_ptr = (uint8_t *)rte_pktmbuf_append(op->sym->m_src, session->auth.ctx_len); if (!append_ptr) { CCP_LOG_ERR("CCP MBUF append failed\n"); return -1; } - dest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr); + if(iommu_mode == 2) + { + src_addr = (phys_addr_t)rte_mem_virt2iova( + rte_pktmbuf_mtod_offset(op->sym->m_src, phys_addr_t*, + op->sym->auth.data.offset)); + dest_addr = (phys_addr_t)rte_mem_virt2iova((void *)append_ptr); + ctx_paddr = (phys_addr_t)rte_mem_virt2iova((void + *)session->auth.pre_compute); + } + else + { + src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, + op->sym->auth.data.offset); + dest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr); + ctx_paddr = (phys_addr_t)rte_mem_virt2phy((void + *)session->auth.pre_compute); + } + dest_addr_t = dest_addr + (session->auth.ctx_len / 2); - ctx_paddr = (phys_addr_t)rte_mem_virt2phy((void - *)session->auth.pre_compute); + desc = &cmd_q->qbase_desc[cmd_q->qidx]; memset(desc, 0, Q_DESC_SIZE); @@ -1964,7 +2030,7 @@ ccp_perform_sha3(struct rte_crypto_op *op, struct ccp_session *session; union ccp_function function; struct ccp_desc *desc; - uint8_t *ctx_addr, *append_ptr; + uint8_t *ctx_addr = NULL, *append_ptr = NULL; uint32_t tail; phys_addr_t src_addr, dest_addr, ctx_paddr; @@ -1972,18 +2038,29 @@ ccp_perform_sha3(struct rte_crypto_op *op, op->sym->session, ccp_cryptodev_driver_id); - src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, - op->sym->auth.data.offset); append_ptr = (uint8_t *)rte_pktmbuf_append(op->sym->m_src, session->auth.ctx_len); if (!append_ptr) { CCP_LOG_ERR("CCP MBUF append failed\n"); return -1; } - dest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr); - ctx_addr = session->auth.sha3_ctx; - ctx_paddr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr); + if(iommu_mode == 2) + { + src_addr = (phys_addr_t)rte_mem_virt2iova( + rte_pktmbuf_mtod_offset(op->sym->m_src, phys_addr_t*, + op->sym->auth.data.offset)); + dest_addr = (phys_addr_t)rte_mem_virt2iova((void *)append_ptr); + ctx_paddr = (phys_addr_t)rte_mem_virt2iova((void *)ctx_addr); + } + else + { + src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, + op->sym->auth.data.offset); + dest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr); + ctx_paddr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr); + } + ctx_addr = session->auth.sha3_ctx; desc = &cmd_q->qbase_desc[cmd_q->qidx]; memset(desc, 0, Q_DESC_SIZE); @@ -2032,20 +2109,31 @@ ccp_perform_aes_cmac(struct rte_crypto_op *op, struct ccp_passthru pst; struct ccp_desc *desc; uint32_t tail; - uint8_t *src_tb, *append_ptr, *ctx_addr; + uint8_t *src_tb, *append_ptr = NULL, *ctx_addr; phys_addr_t src_addr, dest_addr, key_addr; int length, non_align_len; session = (struct ccp_session *)get_sym_session_private_data( op->sym->session, ccp_cryptodev_driver_id); - key_addr = rte_mem_virt2phy(session->auth.key_ccp); + if(iommu_mode == 2) + { + key_addr = rte_mem_virt2iova(session->auth.key_ccp); + src_addr = (phys_addr_t)rte_mem_virt2iova( + rte_pktmbuf_mtod_offset(op->sym->m_src, phys_addr_t*, + op->sym->auth.data.offset)); + dest_addr = (phys_addr_t)rte_mem_virt2iova((void *)append_ptr); + } + else + { + key_addr = rte_mem_virt2phy(session->auth.key_ccp); + src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, + op->sym->auth.data.offset); + dest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr); + } - src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, - op->sym->auth.data.offset); append_ptr = (uint8_t *)rte_pktmbuf_append(op->sym->m_src, session->auth.ctx_len); - dest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr); function.raw = 0; CCP_AES_ENCRYPT(&function) = CCP_CIPHER_DIR_ENCRYPT; @@ -2056,7 +2144,10 @@ ccp_perform_aes_cmac(struct rte_crypto_op *op, ctx_addr = session->auth.pre_compute; memset(ctx_addr, 0, AES_BLOCK_SIZE); - pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr); + if(iommu_mode == 2) + pst.src_addr = (phys_addr_t)rte_mem_virt2iova((void *)ctx_addr); + else + pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr); pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES); pst.len = CCP_SB_BYTES; pst.dir = 1; @@ -2094,7 +2185,10 @@ ccp_perform_aes_cmac(struct rte_crypto_op *op, } else { ctx_addr = session->auth.pre_compute + CCP_SB_BYTES; memset(ctx_addr, 0, AES_BLOCK_SIZE); - pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr); + if(iommu_mode == 2) + pst.src_addr = (phys_addr_t)rte_mem_virt2iova((void *)ctx_addr); + else + pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr); pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES); pst.len = CCP_SB_BYTES; pst.dir = 1; @@ -2221,11 +2315,23 @@ ccp_perform_aes(struct rte_crypto_op *op, desc = &cmd_q->qbase_desc[cmd_q->qidx]; - src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, + if(iommu_mode == 2) + src_addr = (phys_addr_t)rte_mem_virt2iova( + rte_pktmbuf_mtod_offset(op->sym->m_src, void *, + op->sym->cipher.data.offset)); + else + src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, op->sym->cipher.data.offset); if (likely(op->sym->m_dst != NULL)) - dest_addr = rte_pktmbuf_mtophys_offset(op->sym->m_dst, - op->sym->cipher.data.offset); + { + if(iommu_mode == 2) + dest_addr = (phys_addr_t)rte_mem_virt2iova( + rte_pktmbuf_mtod_offset(op->sym->m_dst, void *, + op->sym->cipher.data.offset)); + else + dest_addr = rte_pktmbuf_mtophys_offset(op->sym->m_dst, + op->sym->cipher.data.offset); + } else dest_addr = src_addr; key_addr = session->cipher.key_phys; @@ -2289,7 +2395,11 @@ ccp_perform_3des(struct rte_crypto_op *op, rte_memcpy(lsb_buf + (CCP_SB_BYTES - session->iv.length), iv, session->iv.length); - pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *) lsb_buf); + if(iommu_mode == 2) + pst.src_addr = (phys_addr_t)rte_mem_virt2iova((void *) lsb_buf); + else + pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *) lsb_buf); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES); pst.len = CCP_SB_BYTES; pst.dir = 1; @@ -2303,16 +2413,30 @@ ccp_perform_3des(struct rte_crypto_op *op, return -ENOTSUP; } - src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, - op->sym->cipher.data.offset); + if(iommu_mode == 2) + src_addr = (phys_addr_t)rte_mem_virt2iova( + rte_pktmbuf_mtod_offset(op->sym->m_src, void *, + op->sym->cipher.data.offset)); + else + src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, + op->sym->cipher.data.offset); if (unlikely(op->sym->m_dst != NULL)) - dest_addr = - rte_pktmbuf_mtophys_offset(op->sym->m_dst, - op->sym->cipher.data.offset); + { + if(iommu_mode == 2) + dest_addr = (phys_addr_t)rte_mem_virt2iova( + rte_pktmbuf_mtod_offset(op->sym->m_dst, void *, + op->sym->cipher.data.offset)); + else + dest_addr = rte_pktmbuf_mtophys_offset(op->sym->m_dst, + op->sym->cipher.data.offset); + } else dest_addr = src_addr; - key_addr = rte_mem_virt2phy(session->cipher.key_ccp); + if(iommu_mode == 2) + key_addr = rte_mem_virt2iova(session->cipher.key_ccp); + else + key_addr = rte_mem_virt2phy(session->cipher.key_ccp); desc = &cmd_q->qbase_desc[cmd_q->qidx]; @@ -2385,11 +2509,23 @@ ccp_perform_aes_gcm(struct rte_crypto_op *op, struct ccp_queue *cmd_q) iv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset); key_addr = session->cipher.key_phys; - src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, - op->sym->aead.data.offset); + if(iommu_mode == 2) + src_addr = (phys_addr_t)rte_mem_virt2iova( + rte_pktmbuf_mtod_offset(op->sym->m_src, void *, + op->sym->aead.data.offset)); + else + src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, + op->sym->aead.data.offset); if (unlikely(op->sym->m_dst != NULL)) - dest_addr = rte_pktmbuf_mtophys_offset(op->sym->m_dst, - op->sym->aead.data.offset); + { + if(iommu_mode == 2) + dest_addr = (phys_addr_t)rte_mem_virt2iova( + rte_pktmbuf_mtod_offset(op->sym->m_dst, void *, + op->sym->aead.data.offset)); + else + dest_addr = rte_pktmbuf_mtophys_offset(op->sym->m_dst, + op->sym->aead.data.offset); + } else dest_addr = src_addr; rte_pktmbuf_append(op->sym->m_src, session->auth.ctx_len); @@ -2704,8 +2840,14 @@ process_ops_to_enqueue(struct ccp_qp *qp, b_info->lsb_buf_idx = 0; b_info->desccnt = 0; b_info->cmd_q = cmd_q; - b_info->lsb_buf_phys = - (phys_addr_t)rte_mem_virt2phy((void *)b_info->lsb_buf); + + if(iommu_mode == 2) + b_info->lsb_buf_phys = + (phys_addr_t)rte_mem_virt2iova((void *)b_info->lsb_buf); + else + b_info->lsb_buf_phys = + (phys_addr_t)rte_mem_virt2phy((void *)b_info->lsb_buf); + rte_atomic64_sub(&b_info->cmd_q->free_slots, slots_req); b_info->head_offset = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * diff --git a/drivers/crypto/ccp/ccp_dev.c b/drivers/crypto/ccp/ccp_dev.c index 80fe6a453..69ba61a3d 100644 --- a/drivers/crypto/ccp/ccp_dev.c +++ b/drivers/crypto/ccp/ccp_dev.c @@ -23,6 +23,8 @@ #include "ccp_pci.h" #include "ccp_pmd_private.h" +int iommu_mode = 0; + struct ccp_list ccp_list = TAILQ_HEAD_INITIALIZER(ccp_list); static int ccp_dev_id; @@ -512,7 +514,7 @@ ccp_add_device(struct ccp_device *dev, int type) CCP_WRITE_REG(vaddr, CMD_CLK_GATE_CTL_OFFSET, 0x00108823); } - CCP_WRITE_REG(vaddr, CMD_REQID_CONFIG_OFFSET, 0x00001249); + CCP_WRITE_REG(vaddr, CMD_REQID_CONFIG_OFFSET, 0x0); /* Copy the private LSB mask to the public registers */ status_lo = CCP_READ_REG(vaddr, LSB_PRIVATE_MASK_LO_OFFSET); @@ -657,9 +659,7 @@ ccp_probe_device(const char *dirname, uint16_t domain, struct rte_pci_device *pci; char filename[PATH_MAX]; unsigned long tmp; - int uio_fd = -1, i, uio_num; - char uio_devname[PATH_MAX]; - void *map_addr; + int uio_fd = -1; ccp_dev = rte_zmalloc("ccp_device", sizeof(*ccp_dev), RTE_CACHE_LINE_SIZE); @@ -710,46 +710,14 @@ ccp_probe_device(const char *dirname, uint16_t domain, snprintf(filename, sizeof(filename), "%s/resource", dirname); if (ccp_pci_parse_sysfs_resource(filename, pci) < 0) goto fail; + if(iommu_mode == 2) + pci->kdrv = RTE_KDRV_VFIO; + else if(iommu_mode == 0) + pci->kdrv = RTE_KDRV_IGB_UIO; + else if (iommu_mode == 1) + pci->kdrv = RTE_KDRV_UIO_GENERIC; - uio_num = ccp_find_uio_devname(dirname); - if (uio_num < 0) { - /* - * It may take time for uio device to appear, - * wait here and try again - */ - usleep(100000); - uio_num = ccp_find_uio_devname(dirname); - if (uio_num < 0) - goto fail; - } - snprintf(uio_devname, sizeof(uio_devname), "/dev/uio%u", uio_num); - - uio_fd = open(uio_devname, O_RDWR | O_NONBLOCK); - if (uio_fd < 0) - goto fail; - if (flock(uio_fd, LOCK_EX | LOCK_NB)) - goto fail; - - /* Map the PCI memory resource of device */ - for (i = 0; i < PCI_MAX_RESOURCE; i++) { - - char devname[PATH_MAX]; - int res_fd; - - if (pci->mem_resource[i].phys_addr == 0) - continue; - snprintf(devname, sizeof(devname), "%s/resource%d", dirname, i); - res_fd = open(devname, O_RDWR); - if (res_fd < 0) - goto fail; - map_addr = mmap(NULL, pci->mem_resource[i].len, - PROT_READ | PROT_WRITE, - MAP_SHARED, res_fd, 0); - if (map_addr == MAP_FAILED) - goto fail; - - pci->mem_resource[i].addr = map_addr; - } + rte_pci_map_device(pci); /* device is valid, add in list */ if (ccp_add_device(ccp_dev, ccp_type)) { @@ -783,7 +751,7 @@ ccp_probe_devices(const struct rte_pci_id *ccp_id) module_idx = ccp_check_pci_uio_module(); if (module_idx < 0) return -1; - + iommu_mode = module_idx; TAILQ_INIT(&ccp_list); dir = opendir(SYSFS_PCI_DEVICES); if (dir == NULL) diff --git a/drivers/crypto/ccp/ccp_dev.h b/drivers/crypto/ccp/ccp_dev.h index de3e4bcc6..f4ad9eafd 100644 --- a/drivers/crypto/ccp/ccp_dev.h +++ b/drivers/crypto/ccp/ccp_dev.h @@ -59,7 +59,7 @@ #define CMD_Q_RUN 0x1 #define CMD_Q_SIZE 0x1F #define CMD_Q_SHIFT 3 -#define COMMANDS_PER_QUEUE 2048 +#define COMMANDS_PER_QUEUE 8192 #define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \ CMD_Q_SIZE) diff --git a/drivers/crypto/ccp/ccp_pci.c b/drivers/crypto/ccp/ccp_pci.c index 1702a09c4..38029a908 100644 --- a/drivers/crypto/ccp/ccp_pci.c +++ b/drivers/crypto/ccp/ccp_pci.c @@ -15,6 +15,7 @@ static const char * const uio_module_names[] = { "igb_uio", "uio_pci_generic", + "vfio_pci" }; int diff --git a/drivers/crypto/ccp/ccp_pci.h b/drivers/crypto/ccp/ccp_pci.h index 7ed3bac40..bcde1d970 100644 --- a/drivers/crypto/ccp/ccp_pci.h +++ b/drivers/crypto/ccp/ccp_pci.h @@ -12,6 +12,7 @@ #define SYSFS_PCI_DEVICES "/sys/bus/pci/devices" #define PROC_MODULES "/proc/modules" + int ccp_check_pci_uio_module(void); int ccp_parse_pci_addr_format(const char *buf, int bufsize, uint16_t *domain, diff --git a/drivers/crypto/ccp/rte_ccp_pmd.c b/drivers/crypto/ccp/rte_ccp_pmd.c index 4810d799c..45221097d 100644 --- a/drivers/crypto/ccp/rte_ccp_pmd.c +++ b/drivers/crypto/ccp/rte_ccp_pmd.c @@ -22,6 +22,7 @@ */ static unsigned int ccp_pmd_init_done; uint8_t ccp_cryptodev_driver_id; +extern void *sha_ctx; struct ccp_pmd_init_params { struct rte_cryptodev_pmd_init_params def_p; @@ -279,6 +280,7 @@ cryptodev_ccp_remove(struct rte_vdev_device *dev) ccp_pmd_init_done = 0; name = rte_vdev_device_name(dev); + rte_free((void*) sha_ctx); if (name == NULL) return -EINVAL; @@ -296,7 +298,6 @@ cryptodev_ccp_create(const char *name, { struct rte_cryptodev *dev; struct ccp_private *internals; - uint8_t cryptodev_cnt = 0; if (init_params->def_p.name[0] == '\0') strlcpy(init_params->def_p.name, name, @@ -361,7 +362,7 @@ cryptodev_ccp_probe(struct rte_vdev_device *vdev) .auth_opt = CCP_PMD_AUTH_OPT_CCP, }; const char *input_args; - + sha_ctx = (void *)rte_malloc(NULL,SHA512_DIGEST_SIZE,64); if (ccp_pmd_init_done) { RTE_LOG(INFO, PMD, "CCP PMD already initialized\n"); return -EFAULT; From patchwork Mon Oct 14 05:22:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AMARANATH SOMALAPURAM X-Patchwork-Id: 61041 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1D6A11BEF2; Mon, 14 Oct 2019 07:22:27 +0200 (CEST) Received: from NAM01-BY2-obe.outbound.protection.outlook.com (mail-eopbgr810088.outbound.protection.outlook.com [40.107.81.88]) by dpdk.org (Postfix) with ESMTP id 246AE1B994; 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Mon, 14 Oct 2019 05:22:23 +0000 From: To: "dev@dpdk.org" CC: "stable@dpdk.org" Thread-Topic: [PATCH v1 6/6] crypto/ccp: fix for scheduling multiple CCP within single burst ccp driver was scheduling only one CCP in a single burst. Effective throughput was limited to 1 CCP performance. Scheduling multiple ccp within one burst will increase the c... Thread-Index: AQHVgk9cW5Hj9LWN6kWQSpCxowEkUA== Date: Mon, 14 Oct 2019 05:22:23 +0000 Message-ID: <20191014052202.12625-1-asomalap@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MAXPR0101CA0012.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:c::22) To DM5PR1201MB2474.namprd12.prod.outlook.com (2603:10b6:3:e3::8) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Amaranath.Somalapuram@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.156.251] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 33ddab40-ed84-44a2-dc15-08d750667e87 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: DM5PR1201MB0027: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:561; x-forefront-prvs: 01901B3451 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(346002)(376002)(39860400002)(136003)(396003)(366004)(199004)(189003)(1076003)(14454004)(5660300002)(2616005)(66066001)(486006)(4326008)(476003)(99286004)(256004)(66556008)(71200400001)(66476007)(64756008)(66946007)(66446008)(71190400001)(6436002)(478600001)(6512007)(5640700003)(2906002)(316002)(450100002)(7736002)(25786009)(2351001)(2501003)(6486002)(6916009)(386003)(6506007)(102836004)(26005)(52116002)(186003)(3846002)(6116002)(36756003)(305945005)(8676002)(50226002)(81156014)(1730700003)(8936002)(81166006)(219693003); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR1201MB0027; H:DM5PR1201MB2474.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: RU0d9WjILHdUuYmhmfuMYmMZpDG7ZFdnKqTX3ZSfKClRv92E+btNE6VFTfy7wgDJxUk+J4TD2SHiHBZ7Jd7Im1LJLT5CZQadzyOv2ZznWtkn1sLomv7m22m0qr7RwDlnzcvOij+z8c6ISjKmgRqEE7LCWDc+jbkZcEmkKl4Ae1eDCUAmGsWIBV1nbCsp1JB+8NNi8ATRQ9CfoZsz16rHCE2f+kZzvFimzws/XYOVL+3llFlEPGlcqRBTL+m4/OLY5YhQOjJrOvmJgNPSKAFXWGS2FhO/aDfCwSe+ydJ1bIzq9GaBDHAkQ4dMuEw5rJflBo6/oI415UT5oWaQAi9zpA5dhBOpPh+nHWbX8hVkgYo7eFqo7vBnJZ8djRLBNEQoz5frUugFntOGcX7ciZ1CxTcJu5ZAx50syARlkpoCCZI= x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 33ddab40-ed84-44a2-dc15-08d750667e87 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2019 05:22:23.7872 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: PKMVOSbuyrwbThQ6RX7ONrbCp6YBzlyLTOfDiolBCBWRrfuEankcLxC/+WLyqXK02UgVhItBEAGM6jXHAQRQew== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0027 Subject: [dpdk-dev] [PATCH v1 6/6] crypto/ccp: fix for scheduling multiple CCP within single burst ccp driver was scheduling only one CCP in a single burst. Effective throughput was limited to 1 CCP performance. Scheduling multiple ccp within one burst will increase the c... X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Amaranath Somalapuram Signed-off-by: Amaranath Somalapuram --- drivers/crypto/ccp/ccp_crypto.c | 22 ++++++---- drivers/crypto/ccp/ccp_crypto.h | 7 +++- drivers/crypto/ccp/ccp_pmd_private.h | 2 + drivers/crypto/ccp/rte_ccp_pmd.c | 63 ++++++++++++++++++++-------- 4 files changed, 68 insertions(+), 26 deletions(-) diff --git a/drivers/crypto/ccp/ccp_crypto.c b/drivers/crypto/ccp/ccp_crypto.c index c0ece4e37..26874117e 100644 --- a/drivers/crypto/ccp/ccp_crypto.c +++ b/drivers/crypto/ccp/ccp_crypto.c @@ -2816,7 +2816,9 @@ process_ops_to_enqueue(struct ccp_qp *qp, struct rte_crypto_op **op, struct ccp_queue *cmd_q, uint16_t nb_ops, - int slots_req) + uint16_t total_nb_ops, + int slots_req, + uint16_t b_idx) { int i, result = 0; struct ccp_batch_info *b_info; @@ -2837,6 +2839,7 @@ process_ops_to_enqueue(struct ccp_qp *qp, /* populate batch info necessary for dequeue */ b_info->op_idx = 0; + b_info->b_idx = 0; b_info->lsb_buf_idx = 0; b_info->desccnt = 0; b_info->cmd_q = cmd_q; @@ -2852,7 +2855,7 @@ process_ops_to_enqueue(struct ccp_qp *qp, b_info->head_offset = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE); - for (i = 0; i < nb_ops; i++) { + for (i = b_idx; i < (nb_ops+b_idx); i++) { session = (struct ccp_session *)get_sym_session_private_data( op[i]->sym->session, ccp_cryptodev_driver_id); @@ -2904,6 +2907,8 @@ process_ops_to_enqueue(struct ccp_qp *qp, } b_info->opcnt = i; + b_info->b_idx = b_idx; + b_info->total_nb_ops = total_nb_ops; b_info->tail_offset = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE); @@ -2918,7 +2923,7 @@ process_ops_to_enqueue(struct ccp_qp *qp, rte_ring_enqueue(qp->processed_pkts, (void *)b_info); EVP_MD_CTX_destroy(auth_ctx); - return i; + return i-b_idx; } static inline void ccp_auth_dq_prepare(struct rte_crypto_op *op) @@ -3003,8 +3008,8 @@ ccp_prepare_ops(struct ccp_qp *qp, } min_ops = RTE_MIN(nb_ops, b_info->opcnt); - for (i = 0; i < min_ops; i++) { - op_d[i] = b_info->op[b_info->op_idx++]; + for (i = b_info->b_idx; i < min_ops; i++) { + op_d[i] = b_info->op[b_info->b_idx + b_info->op_idx++]; session = (struct ccp_session *)get_sym_session_private_data( op_d[i]->sym->session, ccp_cryptodev_driver_id); @@ -3045,7 +3050,8 @@ ccp_prepare_ops(struct ccp_qp *qp, int process_ops_to_dequeue(struct ccp_qp *qp, struct rte_crypto_op **op, - uint16_t nb_ops) + uint16_t nb_ops, + uint16_t *total_nb_ops) { struct ccp_batch_info *b_info; uint32_t cur_head_offset; @@ -3060,6 +3066,7 @@ process_ops_to_dequeue(struct ccp_qp *qp, if (b_info->auth_ctr == b_info->opcnt) goto success; + *total_nb_ops = b_info->total_nb_ops; cur_head_offset = CCP_READ_REG(b_info->cmd_q->reg_base, CMD_Q_HEAD_LO_BASE); @@ -3069,7 +3076,7 @@ process_ops_to_dequeue(struct ccp_qp *qp, qp->b_info = b_info; return 0; } - } else { + } else if(b_info->tail_offset != b_info->head_offset) { if ((cur_head_offset >= b_info->head_offset) || (cur_head_offset < b_info->tail_offset)) { qp->b_info = b_info; @@ -3079,6 +3086,7 @@ process_ops_to_dequeue(struct ccp_qp *qp, success: + *total_nb_ops = b_info->total_nb_ops; nb_ops = ccp_prepare_ops(qp, op, b_info, nb_ops); rte_atomic64_add(&b_info->cmd_q->free_slots, b_info->desccnt); b_info->desccnt = 0; diff --git a/drivers/crypto/ccp/ccp_crypto.h b/drivers/crypto/ccp/ccp_crypto.h index 882b398ac..8e6d03efc 100644 --- a/drivers/crypto/ccp/ccp_crypto.h +++ b/drivers/crypto/ccp/ccp_crypto.h @@ -353,7 +353,9 @@ int process_ops_to_enqueue(struct ccp_qp *qp, struct rte_crypto_op **op, struct ccp_queue *cmd_q, uint16_t nb_ops, - int slots_req); + uint16_t total_nb_ops, + int slots_req, + uint16_t b_idx); /** * process crypto ops to be dequeued @@ -365,7 +367,8 @@ int process_ops_to_enqueue(struct ccp_qp *qp, */ int process_ops_to_dequeue(struct ccp_qp *qp, struct rte_crypto_op **op, - uint16_t nb_ops); + uint16_t nb_ops, + uint16_t *total_nb_ops); /** diff --git a/drivers/crypto/ccp/ccp_pmd_private.h b/drivers/crypto/ccp/ccp_pmd_private.h index 781050c31..1c4118ee3 100644 --- a/drivers/crypto/ccp/ccp_pmd_private.h +++ b/drivers/crypto/ccp/ccp_pmd_private.h @@ -50,8 +50,10 @@ struct ccp_batch_info { struct rte_crypto_op *op[CCP_MAX_BURST]; /**< optable populated at enque time from app*/ int op_idx; + uint16_t b_idx; struct ccp_queue *cmd_q; uint16_t opcnt; + uint16_t total_nb_ops; /**< no. of crypto ops in batch*/ int desccnt; /**< no. of ccp queue descriptors*/ diff --git a/drivers/crypto/ccp/rte_ccp_pmd.c b/drivers/crypto/ccp/rte_ccp_pmd.c index 45221097d..b778cd11c 100644 --- a/drivers/crypto/ccp/rte_ccp_pmd.c +++ b/drivers/crypto/ccp/rte_ccp_pmd.c @@ -23,6 +23,7 @@ static unsigned int ccp_pmd_init_done; uint8_t ccp_cryptodev_driver_id; extern void *sha_ctx; +uint8_t cryptodev_cnt = 0; struct ccp_pmd_init_params { struct rte_cryptodev_pmd_init_params def_p; @@ -202,30 +203,50 @@ ccp_pmd_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops, struct ccp_queue *cmd_q; struct rte_cryptodev *dev = qp->dev; uint16_t i, enq_cnt = 0, slots_req = 0; + uint16_t tmp_ops = nb_ops,b_idx,cur_ops=0; if (nb_ops == 0) return 0; if (unlikely(rte_ring_full(qp->processed_pkts) != 0)) return 0; + if(tmp_ops >= cryptodev_cnt) + { + cur_ops = nb_ops / cryptodev_cnt+ (nb_ops)%cryptodev_cnt ; + } + else + cur_ops = tmp_ops; + while(tmp_ops) + { + b_idx = nb_ops - tmp_ops; + slots_req = 0; + if(cur_ops <= tmp_ops ) + { + tmp_ops -= cur_ops; + } + else + { + cur_ops = tmp_ops; + tmp_ops = 0; + } + for (i = 0; i < cur_ops; i++) { + sess = get_ccp_session(qp, ops[i + b_idx]); + if (unlikely(sess == NULL) && (i == 0)) { + qp->qp_stats.enqueue_err_count++; + return 0; + } else if (sess == NULL) { + cur_ops = i; + break; + } + slots_req += ccp_compute_slot_count(sess); + } - for (i = 0; i < nb_ops; i++) { - sess = get_ccp_session(qp, ops[i]); - if (unlikely(sess == NULL) && (i == 0)) { - qp->qp_stats.enqueue_err_count++; + cmd_q = ccp_allot_queue(dev, slots_req); + if (unlikely(cmd_q == NULL)) return 0; - } else if (sess == NULL) { - nb_ops = i; - break; - } - slots_req += ccp_compute_slot_count(sess); + enq_cnt += process_ops_to_enqueue(qp, ops, cmd_q, cur_ops, nb_ops, slots_req, b_idx); + i++; } - - cmd_q = ccp_allot_queue(dev, slots_req); - if (unlikely(cmd_q == NULL)) - return 0; - - enq_cnt = process_ops_to_enqueue(qp, ops, cmd_q, nb_ops, slots_req); qp->qp_stats.enqueued_count += enq_cnt; return enq_cnt; } @@ -235,9 +256,17 @@ ccp_pmd_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops, uint16_t nb_ops) { struct ccp_qp *qp = queue_pair; - uint16_t nb_dequeued = 0, i; + uint16_t nb_dequeued = 0, i, total_nb_ops; + + nb_dequeued = process_ops_to_dequeue(qp, ops, nb_ops,&total_nb_ops); - nb_dequeued = process_ops_to_dequeue(qp, ops, nb_ops); + if(total_nb_ops) + { + while(nb_dequeued != total_nb_ops) + { + nb_dequeued = process_ops_to_dequeue(qp, ops, nb_ops,&total_nb_ops); + } + } /* Free session if a session-less crypto op */ for (i = 0; i < nb_dequeued; i++)