From patchwork Mon Oct 14 04:29:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kiran Kumar Kokkilagadda X-Patchwork-Id: 61035 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 90A441C129; Mon, 14 Oct 2019 06:30:12 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id E657F1C125 for ; Mon, 14 Oct 2019 06:30:10 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9E4TUqv002263; Sun, 13 Oct 2019 21:30:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0818; bh=YU7w6UGwUgRzLodDgL5RjxeEejbTKMPbVy6pbimwtdg=; b=MT3rYAJBuUK4ta9Y5Un/8lrw78PHBVDa22LQh2wHWtKhaiy3zz/glVw0Q62h2OaL1j6X zBsosTtUvniovbhDDYbqcNhDtvAqDAu/H7z7AAhk1D0sB72/BNTAfB8DV5jY1nRLU+sZ UN/l306HPYCa9JURzw17nNRd8Cguw+gePmNAPF9JijJDV59cghCNOUGL87Ghd1RIfALM LczNXulQIIZ5eHmR2KS1+jcPE8HhbfheuHR3okXGt7+wsdbtsetUu05TP/BtexwsrzaD mtSIRPSogWP8yMufRdLKhicxNs5uXBSF2TTsO/CqacikforhWzFgZmJdDZ/LY4MJZgTx Dg== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2vkebnvfr7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 13 Oct 2019 21:30:05 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 13 Oct 2019 21:30:03 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sun, 13 Oct 2019 21:30:03 -0700 Received: from localhost.localdomain (unknown [10.28.34.15]) by maili.marvell.com (Postfix) with ESMTP id 71D0C3F703F; Sun, 13 Oct 2019 21:30:00 -0700 (PDT) From: To: Adrien Mazarguil , John McNamara , Marko Kovacevic , Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko CC: , , Kiran Kumar K Date: Mon, 14 Oct 2019 09:59:56 +0530 Message-ID: <20191014042956.18616-1-kirankumark@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-14_03:2019-10-10,2019-10-14 signatures=0 Subject: [dpdk-dev] [PATCH] ethdev: add HIGIG2 key field to flow API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar K Add new rte_flow_item_higig2_hdr in order to match higig2 header. It is a layer 2.5 protocol and used in broadcom switches. Header format is based on the following document. http://read.pudn.com/downloads558/doc/comm/2301468/HiGig_protocol.pdf Signed-off-by: Kiran Kumar K --- doc/guides/prog_guide/rte_flow.rst | 8 ++++ lib/librte_ethdev/rte_flow.c | 1 + lib/librte_ethdev/rte_flow.h | 77 ++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index 1c837ff13..71365b159 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -1290,6 +1290,14 @@ Matches a IP Authentication Header (RFC 4302). - Default ``mask`` matches spi. +Item: ``HIGIG2`` +^^^^^^^^^^^^^^^^^ + +Matches a HIGIG2 header field. It is layer 2.5 protocol and used in +broadcom switches. + +- Default ``mask`` matches classification and vlan. + Actions ~~~~~~~ diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c index 81a85b995..ca0f68016 100644 --- a/lib/librte_ethdev/rte_flow.c +++ b/lib/librte_ethdev/rte_flow.c @@ -83,6 +83,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = { MK_FLOW_ITEM(NSH, sizeof(struct rte_flow_item_nsh)), MK_FLOW_ITEM(IGMP, sizeof(struct rte_flow_item_igmp)), MK_FLOW_ITEM(AH, sizeof(struct rte_flow_item_ah)), + MK_FLOW_ITEM(HIGIG2, sizeof(struct rte_flow_item_higig2_hdr)), }; /** Generate flow_action[] entry. */ diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h index bcfc06cdc..59e37f714 100644 --- a/lib/librte_ethdev/rte_flow.h +++ b/lib/librte_ethdev/rte_flow.h @@ -491,6 +491,12 @@ enum rte_flow_item_type { * */ RTE_FLOW_ITEM_TYPE_AH, + + /** + * Matches a HIGIG header. + * see struct rte_flow_item_higig2_hdr. + */ + RTE_FLOW_ITEM_TYPE_HIGIG2, }; /** @@ -515,6 +521,77 @@ static const struct rte_flow_item_any rte_flow_item_any_mask = { }; #endif +/** + * RTE_FLOW_ITEM_TYPE_HIGIG2 + * Matches higig2 header. + */ +struct rte_higig2_frc { + uint32_t ksop:8; + uint32_t resv:3; + uint32_t mcst:1; + uint32_t tc:4; + uint32_t dst_modid:8; + uint32_t dst_pid:8; + uint32_t src_modid:8; + uint32_t src_pid:8; + uint32_t lbid:8; + uint32_t dp:2; + uint32_t resv1:3; + uint32_t ppd_type:3; +} __attribute__((packed)); + +struct rte_higig2_ppt_type0 { + uint32_t dst_t:1; + uint32_t dst_tgid:3; + uint32_t ingress_tagged:1; + uint32_t mirror_only:1; + uint32_t mirror_done:1; + uint32_t mirror:1; + uint32_t res:2; + uint32_t l3:1; + uint32_t label_present:1; + uint32_t vc_label2:4; + uint32_t vc_label1:8; + uint32_t vc_label0:8; + uint32_t vid_high:8; + uint32_t vid_low:8; + uint32_t pfm:2; + uint32_t src_t:1; + uint32_t res1:2; + uint32_t opcode:3; + uint32_t hdr_ext_len:3; + uint32_t res2:5; +} __attribute__((packed)); + +struct rte_higig2_ppt_type1 { + uint32_t classification:16; + uint32_t resv:16; + uint32_t vid:16; + uint32_t pfm:2; + uint32_t src_t:1; + uint32_t resv1:2; + uint32_t opcode:3; + uint32_t hdr_ext_len:3; + uint32_t resv2:5; +} __attribute__((packed)); + +RTE_STD_C11 +struct rte_flow_item_higig2_hdr { + struct rte_higig2_frc fcr; + union { + struct rte_higig2_ppt_type0 ppt0; + struct rte_higig2_ppt_type1 ppt1; + }; +} __attribute__((packed)); + +/** Default mask for RTE_FLOW_ITEM_TYPE_HIGIG2. */ +#ifndef __cplusplus +static const struct rte_flow_item_higig2_hdr rte_flow_item_higig2_hdr_mask = { + .ppt1.classification = 0xffff, + .ppt1.vid = 0xfff, +}; +#endif + /** * RTE_FLOW_ITEM_TYPE_VF *