From patchwork Fri Sep 27 04:16:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59939 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 861672C08; Fri, 27 Sep 2019 06:13:58 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 43E86271 for ; Fri, 27 Sep 2019 06:13:55 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2019 21:13:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,554,1559545200"; d="scan'208";a="219641142" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga002.fm.intel.com with ESMTP; 26 Sep 2019 21:13:53 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Fri, 27 Sep 2019 12:16:39 +0800 Message-Id: <20190927041646.34712-2-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190927041646.34712-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190927041646.34712-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 1/8] net/ice/base: fix for adding PPPoE switch rule X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Update VLAN protocol ID to correct value for single VXLAN scenario. Correct the PPPOE training packet. Fixes: d341bdc30290 ("net/ice/base: add support for GTP and PPPoE protocols") Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Tested-by: Wei Zhao --- drivers/net/ice/base/ice_protocol_type.h | 2 +- drivers/net/ice/base/ice_switch.c | 12 +++++++----- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index f61345a7f..548c9730a 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -118,7 +118,7 @@ enum ice_prot_id { #define ICE_MAC_OFOS_HW 1 #define ICE_MAC_IL_HW 4 #define ICE_ETYPE_OL_HW 9 -#define ICE_VLAN_OL_HW 16 +#define ICE_VLAN_OL_HW 17 #define ICE_IPV4_OFOS_HW 32 #define ICE_IPV4_IL_HW 33 #define ICE_IPV6_OFOS_HW 40 diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 80afa74cd..a72f4b430 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -433,16 +433,18 @@ dummy_pppoe_packet[] = { 0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 14 */ - 0x11, 0x00, 0x00, 0x01, /* ICE_PPPOE 18 */ - 0x00, 0x4e, 0x00, 0x21, + 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */ + 0x00, 0x16, - 0x45, 0x00, 0x00, 0x30, /* PDU */ + 0x00, 0x21, /* PPP Link Layer 24 */ + + 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 26 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, /* 2 bytes for 4 byte alignment */ + 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; /* this is a recipe to profile association bitmap */ From patchwork Fri Sep 27 04:16:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59940 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 478142C0C; Fri, 27 Sep 2019 06:14:14 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 3C51A28EE for ; Fri, 27 Sep 2019 06:13:56 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2019 21:13:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,554,1559545200"; d="scan'208";a="219641158" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga002.fm.intel.com with ESMTP; 26 Sep 2019 21:13:54 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Fri, 27 Sep 2019 12:16:40 +0800 Message-Id: <20190927041646.34712-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190927041646.34712-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190927041646.34712-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 2/8] net/ice/base: fix for NVGRE switch rule programming X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Correct for GRE/NVGRE training packets to include the correct protocol IDs for TCP and UDP respectively. Fixes: b83a0c290322 ("net/ice/base: fix inner TCP and UDP support for GRE") Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Tested-by: Wei Zhao --- drivers/net/ice/base/ice_switch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index a72f4b430..c22235b68 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -93,7 +93,7 @@ u8 dummy_gre_tcp_packet[] = { 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 56 */ 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, + 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -140,7 +140,7 @@ u8 dummy_gre_udp_packet[] = { 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 56 */ 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, From patchwork Fri Sep 27 04:16:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59941 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C59F42C38; Fri, 27 Sep 2019 06:14:16 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 069E328EE for ; Fri, 27 Sep 2019 06:13:57 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2019 21:13:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,554,1559545200"; d="scan'208";a="219641168" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga002.fm.intel.com with ESMTP; 26 Sep 2019 21:13:56 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Fri, 27 Sep 2019 12:16:41 +0800 Message-Id: <20190927041646.34712-4-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190927041646.34712-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190927041646.34712-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 3/8] net/ice/base: update flow ptype bitmaps X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In the flow api, the outer first ptype bitmaps contained many references to inner ptypes. Because of PTG assignments, these were causing issues when programming rules on the inner ptypes. For example, in RSS when programming the outer IPV6 hash fields, it also programmed several inner IPV4 PTGs with the same extraction. There were several ptypes that have been removed, thus this patch removes those bits from the type bitmaps. Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index e03c5d0e7..8ed3f8eb7 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -141,9 +141,9 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { * Packet types for packets with an Outer/First/Single MAC header */ static const u32 ice_ptypes_mac_ofos[] = { - 0xFDC00CC6, 0xBFBF7F7E, 0xF7EFDFDF, 0xFEFDFDFB, - 0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000, - 0x000B0F0F, 0x00003000, 0x00000000, 0x00000000, + 0xFDC00846, 0xBFBF7F7E, 0xF70001DF, 0xFEFDFDFB, + 0x0000077E, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00003000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -165,9 +165,9 @@ static const u32 ice_ptypes_macvlan_il[] = { /* Packet types for packets with an Outer/First/Single IPv4 header */ static const u32 ice_ptypes_ipv4_ofos[] = { - 0xFDC00000, 0xBFBF7F7E, 0x00EFDFDF, 0x00000000, + 0x1DC00000, 0x04000800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x0003000F, 0x000FC000, 0x00000000, 0x00000000, + 0x00000000, 0x000FC000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -189,9 +189,9 @@ static const u32 ice_ptypes_ipv4_il[] = { /* Packet types for packets with an Outer/First/Single IPv6 header */ static const u32 ice_ptypes_ipv6_ofos[] = { - 0x00000000, 0x00000000, 0xF7000000, 0xFEFDFDFB, - 0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000, - 0x00080F00, 0x03F00000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x77000000, 0x10002000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x03F00000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -201,8 +201,8 @@ static const u32 ice_ptypes_ipv6_ofos[] = { /* Packet types for packets with an Innermost/Last IPv6 header */ static const u32 ice_ptypes_ipv6_il[] = { - 0x00000000, 0x03B80770, 0x00EE01DC, 0x0EE00000, - 0x03B80770, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x03B80770, 0x000001DC, 0x0EE00000, + 0x00000770, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7FE00000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -228,7 +228,7 @@ static const u32 ice_ptypes_arp_of[] = { */ static const u32 ice_ptypes_udp_il[] = { 0x81000000, 0x20204040, 0x04000010, 0x80810102, - 0x00200040, 0x00000000, 0x00000000, 0x00000000, + 0x00000040, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00410000, 0x10842000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -240,7 +240,7 @@ static const u32 ice_ptypes_udp_il[] = { /* Packet types for packets with an Innermost/Last TCP header */ static const u32 ice_ptypes_tcp_il[] = { 0x04000000, 0x80810102, 0x10000040, 0x02040408, - 0x00810102, 0x00000000, 0x00000000, 0x00000000, + 0x00000102, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00820000, 0x21084000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -252,7 +252,7 @@ static const u32 ice_ptypes_tcp_il[] = { /* Packet types for packets with an Innermost/Last SCTP header */ static const u32 ice_ptypes_sctp_il[] = { 0x08000000, 0x01020204, 0x20000081, 0x04080810, - 0x01020204, 0x00000000, 0x00000000, 0x00000000, + 0x00000204, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01040000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -275,8 +275,8 @@ static const u32 ice_ptypes_icmp_of[] = { /* Packet types for packets with an Innermost/Last ICMP header */ static const u32 ice_ptypes_icmp_il[] = { - 0x00000000, 0x02040408, 0x40810102, 0x08101020, - 0x02040408, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x02040408, 0x40000102, 0x08101020, + 0x00000408, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x42108000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -287,8 +287,8 @@ static const u32 ice_ptypes_icmp_il[] = { /* Packet types for packets with an Outermost/First GRE header */ static const u32 ice_ptypes_gre_of[] = { - 0x00000000, 0xBFBF7800, 0x00EFDFDF, 0xFEFDE000, - 0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xBFBF7800, 0x000001DF, 0xFEFDE000, + 0x0000017E, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -299,8 +299,8 @@ static const u32 ice_ptypes_gre_of[] = { /* Packet types for packets with an Innermost/Last MAC header */ static const u32 ice_ptypes_mac_il[] = { - 0x00000000, 0x00000000, 0x00EFDE00, 0x00000000, - 0x03BF7800, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, From patchwork Fri Sep 27 04:16:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59942 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1A5EB2C57; Fri, 27 Sep 2019 06:14:19 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 6E83F28EE for ; Fri, 27 Sep 2019 06:13:59 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2019 21:13:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,554,1559545200"; d="scan'208";a="219641176" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga002.fm.intel.com with ESMTP; 26 Sep 2019 21:13:57 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Junfeng Guo , Paul M Stillwell Jr Date: Fri, 27 Sep 2019 12:16:42 +0800 Message-Id: <20190927041646.34712-5-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190927041646.34712-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190927041646.34712-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 4/8] net/ice/base: add GTPU TEID support for FD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added the training packet for GTPU TEID field to the Flow director to allow matching against this field. Signed-off-by: Junfeng Guo Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 2 ++ drivers/net/ice/base/ice_fdir.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 219588c46..37b388169 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -786,6 +786,8 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP: case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP: case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER: + ice_pkt_insert_u32(loc, ICE_IPV4_GTPU_TEID_OFFSET, + input->gtpu_data.teid); ice_pkt_insert_u6_qfi(loc, ICE_IPV4_GTPU_QFI_OFFSET, input->gtpu_data.qfi); break; diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index 22e5bcf8c..db1f8351f 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -87,6 +87,7 @@ enum ice_status ice_clear_pf_fd_table(struct ice_hw *hw); #define ICE_IPV6_TC_OFFSET 14 #define ICE_IPV6_HLIM_OFFSET 21 #define ICE_IPV6_PROTO_OFFSET 20 +#define ICE_IPV4_GTPU_TEID_OFFSET 46 #define ICE_IPV4_GTPU_QFI_OFFSET 56 #define ICE_FDIR_MAX_FLTRS 16384 From patchwork Fri Sep 27 04:16:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59943 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 416FB2C6A; Fri, 27 Sep 2019 06:14:22 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 3A51A2C16 for ; Fri, 27 Sep 2019 06:14:01 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2019 21:14:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,554,1559545200"; d="scan'208";a="219641185" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga002.fm.intel.com with ESMTP; 26 Sep 2019 21:13:59 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Fri, 27 Sep 2019 12:16:43 +0800 Message-Id: <20190927041646.34712-6-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190927041646.34712-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190927041646.34712-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 5/8] net/ice/base: improvements to Flow Director masking X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, 3-tuple FD matching is implemented using masking. However, this is using up twenty-four of the thirty-two FD masks available. This patch uses the swap register more efficiently to implement the 3-tuple matches, which saves all FD masks for other uses. Added IPV6 versions of DSCP, TTL and Protocol fields for FD use. Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flex_pipe.c | 71 +++++++++------------ drivers/net/ice/base/ice_flex_type.h | 4 +- drivers/net/ice/base/ice_flow.c | 118 ++++++++++++++++++++--------------- drivers/net/ice/base/ice_flow.h | 10 ++- 4 files changed, 108 insertions(+), 95 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 75bb87079..8f8cab86e 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1248,25 +1248,6 @@ void ice_free_seg(struct ice_hw *hw) } /** - * ice_init_fd_mask_regs - initialize Flow Director mask registers - * @hw: pointer to the HW struct - * - * This function sets up the Flow Director mask registers to allow for complete - * masking off of any of the 24 Field Vector words. After this call, mask 0 will - * mask off all of FV index 0, mask 1 will mask off all of FV index 1, etc. - */ -static void ice_init_fd_mask_regs(struct ice_hw *hw) -{ - u16 i; - - for (i = 0; i < hw->blk[ICE_BLK_FD].es.fvw; i++) { - wr32(hw, GLQF_FDMASK(i), i); - ice_debug(hw, ICE_DBG_INIT, "init fd mask(%d): %x = %x\n", i, - GLQF_FDMASK(i), i); - } -} - -/** * ice_init_pkg_regs - initialize additional package registers * @hw: pointer to the hardware structure */ @@ -1279,8 +1260,6 @@ static void ice_init_pkg_regs(struct ice_hw *hw) /* setup Switch block input mask, which is 48-bits in two parts */ wr32(hw, GL_PREEXT_L2_PMASK0(ICE_SW_BLK_IDX), ICE_SW_BLK_INP_MASK_L); wr32(hw, GL_PREEXT_L2_PMASK1(ICE_SW_BLK_IDX), ICE_SW_BLK_INP_MASK_H); - /* setup default flow director masks */ - ice_init_fd_mask_regs(hw); } /** @@ -2643,7 +2622,8 @@ ice_prof_has_mask_idx(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 idx, expect_no_mask = true; /* Scan the enabled masks on this profile, for the specified idx */ - for (i = 0; i < ICE_PROFILE_MASK_COUNT; i++) + for (i = hw->blk[blk].masks.first; i < hw->blk[blk].masks.first + + hw->blk[blk].masks.count; i++) if (hw->blk[blk].es.mask_ena[prof] & BIT(i)) if (hw->blk[blk].masks.masks[i].in_use && hw->blk[blk].masks.masks[i].idx == idx) { @@ -2981,14 +2961,15 @@ ice_write_prof_mask_enable_res(struct ice_hw *hw, enum ice_block blk, */ static void ice_init_prof_masks(struct ice_hw *hw, enum ice_block blk) { -#define MAX_NUM_PORTS 8 - u16 num_ports = MAX_NUM_PORTS; + u16 per_pf; u16 i; ice_init_lock(&hw->blk[blk].masks.lock); - hw->blk[blk].masks.count = ICE_PROFILE_MASK_COUNT / num_ports; - hw->blk[blk].masks.first = hw->pf_id * hw->blk[blk].masks.count; + per_pf = ICE_PROF_MASK_COUNT / hw->dev_caps.num_funcs; + + hw->blk[blk].masks.count = per_pf; + hw->blk[blk].masks.first = hw->pf_id * per_pf; ice_memset(hw->blk[blk].masks.masks, 0, sizeof(hw->blk[blk].masks.masks), ICE_NONDMA_MEM); @@ -4241,8 +4222,6 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es) ice_zero_bitmap(pair_list, ICE_FD_SRC_DST_PAIR_COUNT); - ice_init_fd_mask_regs(hw); - /* This code assumes that the Flow Director field vectors are assigned * from the end of the FV indexes working towards the zero index, that * only complete fields will be included and will be consecutive, and @@ -4298,7 +4277,7 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es) return ICE_ERR_OUT_OF_RANGE; /* keep track of non-relevant fields */ - mask_sel |= 1 << (first_free - k); + mask_sel |= BIT(first_free - k); } pair_start[index] = first_free; @@ -4342,29 +4321,39 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es) si -= indexes_used; } - /* for each set of 4 swap indexes, write the appropriate register */ + /* for each set of 4 swap and 4 inset indexes, write the appropriate + * register + */ for (j = 0; j < hw->blk[ICE_BLK_FD].es.fvw / 4; j++) { - u32 raw_entry = 0; + u32 raw_swap = 0; + u32 raw_in = 0; for (k = 0; k < 4; k++) { u8 idx; idx = (j * 4) + k; - if (used[idx]) - raw_entry |= used[idx] << (k * BITS_PER_BYTE); + if (used[idx] && !(mask_sel & BIT(idx))) { + raw_swap |= used[idx] << (k * BITS_PER_BYTE); +#define ICE_INSET_DFLT 0x9f + raw_in |= ICE_INSET_DFLT << (k * BITS_PER_BYTE); + } } - /* write the appropriate register set, based on HW block */ - wr32(hw, GLQF_FDSWAP(prof_id, j), raw_entry); + /* write the appropriate swap register set */ + wr32(hw, GLQF_FDSWAP(prof_id, j), raw_swap); + + ice_debug(hw, ICE_DBG_INIT, "swap wr(%d, %d): %x = %08x\n", + prof_id, j, GLQF_FDSWAP(prof_id, j), raw_swap); - ice_debug(hw, ICE_DBG_INIT, "swap wr(%d, %d): %x = %x\n", - prof_id, j, GLQF_FDSWAP(prof_id, j), raw_entry); + /* write the appropriate inset register set */ + wr32(hw, GLQF_FDINSET(prof_id, j), raw_in); + + ice_debug(hw, ICE_DBG_INIT, "inset wr(%d, %d): %x = %08x\n", + prof_id, j, GLQF_FDINSET(prof_id, j), raw_in); } - /* update the masks for this profile to be sure we ignore fields that - * are not relevant to our match criteria - */ - ice_update_fd_mask(hw, prof_id, mask_sel); + /* initially clear the mask select for this profile */ + ice_update_fd_mask(hw, prof_id, 0); return ICE_SUCCESS; } diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 48c1e5184..92d205ac7 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -668,8 +668,8 @@ struct ice_masks { struct ice_lock lock; /* lock to protect this structure */ u16 first; /* first mask owned by the PF */ u16 count; /* number of masks owned by the PF */ -#define ICE_PROFILE_MASK_COUNT 32 - struct ice_mask masks[ICE_PROFILE_MASK_COUNT]; +#define ICE_PROF_MASK_COUNT 32 + struct ice_mask masks[ICE_PROF_MASK_COUNT]; }; /* Tables per block */ diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 8ed3f8eb7..370ad9ba3 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -22,15 +22,6 @@ #define ICE_FLOW_FLD_SZ_GTP_TEID 4 #define ICE_FLOW_FLD_SZ_PPPOE_SESS_ID 2 -/* Protocol header fields are extracted at the word boundaries as word-sized - * values. Specify the displacement value of some non-word-aligned fields needed - * to compute the offset of words containing the fields in the corresponding - * protocol headers. Displacement values are expressed in number of bits. - */ -#define ICE_FLOW_FLD_IPV6_TTL_DSCP_DISP (-4) -#define ICE_FLOW_FLD_IPV6_TTL_PROT_DISP ((-2) * BITS_PER_BYTE) -#define ICE_FLOW_FLD_IPV6_TTL_TTL_DISP ((-1) * BITS_PER_BYTE) - /* Describe properties of a protocol header field */ struct ice_flow_field_info { enum ice_flow_seg_hdr hdr; @@ -67,18 +58,29 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_VLAN, 14, ICE_FLOW_FLD_SZ_VLAN), /* ICE_FLOW_FIELD_IDX_ETH_TYPE */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ETH, 12, ICE_FLOW_FLD_SZ_ETH_TYPE), - /* IPv4 */ - /* ICE_FLOW_FIELD_IDX_IP_DSCP */ - ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV4, 1, 1), - /* ICE_FLOW_FIELD_IDX_IP_TTL */ - ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_NONE, 8, 1), - /* ICE_FLOW_FIELD_IDX_IP_PROT */ - ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_NONE, 9, ICE_FLOW_FLD_SZ_IP_PROT), + /* IPv4 / IPv6 */ + /* ICE_FLOW_FIELD_IDX_IPV4_DSCP */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_IPV4, 0, ICE_FLOW_FLD_SZ_IP_DSCP, + 0x00fc), + /* ICE_FLOW_FIELD_IDX_IPV6_DSCP */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_IPV6, 0, ICE_FLOW_FLD_SZ_IP_DSCP, + 0x0ff0), + /* ICE_FLOW_FIELD_IDX_IPV4_TTL */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_NONE, 8, + ICE_FLOW_FLD_SZ_IP_TTL, 0xff00), + /* ICE_FLOW_FIELD_IDX_IPV4_PROT */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_NONE, 8, + ICE_FLOW_FLD_SZ_IP_PROT, 0x00ff), + /* ICE_FLOW_FIELD_IDX_IPV6_TTL */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_NONE, 6, + ICE_FLOW_FLD_SZ_IP_TTL, 0x00ff), + /* ICE_FLOW_FIELD_IDX_IPV6_PROT */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_NONE, 6, + ICE_FLOW_FLD_SZ_IP_PROT, 0xff00), /* ICE_FLOW_FIELD_IDX_IPV4_SA */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV4, 12, ICE_FLOW_FLD_SZ_IPV4_ADDR), /* ICE_FLOW_FIELD_IDX_IPV4_DA */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV4, 16, ICE_FLOW_FLD_SZ_IPV4_ADDR), - /* IPv6 */ /* ICE_FLOW_FIELD_IDX_IPV6_SA */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV6, 8, ICE_FLOW_FLD_SZ_IPV6_ADDR), /* ICE_FLOW_FIELD_IDX_IPV6_DA */ @@ -608,6 +610,7 @@ ice_flow_xtract_pkt_flags(struct ice_hw *hw, * @params: information about the flow to be processed * @seg: packet segment index of the field to be extracted * @fld: ID of field to be extracted + * @match: bitfield of all fields * * This function determines the protocol ID, offset, and size of the given * field. It then allocates one or more extraction sequence entries for the @@ -615,13 +618,14 @@ ice_flow_xtract_pkt_flags(struct ice_hw *hw, */ static enum ice_status ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, - u8 seg, enum ice_flow_field fld) + u8 seg, enum ice_flow_field fld, u64 match) { enum ice_flow_field sib = ICE_FLOW_FIELD_IDX_MAX; enum ice_prot_id prot_id = ICE_PROT_ID_INVAL; u8 fv_words = hw->blk[params->blk].es.fvw; struct ice_flow_fld_info *flds; u16 cnt, ese_bits, i; + u16 sib_mask = 0; s16 adj = 0; u16 mask; u16 off; @@ -638,35 +642,49 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, case ICE_FLOW_FIELD_IDX_ETH_TYPE: prot_id = seg == 0 ? ICE_PROT_ETYPE_OL : ICE_PROT_ETYPE_IL; break; - case ICE_FLOW_FIELD_IDX_IP_DSCP: - if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_IPV6) - adj = ICE_FLOW_FLD_IPV6_TTL_DSCP_DISP; - /* Fall through */ - case ICE_FLOW_FIELD_IDX_IP_TTL: - case ICE_FLOW_FIELD_IDX_IP_PROT: - /* Some fields are located at different offsets in IPv4 and - * IPv6 + case ICE_FLOW_FIELD_IDX_IPV4_DSCP: + prot_id = seg == 0 ? ICE_PROT_IPV4_OF_OR_S : ICE_PROT_IPV4_IL; + break; + case ICE_FLOW_FIELD_IDX_IPV6_DSCP: + prot_id = seg == 0 ? ICE_PROT_IPV6_OF_OR_S : ICE_PROT_IPV6_IL; + break; + case ICE_FLOW_FIELD_IDX_IPV4_TTL: + case ICE_FLOW_FIELD_IDX_IPV4_PROT: + prot_id = seg == 0 ? ICE_PROT_IPV4_OF_OR_S : ICE_PROT_IPV4_IL; + + /* TTL and PROT share the same extraction seq. entry. + * Each is considered a sibling to the other in terms of sharing + * the same extraction sequence entry. */ - if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_IPV4) { - prot_id = seg == 0 ? ICE_PROT_IPV4_OF_OR_S : - ICE_PROT_IPV4_IL; - /* TTL and PROT share the same extraction seq. entry. - * Each is considered a sibling to the other in term - * sharing the same extraction sequence entry. - */ - if (fld == ICE_FLOW_FIELD_IDX_IP_TTL) - sib = ICE_FLOW_FIELD_IDX_IP_PROT; - else if (fld == ICE_FLOW_FIELD_IDX_IP_PROT) - sib = ICE_FLOW_FIELD_IDX_IP_TTL; - } else if (params->prof->segs[seg].hdrs & - ICE_FLOW_SEG_HDR_IPV6) { - prot_id = seg == 0 ? ICE_PROT_IPV6_OF_OR_S : - ICE_PROT_IPV6_IL; - if (fld == ICE_FLOW_FIELD_IDX_IP_TTL) - adj = ICE_FLOW_FLD_IPV6_TTL_TTL_DISP; - else if (fld == ICE_FLOW_FIELD_IDX_IP_PROT) - adj = ICE_FLOW_FLD_IPV6_TTL_PROT_DISP; - } + if (fld == ICE_FLOW_FIELD_IDX_IPV4_TTL) + sib = ICE_FLOW_FIELD_IDX_IPV4_PROT; + else if (fld == ICE_FLOW_FIELD_IDX_IPV4_PROT) + sib = ICE_FLOW_FIELD_IDX_IPV4_TTL; + + /* If the sibling field is also included, that field's + * mask needs to be included. + */ + if (match & BIT(sib)) + sib_mask = ice_flds_info[sib].mask; + break; + case ICE_FLOW_FIELD_IDX_IPV6_TTL: + case ICE_FLOW_FIELD_IDX_IPV6_PROT: + prot_id = seg == 0 ? ICE_PROT_IPV6_OF_OR_S : ICE_PROT_IPV6_IL; + + /* TTL and PROT share the same extraction seq. entry. + * Each is considered a sibling to the other in terms of sharing + * the same extraction sequence entry. + */ + if (fld == ICE_FLOW_FIELD_IDX_IPV6_TTL) + sib = ICE_FLOW_FIELD_IDX_IPV6_PROT; + else if (fld == ICE_FLOW_FIELD_IDX_IPV6_PROT) + sib = ICE_FLOW_FIELD_IDX_IPV6_TTL; + + /* If the sibling field is also included, that field's + * mask needs to be included. + */ + if (match & BIT(sib)) + sib_mask = ice_flds_info[sib].mask; break; case ICE_FLOW_FIELD_IDX_IPV4_SA: case ICE_FLOW_FIELD_IDX_IPV4_DA: @@ -733,6 +751,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, ICE_FLOW_FV_EXTRACT_SZ; flds[fld].xtrct.disp = (u8)((ice_flds_info[fld].off + adj) % ese_bits); flds[fld].xtrct.idx = params->es_cnt; + flds[fld].xtrct.mask = ice_flds_info[fld].mask; /* Adjust the next field-entry index after accommodating the number of * entries this field consumes @@ -742,7 +761,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, /* Fill in the extraction sequence entries needed for this field */ off = flds[fld].xtrct.off; - mask = ice_flds_info[fld].mask; + mask = flds[fld].xtrct.mask; for (i = 0; i < cnt; i++) { /* Only consume an extraction sequence entry if there is no * sibling field associated with this field or the sibling entry @@ -767,7 +786,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, params->es[idx].prot_id = prot_id; params->es[idx].off = off; - params->mask[idx] = mask; + params->mask[idx] = mask | sib_mask; params->es_cnt++; } @@ -885,7 +904,8 @@ ice_flow_create_xtrct_seq(struct ice_hw *hw, if (match & bit) { status = ice_flow_xtract_fld - (hw, params, i, (enum ice_flow_field)j); + (hw, params, i, (enum ice_flow_field)j, + match); if (status) return status; match &= ~bit; diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index 326ff6f81..c224e6ebf 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -114,9 +114,12 @@ enum ice_flow_field { ICE_FLOW_FIELD_IDX_C_VLAN, ICE_FLOW_FIELD_IDX_ETH_TYPE, /* L3 */ - ICE_FLOW_FIELD_IDX_IP_DSCP, - ICE_FLOW_FIELD_IDX_IP_TTL, - ICE_FLOW_FIELD_IDX_IP_PROT, + ICE_FLOW_FIELD_IDX_IPV4_DSCP, + ICE_FLOW_FIELD_IDX_IPV6_DSCP, + ICE_FLOW_FIELD_IDX_IPV4_TTL, + ICE_FLOW_FIELD_IDX_IPV4_PROT, + ICE_FLOW_FIELD_IDX_IPV6_TTL, + ICE_FLOW_FIELD_IDX_IPV6_PROT, ICE_FLOW_FIELD_IDX_IPV4_SA, ICE_FLOW_FIELD_IDX_IPV4_DA, ICE_FLOW_FIELD_IDX_IPV6_SA, @@ -232,6 +235,7 @@ struct ice_flow_seg_xtrct { u16 off; /* Starting offset of the field in header in bytes */ u8 idx; /* Index of FV entry used */ u8 disp; /* Displacement of field in bits fr. FV entry's start */ + u16 mask; /* Mask for field */ }; enum ice_flow_fld_match_type { From patchwork Fri Sep 27 04:16:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59944 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BD6FF3423; Fri, 27 Sep 2019 06:14:24 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id C4FD92C23 for ; Fri, 27 Sep 2019 06:14:02 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2019 21:14:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,554,1559545200"; d="scan'208";a="219641197" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga002.fm.intel.com with ESMTP; 26 Sep 2019 21:14:00 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Jeb Cramer , Paul M Stillwell Jr Date: Fri, 27 Sep 2019 12:16:44 +0800 Message-Id: <20190927041646.34712-7-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190927041646.34712-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190927041646.34712-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 6/8] net/ice/base: remove dead error condition X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The pointer cmd is set to an address of a structure, which can never be NULL. Remove the check-for-NULL lines since it's dead code anyway. Signed-off-by: Jeb Cramer Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 48ba160f7..4ba3ab202 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -176,9 +176,6 @@ ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, cmd = &desc.params.get_link_topo; - if (!cmd) - return ICE_ERR_PARAM; - ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << From patchwork Fri Sep 27 04:16:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59945 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 983C334F0; Fri, 27 Sep 2019 06:14:27 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 6F81E2C16 for ; Fri, 27 Sep 2019 06:14:04 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2019 21:14:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,554,1559545200"; d="scan'208";a="219641206" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga002.fm.intel.com with ESMTP; 26 Sep 2019 21:14:02 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Jeb Cramer , Jesse Brandeburg , Paul M Stillwell Jr Date: Fri, 27 Sep 2019 12:16:45 +0800 Message-Id: <20190927041646.34712-8-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190927041646.34712-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190927041646.34712-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 7/8] net/ice/base: zero initialize structures X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Some functions create ice_pkg_enum structure, but it seems it's possible some of the members are used un-initialized. So we'll initialize all instantiations of this structure within ice_flex_pipe.c The patch also fix header comment mismatch issue for ice_init_prof_result_bm Signed-off-by: Jeb Cramer Signed-off-by: Jesse Brandeburg Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flex_pipe.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 8f8cab86e..bf14149b8 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -470,6 +470,7 @@ static void ice_init_pkg_hints(struct ice_hw *hw, struct ice_seg *ice_seg) int i; ice_memset(&hw->tnl, 0, sizeof(hw->tnl), ICE_NONDMA_MEM); + ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); if (!ice_seg) return; @@ -1517,6 +1518,8 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type, struct ice_seg *ice_seg; struct ice_fv *fv; + ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); + if (type == ICE_PROF_ALL) { u16 i; @@ -1573,6 +1576,8 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt, struct ice_fv *fv; u32 offset; + ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); + if (!ids_cnt || !hw->seg) return ICE_ERR_PARAM; @@ -1633,16 +1638,17 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt, } /** - * ice_init_profile_to_result_bm - Initialize the profile result index bitmap + * ice_init_prof_result_bm - Initialize the profile result index bitmap * @hw: pointer to hardware structure */ -void -ice_init_prof_result_bm(struct ice_hw *hw) +void ice_init_prof_result_bm(struct ice_hw *hw) { struct ice_pkg_enum state; struct ice_seg *ice_seg; struct ice_fv *fv; + ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); + if (!hw->seg) return; From patchwork Fri Sep 27 04:16:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59946 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D70C63977; Fri, 27 Sep 2019 06:14:29 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id C07A42C16 for ; Fri, 27 Sep 2019 06:14:05 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2019 21:14:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,554,1559545200"; d="scan'208";a="219641212" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga002.fm.intel.com with ESMTP; 26 Sep 2019 21:14:04 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Paul M Stillwell Jr Date: Fri, 27 Sep 2019 12:16:46 +0800 Message-Id: <20190927041646.34712-9-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190927041646.34712-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190927041646.34712-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 8/8] net/ice/base: fix unexpected switch rule overwrite X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" A switch rule with "drop" action will be overwritten by a rule with same pattern match but with a "to queue" action. While in an inversed flow creation sequence, the "to queue" can't be overwritten by the "drop" rule. The inconsistent behavior is not expected, the patch fix the issue by preventing rule overwrite in both cases. Fixes: fed0c5ca5f19 ("net/ice/base: support programming a new switch recipe") Signed-off-by: Qi Zhang Signed-off-by: Paul M Stillwell Jr --- drivers/net/ice/base/ice_switch.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index c22235b68..6ca50e13d 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -5975,13 +5975,10 @@ ice_adv_add_update_vsi_list(struct ice_hw *hw, u16 vsi_list_id = 0; if (cur_fltr->sw_act.fltr_act == ICE_FWD_TO_Q || - cur_fltr->sw_act.fltr_act == ICE_FWD_TO_QGRP) + cur_fltr->sw_act.fltr_act == ICE_FWD_TO_QGRP || + cur_fltr->sw_act.fltr_act == ICE_DROP_PACKET) return ICE_ERR_NOT_IMPL; - if (cur_fltr->sw_act.fltr_act == ICE_DROP_PACKET && - new_fltr->sw_act.fltr_act == ICE_DROP_PACKET) - return ICE_ERR_ALREADY_EXISTS; - if ((new_fltr->sw_act.fltr_act == ICE_FWD_TO_Q || new_fltr->sw_act.fltr_act == ICE_FWD_TO_QGRP) && (cur_fltr->sw_act.fltr_act == ICE_FWD_TO_VSI ||