From patchwork Mon Sep 23 07:44:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59573 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 325211BE8D; Mon, 23 Sep 2019 09:42:06 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 9C2321BE82 for ; Mon, 23 Sep 2019 09:41:58 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:41:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445473" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:41:55 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:19 +0800 Message-Id: <20190923074448.7847-2-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 01/30] net/ice/base: remove redundant empty lines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove redundant empty lines Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 111 ------------------------------- drivers/net/ice/base/ice_bitops.h | 2 - drivers/net/ice/base/ice_common.c | 25 ------- drivers/net/ice/base/ice_common.h | 2 - drivers/net/ice/base/ice_controlq.c | 9 --- drivers/net/ice/base/ice_controlq.h | 1 - drivers/net/ice/base/ice_devids.h | 1 - drivers/net/ice/base/ice_flex_pipe.c | 5 -- drivers/net/ice/base/ice_flex_pipe.h | 1 - drivers/net/ice/base/ice_hw_autogen.h | 2 - drivers/net/ice/base/ice_lan_tx_rx.h | 9 --- drivers/net/ice/base/ice_nvm.c | 4 -- drivers/net/ice/base/ice_protocol_type.h | 2 - drivers/net/ice/base/ice_sched.c | 4 -- drivers/net/ice/base/ice_switch.c | 8 --- drivers/net/ice/base/ice_switch.h | 2 - drivers/net/ice/base/ice_type.h | 9 --- 17 files changed, 197 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 8e1d6a07d..e6a1350ba 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -9,12 +9,10 @@ * descriptor format. It is shared between Firmware and Software. */ - #define ICE_MAX_VSI 768 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 - struct ice_aqc_generic { __le32 param0; __le32 param1; @@ -22,7 +20,6 @@ struct ice_aqc_generic { __le32 addr_low; }; - /* Get version (direct 0x0001) */ struct ice_aqc_get_ver { __le32 rom_ver; @@ -37,7 +34,6 @@ struct ice_aqc_get_ver { u8 api_patch; }; - /* Send driver version (indirect 0x0002) */ struct ice_aqc_driver_ver { u8 major_ver; @@ -49,7 +45,6 @@ struct ice_aqc_driver_ver { __le32 addr_low; }; - /* Queue Shutdown (direct 0x0003) */ struct ice_aqc_q_shutdown { u8 driver_unloading; @@ -57,9 +52,6 @@ struct ice_aqc_q_shutdown { u8 reserved[15]; }; - - - /* Request resource ownership (direct 0x0008) * Release resource ownership (direct 0x0009) */ @@ -92,7 +84,6 @@ struct ice_aqc_req_res { u8 reserved[2]; }; - /* Get function capabilities (indirect 0x000A) * Get device capabilities (indirect 0x000B) */ @@ -105,7 +96,6 @@ struct ice_aqc_list_caps { __le32 addr_low; }; - /* Device/Function buffer entry, repeated per reported capability */ struct ice_aqc_list_caps_elem { __le16 cap; @@ -132,7 +122,6 @@ struct ice_aqc_list_caps_elem { __le64 rsvd2; }; - /* Manage MAC address, read command - indirect (0x0107) * This struct is also used for the response */ @@ -153,7 +142,6 @@ struct ice_aqc_manage_mac_read { __le32 addr_low; }; - /* Response buffer format for manage MAC read command */ struct ice_aqc_manage_mac_read_resp { u8 lport_num; @@ -163,7 +151,6 @@ struct ice_aqc_manage_mac_read_resp { u8 mac_addr[ETH_ALEN]; }; - /* Manage MAC address, write command - direct (0x0108) */ struct ice_aqc_manage_mac_write { u8 rsvd; @@ -182,7 +169,6 @@ struct ice_aqc_manage_mac_write { __le32 addr_low; }; - /* Clear PXE Command and response (direct 0x0110) */ struct ice_aqc_clear_pxe { u8 rx_cnt; @@ -190,7 +176,6 @@ struct ice_aqc_clear_pxe { u8 reserved[15]; }; - /* Configure No-Drop Policy Command (direct 0x0112) */ struct ice_aqc_config_no_drop_policy { u8 opts; @@ -215,7 +200,6 @@ struct ice_aqc_get_sw_cfg { __le32 addr_low; }; - /* Each entry in the response buffer is of the following type: */ struct ice_aqc_get_sw_cfg_resp_elem { /* VSI/Port Number */ @@ -242,7 +226,6 @@ struct ice_aqc_get_sw_cfg_resp_elem { #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) }; - /* The response buffer is as follows. Note that the length of the * elements array varies with the length of the command response. */ @@ -250,8 +233,6 @@ struct ice_aqc_get_sw_cfg_resp { struct ice_aqc_get_sw_cfg_resp_elem elements[1]; }; - - /* These resource type defines are used for all switch resource * commands where a resource type is required, such as: * Get Resource Allocation command (indirect 0x0204) @@ -324,7 +305,6 @@ struct ice_aqc_get_res_resp { struct ice_aqc_get_res_resp_elem elem[1]; }; - /* Allocate Resources command (indirect 0x0208) * Free Resources command (indirect 0x0209) */ @@ -335,7 +315,6 @@ struct ice_aqc_alloc_free_res_cmd { __le32 addr_low; }; - /* Resource descriptor */ struct ice_aqc_res_elem { union { @@ -344,7 +323,6 @@ struct ice_aqc_res_elem { } e; }; - /* Buffer for Allocate/Free Resources commands */ struct ice_aqc_alloc_free_res_elem { __le16 res_type; /* Types defined above cmd 0x0204 */ @@ -355,7 +333,6 @@ struct ice_aqc_alloc_free_res_elem { struct ice_aqc_res_elem elem[1]; }; - /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ struct ice_aqc_get_allocd_res_desc { union { @@ -379,7 +356,6 @@ struct ice_aqc_get_allocd_res_desc_resp { struct ice_aqc_res_elem elem[1]; }; - /* Add VSI (indirect 0x0210) * Update VSI (indirect 0x0211) * Get VSI (indirect 0x0212) @@ -405,7 +381,6 @@ struct ice_aqc_add_get_update_free_vsi { __le32 addr_low; }; - /* Response descriptor for: * Add VSI (indirect 0x0210) * Update VSI (indirect 0x0211) @@ -420,7 +395,6 @@ struct ice_aqc_add_update_free_vsi_resp { __le32 addr_low; }; - struct ice_aqc_get_vsi_resp { __le16 vsi_num; u8 vf_id; @@ -434,7 +408,6 @@ struct ice_aqc_get_vsi_resp { __le32 addr_low; }; - struct ice_aqc_vsi_props { __le16 valid_sections; #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) @@ -589,7 +562,6 @@ struct ice_aqc_vsi_props { u8 reserved[24]; }; - /* Add/update mirror rule - direct (0x0260) */ #define ICE_AQC_RULE_ID_VALID_S 7 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) @@ -694,7 +666,6 @@ struct ice_aqc_storm_cfg { __le32 reserved; }; - #define ICE_MAX_NUM_RECIPES 64 /* Add/Get Recipe (indirect 0x0290/0x0292)*/ @@ -779,7 +750,6 @@ struct ice_aqc_sw_rules { __le32 addr_low; }; - #pragma pack(1) /* Add/Update/Get/Remove lookup Rx/Tx command/response entry * This structures describes the lookup rules and associated actions. "index" @@ -867,7 +837,6 @@ struct ice_sw_rule_lkup_rx_tx { }; #pragma pack() - /* Add/Update/Remove large action command/response entry * "index" is returned as part of a response to a successful Add command, and * can be used to identify the action for Update/Get/Remove commands. @@ -928,7 +897,6 @@ struct ice_sw_rule_lg_act { #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) }; - /* Add/Update/Remove VSI list command/response entry * "index" is returned as part of a response to a successful Add command, and * can be used to identify the VSI list for Update/Get/Remove commands. @@ -939,7 +907,6 @@ struct ice_sw_rule_vsi_list { __le16 vsi[1]; /* Array of number_vsi VSI numbers */ }; - #pragma pack(1) /* Query VSI list command/response entry */ struct ice_sw_rule_vsi_list_query { @@ -948,7 +915,6 @@ struct ice_sw_rule_vsi_list_query { }; #pragma pack() - #pragma pack(1) /* Add switch rule response: * Content of return buffer is same as the input buffer. The status field and @@ -974,7 +940,6 @@ struct ice_aqc_sw_rules_elem { #pragma pack() - /* PFC Ignore (direct 0x0301) * The command and response use the same descriptor structure */ @@ -1009,7 +974,6 @@ struct ice_aqc_set_dcb_params { u8 rsvd[14]; }; - /* Get Default Topology (indirect 0x0400) */ struct ice_aqc_get_topo { u8 port_num; @@ -1020,7 +984,6 @@ struct ice_aqc_get_topo { __le32 addr_low; }; - /* Update TSE (indirect 0x0403) * Get TSE (indirect 0x0404) * Add TSE (indirect 0x0401) @@ -1037,7 +1000,6 @@ struct ice_aqc_sched_elem_cmd { __le32 addr_low; }; - /* This is the buffer for: * Suspend Nodes (indirect 0x0409) * Resume Nodes (indirect 0x040A) @@ -1046,7 +1008,6 @@ struct ice_aqc_suspend_resume_elem { __le32 teid[1]; }; - struct ice_aqc_txsched_move_grp_info_hdr { __le32 src_parent_teid; __le32 dest_parent_teid; @@ -1054,19 +1015,16 @@ struct ice_aqc_txsched_move_grp_info_hdr { __le16 reserved; }; - struct ice_aqc_move_elem { struct ice_aqc_txsched_move_grp_info_hdr hdr; __le32 teid[1]; }; - struct ice_aqc_elem_info_bw { __le16 bw_profile_idx; __le16 bw_alloc; }; - struct ice_aqc_txsched_elem { u8 elem_type; /* Special field, reserved for some aq calls */ #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 @@ -1098,50 +1056,42 @@ struct ice_aqc_txsched_elem { __le16 reserved2; }; - struct ice_aqc_txsched_elem_data { __le32 parent_teid; __le32 node_teid; struct ice_aqc_txsched_elem data; }; - struct ice_aqc_txsched_topo_grp_info_hdr { __le32 parent_teid; __le16 num_elems; __le16 reserved2; }; - struct ice_aqc_add_elem { struct ice_aqc_txsched_topo_grp_info_hdr hdr; struct ice_aqc_txsched_elem_data generic[1]; }; - struct ice_aqc_conf_elem { struct ice_aqc_txsched_elem_data generic[1]; }; - struct ice_aqc_get_elem { struct ice_aqc_txsched_elem_data generic[1]; }; - struct ice_aqc_get_topo_elem { struct ice_aqc_txsched_topo_grp_info_hdr hdr; struct ice_aqc_txsched_elem_data generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; }; - struct ice_aqc_delete_elem { struct ice_aqc_txsched_topo_grp_info_hdr hdr; __le32 teid[1]; }; - /* Query Port ETS (indirect 0x040E) * * This indirect command is used to query port TC node configuration. @@ -1168,7 +1118,6 @@ struct ice_aqc_port_ets_elem { __le32 tc_node_teid[8]; /* Used for response, reserved in command */ }; - /* Rate limiting profile for * Add RL profile (indirect 0x0410) * Query RL profile (indirect 0x0411) @@ -1184,7 +1133,6 @@ struct ice_aqc_rl_profile { __le32 addr_low; }; - struct ice_aqc_rl_profile_elem { u8 level; u8 flags; @@ -1204,13 +1152,10 @@ struct ice_aqc_rl_profile_elem { __le16 rl_encode; }; - struct ice_aqc_rl_profile_generic_elem { struct ice_aqc_rl_profile_elem generic[1]; }; - - /* Configure L2 Node CGD (indirect 0x0414) * This indirect command allows configuring a congestion domain for given L2 * node TEIDs in the scheduler topology. @@ -1222,19 +1167,16 @@ struct ice_aqc_cfg_l2_node_cgd { __le32 addr_low; }; - struct ice_aqc_cfg_l2_node_cgd_elem { __le32 node_teid; u8 cgd; u8 reserved[3]; }; - struct ice_aqc_cfg_l2_node_cgd_data { struct ice_aqc_cfg_l2_node_cgd_elem elem[1]; }; - /* Query Scheduler Resource Allocation (indirect 0x0412) * This indirect command retrieves the scheduler resources allocated by * EMP Firmware to the given PF. @@ -1245,7 +1187,6 @@ struct ice_aqc_query_txsched_res { __le32 addr_low; }; - struct ice_aqc_generic_sched_props { __le16 phys_levels; __le16 logical_levels; @@ -1257,7 +1198,6 @@ struct ice_aqc_generic_sched_props { u8 rsvd1[22]; }; - struct ice_aqc_layer_props { u8 logical_layer; u8 chunk_size; @@ -1271,13 +1211,11 @@ struct ice_aqc_layer_props { u8 rsvd1[14]; }; - struct ice_aqc_query_txsched_res_resp { struct ice_aqc_generic_sched_props sched_props; struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; }; - /* Query Node to Root Topology (indirect 0x0413) * This command uses ice_aqc_get_elem as its data buffer. */ @@ -1288,7 +1226,6 @@ struct ice_aqc_query_node_to_root { __le32 addr_low; }; - /* Get PHY capabilities (indirect 0x0600) */ struct ice_aqc_get_phy_caps { u8 lport_num; @@ -1311,7 +1248,6 @@ struct ice_aqc_get_phy_caps { __le32 addr_low; }; - /* This is #define of PHY type (Extended): * The first set of defines is for phy_type_low. */ @@ -1453,7 +1389,6 @@ struct ice_aqc_get_phy_caps_data { } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; }; - /* Set PHY capabilities (direct 0x0601) * NOTE: This command must be followed by setup link and restart auto-neg */ @@ -1464,7 +1399,6 @@ struct ice_aqc_set_phy_cfg { __le32 addr_low; }; - /* Set PHY config command data structure */ struct ice_aqc_set_phy_cfg_data { __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ @@ -1485,7 +1419,6 @@ struct ice_aqc_set_phy_cfg_data { u8 rsvd1; }; - /* Set MAC Config command data structure (direct 0x0603) */ struct ice_aqc_set_mac_cfg { __le16 max_frame_size; @@ -1505,7 +1438,6 @@ struct ice_aqc_set_mac_cfg { u8 reserved[7]; }; - /* Restart AN command data structure (direct 0x0605) * Also used for response, with only the lport_num field present. */ @@ -1518,7 +1450,6 @@ struct ice_aqc_restart_an { u8 reserved2[13]; }; - /* Get link status (indirect 0x0607), also used for Link Status Event */ struct ice_aqc_get_link_status { u8 lport_num; @@ -1535,7 +1466,6 @@ struct ice_aqc_get_link_status { __le32 addr_low; }; - /* Get link status response data structure, also used for Link Status Event */ struct ice_aqc_get_link_status_data { u8 topo_media_conflict; @@ -1621,7 +1551,6 @@ struct ice_aqc_get_link_status_data { __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ }; - /* Set event mask command (direct 0x0613) */ struct ice_aqc_set_event_mask { u8 lport_num; @@ -1641,8 +1570,6 @@ struct ice_aqc_set_event_mask { u8 reserved1[6]; }; - - /* Set MAC Loopback command (direct 0x0620) */ struct ice_aqc_set_mac_lb { u8 lb_mode; @@ -1651,9 +1578,6 @@ struct ice_aqc_set_mac_lb { u8 reserved[15]; }; - - - struct ice_aqc_link_topo_addr { u8 lport_num; u8 lport_num_valid; @@ -1716,8 +1640,6 @@ struct ice_aqc_set_port_id_led { u8 rsvd[13]; }; - - /* Read/Write SFF EEPROM command (indirect 0x06EE) */ struct ice_aqc_sff_eeprom { u8 lport_num; @@ -1797,7 +1719,6 @@ struct ice_aqc_nvm { #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ - /* Used for 0x0704 as well as for 0x0705 commands */ struct ice_aqc_nvm_cfg { u8 cmd_flags; @@ -1812,14 +1733,12 @@ struct ice_aqc_nvm_cfg { __le32 addr_low; }; - struct ice_aqc_nvm_cfg_data { __le16 field_id; __le16 field_options; __le16 field_value; }; - /* NVM Checksum Command (direct, 0x0706) */ struct ice_aqc_nvm_checksum { u8 flags; @@ -1831,9 +1750,6 @@ struct ice_aqc_nvm_checksum { u8 rsvd2[12]; }; - - - /* Get LLDP MIB (indirect 0x0A00) * Note: This is also used by the LLDP MIB Change Event (0x0A01) * as the format is the same. @@ -1985,7 +1901,6 @@ struct ice_aqc_lldp_stop_start_specific_agent { u8 reserved[15]; }; - /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ struct ice_aqc_get_set_rss_key { #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) @@ -1997,7 +1912,6 @@ struct ice_aqc_get_set_rss_key { __le32 addr_low; }; - #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ @@ -2019,7 +1933,6 @@ struct ice_aqc_get_set_rss_keys { u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; }; - /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ struct ice_aqc_get_set_rss_lut { #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) @@ -2055,7 +1968,6 @@ struct ice_aqc_get_set_rss_lut { __le32 addr_low; }; - /* Clear FD Table Command (direct, 0x0B06) */ struct ice_aqc_clear_fd_table { u8 clear_type; @@ -2066,9 +1978,6 @@ struct ice_aqc_clear_fd_table { u8 reserved[12]; }; - - - /* Add Tx LAN Queues (indirect 0x0C30) */ struct ice_aqc_add_txqs { u8 num_qgrps; @@ -2078,7 +1987,6 @@ struct ice_aqc_add_txqs { __le32 addr_low; }; - /* This is the descriptor of each queue entry for the Add Tx LAN Queues * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. */ @@ -2091,7 +1999,6 @@ struct ice_aqc_add_txqs_perq { struct ice_aqc_txsched_elem info; }; - /* The format of the command buffer for Add Tx LAN Queues (0x0C30) * is an array of the following structs. Please note that the length of * each struct ice_aqc_add_tx_qgrp is variable due @@ -2104,7 +2011,6 @@ struct ice_aqc_add_tx_qgrp { struct ice_aqc_add_txqs_perq txqs[1]; }; - /* Disable Tx LAN Queues (indirect 0x0C31) */ struct ice_aqc_dis_txqs { u8 cmd_type; @@ -2127,7 +2033,6 @@ struct ice_aqc_dis_txqs { __le32 addr_low; }; - /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) * contains the following structures, arrayed one after the * other. @@ -2150,12 +2055,10 @@ struct ice_aqc_dis_txq_item { (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) }; - struct ice_aqc_dis_txq { struct ice_aqc_dis_txq_item qgrps[1]; }; - /* Tx LAN Queues Cleanup Event (0x0C31) */ struct ice_aqc_txqs_cleanup { __le16 caller_opc; @@ -2163,7 +2066,6 @@ struct ice_aqc_txqs_cleanup { u8 reserved[12]; }; - /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ struct ice_aqc_move_txqs { u8 cmd_type; @@ -2184,7 +2086,6 @@ struct ice_aqc_move_txqs { __le32 addr_low; }; - /* This is the descriptor of each queue entry for the move Tx LAN Queues * command (0x0C32). */ @@ -2195,15 +2096,12 @@ struct ice_aqc_move_txqs_elem { __le32 q_teid; }; - struct ice_aqc_move_txqs_data { __le32 src_teid; __le32 dest_teid; struct ice_aqc_move_txqs_elem txqs[1]; }; - - /* Download Package (indirect 0x0C40) */ /* Also used for Update Package (indirect 0x0C42) */ struct ice_aqc_download_pkg { @@ -2255,9 +2153,6 @@ struct ice_aqc_get_pkg_info_resp { struct ice_aqc_get_pkg_info pkg_info[1]; }; - - - /* Lan Queue Overflow Event (direct, 0x1001) */ struct ice_aqc_event_lan_overflow { __le32 prtdcb_ruptq; @@ -2265,9 +2160,6 @@ struct ice_aqc_event_lan_overflow { u8 reserved[8]; }; - - - /** * struct ice_aq_desc - Admin Queue (AQ) descriptor * @flags: ICE_AQ_FLAG_* flags @@ -2361,7 +2253,6 @@ struct ice_aq_desc { } params; }; - /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ #define ICE_AQ_LG_BUF 512 @@ -2572,8 +2463,6 @@ enum ice_adminq_opc { ice_aqc_opc_update_pkg = 0x0C42, ice_aqc_opc_get_pkg_info_list = 0x0C43, - - /* Standalone Commands/Events */ ice_aqc_opc_event_lan_overflow = 0x1001, }; diff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h index f0aa8ce88..32f64cac0 100644 --- a/drivers/net/ice/base/ice_bitops.h +++ b/drivers/net/ice/base/ice_bitops.h @@ -8,7 +8,6 @@ /* Define the size of the bitmap chunk */ typedef u32 ice_bitmap_t; - /* Number of bits per bitmap chunk */ #define BITS_PER_CHUNK (BITS_PER_BYTE * sizeof(ice_bitmap_t)) /* Determine which chunk a bit belongs in */ @@ -372,5 +371,4 @@ ice_cmp_bitmap(ice_bitmap_t *bmp1, ice_bitmap_t *bmp2, u16 size) return true; } - #endif /* _ICE_BITOPS_H_ */ diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 11e902ea1..16b91dc12 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -11,7 +11,6 @@ #define ICE_PF_RESET_WAIT_COUNT 200 - /** * ice_set_mac_type - Sets MAC type * @hw: pointer to the HW structure @@ -41,7 +40,6 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw) return status; } - /** * ice_clear_pf_cfg - Clear PF configuration * @hw: pointer to the hardware structure @@ -113,7 +111,6 @@ ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, ETH_ALEN, ICE_DMA_TO_NONDMA); break; } - return ICE_SUCCESS; } @@ -533,7 +530,6 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) ice_free(hw, sw); } - /** * ice_get_itr_intrl_gran * @hw: pointer to the HW struct @@ -598,7 +594,6 @@ void ice_print_rollback_msg(struct ice_hw *hw) &ver_lo); SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi, ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch); - ice_warn(hw, "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode", nvm_str, hw->fw_maj_ver, hw->fw_min_ver); @@ -617,7 +612,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw) ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); - /* Set MAC type based on DeviceID */ status = ice_set_mac_type(hw); if (status) @@ -627,14 +621,12 @@ enum ice_status ice_init_hw(struct ice_hw *hw) PF_FUNC_RID_FUNCTION_NUMBER_M) >> PF_FUNC_RID_FUNCTION_NUMBER_S; - status = ice_reset(hw, ICE_RESET_PFR); if (status) return status; ice_get_itr_intrl_gran(hw); - status = ice_create_all_ctrlq(hw); if (status) goto err_unroll_cqinit; @@ -686,7 +678,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw) goto err_unroll_alloc; } - /* Initialize port_info struct with scheduler data */ status = ice_sched_init_port(hw->port_info); if (status) @@ -725,7 +716,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw) if (status) goto err_unroll_sched; - /* Get MAC information */ /* A single port can report up to two (LAN and WoL) addresses */ mac_buf = ice_calloc(hw, 2, @@ -926,7 +916,6 @@ enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) wr32(hw, GLGEN_RTRIG, val); ice_flush(hw); - /* wait for the FW to be ready */ return ice_check_reset(hw); } @@ -997,8 +986,6 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, return ICE_ERR_DOES_NOT_EXIST; } - - /** * ice_copy_rxq_ctx_to_hw * @hw: pointer to the hardware structure @@ -1321,7 +1308,6 @@ ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) } #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */ - /* FW Admin Queue command wrappers */ /** @@ -2142,7 +2128,6 @@ ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, cmd->flags = flags; - /* Prep values for flags, sah, sal */ cmd->sah = HTONS(*((const u16 *)mac_addr)); cmd->sal = HTONL(*((const u32 *)(mac_addr + 2))); @@ -2179,7 +2164,6 @@ void ice_clear_pxe_mode(struct ice_hw *hw) ice_aq_clear_pxe_mode(hw); } - /** * ice_get_link_speed_based_on_phy_type - returns link speed * @phy_type_low: lower part of phy_type @@ -2848,7 +2832,6 @@ ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); } - /** * ice_aq_set_port_id_led * @pi: pointer to the port information @@ -2869,7 +2852,6 @@ ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); - if (is_orig_mode) cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; else @@ -3357,7 +3339,6 @@ ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, return status; } - /* End of FW Admin Queue command wrappers */ /** @@ -3581,9 +3562,6 @@ ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) return ICE_SUCCESS; } - - - /** * ice_read_byte - read context byte into struct * @src_ctx: the context structure to read from @@ -4047,8 +4025,6 @@ ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, ICE_SCHED_NODE_OWNER_LAN); } - - /** * ice_replay_pre_init - replay pre initialization * @hw: pointer to the HW struct @@ -4246,7 +4222,6 @@ ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, cur_stats->rx_errors += error_cnt; } - /** * ice_sched_query_elem - query element information from HW * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index c42c58670..bcb0a999d 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -169,7 +169,6 @@ ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, enum ice_status ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd); - enum ice_status ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, struct ice_sq_cd *cd); @@ -178,7 +177,6 @@ ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, bool write, struct ice_sq_cd *cd); - enum ice_status ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info); enum ice_status diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c index 1ea8f3a24..8a65fae40 100644 --- a/drivers/net/ice/base/ice_controlq.c +++ b/drivers/net/ice/base/ice_controlq.c @@ -4,7 +4,6 @@ #include "ice_common.h" - #define ICE_CQ_INIT_REGS(qinfo, prefix) \ do { \ (qinfo)->sq.head = prefix##_ATQH; \ @@ -53,7 +52,6 @@ static void ice_mailbox_init_regs(struct ice_hw *hw) ICE_CQ_INIT_REGS(cq, PF_MBX); } - /** * ice_check_sq_alive * @hw: pointer to the HW struct @@ -521,7 +519,6 @@ ice_shutdown_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq) return ret_code; } - /** * ice_init_check_adminq - Check version for Admin Queue to know if its alive * @hw: pointer to the hardware structure @@ -533,12 +530,10 @@ static enum ice_status ice_init_check_adminq(struct ice_hw *hw) ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); - status = ice_aq_get_fw_ver(hw, NULL); if (status) goto init_ctrlq_free_rq; - if (!ice_aq_ver_check(hw)) { status = ICE_ERR_FW_API_VER; goto init_ctrlq_free_rq; @@ -633,7 +628,6 @@ enum ice_status ice_init_all_ctrlq(struct ice_hw *hw) ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); - /* Init FW admin queue */ ret_code = ice_init_ctrlq(hw, ICE_CTL_Q_ADMIN); if (ret_code) @@ -972,7 +966,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, ice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size); - (cq->sq.next_to_use)++; if (cq->sq.next_to_use == cq->sq.count) cq->sq.next_to_use = 0; @@ -1025,7 +1018,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, ice_debug_cq(hw, (void *)desc, buf, buf_size); - /* save writeback AQ if requested */ if (details->wb_desc) ice_memcpy(details->wb_desc, desc_on_ring, @@ -1158,7 +1150,6 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, ice_debug_cq(hw, (void *)desc, e->msg_buf, cq->rq_buf_size); - /* Restore the original datalen and buffer address in the desc, * FW updates datalen to indicate the event message size */ diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h index b1214f670..8ad7857c8 100644 --- a/drivers/net/ice/base/ice_controlq.h +++ b/drivers/net/ice/base/ice_controlq.h @@ -7,7 +7,6 @@ #include "ice_adminq_cmd.h" - /* Maximum buffer lengths for all control queue types */ #define ICE_AQ_MAX_BUF_LEN 4096 #define ICE_MBXQ_MAX_BUF_LEN 4096 diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h index c9a567fb1..0ff3b9b34 100644 --- a/drivers/net/ice/base/ice_devids.h +++ b/drivers/net/ice/base/ice_devids.h @@ -5,7 +5,6 @@ #ifndef _ICE_DEVIDS_H_ #define _ICE_DEVIDS_H_ - /* Device IDs */ /* Intel(R) Ethernet Controller E810-C for backplane */ #define ICE_DEV_ID_E810C_BACKPLANE 0x1591 diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 4ad816874..05cd39b17 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -808,7 +808,6 @@ ice_aq_download_pkg(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf, return status; } - /** * ice_aq_update_pkg * @hw: pointer to the hardware structure @@ -1180,7 +1179,6 @@ static enum ice_status ice_get_pkg_info(struct ice_hw *hw) return status; } - /** * ice_verify_pkg - verify package * @pkg: pointer to the package buffer @@ -2084,7 +2082,6 @@ ice_find_prot_off(struct ice_hw *hw, enum ice_block blk, u8 prof, u8 fv_idx, /* PTG Management */ - /** * ice_ptg_find_ptype - Search for packet type group using packet type (ptype) * @hw: pointer to the hardware structure @@ -2121,7 +2118,6 @@ void ice_ptg_alloc_val(struct ice_hw *hw, enum ice_block blk, u8 ptg) hw->blk[blk].xlt1.ptg_tbl[ptg].in_use = true; } - /** * ice_ptg_remove_ptype - Removes ptype from a particular packet type group * @hw: pointer to the hardware structure @@ -2315,7 +2311,6 @@ ice_match_prop_lst(struct LIST_HEAD_TYPE *list1, struct LIST_HEAD_TYPE *list2) /* VSIG Management */ - /** * ice_vsig_find_vsi - find a VSIG that contains a specified VSI * @hw: pointer to the hardware structure diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h index 3b5c1c39a..137eaa7f8 100644 --- a/drivers/net/ice/base/ice_flex_pipe.h +++ b/drivers/net/ice/base/ice_flex_pipe.h @@ -46,7 +46,6 @@ bool ice_tunnel_port_in_use(struct ice_hw *hw, u16 port, u16 *index); bool ice_tunnel_get_type(struct ice_hw *hw, u16 port, enum ice_tunnel_type *type); - /* XLT2/VSI group functions */ enum ice_status ice_vsig_find_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 *vsig); diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h index 6f227adb8..92d432044 100644 --- a/drivers/net/ice/base/ice_hw_autogen.h +++ b/drivers/net/ice/base/ice_hw_autogen.h @@ -6,8 +6,6 @@ #ifndef _ICE_HW_AUTOGEN_H_ #define _ICE_HW_AUTOGEN_H_ - - #define GL_RDPU_CNTRL 0x00052054 /* Reset Source: CORER */ #define GL_RDPU_CNTRL_RX_PAD_EN_S 0 #define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0) diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index e77d4bf50..a97c63cc9 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -173,7 +173,6 @@ struct ice_fltr_desc { (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S) #define ICE_FXD_FLTR_QW1_FDID_ZERO 0x0ULL - enum ice_rx_desc_status_bits { /* Note: These are predefined bit offsets */ ICE_RX_DESC_STATUS_DD_S = 0, @@ -204,7 +203,6 @@ enum ice_rx_desc_status_bits { #define ICE_RXD_QW1_STATUS_TSYNVALID_S ICE_RX_DESC_STATUS_TSYNVALID_S #define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S) - enum ice_rx_desc_fltstat_values { ICE_RX_DESC_FLTSTAT_NO_DATA = 0, ICE_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ @@ -212,7 +210,6 @@ enum ice_rx_desc_fltstat_values { ICE_RX_DESC_FLTSTAT_RSS_HASH = 3, }; - #define ICE_RXD_QW1_ERROR_S 19 #define ICE_RXD_QW1_ERROR_M (0xFFUL << ICE_RXD_QW1_ERROR_S) @@ -310,7 +307,6 @@ enum ice_rx_ptype_payload_layer { ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, }; - #define ICE_RXD_QW1_LEN_PBUF_S 38 #define ICE_RXD_QW1_LEN_PBUF_M (0x3FFFULL << ICE_RXD_QW1_LEN_PBUF_S) @@ -320,7 +316,6 @@ enum ice_rx_ptype_payload_layer { #define ICE_RXD_QW1_LEN_SPH_S 63 #define ICE_RXD_QW1_LEN_SPH_M BIT_ULL(ICE_RXD_QW1_LEN_SPH_S) - enum ice_rx_desc_ext_status_bits { /* Note: These are predefined bit offsets */ ICE_RX_DESC_EXT_STATUS_L2TAG2P_S = 0, @@ -331,7 +326,6 @@ enum ice_rx_desc_ext_status_bits { ICE_RX_DESC_EXT_STATUS_PELONGB_S = 11, }; - enum ice_rx_desc_pe_status_bits { /* Note: These are predefined bit offsets */ ICE_RX_DESC_PE_STATUS_QPID_S = 0, /* 18 BITS */ @@ -352,7 +346,6 @@ enum ice_rx_desc_pe_status_bits { #define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_M \ (0x7UL << ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S) - #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S 19 #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_M \ (0x3FUL << ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S) @@ -840,7 +833,6 @@ enum ice_rx_flex_desc_exstat_bits { ICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3, }; - #define ICE_RXQ_CTX_SIZE_DWORDS 8 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22 @@ -1056,7 +1048,6 @@ enum ice_tx_ctx_desc_eipt_offload { #define ICE_TXD_CTX_QW0_L4T_CS_S 23 #define ICE_TXD_CTX_QW0_L4T_CS_M BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S) - #define ICE_LAN_TXQ_MAX_QGRPS 127 #define ICE_LAN_TXQ_MAX_QDIS 1023 diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 66cfec641..e00942528 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -4,7 +4,6 @@ #include "ice_common.h" - /** * ice_aq_read_nvm * @hw: pointer to the HW struct @@ -138,7 +137,6 @@ ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data) return status; } - /** * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ * @hw: pointer to the HW structure @@ -354,7 +352,6 @@ enum ice_status ice_init_nvm(struct ice_hw *hw) return ICE_SUCCESS; } - /** * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary * @hw: pointer to the HW structure @@ -380,7 +377,6 @@ ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data) return status; } - /** * ice_nvm_validate_checksum * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index 91f56f3fa..cdb691523 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -114,7 +114,6 @@ enum ice_prot_id { #define ICE_VNI_OFFSET 12 /* offset of VNI from ICE_PROT_UDP_OF */ - #define ICE_MAC_OFOS_HW 1 #define ICE_MAC_IL_HW 4 #define ICE_ETYPE_OL_HW 9 @@ -148,7 +147,6 @@ struct ice_protocol_entry { u8 protocol_id; }; - struct ice_ether_hdr { u8 dst_addr[ETH_ALEN]; u8 src_addr[ETH_ALEN]; diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 1cfc3bc20..6732e291a 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -4,7 +4,6 @@ #include "ice_sched.h" - /** * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB * @pi: port information structure @@ -876,7 +875,6 @@ ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_l2_nodes, return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); } - /** * ice_sched_add_elems - add nodes to HW and SW DB * @pi: port information structure @@ -1366,7 +1364,6 @@ enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw) goto sched_query_out; } - sched_query_out: ice_free(hw, buf); return status; @@ -2021,7 +2018,6 @@ enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle) return ice_sched_rm_vsi_cfg(pi, vsi_handle, ICE_SCHED_NODE_OWNER_LAN); } - /** * ice_sched_is_tree_balanced - Check tree nodes are identical or not * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 2437faead..00358e4db 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -6,7 +6,6 @@ #include "ice_flex_type.h" #include "ice_flow.h" - #define ICE_ETH_DA_OFFSET 0 #define ICE_ETH_ETHTYPE_OFFSET 12 #define ICE_ETH_VLAN_TCI_OFFSET 14 @@ -743,7 +742,6 @@ ice_aq_get_sw_cfg(struct ice_hw *hw, struct ice_aqc_get_sw_cfg_resp *buf, return status; } - /** * ice_alloc_sw - allocate resources specific to switch * @hw: pointer to the HW struct @@ -1787,13 +1785,11 @@ enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw) } } while (req_desc && !status); - out: ice_free(hw, (void *)rbuf); return status; } - /** * ice_fill_sw_info - Helper function to populate lb_en and lan_en * @hw: pointer to the hardware structure @@ -3424,7 +3420,6 @@ ice_remove_eth_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *em_list) return ICE_SUCCESS; } - /** * ice_rem_sw_rule_info * @hw: pointer to the hardware structure @@ -3823,7 +3818,6 @@ ice_add_to_vsi_fltr_list(struct ice_hw *hw, u16 vsi_handle, return status; } - /** * ice_determine_promisc_mask * @fi: filter info to parse @@ -4811,8 +4805,6 @@ ice_fill_valid_words(struct ice_adv_lkup_elem *rule, return ret_val; } - - /** * ice_create_first_fit_recp_def - Create a recipe grouping * @hw: pointer to the hardware structure diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index 515ad3bb6..0f0a1e98e 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -15,7 +15,6 @@ #define ICE_FLTR_TX BIT(1) #define ICE_FLTR_TX_RX (ICE_FLTR_RX | ICE_FLTR_TX) - /* Worst case buffer length for ice_aqc_opc_get_res_alloc */ #define ICE_MAX_RES_TYPES 0x80 #define ICE_AQ_GET_RES_ALLOC_BUF_LEN \ @@ -391,7 +390,6 @@ enum ice_status ice_add_mac_with_counter(struct ice_hw *hw, struct ice_fltr_info *f_info); void ice_remove_vsi_fltr(struct ice_hw *hw, u16 vsi_handle); - /* Promisc/defport setup for VSIs */ enum ice_status ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set, diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index deb614e37..150b4c5c5 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -134,10 +134,6 @@ static inline u32 ice_round_to_num(u32 N, u32 R) #define __ALWAYS_UNUSED #endif - - - - #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \ (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \ ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \ @@ -384,7 +380,6 @@ struct ice_hw_common_caps { u8 proxy_support; }; - /* Function specific capabilities */ struct ice_hw_func_caps { struct ice_hw_common_caps common_cap; @@ -401,7 +396,6 @@ struct ice_hw_dev_caps { u32 num_funcs; }; - /* Information about MAC such as address, etc... */ struct ice_mac_info { u8 lan_addr[ETH_ALEN]; @@ -567,7 +561,6 @@ enum ice_rl_type { #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc) #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode) - /* The following tree example shows the naming conventions followed under * ice_port_info struct for default scheduler tree topology. * @@ -729,7 +722,6 @@ struct ice_switch_info { struct ice_sw_recipe *recp_list; }; - /* Port hardware description */ struct ice_hw { u8 *hw_addr; @@ -787,7 +779,6 @@ struct ice_hw { u8 fw_patch; /* firmware patch version */ u32 fw_build; /* firmware build number */ - /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL * register. Used for determining the ITR/INTRL granularity during * initialization. From patchwork Mon Sep 23 07:44:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59574 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 748261BE96; Mon, 23 Sep 2019 09:42:09 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 904581BE8A for ; Mon, 23 Sep 2019 09:42:00 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445487" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:41:58 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Henry Tieman , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:20 +0800 Message-Id: <20190923074448.7847-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 02/30] net/ice/base: add support for tunnel packets X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add VXLAN tunnel training packets to flow director and change the interface to support tunnel packets. Signed-off-by: Henry Tieman Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 266 ++++++++++++++++++++++++++++++++-------- drivers/net/ice/base/ice_fdir.h | 8 +- drivers/net/ice/base/ice_type.h | 10 +- 3 files changed, 228 insertions(+), 56 deletions(-) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 9ef91b3b8..b92603e10 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -5,7 +5,7 @@ #include "ice_common.h" #include "ice_fdir.h" -/* These are dummy packet headers used to program flow director filters. */ +/* These are training packet headers used to program flow director filters. */ static const u8 ice_fdir_tcpv4_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, @@ -88,47 +88,177 @@ static const u8 ice_fdir_ipv6_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -/* Flow Director dummy packet table */ +static const u8 ice_fdir_tcp4_tun_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x5a, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, + 0x45, 0x00, 0x00, 0x28, 0x00, 0x00, 0x40, 0x00, + 0x40, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_udp4_tun_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x4e, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, + 0x45, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x40, 0x00, + 0x40, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_sctp4_tun_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x52, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, + 0x45, 0x00, 0x00, 0x20, 0x00, 0x01, 0x00, 0x00, + 0x40, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_ip4_tun_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x46, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, + 0x45, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, + 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_tcp6_tun_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x6e, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, + 0x60, 0x00, 0x00, 0x00, 0x00, 0x14, 0x06, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_udp6_tun_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x62, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, + 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x11, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_sctp6_tun_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x66, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, + 0x60, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x84, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_ip6_tun_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x5a, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, + 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +/* Flow Director no-op training packet table */ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = { { ICE_FLTR_PTYPE_NONF_IPV4_TCP, - sizeof(ice_fdir_tcpv4_pkt), - ice_fdir_tcpv4_pkt, + sizeof(ice_fdir_tcpv4_pkt), ice_fdir_tcpv4_pkt, + sizeof(ice_fdir_tcp4_tun_pkt), ice_fdir_tcp4_tun_pkt, }, { ICE_FLTR_PTYPE_NONF_IPV4_UDP, - sizeof(ice_fdir_udpv4_pkt), - ice_fdir_udpv4_pkt, + sizeof(ice_fdir_udpv4_pkt), ice_fdir_udpv4_pkt, + sizeof(ice_fdir_udp4_tun_pkt), ice_fdir_udp4_tun_pkt, }, { ICE_FLTR_PTYPE_NONF_IPV4_SCTP, - sizeof(ice_fdir_sctpv4_pkt), - ice_fdir_sctpv4_pkt, + sizeof(ice_fdir_sctpv4_pkt), ice_fdir_sctpv4_pkt, + sizeof(ice_fdir_sctp4_tun_pkt), ice_fdir_sctp4_tun_pkt, }, { ICE_FLTR_PTYPE_NONF_IPV4_OTHER, - sizeof(ice_fdir_ipv4_pkt), - ice_fdir_ipv4_pkt, + sizeof(ice_fdir_ipv4_pkt), ice_fdir_ipv4_pkt, + sizeof(ice_fdir_ip4_tun_pkt), ice_fdir_ip4_tun_pkt, }, { ICE_FLTR_PTYPE_NONF_IPV6_TCP, - sizeof(ice_fdir_tcpv6_pkt), - ice_fdir_tcpv6_pkt, + sizeof(ice_fdir_tcpv6_pkt), ice_fdir_tcpv6_pkt, + sizeof(ice_fdir_tcp6_tun_pkt), ice_fdir_tcp6_tun_pkt, }, { ICE_FLTR_PTYPE_NONF_IPV6_UDP, - sizeof(ice_fdir_udpv6_pkt), - ice_fdir_udpv6_pkt, + sizeof(ice_fdir_udpv6_pkt), ice_fdir_udpv6_pkt, + sizeof(ice_fdir_udp6_tun_pkt), ice_fdir_udp6_tun_pkt, }, { ICE_FLTR_PTYPE_NONF_IPV6_SCTP, - sizeof(ice_fdir_sctpv6_pkt), - ice_fdir_sctpv6_pkt, + sizeof(ice_fdir_sctpv6_pkt), ice_fdir_sctpv6_pkt, + sizeof(ice_fdir_sctp6_tun_pkt), ice_fdir_sctp6_tun_pkt, }, { ICE_FLTR_PTYPE_NONF_IPV6_OTHER, - sizeof(ice_fdir_ipv6_pkt), - ice_fdir_ipv6_pkt, + sizeof(ice_fdir_ipv6_pkt), ice_fdir_ipv6_pkt, + sizeof(ice_fdir_ip6_tun_pkt), ice_fdir_ip6_tun_pkt, }, }; @@ -377,15 +507,20 @@ static void ice_pkt_insert_u32(u8 *pkt, int offset, __be32 data) } /** - * ice_fdir_get_prgm_pkt - generate a dummy packet + * ice_fdir_get_gen_prgm_pkt - generate a training packet + * @hw: pointer to the hardware structure * @input: flow director filter data structure * @pkt: pointer to return filter packet * @frag: generate a fragment packet + * @tun: true implies generate a tunnel packet */ enum ice_status -ice_fdir_get_prgm_pkt(struct ice_fdir_fltr *input, u8 *pkt, bool frag) +ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, + u8 *pkt, bool frag, bool tun) { enum ice_fltr_ptype flow; + u16 tnl_port; + u8 *loc; u16 idx; if (input->flow_type == ICE_FLTR_PTYPE_NONF_IPV4_OTHER) { @@ -431,83 +566,96 @@ ice_fdir_get_prgm_pkt(struct ice_fdir_fltr *input, u8 *pkt, bool frag) break; if (idx == ICE_FDIR_NUM_PKT) return ICE_ERR_PARAM; - ice_memcpy(pkt, ice_fdir_pkt[idx].pkt, ice_fdir_pkt[idx].pkt_len, - ICE_NONDMA_TO_NONDMA); + if (!tun) { + ice_memcpy(pkt, ice_fdir_pkt[idx].pkt, + ice_fdir_pkt[idx].pkt_len, ICE_NONDMA_TO_NONDMA); + loc = pkt; + } else { + if (!ice_get_open_tunnel_port(hw, TNL_ALL, &tnl_port)) + return ICE_ERR_DOES_NOT_EXIST; + if (!ice_fdir_pkt[idx].tun_pkt) + return ICE_ERR_PARAM; + ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt, + ice_fdir_pkt[idx].tun_pkt_len, ICE_NONDMA_TO_NONDMA); + ice_pkt_insert_u16(pkt, ICE_IPV4_UDP_DST_PORT_OFFSET, + HTONS(tnl_port)); + loc = &pkt[ICE_FDIR_TUN_PKT_OFF]; + } switch (flow) { case ICE_FLTR_PTYPE_NONF_IPV4_TCP: - ice_pkt_insert_u32(pkt, ICE_IPV4_DST_ADDR_OFFSET, + ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, input->ip.v4.dst_ip); - ice_pkt_insert_u16(pkt, ICE_IPV4_TCP_DST_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV4_TCP_DST_PORT_OFFSET, input->ip.v4.dst_port); - ice_pkt_insert_u32(pkt, ICE_IPV4_SRC_ADDR_OFFSET, + ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET, input->ip.v4.src_ip); - ice_pkt_insert_u16(pkt, ICE_IPV4_TCP_SRC_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV4_TCP_SRC_PORT_OFFSET, input->ip.v4.src_port); if (frag) - pkt[20] = ICE_FDIR_IPV4_PKT_FLAG_DF; + loc[20] = ICE_FDIR_IPV4_PKT_FLAG_DF; break; case ICE_FLTR_PTYPE_NONF_IPV4_UDP: - ice_pkt_insert_u32(pkt, ICE_IPV4_DST_ADDR_OFFSET, + ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, input->ip.v4.dst_ip); - ice_pkt_insert_u16(pkt, ICE_IPV4_UDP_DST_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV4_UDP_DST_PORT_OFFSET, input->ip.v4.dst_port); - ice_pkt_insert_u32(pkt, ICE_IPV4_SRC_ADDR_OFFSET, + ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET, input->ip.v4.src_ip); - ice_pkt_insert_u16(pkt, ICE_IPV4_UDP_SRC_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV4_UDP_SRC_PORT_OFFSET, input->ip.v4.src_port); break; case ICE_FLTR_PTYPE_NONF_IPV4_SCTP: - ice_pkt_insert_u32(pkt, ICE_IPV4_DST_ADDR_OFFSET, + ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, input->ip.v4.dst_ip); - ice_pkt_insert_u16(pkt, ICE_IPV4_SCTP_DST_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV4_SCTP_DST_PORT_OFFSET, input->ip.v4.dst_port); - ice_pkt_insert_u32(pkt, ICE_IPV4_SRC_ADDR_OFFSET, + ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET, input->ip.v4.src_ip); - ice_pkt_insert_u16(pkt, ICE_IPV4_SCTP_SRC_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV4_SCTP_SRC_PORT_OFFSET, input->ip.v4.src_port); break; case ICE_FLTR_PTYPE_NONF_IPV4_OTHER: - ice_pkt_insert_u32(pkt, ICE_IPV4_DST_ADDR_OFFSET, + ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, input->ip.v4.dst_ip); - ice_pkt_insert_u32(pkt, ICE_IPV4_SRC_ADDR_OFFSET, + ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET, input->ip.v4.src_ip); - ice_pkt_insert_u16(pkt, ICE_IPV4_PROTO_OFFSET, 0); + ice_pkt_insert_u16(loc, ICE_IPV4_PROTO_OFFSET, 0); break; case ICE_FLTR_PTYPE_NONF_IPV6_TCP: - ice_pkt_insert_ipv6_addr(pkt, ICE_IPV6_DST_ADDR_OFFSET, + ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, input->ip.v6.dst_ip); - ice_pkt_insert_ipv6_addr(pkt, ICE_IPV6_SRC_ADDR_OFFSET, + ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_SRC_ADDR_OFFSET, input->ip.v6.src_ip); - ice_pkt_insert_u16(pkt, ICE_IPV6_TCP_DST_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV6_TCP_DST_PORT_OFFSET, input->ip.v6.dst_port); - ice_pkt_insert_u16(pkt, ICE_IPV6_TCP_SRC_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV6_TCP_SRC_PORT_OFFSET, input->ip.v6.src_port); break; case ICE_FLTR_PTYPE_NONF_IPV6_UDP: - ice_pkt_insert_ipv6_addr(pkt, ICE_IPV6_DST_ADDR_OFFSET, + ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, input->ip.v6.dst_ip); - ice_pkt_insert_ipv6_addr(pkt, ICE_IPV6_SRC_ADDR_OFFSET, + ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_SRC_ADDR_OFFSET, input->ip.v6.src_ip); - ice_pkt_insert_u16(pkt, ICE_IPV6_UDP_DST_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV6_UDP_DST_PORT_OFFSET, input->ip.v6.dst_port); - ice_pkt_insert_u16(pkt, ICE_IPV6_UDP_SRC_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV6_UDP_SRC_PORT_OFFSET, input->ip.v6.src_port); break; case ICE_FLTR_PTYPE_NONF_IPV6_SCTP: - ice_pkt_insert_ipv6_addr(pkt, ICE_IPV6_DST_ADDR_OFFSET, + ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, input->ip.v6.dst_ip); - ice_pkt_insert_ipv6_addr(pkt, ICE_IPV6_SRC_ADDR_OFFSET, + ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_SRC_ADDR_OFFSET, input->ip.v6.src_ip); - ice_pkt_insert_u16(pkt, ICE_IPV6_SCTP_DST_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV6_SCTP_DST_PORT_OFFSET, input->ip.v6.dst_port); - ice_pkt_insert_u16(pkt, ICE_IPV6_SCTP_SRC_PORT_OFFSET, + ice_pkt_insert_u16(loc, ICE_IPV6_SCTP_SRC_PORT_OFFSET, input->ip.v6.src_port); break; case ICE_FLTR_PTYPE_NONF_IPV6_OTHER: - ice_pkt_insert_ipv6_addr(pkt, ICE_IPV6_DST_ADDR_OFFSET, + ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, input->ip.v6.dst_ip); - ice_pkt_insert_ipv6_addr(pkt, ICE_IPV6_SRC_ADDR_OFFSET, + ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_SRC_ADDR_OFFSET, input->ip.v6.src_ip); break; default: @@ -515,12 +663,24 @@ ice_fdir_get_prgm_pkt(struct ice_fdir_fltr *input, u8 *pkt, bool frag) } if (input->flex_fltr) - ice_pkt_insert_u16(pkt, input->flex_offset, input->flex_word); + ice_pkt_insert_u16(loc, input->flex_offset, input->flex_word); return ICE_SUCCESS; } /** + * ice_fdir_get_prgm_pkt - generate a training packet + * @input: flow director filter data structure + * @pkt: pointer to return filter packet + * @frag: generate a fragment packet + */ +enum ice_status +ice_fdir_get_prgm_pkt(struct ice_fdir_fltr *input, u8 *pkt, bool frag) +{ + return ice_fdir_get_gen_prgm_pkt(NULL, input, pkt, frag, false); +} + +/** * ice_fdir_has_frag - does flow type have 2 ptypes * @flow: flow ptype * diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index 8490fac61..9e7e22033 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -58,7 +58,8 @@ enum ice_status ice_clear_pf_fd_table(struct ice_hw *hw); #define ICE_IP_PROTO_IP 0 #define ICE_IP_PROTO_ESP 50 -#define ICE_FDIR_MAX_RAW_PKT_SIZE 512 +#define ICE_FDIR_TUN_PKT_OFF 50 +#define ICE_FDIR_MAX_RAW_PKT_SIZE (512 + ICE_FDIR_TUN_PKT_OFF) #define ICE_FDIR_BUF_FULL_MARGIN 10 #define ICE_FDIR_BUF_HEAD_ROOM 32 @@ -175,12 +176,17 @@ struct ice_fdir_base_pkt { enum ice_fltr_ptype flow; u16 pkt_len; const u8 *pkt; + u16 tun_pkt_len; + const u8 *tun_pkt; }; void ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input, struct ice_fltr_desc *fdesc, bool add); enum ice_status +ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, + u8 *pkt, bool frag, bool tun); +enum ice_status ice_fdir_get_prgm_pkt(struct ice_fdir_fltr *input, u8 *pkt, bool frag); enum ice_status ice_add_del_fdir(struct ice_hw *hw, struct ice_fdir_fltr *input, bool add); diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 150b4c5c5..7d0a4f63f 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -296,13 +296,19 @@ enum ice_fltr_ptype { ICE_FLTR_PTYPE_MAX, }; +enum ice_fd_hw_seg { + ICE_FD_HW_SEG_NON_TUN = 0, + ICE_FD_HW_SEG_TUN, + ICE_FD_HW_SEG_MAX, +}; + /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */ #define ICE_MAX_FDIR_VSI_PER_FILTER 2 struct ice_fd_hw_prof { - struct ice_flow_seg_info *fdir_seg; + struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; int cnt; - u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER]; + u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; }; From patchwork Mon Sep 23 07:44:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59575 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4D0AE1BEA1; Mon, 23 Sep 2019 09:42:13 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 6242D1BE8B for ; Mon, 23 Sep 2019 09:42:02 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445514" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:00 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Junfeng Guo , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:21 +0800 Message-Id: <20190923074448.7847-4-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 03/30] net/ice/base: add non-word aligned ip field support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add non-word aligned field support for ipv4 with ttl, tos and proto. All these fields are one byte within one word. In order to match bytes within the IPv4 header for flow director we need to use a mask. Signed-off-by: Junfeng Guo Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 30 +++++++++++++++++++++++------- drivers/net/ice/base/ice_fdir.h | 4 ++++ 2 files changed, 27 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index b92603e10..db5bbc6ad 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -485,6 +485,17 @@ static void ice_pkt_insert_ipv6_addr(u8 *pkt, int offset, __be32 *addr) } /** + * ice_pkt_insert_u8 - insert a u8 value into a memory buffer. + * @pkt: packet buffer + * @offset: offset into buffer + * @data: 8 bit value to convert and insert into pkt at offset + */ +static void ice_pkt_insert_u8(u8 *pkt, int offset, u8 data) +{ + ice_memcpy(pkt + offset, &data, sizeof(data), ICE_NONDMA_TO_NONDMA); +} + +/** * ice_pkt_insert_u16 - insert a be16 value into a memory buffer. * @pkt: packet buffer * @offset: offset into buffer @@ -534,11 +545,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, case ICE_IP_PROTO_SCTP: flow = ICE_FLTR_PTYPE_NONF_IPV4_SCTP; break; - case ICE_IP_PROTO_IP: + default: flow = ICE_FLTR_PTYPE_NONF_IPV4_OTHER; break; - default: - return ICE_ERR_PARAM; } } else if (input->flow_type == ICE_FLTR_PTYPE_NONF_IPV6_OTHER) { switch (input->ip.v6.proto) { @@ -551,11 +560,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, case ICE_IP_PROTO_SCTP: flow = ICE_FLTR_PTYPE_NONF_IPV6_SCTP; break; - case ICE_IP_PROTO_IP: + default: flow = ICE_FLTR_PTYPE_NONF_IPV6_OTHER; break; - default: - return ICE_ERR_PARAM; } } else { flow = input->flow_type; @@ -592,6 +599,8 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v4.src_ip); ice_pkt_insert_u16(loc, ICE_IPV4_TCP_SRC_PORT_OFFSET, input->ip.v4.src_port); + ice_pkt_insert_u8(loc, ICE_IPV4_TOS_OFFSET, input->ip.v4.tos); + ice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl); if (frag) loc[20] = ICE_FDIR_IPV4_PKT_FLAG_DF; break; @@ -604,6 +613,8 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v4.src_ip); ice_pkt_insert_u16(loc, ICE_IPV4_UDP_SRC_PORT_OFFSET, input->ip.v4.src_port); + ice_pkt_insert_u8(loc, ICE_IPV4_TOS_OFFSET, input->ip.v4.tos); + ice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl); break; case ICE_FLTR_PTYPE_NONF_IPV4_SCTP: ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, @@ -614,13 +625,18 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v4.src_ip); ice_pkt_insert_u16(loc, ICE_IPV4_SCTP_SRC_PORT_OFFSET, input->ip.v4.src_port); + ice_pkt_insert_u8(loc, ICE_IPV4_TOS_OFFSET, input->ip.v4.tos); + ice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl); break; case ICE_FLTR_PTYPE_NONF_IPV4_OTHER: ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, input->ip.v4.dst_ip); ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET, input->ip.v4.src_ip); - ice_pkt_insert_u16(loc, ICE_IPV4_PROTO_OFFSET, 0); + ice_pkt_insert_u8(loc, ICE_IPV4_TOS_OFFSET, input->ip.v4.tos); + ice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl); + ice_pkt_insert_u8(loc, ICE_IPV4_PROTO_OFFSET, + input->ip.v4.proto); break; case ICE_FLTR_PTYPE_NONF_IPV6_TCP: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index 9e7e22033..e817057c8 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -82,6 +82,9 @@ enum ice_status ice_clear_pf_fd_table(struct ice_hw *hw); #define ICE_IPV6_SCTP_SRC_PORT_OFFSET 54 #define ICE_IPV6_SCTP_DST_PORT_OFFSET 56 +#define ICE_IPV4_TOS_OFFSET 15 +#define ICE_IPV4_TTL_OFFSET 22 + #define ICE_FDIR_MAX_FLTRS 16384 /* IP v4 has 2 flag bits that enable fragment processing: DF and MF. DF @@ -123,6 +126,7 @@ struct ice_fdir_v4 { u8 tos; u8 ip_ver; u8 proto; + u8 ttl; }; #define ICE_IPV6_ADDR_LEN_AS_U32 4 From patchwork Mon Sep 23 07:44:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59576 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 18F401BEA6; Mon, 23 Sep 2019 09:42:18 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id B49231BE8D for ; Mon, 23 Sep 2019 09:42:04 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445537" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:02 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Junfeng Guo , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:22 +0800 Message-Id: <20190923074448.7847-5-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 04/30] net/ice/base: add non-word aligned ipv6 field support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add non-word aligned field support for IPv6 with hlim, tc and proto. All these fields are one byte within one word. In order to match bytes within the IPv6 header for flow director we need to use a mask. Signed-off-by: Junfeng Guo Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 32 ++++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_fdir.h | 4 ++++ 2 files changed, 36 insertions(+) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index db5bbc6ad..e35506006 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -496,6 +496,28 @@ static void ice_pkt_insert_u8(u8 *pkt, int offset, u8 data) } /** + * ice_pkt_insert_u8_tc - insert a u8 value into a memory buffer for tc ipv6. + * @pkt: packet buffer + * @offset: offset into buffer + * @data: 8 bit value to convert and insert into pkt at offset + * + * This function is designed for inserting Traffic Class (tc) for IPv6, + * since that tc is not aligned in number of bytes. Here we split it out + * into two part and fill each byte with data copy from pkt, then insert + * the two bytes data one by one. + */ +static void ice_pkt_insert_u8_tc(u8 *pkt, int offset, u8 data) +{ + u8 high, low; + + high = (data >> 4) + (*(pkt + offset) & 0xF0); + ice_memcpy(pkt + offset, &high, sizeof(high), ICE_NONDMA_TO_NONDMA); + + low = (*(pkt + offset + 1) & 0x0F) + ((data & 0x0F) << 4); + ice_memcpy(pkt + offset + 1, &low, sizeof(low), ICE_NONDMA_TO_NONDMA); +} + +/** * ice_pkt_insert_u16 - insert a be16 value into a memory buffer. * @pkt: packet buffer * @offset: offset into buffer @@ -647,6 +669,8 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v6.dst_port); ice_pkt_insert_u16(loc, ICE_IPV6_TCP_SRC_PORT_OFFSET, input->ip.v6.src_port); + ice_pkt_insert_u8_tc(loc, ICE_IPV6_TC_OFFSET, input->ip.v6.tc); + ice_pkt_insert_u8(loc, ICE_IPV6_HLIM_OFFSET, input->ip.v6.hlim); break; case ICE_FLTR_PTYPE_NONF_IPV6_UDP: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, @@ -657,6 +681,8 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v6.dst_port); ice_pkt_insert_u16(loc, ICE_IPV6_UDP_SRC_PORT_OFFSET, input->ip.v6.src_port); + ice_pkt_insert_u8_tc(loc, ICE_IPV6_TC_OFFSET, input->ip.v6.tc); + ice_pkt_insert_u8(loc, ICE_IPV6_HLIM_OFFSET, input->ip.v6.hlim); break; case ICE_FLTR_PTYPE_NONF_IPV6_SCTP: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, @@ -667,12 +693,18 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v6.dst_port); ice_pkt_insert_u16(loc, ICE_IPV6_SCTP_SRC_PORT_OFFSET, input->ip.v6.src_port); + ice_pkt_insert_u8_tc(loc, ICE_IPV6_TC_OFFSET, input->ip.v6.tc); + ice_pkt_insert_u8(loc, ICE_IPV6_HLIM_OFFSET, input->ip.v6.hlim); break; case ICE_FLTR_PTYPE_NONF_IPV6_OTHER: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, input->ip.v6.dst_ip); ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_SRC_ADDR_OFFSET, input->ip.v6.src_ip); + ice_pkt_insert_u8_tc(loc, ICE_IPV6_TC_OFFSET, input->ip.v6.tc); + ice_pkt_insert_u8(loc, ICE_IPV6_HLIM_OFFSET, input->ip.v6.hlim); + ice_pkt_insert_u8(loc, ICE_IPV6_PROTO_OFFSET, + input->ip.v6.proto); break; default: return ICE_ERR_PARAM; diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index e817057c8..e0f3cd481 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -84,6 +84,9 @@ enum ice_status ice_clear_pf_fd_table(struct ice_hw *hw); #define ICE_IPV4_TOS_OFFSET 15 #define ICE_IPV4_TTL_OFFSET 22 +#define ICE_IPV6_TC_OFFSET 14 +#define ICE_IPV6_HLIM_OFFSET 21 +#define ICE_IPV6_PROTO_OFFSET 20 #define ICE_FDIR_MAX_FLTRS 16384 @@ -140,6 +143,7 @@ struct ice_fdir_v6 { __be32 sec_parm_idx; /* security parameter index */ u8 tc; u8 proto; + u8 hlim; }; struct ice_fdir_extra { From patchwork Mon Sep 23 07:44:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59577 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1570E1BEB2; Mon, 23 Sep 2019 09:42:29 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 82ADA1BE92 for ; Mon, 23 Sep 2019 09:42:06 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445553" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:04 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Zhirun Yan , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:23 +0800 Message-Id: <20190923074448.7847-6-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 05/30] net/ice/base: correct the mask for checking protocol header X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Before this patch, the logic of protocol header checking only support non-tunneled packet. This patch remove the inner protocol in L3/L4 RSS seg hdr mask and change the protocol header validation to reflect this. So, for ice_add_rss_cfg(), the last parameter addl_hdrs could specify the protocol header for tunnel. Signed-off-by: Zhirun Yan Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 769fd2da7..682f26ce6 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -372,15 +372,18 @@ struct ice_flow_prof_params { ice_declare_bitmap(ptypes, ICE_FLOW_PTYPE_MAX); }; +#define ICE_FLOW_RSS_HDRS_INNER_MASK \ + (ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_GTPC | \ + ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU) + #define ICE_FLOW_SEG_HDRS_L2_MASK \ (ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN) #define ICE_FLOW_SEG_HDRS_L3_MASK \ (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | \ - ICE_FLOW_SEG_HDR_ARP | ICE_FLOW_SEG_HDR_PPPOE) + ICE_FLOW_SEG_HDR_ARP) #define ICE_FLOW_SEG_HDRS_L4_MASK \ (ICE_FLOW_SEG_HDR_ICMP | ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \ - ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC | \ - ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU) + ICE_FLOW_SEG_HDR_SCTP) /** * ice_flow_val_hdrs - validates packet segments for valid protocol headers @@ -1686,13 +1689,11 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len, (ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN) #define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \ - (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_PPPOE) + (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6) #define ICE_FLOW_RSS_SEG_HDR_L4_MASKS \ (ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \ - ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC_TEID | \ - ICE_FLOW_SEG_HDR_GTPU) - + ICE_FLOW_SEG_HDR_SCTP) #define ICE_FLOW_RSS_SEG_HDR_VAL_MASKS \ (ICE_FLOW_RSS_SEG_HDR_L2_MASKS | \ @@ -1729,11 +1730,12 @@ ice_flow_set_rss_seg_info(struct ice_flow_seg_info *segs, u64 hash_fields, } ICE_FLOW_SET_HDRS(segs, flow_hdr); - if (segs->hdrs & ~ICE_FLOW_RSS_SEG_HDR_VAL_MASKS) + if (segs->hdrs & ~ICE_FLOW_RSS_SEG_HDR_VAL_MASKS & + ~ICE_FLOW_RSS_HDRS_INNER_MASK) return ICE_ERR_PARAM; val = (u64)(segs->hdrs & ICE_FLOW_RSS_SEG_HDR_L3_MASKS); - if (!ice_is_pow2(val)) + if (val && !ice_is_pow2(val)) return ICE_ERR_CFG; val = (u64)(segs->hdrs & ICE_FLOW_RSS_SEG_HDR_L4_MASKS); From patchwork Mon Sep 23 07:44:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59578 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D809B1BEB9; Mon, 23 Sep 2019 09:42:30 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 01B7E1BE92 for ; Mon, 23 Sep 2019 09:42:07 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445561" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:06 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:24 +0800 Message-Id: <20190923074448.7847-7-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 06/30] net/ice/base: propagate errors from functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" There could be an error returned from ice_fill_adv_dummy_packet() so we need to propagate that to the caller. Additionally, the call to ice_flow_xtract_pkt_flags() could also return an error so we need to propagate it as well. Also add in the correct offsets for GENEVE and VXLAN_GPE to the dummy packets. Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 9 ++++++--- drivers/net/ice/base/ice_switch.c | 8 ++++++-- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 682f26ce6..7dae53270 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -869,9 +869,12 @@ ice_flow_create_xtrct_seq(struct ice_hw *hw, /* For ACL, we also need to extract the direction bit (Rx,Tx) data from * packet flags */ - if (params->blk == ICE_BLK_ACL) - ice_flow_xtract_pkt_flags(hw, params, - ICE_RX_MDID_PKT_FLAGS_15_0); + if (params->blk == ICE_BLK_ACL) { + status = ice_flow_xtract_pkt_flags(hw, params, + ICE_RX_MDID_PKT_FLAGS_15_0); + if (status) + return status; + } for (i = 0; i < params->prof->segs_cnt; i++) { u64 match = params->prof->segs[i].match; diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 00358e4db..fa023169d 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -156,6 +156,7 @@ struct ice_dummy_pkt_offsets dummy_udp_tun_tcp_packet_offsets[] = { { ICE_UDP_OF, 34 }, { ICE_VXLAN, 42 }, { ICE_GENEVE, 42 }, + { ICE_VXLAN_GPE, 42 }, { ICE_MAC_IL, 50 }, { ICE_IPV4_IL, 64 }, { ICE_TCP_IL, 84 }, @@ -208,6 +209,7 @@ struct ice_dummy_pkt_offsets dummy_udp_tun_udp_packet_offsets[] = { { ICE_UDP_OF, 34 }, { ICE_VXLAN, 42 }, { ICE_GENEVE, 42 }, + { ICE_VXLAN_GPE, 42 }, { ICE_MAC_IL, 50 }, { ICE_IPV4_IL, 64 }, { ICE_UDP_ILOS, 84 }, @@ -6189,8 +6191,10 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, s_rule->pdata.lkup_tx_rx.recipe_id = CPU_TO_LE16(rid); s_rule->pdata.lkup_tx_rx.act = CPU_TO_LE32(act); - ice_fill_adv_dummy_packet(lkups, lkups_cnt, s_rule, pkt, pkt_len, - pkt_offsets); + status = ice_fill_adv_dummy_packet(lkups, lkups_cnt, s_rule, pkt, + pkt_len, pkt_offsets); + if (status) + goto err_ice_add_adv_rule; if (rinfo->tun_type != ICE_NON_TUN) { status = ice_fill_adv_packet_tun(hw, rinfo->tun_type, From patchwork Mon Sep 23 07:44:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59579 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7B7641BEB8; Mon, 23 Sep 2019 09:42:33 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id D32811BE9D for ; Mon, 23 Sep 2019 09:42:09 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445573" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:07 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Jacob Keller , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:25 +0800 Message-Id: <20190923074448.7847-8-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 07/30] net/ice/base: remove pointless NULL check of port info X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The code in ice_sched_cleanup_all checks whether the port info is NULL prior to calling ice_sched_clear_port. More importantly, it also checks whether the port structure has been initialized by checking its port_state field as well. Signed-off-by: Jacob Keller Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_sched.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 6732e291a..553fc28ff 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -840,8 +840,7 @@ void ice_sched_cleanup_all(struct ice_hw *hw) hw->layer_info = NULL; } - if (hw->port_info) - ice_sched_clear_port(hw->port_info); + ice_sched_clear_port(hw->port_info); hw->num_tx_sched_layers = 0; hw->num_tx_sched_phys_layers = 0; From patchwork Mon Sep 23 07:44:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59580 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 422F81BEC3; Mon, 23 Sep 2019 09:42:36 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 7B55C1BE9D for ; Mon, 23 Sep 2019 09:42:11 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445579" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:09 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:26 +0800 Message-Id: <20190923074448.7847-9-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 08/30] net/ice/base: remove RSS code as iavf host X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The DPDK PF doesn't support SRIOV so remove the related iavf host code. Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 128 ---------------------------------------- 1 file changed, 128 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 7dae53270..5d1b12d43 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -2128,134 +2128,6 @@ ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, return status; } -/* Mapping of AVF hash bit fields to an L3-L4 hash combination. - * As the ice_flow_avf_hdr_field represent individual bit shifts in a hash, - * convert its values to their appropriate flow L3, L4 values. - */ -#define ICE_FLOW_AVF_RSS_IPV4_MASKS \ - (BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_OTHER) | \ - BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV4)) -#define ICE_FLOW_AVF_RSS_TCP_IPV4_MASKS \ - (BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP_SYN_NO_ACK) | \ - BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP)) -#define ICE_FLOW_AVF_RSS_UDP_IPV4_MASKS \ - (BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV4_UDP) | \ - BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV4_UDP) | \ - BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_UDP)) -#define ICE_FLOW_AVF_RSS_ALL_IPV4_MASKS \ - (ICE_FLOW_AVF_RSS_TCP_IPV4_MASKS | ICE_FLOW_AVF_RSS_UDP_IPV4_MASKS | \ - ICE_FLOW_AVF_RSS_IPV4_MASKS | BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP)) - -#define ICE_FLOW_AVF_RSS_IPV6_MASKS \ - (BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_OTHER) | \ - BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV6)) -#define ICE_FLOW_AVF_RSS_UDP_IPV6_MASKS \ - (BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP) | \ - BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP) | \ - BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_UDP)) -#define ICE_FLOW_AVF_RSS_TCP_IPV6_MASKS \ - (BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP_SYN_NO_ACK) | \ - BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP)) -#define ICE_FLOW_AVF_RSS_ALL_IPV6_MASKS \ - (ICE_FLOW_AVF_RSS_TCP_IPV6_MASKS | ICE_FLOW_AVF_RSS_UDP_IPV6_MASKS | \ - ICE_FLOW_AVF_RSS_IPV6_MASKS | BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP)) - -#define ICE_FLOW_MAX_CFG 10 - -/** - * ice_add_avf_rss_cfg - add an RSS configuration for AVF driver - * @hw: pointer to the hardware structure - * @vsi_handle: software VSI handle - * @avf_hash: hash bit fields (ICE_AVF_FLOW_FIELD_*) to configure - * - * This function will take the hash bitmap provided by the AVF driver via a - * message, convert it to ICE-compatible values, and configure RSS flow - * profiles. - */ -enum ice_status -ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 avf_hash) -{ - enum ice_status status = ICE_SUCCESS; - u64 hash_flds; - - if (avf_hash == ICE_AVF_FLOW_FIELD_INVALID || - !ice_is_vsi_valid(hw, vsi_handle)) - return ICE_ERR_PARAM; - - /* Make sure no unsupported bits are specified */ - if (avf_hash & ~(ICE_FLOW_AVF_RSS_ALL_IPV4_MASKS | - ICE_FLOW_AVF_RSS_ALL_IPV6_MASKS)) - return ICE_ERR_CFG; - - hash_flds = avf_hash; - - /* Always create an L3 RSS configuration for any L4 RSS configuration */ - if (hash_flds & ICE_FLOW_AVF_RSS_ALL_IPV4_MASKS) - hash_flds |= ICE_FLOW_AVF_RSS_IPV4_MASKS; - - if (hash_flds & ICE_FLOW_AVF_RSS_ALL_IPV6_MASKS) - hash_flds |= ICE_FLOW_AVF_RSS_IPV6_MASKS; - - /* Create the corresponding RSS configuration for each valid hash bit */ - while (hash_flds) { - u64 rss_hash = ICE_HASH_INVALID; - - if (hash_flds & ICE_FLOW_AVF_RSS_ALL_IPV4_MASKS) { - if (hash_flds & ICE_FLOW_AVF_RSS_IPV4_MASKS) { - rss_hash = ICE_FLOW_HASH_IPV4; - hash_flds &= ~ICE_FLOW_AVF_RSS_IPV4_MASKS; - } else if (hash_flds & - ICE_FLOW_AVF_RSS_TCP_IPV4_MASKS) { - rss_hash = ICE_FLOW_HASH_IPV4 | - ICE_FLOW_HASH_TCP_PORT; - hash_flds &= ~ICE_FLOW_AVF_RSS_TCP_IPV4_MASKS; - } else if (hash_flds & - ICE_FLOW_AVF_RSS_UDP_IPV4_MASKS) { - rss_hash = ICE_FLOW_HASH_IPV4 | - ICE_FLOW_HASH_UDP_PORT; - hash_flds &= ~ICE_FLOW_AVF_RSS_UDP_IPV4_MASKS; - } else if (hash_flds & - BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP)) { - rss_hash = ICE_FLOW_HASH_IPV4 | - ICE_FLOW_HASH_SCTP_PORT; - hash_flds &= - ~BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP); - } - } else if (hash_flds & ICE_FLOW_AVF_RSS_ALL_IPV6_MASKS) { - if (hash_flds & ICE_FLOW_AVF_RSS_IPV6_MASKS) { - rss_hash = ICE_FLOW_HASH_IPV6; - hash_flds &= ~ICE_FLOW_AVF_RSS_IPV6_MASKS; - } else if (hash_flds & - ICE_FLOW_AVF_RSS_TCP_IPV6_MASKS) { - rss_hash = ICE_FLOW_HASH_IPV6 | - ICE_FLOW_HASH_TCP_PORT; - hash_flds &= ~ICE_FLOW_AVF_RSS_TCP_IPV6_MASKS; - } else if (hash_flds & - ICE_FLOW_AVF_RSS_UDP_IPV6_MASKS) { - rss_hash = ICE_FLOW_HASH_IPV6 | - ICE_FLOW_HASH_UDP_PORT; - hash_flds &= ~ICE_FLOW_AVF_RSS_UDP_IPV6_MASKS; - } else if (hash_flds & - BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP)) { - rss_hash = ICE_FLOW_HASH_IPV6 | - ICE_FLOW_HASH_SCTP_PORT; - hash_flds &= - ~BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP); - } - } - - if (rss_hash == ICE_HASH_INVALID) - return ICE_ERR_OUT_OF_RANGE; - - status = ice_add_rss_cfg(hw, vsi_handle, rss_hash, - ICE_FLOW_SEG_HDR_NONE); - if (status) - break; - } - - return status; -} - /** * ice_replay_rss_cfg - replay RSS configurations associated with VSI * @hw: pointer to the hardware structure From patchwork Mon Sep 23 07:44:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59581 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 058A91BEC6; Mon, 23 Sep 2019 09:42:39 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 42C751BEA0 for ; Mon, 23 Sep 2019 09:42:13 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445589" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:11 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Junfeng Guo , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:27 +0800 Message-Id: <20190923074448.7847-10-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 09/30] net/ice/base: add support for switch rule about VLAN PPPoE X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for switch rule about single-VLAN-PPPoE. Note that double VLAN is not supported by the hardware at this point, therefore only single-VLAN support for PPPoE is added. Signed-off-by: Junfeng Guo Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_protocol_type.h | 8 ++++++++ drivers/net/ice/base/ice_switch.c | 19 +++++++++++++++---- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index cdb691523..c6caa8562 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -31,6 +31,7 @@ enum ice_protocol_type { ICE_MAC_OFOS = 0, ICE_MAC_IL, ICE_ETYPE_OL, + ICE_VLAN_OFOS, ICE_IPV4_OFOS, ICE_IPV4_IL, ICE_IPV6_OFOS, @@ -117,6 +118,7 @@ enum ice_prot_id { #define ICE_MAC_OFOS_HW 1 #define ICE_MAC_IL_HW 4 #define ICE_ETYPE_OL_HW 9 +#define ICE_VLAN_OL_HW 16 #define ICE_IPV4_OFOS_HW 32 #define ICE_IPV4_IL_HW 33 #define ICE_IPV6_OFOS_HW 40 @@ -162,6 +164,11 @@ struct ice_ether_vlan_hdr { u32 vlan_id; }; +struct ice_vlan_hdr { + u16 vlan; + u16 type; +}; + struct ice_ipv4_hdr { u8 version; u8 tos; @@ -239,6 +246,7 @@ struct ice_nvgre { union ice_prot_hdr { struct ice_ether_hdr eth_hdr; struct ice_ethtype_hdr ethertype; + struct ice_vlan_hdr vlan_hdr; struct ice_ipv4_hdr ipv4_hdr; struct ice_ipv6_hdr ipv6_hdr; struct ice_l4_hdr l4_hdr; diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index fa023169d..688584563 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -418,8 +418,9 @@ dummy_udp_gtp_packet[] = { static const struct ice_dummy_pkt_offsets dummy_pppoe_packet_offsets[] = { - { ICE_MAC_OFOS, 0 }, - { ICE_PPPOE, 14 }, + { ICE_MAC_OFOS, 0 }, + { ICE_VLAN_OFOS, 14}, + { ICE_PPPOE, 18 }, { ICE_PROTOCOL_LAST, 0 }, }; @@ -428,9 +429,11 @@ dummy_pppoe_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x88, 0x64, + 0x81, 0x00, + + 0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 14 */ - 0x11, 0x00, 0x00, 0x01, /* ICE_PPPOE 14 */ + 0x11, 0x00, 0x00, 0x01, /* ICE_PPPOE 18 */ 0x00, 0x4e, 0x00, 0x21, 0x45, 0x00, 0x00, 0x30, /* PDU */ @@ -4632,6 +4635,7 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[] = { { ICE_MAC_OFOS, { 0, 2, 4, 6, 8, 10, 12 } }, { ICE_MAC_IL, { 0, 2, 4, 6, 8, 10, 12 } }, { ICE_ETYPE_OL, { 0 } }, + { ICE_VLAN_OFOS, { 0, 2 } }, { ICE_IPV4_OFOS, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18 } }, { ICE_IPV4_IL, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18 } }, { ICE_IPV6_IL, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, @@ -4661,6 +4665,7 @@ static const struct ice_protocol_entry ice_prot_id_tbl[] = { { ICE_MAC_OFOS, ICE_MAC_OFOS_HW }, { ICE_MAC_IL, ICE_MAC_IL_HW }, { ICE_ETYPE_OL, ICE_ETYPE_OL_HW }, + { ICE_VLAN_OFOS, ICE_VLAN_OL_HW }, { ICE_IPV4_OFOS, ICE_IPV4_OFOS_HW }, { ICE_IPV4_IL, ICE_IPV4_IL_HW }, { ICE_IPV6_OFOS, ICE_IPV6_OFOS_HW }, @@ -5784,6 +5789,9 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, case ICE_ETYPE_OL: len = sizeof(struct ice_ethtype_hdr); break; + case ICE_VLAN_OFOS: + len = sizeof(struct ice_vlan_hdr); + break; case ICE_IPV4_OFOS: case ICE_IPV4_IL: len = sizeof(struct ice_ipv4_hdr); @@ -5812,6 +5820,9 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, case ICE_GTP: len = sizeof(struct ice_udp_gtp_hdr); break; + case ICE_PPPOE: + len = sizeof(struct ice_pppoe_hdr); + break; default: return ICE_ERR_PARAM; } From patchwork Mon Sep 23 07:44:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59582 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 547CE1BECD; Mon, 23 Sep 2019 09:42:41 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 446B61BE94 for ; Mon, 23 Sep 2019 09:42:15 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445600" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:13 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Jesse Brandeburg , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:28 +0800 Message-Id: <20190923074448.7847-11-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 10/30] net/ice/base: minor structure refactor X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When declaring the ice_prot_ext, and ice_prot_id_tbl structure, we can use a fixed length array instead of a variable length one which helps us catch future code changes that might desynchronize the enum ice_protocol_type and the structs. This change also necessitates removing the last member of the structs which was just there to be a placeholder. Also reorder the ice_prot_ext struct to match the ordering in the associated enum ice_protocol_type. Signed-off-by: Jesse Brandeburg Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_switch.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 688584563..250f664b2 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -4631,17 +4631,17 @@ ice_add_mac_with_counter(struct ice_hw *hw, struct ice_fltr_info *f_info) * matching entry describing its field. This needs to be updated if new * structure is added to that union. */ -static const struct ice_prot_ext_tbl_entry ice_prot_ext[] = { +static const struct ice_prot_ext_tbl_entry ice_prot_ext[ICE_PROTOCOL_LAST] = { { ICE_MAC_OFOS, { 0, 2, 4, 6, 8, 10, 12 } }, { ICE_MAC_IL, { 0, 2, 4, 6, 8, 10, 12 } }, { ICE_ETYPE_OL, { 0 } }, { ICE_VLAN_OFOS, { 0, 2 } }, { ICE_IPV4_OFOS, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18 } }, { ICE_IPV4_IL, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18 } }, - { ICE_IPV6_IL, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, - 26, 28, 30, 32, 34, 36, 38 } }, { ICE_IPV6_OFOS, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38 } }, + { ICE_IPV6_IL, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, + 26, 28, 30, 32, 34, 36, 38 } }, { ICE_TCP_IL, { 0, 2 } }, { ICE_UDP_OF, { 0, 2 } }, { ICE_UDP_ILOS, { 0, 2 } }, @@ -4652,7 +4652,6 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[] = { { ICE_NVGRE, { 0, 2, 4, 6 } }, { ICE_GTP, { 8, 10, 12, 14, 16, 18, 20 } }, { ICE_PPPOE, { 0, 2, 4, 6 } }, - { ICE_PROTOCOL_LAST, { 0 } } }; /* The following table describes preferred grouping of recipes. @@ -4661,7 +4660,7 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[] = { * following policy. */ -static const struct ice_protocol_entry ice_prot_id_tbl[] = { +static const struct ice_protocol_entry ice_prot_id_tbl[ICE_PROTOCOL_LAST] = { { ICE_MAC_OFOS, ICE_MAC_OFOS_HW }, { ICE_MAC_IL, ICE_MAC_IL_HW }, { ICE_ETYPE_OL, ICE_ETYPE_OL_HW }, @@ -4680,7 +4679,6 @@ static const struct ice_protocol_entry ice_prot_id_tbl[] = { { ICE_NVGRE, ICE_GRE_OF_HW }, { ICE_GTP, ICE_UDP_OF_HW }, { ICE_PPPOE, ICE_PPPOE_HW }, - { ICE_PROTOCOL_LAST, 0 } }; /** From patchwork Mon Sep 23 07:44:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59583 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 139BE1BEE1; Mon, 23 Sep 2019 09:42:45 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id C220F1BE94 for ; Mon, 23 Sep 2019 09:42:16 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445622" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:14 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:29 +0800 Message-Id: <20190923074448.7847-12-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 11/30] net/ice/base: associate switch recipe to profiles X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Properly associate switch recipes to profiles. Previous code was using the wrong bitfield for updating the associations, which was causing other PFs to not properly identify and use existing recipes. This sometimes resulted in rules not being added when it should have been possible. Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_switch.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 250f664b2..64c2aec19 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -5581,14 +5581,14 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, if (status) goto err_unroll; - ice_or_bitmap(rm->r_bitmap, r_bitmap, rm->r_bitmap, + ice_or_bitmap(r_bitmap, r_bitmap, rm->r_bitmap, ICE_MAX_NUM_RECIPES); status = ice_acquire_change_lock(hw, ICE_RES_WRITE); if (status) goto err_unroll; status = ice_aq_map_recipe_to_profile(hw, fvit->profile_id, - (u8 *)rm->r_bitmap, + (u8 *)r_bitmap, NULL); ice_release_change_lock(hw); @@ -5596,12 +5596,12 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, goto err_unroll; /* Update profile to recipe bitmap array */ - ice_memcpy(profile_to_recipe[fvit->profile_id], rm->r_bitmap, - sizeof(rm->r_bitmap), ICE_NONDMA_TO_NONDMA); + ice_memcpy(profile_to_recipe[fvit->profile_id], r_bitmap, + sizeof(r_bitmap), ICE_NONDMA_TO_NONDMA); /* Update recipe to profile bitmap array */ for (j = 0; j < ICE_MAX_NUM_RECIPES; j++) - if (ice_is_bit_set(rm->r_bitmap, j)) + if (ice_is_bit_set(r_bitmap, j)) ice_set_bit((u16)fvit->profile_id, recipe_to_profile[j]); } From patchwork Mon Sep 23 07:44:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59584 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8588F1BED3; Mon, 23 Sep 2019 09:42:47 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id BDBE01BEAE for ; Mon, 23 Sep 2019 09:42:18 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445635" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:16 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Zhirun Yan , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:30 +0800 Message-Id: <20190923074448.7847-13-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 12/30] net/ice/base: enable RSS for PPPoE with SCTP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add two ptypes(MAC_PPPOE_IPV4_SCTP and MAC_PPPOE_IPV6_SCTP) in sctp ptype bitmap to enable rss. Signed-off-by: Zhirun Yan Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 5d1b12d43..d91922527 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -253,7 +253,7 @@ static const u32 ice_ptypes_tcp_il[] = { static const u32 ice_ptypes_sctp_il[] = { 0x08000000, 0x01020204, 0x20408081, 0x04080810, 0x01020204, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x01040000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, From patchwork Mon Sep 23 07:44:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59585 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EBB4A1BEE6; Mon, 23 Sep 2019 09:42:49 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 56B541BEAE for ; Mon, 23 Sep 2019 09:42:20 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445640" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:18 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:31 +0800 Message-Id: <20190923074448.7847-14-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 13/30] net/ice/base: enable fdir queue region X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add fdir queue region support. Signed-off-by: Qi Zhang Signed-off-by: Paul M Stillwell Jr --- drivers/net/ice/base/ice_fdir.c | 3 +++ drivers/net/ice/base/ice_fdir.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index e35506006..4632f1a53 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -343,6 +343,9 @@ ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input, fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_YES; fdir_fltr_ctx.qindex = 0; } else { + if (input->dest_ctl == + ICE_FLTR_PRGM_DESC_DEST_DIRECT_PKT_QGROUP) + fdir_fltr_ctx.toq = input->q_region; fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_NO; fdir_fltr_ctx.qindex = input->q_index; } diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index e0f3cd481..ccfc30c85 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -167,6 +167,8 @@ struct ice_fdir_fltr { /* flex byte filter data */ __be16 flex_word; + /* queue region size (=2^q_region) */ + u8 q_region; u16 flex_offset; u16 flex_fltr; From patchwork Mon Sep 23 07:44:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59586 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 88CDF1BEEC; Mon, 23 Sep 2019 09:42:52 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 04E471BEAE for ; Mon, 23 Sep 2019 09:42:21 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445649" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:20 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Junfeng Guo , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:32 +0800 Message-Id: <20190923074448.7847-15-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 14/30] net/ice/base: enable setting up FDIR counters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Enable getting value from input to set up flow director counters, so that the FDIR counters can count none, packets only, bytes only or both packets and bytes as demanded. Signed-off-by: Junfeng Guo Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 2 +- drivers/net/ice/base/ice_fdir.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 4632f1a53..1c455ffe4 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -349,7 +349,7 @@ ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input, fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_NO; fdir_fltr_ctx.qindex = input->q_index; } - fdir_fltr_ctx.cnt_ena = ICE_FXD_FLTR_QW0_STAT_ENA_PKTS; + fdir_fltr_ctx.cnt_ena = input->cnt_ena; fdir_fltr_ctx.cnt_index = input->cnt_index; fdir_fltr_ctx.fd_vsi = ice_get_hw_vsi_num(hw, input->dest_vsi); fdir_fltr_ctx.evict_ena = ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE; diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index ccfc30c85..007f6dd8f 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -176,6 +176,7 @@ struct ice_fdir_fltr { u16 q_index; u16 dest_vsi; u8 dest_ctl; + u8 cnt_ena; u8 fltr_status; u16 cnt_index; u32 fltr_id; From patchwork Mon Sep 23 07:44:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59587 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EA8EA1BEF3; Mon, 23 Sep 2019 09:42:54 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 626EC1BEAE for ; Mon, 23 Sep 2019 09:42:24 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445657" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:21 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Junfeng Guo , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:33 +0800 Message-Id: <20190923074448.7847-16-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 15/30] net/ice/base: add dest MAC field support for FDIR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add dest MAC address support so that this field can be matched when we set Flow Director filter with dst addr for MAC. Signed-off-by: Junfeng Guo Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 1c455ffe4..3a2175b30 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -543,6 +543,17 @@ static void ice_pkt_insert_u32(u8 *pkt, int offset, __be32 data) } /** + * ice_pkt_insert_mac_addr - insert a MAC addr into a memory buffer. + * @pkt: packet buffer + * @offset: offset into buffer + * @addr: MAC address to convert and insert into pkt at offset + */ +static void ice_pkt_insert_mac_addr(u8 *pkt, u8 *addr) +{ + ice_memcpy(pkt, addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); +} + +/** * ice_fdir_get_gen_prgm_pkt - generate a training packet * @hw: pointer to the hardware structure * @input: flow director filter data structure @@ -626,6 +637,7 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v4.src_port); ice_pkt_insert_u8(loc, ICE_IPV4_TOS_OFFSET, input->ip.v4.tos); ice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl); + ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); if (frag) loc[20] = ICE_FDIR_IPV4_PKT_FLAG_DF; break; @@ -640,6 +652,7 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v4.src_port); ice_pkt_insert_u8(loc, ICE_IPV4_TOS_OFFSET, input->ip.v4.tos); ice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl); + ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); break; case ICE_FLTR_PTYPE_NONF_IPV4_SCTP: ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, @@ -652,6 +665,7 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v4.src_port); ice_pkt_insert_u8(loc, ICE_IPV4_TOS_OFFSET, input->ip.v4.tos); ice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl); + ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); break; case ICE_FLTR_PTYPE_NONF_IPV4_OTHER: ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, @@ -662,6 +676,7 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, ice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl); ice_pkt_insert_u8(loc, ICE_IPV4_PROTO_OFFSET, input->ip.v4.proto); + ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); break; case ICE_FLTR_PTYPE_NONF_IPV6_TCP: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, @@ -674,6 +689,7 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v6.src_port); ice_pkt_insert_u8_tc(loc, ICE_IPV6_TC_OFFSET, input->ip.v6.tc); ice_pkt_insert_u8(loc, ICE_IPV6_HLIM_OFFSET, input->ip.v6.hlim); + ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); break; case ICE_FLTR_PTYPE_NONF_IPV6_UDP: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, @@ -686,6 +702,7 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v6.src_port); ice_pkt_insert_u8_tc(loc, ICE_IPV6_TC_OFFSET, input->ip.v6.tc); ice_pkt_insert_u8(loc, ICE_IPV6_HLIM_OFFSET, input->ip.v6.hlim); + ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); break; case ICE_FLTR_PTYPE_NONF_IPV6_SCTP: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, @@ -698,6 +715,7 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v6.src_port); ice_pkt_insert_u8_tc(loc, ICE_IPV6_TC_OFFSET, input->ip.v6.tc); ice_pkt_insert_u8(loc, ICE_IPV6_HLIM_OFFSET, input->ip.v6.hlim); + ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); break; case ICE_FLTR_PTYPE_NONF_IPV6_OTHER: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, @@ -708,6 +726,7 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, ice_pkt_insert_u8(loc, ICE_IPV6_HLIM_OFFSET, input->ip.v6.hlim); ice_pkt_insert_u8(loc, ICE_IPV6_PROTO_OFFSET, input->ip.v6.proto); + ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); break; default: return ICE_ERR_PARAM; From patchwork Mon Sep 23 07:44:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59588 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1A9501BEF8; Mon, 23 Sep 2019 09:42:57 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 4408C1BEB2 for ; Mon, 23 Sep 2019 09:42:26 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445662" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:24 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Kevin Scott , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:34 +0800 Message-Id: <20190923074448.7847-17-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 16/30] net/ice/base: update FW API minor version X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Update FW API minor version to align to current value advertised by FW in NVM images. Signed-off-by: Kevin Scott Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_controlq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h index 8ad7857c8..8b6046547 100644 --- a/drivers/net/ice/base/ice_controlq.h +++ b/drivers/net/ice/base/ice_controlq.h @@ -23,7 +23,7 @@ */ #define EXP_FW_API_VER_BRANCH 0x00 #define EXP_FW_API_VER_MAJOR 0x01 -#define EXP_FW_API_VER_MINOR 0x03 +#define EXP_FW_API_VER_MINOR 0x05 /* Different control queue types: These are mainly for SW consumption. */ enum ice_ctl_q { From patchwork Mon Sep 23 07:44:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59589 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 81DBE1BEFD; Mon, 23 Sep 2019 09:42:59 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 3563E1BEA3 for ; Mon, 23 Sep 2019 09:42:28 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445672" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:26 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:35 +0800 Message-Id: <20190923074448.7847-18-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 17/30] net/ice/base: enable symmetric hash for RSS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add parameter "symm" to rss configuration APIs. When symm is 1, Symmetric Teoplitz Hash can be enabled by configuring GLQF_HSYMM properly. NOTE: Symmetric Teoplitz hash will work only if hash schema of VSIQF_HASH_CTL be configured to 01b and it is assumed be enabled in PMD. Signed-off-by: Qi Zhang Signed-off-by: Paul M Stillwell Jr --- drivers/net/ice/base/ice_flow.c | 149 +++++++++++++++++++++++++++++++++++++--- drivers/net/ice/base/ice_flow.h | 5 +- drivers/net/ice/ice_ethdev.c | 16 ++--- 3 files changed, 150 insertions(+), 20 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index d91922527..e0e4fcab6 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -1876,6 +1876,7 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) rss_cfg->hashed_flds = prof->segs[prof->segs_cnt - 1].match; rss_cfg->packet_hdr = prof->segs[prof->segs_cnt - 1].hdrs; + rss_cfg->symm = prof->cfg.symm; ice_set_bit(vsi_handle, rss_cfg->vsis); LIST_ADD_TAIL(&rss_cfg->l_entry, &hw->rss_list_head); @@ -1903,6 +1904,107 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) (((u64)(hdr) << ICE_FLOW_PROF_HDR_S) & ICE_FLOW_PROF_HDR_M) | \ ((u8)((segs_cnt) - 1) ? ICE_FLOW_PROF_ENCAP_M : 0)) +static void +ice_rss_config_xor_word(struct ice_hw *hw, u8 prof_id, u8 src, u8 dst) +{ + u32 s = ((src % 4) << 3); /* byte shift */ + u32 v = dst | 0x80; /* value to program */ + u8 i = src / 4; /* register index */ + u32 reg; + + reg = rd32(hw, GLQF_HSYMM(prof_id, i)); + reg = (reg & ~(0xff << s)) | (v << s); + wr32(hw, GLQF_HSYMM(prof_id, i), reg); +} + +static void +ice_rss_config_xor(struct ice_hw *hw, u8 prof_id, u8 src, u8 dst, u8 len) +{ + int fv_last_word = + ICE_FLOW_SW_FIELD_VECTOR_MAX / ICE_FLOW_FV_EXTRACT_SZ - 1; + int i; + + for (i = 0; i < len; i++) { + ice_rss_config_xor_word(hw, prof_id, + /* Yes, field vector in GLQF_HSYMM and + * GLQF_HINSET is inversed! + */ + fv_last_word - (src + i), + fv_last_word - (dst + i)); + ice_rss_config_xor_word(hw, prof_id, + fv_last_word - (dst + i), + fv_last_word - (src + i)); + } +} + +static void +ice_rss_update_symm(struct ice_hw *hw, + struct ice_flow_prof *prof) +{ + struct ice_prof_map *map; + u8 prof_id, m; + + map = ice_search_prof_id(hw, ICE_BLK_RSS, prof->id); + prof_id = map->prof_id; + + /* clear to default */ + for (m = 0; m < 6; m++) + wr32(hw, GLQF_HSYMM(prof_id, m), 0); + if (prof->cfg.symm) { + struct ice_flow_seg_info *seg = + &prof->segs[prof->segs_cnt - 1]; + + struct ice_flow_seg_xtrct *ipv4_src = + &seg->fields[ICE_FLOW_FIELD_IDX_IPV4_SA].xtrct; + struct ice_flow_seg_xtrct *ipv4_dst = + &seg->fields[ICE_FLOW_FIELD_IDX_IPV4_DA].xtrct; + struct ice_flow_seg_xtrct *ipv6_src = + &seg->fields[ICE_FLOW_FIELD_IDX_IPV6_SA].xtrct; + struct ice_flow_seg_xtrct *ipv6_dst = + &seg->fields[ICE_FLOW_FIELD_IDX_IPV6_DA].xtrct; + + struct ice_flow_seg_xtrct *tcp_src = + &seg->fields[ICE_FLOW_FIELD_IDX_TCP_SRC_PORT].xtrct; + struct ice_flow_seg_xtrct *tcp_dst = + &seg->fields[ICE_FLOW_FIELD_IDX_TCP_DST_PORT].xtrct; + + struct ice_flow_seg_xtrct *udp_src = + &seg->fields[ICE_FLOW_FIELD_IDX_UDP_SRC_PORT].xtrct; + struct ice_flow_seg_xtrct *udp_dst = + &seg->fields[ICE_FLOW_FIELD_IDX_UDP_DST_PORT].xtrct; + + struct ice_flow_seg_xtrct *sctp_src = + &seg->fields[ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT].xtrct; + struct ice_flow_seg_xtrct *sctp_dst = + &seg->fields[ICE_FLOW_FIELD_IDX_SCTP_DST_PORT].xtrct; + + /* xor IPv4 */ + if (ipv4_src->prot_id != 0 && ipv4_dst->prot_id != 0) + ice_rss_config_xor(hw, prof_id, + ipv4_src->idx, ipv4_dst->idx, 2); + + /* xor IPv6 */ + if (ipv6_src->prot_id != 0 && ipv6_dst->prot_id != 0) + ice_rss_config_xor(hw, prof_id, + ipv6_src->idx, ipv6_dst->idx, 8); + + /* xor TCP */ + if (tcp_src->prot_id != 0 && tcp_dst->prot_id != 0) + ice_rss_config_xor(hw, prof_id, + tcp_src->idx, tcp_dst->idx, 1); + + /* xor UDP */ + if (udp_src->prot_id != 0 && udp_dst->prot_id != 0) + ice_rss_config_xor(hw, prof_id, + udp_src->idx, udp_dst->idx, 1); + + /* xor SCTP */ + if (sctp_src->prot_id != 0 && sctp_dst->prot_id != 0) + ice_rss_config_xor(hw, prof_id, + sctp_src->idx, sctp_dst->idx, 1); + } +} + /** * ice_add_rss_cfg_sync - add an RSS configuration * @hw: pointer to the hardware structure @@ -1910,12 +2012,13 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) * @hashed_flds: hash bit fields (ICE_FLOW_HASH_*) to configure * @addl_hdrs: protocol header fields * @segs_cnt: packet segment count + * @symm: symmetric hash enable/disable * * Assumption: lock has already been acquired for RSS list */ static enum ice_status ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, - u32 addl_hdrs, u8 segs_cnt) + u32 addl_hdrs, u8 segs_cnt, bool symm) { const enum ice_block blk = ICE_BLK_RSS; struct ice_flow_prof *prof = NULL; @@ -1944,8 +2047,12 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, vsi_handle, ICE_FLOW_FIND_PROF_CHK_FLDS | ICE_FLOW_FIND_PROF_CHK_VSI); - if (prof) - goto exit; + if (prof) { + if (prof->cfg.symm == symm) + goto exit; + prof->cfg.symm = symm; + goto update_symm; + } /* Check if a flow profile exists with the same protocol headers and * associated with the input VSI. If so disasscociate the VSI from @@ -1976,9 +2083,18 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, vsi_handle, ICE_FLOW_FIND_PROF_CHK_FLDS); if (prof) { - status = ice_flow_assoc_prof(hw, blk, prof, vsi_handle); - if (!status) - status = ice_add_rss_list(hw, vsi_handle, prof); + if (prof->cfg.symm == symm) { + status = ice_flow_assoc_prof(hw, blk, prof, + vsi_handle); + if (!status) + status = ice_add_rss_list(hw, vsi_handle, + prof); + } else { + /* if a profile exist but with different symmetric + * requirement, just return error. + */ + status = ICE_ERR_NOT_SUPPORTED; + } goto exit; } @@ -2004,6 +2120,13 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, status = ice_add_rss_list(hw, vsi_handle, prof); + prof->cfg.symm = symm; + if (!symm) + goto exit; + +update_symm: + ice_rss_update_symm(hw, prof); + exit: ice_free(hw, segs); return status; @@ -2015,6 +2138,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, * @vsi_handle: software VSI handle * @hashed_flds: hash bit fields (ICE_FLOW_HASH_*) to configure * @addl_hdrs: protocol header fields + * @symm: symmetric hash enable/disable * * This function will generate a flow profile based on fields associated with * the input fields to hash on, the flow type and use the VSI number to add @@ -2022,7 +2146,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, */ enum ice_status ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, - u32 addl_hdrs) + u32 addl_hdrs, bool symm) { enum ice_status status; @@ -2032,10 +2156,11 @@ ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, ice_acquire_lock(&hw->rss_locks); status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs, - ICE_RSS_OUTER_HEADERS); + ICE_RSS_OUTER_HEADERS, symm); if (!status) status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds, - addl_hdrs, ICE_RSS_INNER_HEADERS); + addl_hdrs, ICE_RSS_INNER_HEADERS, + symm); ice_release_lock(&hw->rss_locks); return status; @@ -2148,13 +2273,15 @@ enum ice_status ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle) status = ice_add_rss_cfg_sync(hw, vsi_handle, r->hashed_flds, r->packet_hdr, - ICE_RSS_OUTER_HEADERS); + ICE_RSS_OUTER_HEADERS, + r->symm); if (status) break; status = ice_add_rss_cfg_sync(hw, vsi_handle, r->hashed_flds, r->packet_hdr, - ICE_RSS_INNER_HEADERS); + ICE_RSS_INNER_HEADERS, + r->symm); if (status) break; } diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index 3afd201c4..6f26f3935 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -315,6 +315,8 @@ struct ice_flow_prof { /* struct sw_recipe */ /* struct fd */ u32 data; + /* Symmetric Hash for RSS */ + bool symm; } cfg; /* Default actions */ @@ -327,6 +329,7 @@ struct ice_rss_cfg { ice_declare_bitmap(vsis, ICE_MAX_VSI); u64 hashed_flds; u32 packet_hdr; + bool symm; }; enum ice_flow_action_type { @@ -402,7 +405,7 @@ ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds); enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle); enum ice_status ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, - u32 addl_hdrs); + u32 addl_hdrs, bool symm); enum ice_status ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, u32 addl_hdrs); diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 63997fdfb..ccd64f49f 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -1790,50 +1790,50 @@ static int ice_init_rss(struct ice_pf *pf) /* configure RSS for IPv4 with input set IPv4 src/dst */ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, - ICE_FLOW_SEG_HDR_IPV4); + ICE_FLOW_SEG_HDR_IPV4, 0); if (ret) PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret); /* configure RSS for IPv6 with input set IPv6 src/dst */ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, - ICE_FLOW_SEG_HDR_IPV6); + ICE_FLOW_SEG_HDR_IPV6, 0); if (ret) PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret); /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6, - ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6); + ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0); if (ret) PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret); /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6, - ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6); + ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0); if (ret) PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret); /* configure RSS for sctp6 with input set IPv6 src/dst */ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, - ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6); + ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0); if (ret) PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", __func__, ret); /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4, - ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4); + ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0); if (ret) PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret); /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4, - ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4); + ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0); if (ret) PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret); /* configure RSS for sctp4 with input set IP src/dst */ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, - ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4); + ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0); if (ret) PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", __func__, ret); From patchwork Mon Sep 23 07:44:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59590 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7E35A1BEBE; Mon, 23 Sep 2019 09:43:28 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id D80831BEB5 for ; Mon, 23 Sep 2019 09:42:29 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445678" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:28 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Bruce Allan , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:36 +0800 Message-Id: <20190923074448.7847-19-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 18/30] net/ice/base: replace alloc-followed-by-copy with memdup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" ice_memdup() is preferred over an alloc immediately followed by a copy. Signed-off-by: Bruce Allan Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flex_pipe.c | 5 ++--- drivers/net/ice/base/ice_switch.c | 7 ++----- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 05cd39b17..76c26fd4e 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -4939,12 +4939,11 @@ ice_get_profs_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, struct ice_vsig_prof *p; /* copy to the input list */ - p = (struct ice_vsig_prof *)ice_malloc(hw, sizeof(*p)); + p = (struct ice_vsig_prof *)ice_memdup(hw, ent1, sizeof(*p), + ICE_NONDMA_TO_NONDMA); if (!p) goto err_ice_get_profs_vsig; - ice_memcpy(p, ent1, sizeof(*p), ICE_NONDMA_TO_NONDMA); - LIST_ADD_TAIL(&p->list, lst); } diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 64c2aec19..62ccf533c 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -623,14 +623,11 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid, recps[rid].big_recp = (num_recps > 1); recps[rid].n_grp_count = num_recps; recps[rid].root_buf = (struct ice_aqc_recipe_data_elem *) - ice_calloc(hw, recps[rid].n_grp_count, - sizeof(struct ice_aqc_recipe_data_elem)); + ice_memdup(hw, tmp, recps[rid].n_grp_count * + sizeof(*recps[rid].root_buf), ICE_NONDMA_TO_NONDMA); if (!recps[rid].root_buf) goto err_unroll; - ice_memcpy(recps[rid].root_buf, tmp, recps[rid].n_grp_count * - sizeof(*recps[rid].root_buf), ICE_NONDMA_TO_NONDMA); - /* Copy result indexes */ ice_memcpy(recps[rid].res_idxs, result_bm, sizeof(recps[rid].res_idxs), ICE_NONDMA_TO_NONDMA); From patchwork Mon Sep 23 07:44:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59591 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B43121BEDF; Mon, 23 Sep 2019 09:43:33 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 02D8A1BEA3 for ; Mon, 23 Sep 2019 09:42:31 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445683" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:29 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Junfeng Guo , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:37 +0800 Message-Id: <20190923074448.7847-20-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 19/30] net/ice/base: add FDIR support for GTPU qfi field X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add GTPU qfi field support for flow director. Note that for GTPU pkt, only qfi field (6 bits) can be set for FD. The supported GTPU pkts are defined as: ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER (FRAG and PAY belong to this) Signed-off-by: Junfeng Guo Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 111 ++++++++++++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_fdir.h | 22 ++++++++ drivers/net/ice/base/ice_type.h | 4 ++ 3 files changed, 137 insertions(+) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 3a2175b30..219588c46 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -42,6 +42,66 @@ static const u8 ice_fdir_ipv4_pkt[] = { 0x00, 0x00 }; +static const u8 ice_fdir_udp4_gtpu4_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x4c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x00, + 0x00, 0x00, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x1c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, +}; + +static const u8 ice_fdir_tcp4_gtpu4_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x58, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x00, + 0x00, 0x00, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x28, 0x00, 0x00, 0x40, 0x00, 0x40, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_icmp4_gtpu4_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x4c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x00, + 0x00, 0x00, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x1c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, +}; + +static const u8 ice_fdir_ipv4_gtpu4_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x44, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x00, + 0x00, 0x00, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x14, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, +}; + static const u8 ice_fdir_tcpv6_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00, @@ -241,6 +301,34 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = { sizeof(ice_fdir_ip4_tun_pkt), ice_fdir_ip4_tun_pkt, }, { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, + sizeof(ice_fdir_udp4_gtpu4_pkt), + ice_fdir_udp4_gtpu4_pkt, + sizeof(ice_fdir_udp4_gtpu4_pkt), + ice_fdir_udp4_gtpu4_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, + sizeof(ice_fdir_tcp4_gtpu4_pkt), + ice_fdir_tcp4_gtpu4_pkt, + sizeof(ice_fdir_tcp4_gtpu4_pkt), + ice_fdir_tcp4_gtpu4_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, + sizeof(ice_fdir_icmp4_gtpu4_pkt), + ice_fdir_icmp4_gtpu4_pkt, + sizeof(ice_fdir_icmp4_gtpu4_pkt), + ice_fdir_icmp4_gtpu4_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER, + sizeof(ice_fdir_ipv4_gtpu4_pkt), + ice_fdir_ipv4_gtpu4_pkt, + sizeof(ice_fdir_ipv4_gtpu4_pkt), + ice_fdir_ipv4_gtpu4_pkt, + }, + { ICE_FLTR_PTYPE_NONF_IPV6_TCP, sizeof(ice_fdir_tcpv6_pkt), ice_fdir_tcpv6_pkt, sizeof(ice_fdir_tcp6_tun_pkt), ice_fdir_tcp6_tun_pkt, @@ -488,6 +576,22 @@ static void ice_pkt_insert_ipv6_addr(u8 *pkt, int offset, __be32 *addr) } /** + * ice_pkt_insert_u6_qfi - insert a u6 value qfi into a memory buffer for gtpu + * @pkt: packet buffer + * @offset: offset into buffer + * @data: 8 bit value to convert and insert into pkt at offset + * + * This function is designed for inserting qfi (6 bits) for gtpu. + */ +static void ice_pkt_insert_u6_qfi(u8 *pkt, int offset, u8 data) +{ + u8 ret; + + ret = (data & 0x3F) + (*(pkt + offset) & 0xC0); + ice_memcpy(pkt + offset, &ret, sizeof(ret), ICE_NONDMA_TO_NONDMA); +} + +/** * ice_pkt_insert_u8 - insert a u8 value into a memory buffer. * @pkt: packet buffer * @offset: offset into buffer @@ -678,6 +782,13 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v4.proto); ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); break; + case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP: + case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP: + case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP: + case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER: + ice_pkt_insert_u6_qfi(loc, ICE_IPV4_GTPU_QFI_OFFSET, + input->gtpu_data.qfi); + break; case ICE_FLTR_PTYPE_NONF_IPV6_TCP: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, input->ip.v6.dst_ip); diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index 007f6dd8f..22e5bcf8c 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -87,6 +87,7 @@ enum ice_status ice_clear_pf_fd_table(struct ice_hw *hw); #define ICE_IPV6_TC_OFFSET 14 #define ICE_IPV6_HLIM_OFFSET 21 #define ICE_IPV6_PROTO_OFFSET 20 +#define ICE_IPV4_GTPU_QFI_OFFSET 56 #define ICE_FDIR_MAX_FLTRS 16384 @@ -146,6 +147,24 @@ struct ice_fdir_v6 { u8 hlim; }; +struct ice_fdir_udp_gtp { + u8 flags; + u8 msg_type; + u16 rsrvd_len; + u32 teid; + u16 rsrvd_seq_nbr; + u8 rsrvd_n_pdu_nbr; + u8 rsrvd_next_ext_type; + u8 rsvrd_ext_len; + u8 pdu_type:4, + spare:4; + u8 ppp:1, + rqi:1, + qfi:6; + u32 rsvrd; + u8 next_ext; +}; + struct ice_fdir_extra { u8 dst_mac[ETH_ALEN]; /* dest MAC address */ u32 usr_def[2]; /* user data */ @@ -162,6 +181,9 @@ struct ice_fdir_fltr { struct ice_fdir_v6 v6; } ip, mask; + struct ice_fdir_udp_gtp gtpu_data; + struct ice_fdir_udp_gtp gtpu_mask; + struct ice_fdir_extra ext_data; struct ice_fdir_extra ext_mask; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 7d0a4f63f..500b88461 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -288,6 +288,10 @@ enum ice_fltr_ptype { ICE_FLTR_PTYPE_NONF_IPV4_TCP, ICE_FLTR_PTYPE_NONF_IPV4_SCTP, ICE_FLTR_PTYPE_NONF_IPV4_OTHER, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER, ICE_FLTR_PTYPE_FRAG_IPV4, ICE_FLTR_PTYPE_NONF_IPV6_UDP, ICE_FLTR_PTYPE_NONF_IPV6_TCP, From patchwork Mon Sep 23 07:44:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59592 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EA3231BECE; Mon, 23 Sep 2019 09:43:40 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id C5E861BEC0; Mon, 23 Sep 2019 09:42:33 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445693" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:31 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , stable@dpdk.org, Zhirun Yan , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:38 +0800 Message-Id: <20190923074448.7847-21-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 20/30] net/ice/base: fix the bitmap for TCP in RSS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Before this patch, if set rule for IPv4 first and then set rule for TCP with IPv4. The first rule for inner IP will be overwritten by TCP rule. This is because MAC_IPV6_TUN_MAC_IPV4_PAY using the same ptgs PTG_TUN_INNER_IPV4_OTHER with MAC_IPV4_TUN_MAC_IPV4_PAY, this ptype should not in TCP bitmap. Remove this bit in TCP bitmap. Fixes: aa1cd410fa64 ("net/ice/base: add flow module") Cc: stable@dpdk.org Signed-off-by: Zhirun Yan Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index e0e4fcab6..6782dfaa8 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -239,7 +239,7 @@ static const u32 ice_ptypes_udp_il[] = { /* Packet types for packets with an Innermost/Last TCP header */ static const u32 ice_ptypes_tcp_il[] = { - 0x04000000, 0x80810102, 0x10204040, 0x42040408, + 0x04000000, 0x80810102, 0x10204040, 0x02040408, 0x00810102, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00820000, 0x21084000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, From patchwork Mon Sep 23 07:44:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59595 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 149041BF2F; Mon, 23 Sep 2019 09:43:58 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 63EB51BEC1 for ; Mon, 23 Sep 2019 09:42:35 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445698" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:33 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Zhirun Yan , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:39 +0800 Message-Id: <20190923074448.7847-22-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 21/30] net/ice/base: fix segment in remove existing RSS rule X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Before this patch, RSS tunneled rules can not be destroyed at runtime. This is because it can not find the existing matching profile for tunnels. segs[0] should always be zero and all matched, segs[1] for inner part. It only construct one segment. This patch modifies construct segment in ice_rem_rss_cfg_sync() to match ice_add_rss_cfg_sync(). Fixes: 75bc2ea04af4 ("net/ice/base: packet encapsulation for RSS") Signed-off-by: Zhirun Yan Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 6782dfaa8..f9c65d6a2 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -2185,12 +2185,14 @@ ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds, struct ice_flow_prof *prof; enum ice_status status; - segs = (struct ice_flow_seg_info *)ice_malloc(hw, sizeof(*segs)); + segs = (struct ice_flow_seg_info *)ice_calloc(hw, segs_cnt, + sizeof(*segs)); if (!segs) return ICE_ERR_NO_MEMORY; /* Construct the packet segment info from the hashed fields */ - status = ice_flow_set_rss_seg_info(segs, hashed_flds, addl_hdrs); + status = ice_flow_set_rss_seg_info(&segs[segs_cnt - 1], hashed_flds, + addl_hdrs); if (status) goto out; From patchwork Mon Sep 23 07:44:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59593 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1C2C01BF23; Mon, 23 Sep 2019 09:43:47 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 2BE411BEC8 for ; Mon, 23 Sep 2019 09:42:37 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445701" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:35 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Bruce Allan , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:40 +0800 Message-Id: <20190923074448.7847-23-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 22/30] net/ice/base: remove unused DDP package macros X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Macros no longer be used and can be removed Signed-off-by: Bruce Allan Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_type.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 500b88461..8322d88a0 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -835,11 +835,6 @@ struct ice_hw { /* tunneling info */ struct ice_tunnel_table tnl; -#define ICE_PKG_FILENAME "package_file" -#define ICE_PKG_FILENAME_EXT "pkg" -#define ICE_PKG_FILE_MAJ_VER 1 -#define ICE_PKG_FILE_MIN_VER 0 - /* HW block tables */ struct ice_blk_info blk[ICE_BLK_COUNT]; struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ From patchwork Mon Sep 23 07:44:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59594 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id ED49F1BF07; Mon, 23 Sep 2019 09:43:52 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 3CA701BE0C for ; Mon, 23 Sep 2019 09:42:39 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445711" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:36 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowline , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:41 +0800 Message-Id: <20190923074448.7847-24-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 23/30] net/ice/base: search field vector indices for result slots X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Previously, switch code would use only pre-reserved index slots at the end of each field vector for recipe result index locations. This patch adds code that detects other internal empty index slots that could potentially be used. For each recipe that is added, a determ ination is made as to whether any of these additional index slots alige with all the profiles selected for the recipe; if alignment is achieved, then these result index slots can be used. Signed-off-by: Dan Nowline Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flex_pipe.c | 41 +++++++++++++++++++++ drivers/net/ice/base/ice_flex_pipe.h | 2 ++ drivers/net/ice/base/ice_flex_type.h | 2 ++ drivers/net/ice/base/ice_protocol_type.h | 2 +- drivers/net/ice/base/ice_switch.c | 61 +++++++++++++++----------------- drivers/net/ice/base/ice_switch.h | 1 - drivers/net/ice/base/ice_type.h | 3 ++ 7 files changed, 78 insertions(+), 34 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 76c26fd4e..318168910 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1661,6 +1661,47 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt, } /** + * ice_init_profile_to_result_bm - Initialize the profile result index bitmap + * @hw: pointer to hardware structure + */ +void +ice_init_prof_result_bm(struct ice_hw *hw) +{ + struct ice_pkg_enum state; + struct ice_seg *ice_seg; + struct ice_fv *fv; + + if (!hw->seg) + return; + + ice_seg = hw->seg; + do { + u32 off; + u16 i; + + fv = (struct ice_fv *) + ice_pkg_enum_entry(ice_seg, &state, ICE_SID_FLD_VEC_SW, + &off, ice_sw_fv_handler); + ice_seg = NULL; + if (!fv) + break; + + ice_zero_bitmap(hw->switch_info->prof_res_bm[off], + ICE_MAX_FV_WORDS); + + /* Determine empty field vector indices, these can be + * used for recipe results. Skip index 0, since it is + * always used for Switch ID. + */ + for (i = 1; i < ICE_MAX_FV_WORDS; i++) + if (fv->ew[i].prot_id == ICE_PROT_INVALID && + fv->ew[i].off == ICE_FV_OFFSET_INVAL) + ice_set_bit(i, + hw->switch_info->prof_res_bm[off]); + } while (fv); +} + +/** * ice_pkg_buf_free * @hw: pointer to the HW structure * @bld: pointer to pkg build (allocated by ice_pkg_buf_alloc()) diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h index 137eaa7f8..e7d42e3de 100644 --- a/drivers/net/ice/base/ice_flex_pipe.h +++ b/drivers/net/ice/base/ice_flex_pipe.h @@ -33,6 +33,8 @@ ice_find_label_value(struct ice_seg *ice_seg, char const *name, u32 type, void ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type, ice_bitmap_t *bm); +void +ice_init_prof_result_bm(struct ice_hw *hw); enum ice_status ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt, ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list); diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index c30d407c2..48c1e5184 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -16,6 +16,8 @@ struct ice_fv_word { }; #pragma pack() +#define ICE_MAX_NUM_PROFILES 256 + #define ICE_MAX_FV_WORDS 48 struct ice_fv { struct ice_fv_word ew[ICE_MAX_FV_WORDS]; diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index c6caa8562..98185c9de 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -110,7 +110,7 @@ enum ice_prot_id { ICE_PROT_ARP_OF = 118, ICE_PROT_EAPOL_OF = 120, ICE_PROT_META_ID = 255, /* when offset == metaddata */ - ICE_PROT_INVALID = 255 /* when offset == 0xFF */ + ICE_PROT_INVALID = 255 /* when offset == ICE_FV_OFFSET_INVAL */ }; #define ICE_VNI_OFFSET 12 /* offset of VNI from ICE_PROT_UDP_OF */ diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 62ccf533c..9681d9590 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -467,21 +467,6 @@ static void ice_collect_result_idx(struct ice_aqc_recipe_data_elem *buf, } /** - * ice_init_possible_res_bm - initialize possible result bitmap - * @pos_result_bm: pointer to the bitmap to initialize - */ -static void ice_init_possible_res_bm(ice_bitmap_t *pos_result_bm) -{ - u16 bit; - - ice_zero_bitmap(pos_result_bm, ICE_MAX_FV_WORDS); - - for (bit = 0; bit < ICE_MAX_FV_WORDS; bit++) - if (ICE_POSSIBLE_RES_IDX & BIT_ULL(bit)) - ice_set_bit(bit, pos_result_bm); -} - -/** * ice_get_recp_frm_fw - update SW bookkeeping from FW recipe entries * @hw: pointer to hardware structure * @recps: struct that we need to populate @@ -496,7 +481,6 @@ static enum ice_status ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid, bool *refresh_required) { - ice_declare_bitmap(possible_idx, ICE_MAX_FV_WORDS); ice_declare_bitmap(result_bm, ICE_MAX_FV_WORDS); struct ice_aqc_recipe_data_elem *tmp; u16 num_recps = ICE_MAX_NUM_RECIPES; @@ -505,7 +489,6 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid, enum ice_status status; ice_zero_bitmap(result_bm, ICE_MAX_FV_WORDS); - ice_init_possible_res_bm(possible_idx); /* we need a buffer big enough to accommodate all the recipes */ tmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw, @@ -541,7 +524,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid, for (sub_recps = 0; sub_recps < num_recps; sub_recps++) { struct ice_aqc_recipe_data_elem root_bufs = tmp[sub_recps]; struct ice_recp_grp_entry *rg_entry; - u8 prof_id, idx, prot = 0; + u8 prof, idx, prot = 0; bool is_root; u16 off = 0; @@ -561,8 +544,8 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid, ~ICE_AQ_RECIPE_RESULT_EN, result_bm); /* get the first profile that is associated with rid */ - prof_id = ice_find_first_bit(recipe_to_profile[idx], - ICE_MAX_NUM_PROFILES); + prof = ice_find_first_bit(recipe_to_profile[idx], + ICE_MAX_NUM_PROFILES); for (i = 0; i < ICE_NUM_WORDS_RECIPE; i++) { u8 lkup_indx = root_bufs.content.lkup_indx[i + 1]; @@ -579,12 +562,13 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid, * has ICE_AQ_RECIPE_LKUP_IGNORE or 0 since it isn't a * valid offset value. */ - if (ice_is_bit_set(possible_idx, rg_entry->fv_idx[i]) || + if (ice_is_bit_set(hw->switch_info->prof_res_bm[prof], + rg_entry->fv_idx[i]) || rg_entry->fv_idx[i] & ICE_AQ_RECIPE_LKUP_IGNORE || rg_entry->fv_idx[i] == 0) continue; - ice_find_prot_off(hw, ICE_BLK_SW, prof_id, + ice_find_prot_off(hw, ICE_BLK_SW, prof, rg_entry->fv_idx[i], &prot, &off); lkup_exts->fv_words[fv_word_idx].prot_id = prot; lkup_exts->fv_words[fv_word_idx].off = off; @@ -4950,30 +4934,32 @@ ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles, ice_bitmap_t *free_idx) { ice_declare_bitmap(possible_idx, ICE_MAX_FV_WORDS); - ice_declare_bitmap(used_idx, ICE_MAX_FV_WORDS); ice_declare_bitmap(recipes, ICE_MAX_NUM_RECIPES); + ice_declare_bitmap(used_idx, ICE_MAX_FV_WORDS); u16 count = 0; u16 bit; - ice_zero_bitmap(free_idx, ICE_MAX_FV_WORDS); - ice_zero_bitmap(used_idx, ICE_MAX_FV_WORDS); + ice_zero_bitmap(possible_idx, ICE_MAX_FV_WORDS); ice_zero_bitmap(recipes, ICE_MAX_NUM_RECIPES); - ice_init_possible_res_bm(possible_idx); + ice_zero_bitmap(used_idx, ICE_MAX_FV_WORDS); + ice_zero_bitmap(free_idx, ICE_MAX_FV_WORDS); - for (bit = 0; bit < ICE_MAX_FV_WORDS; bit++) - if (ICE_POSSIBLE_RES_IDX & BIT_ULL(bit)) - ice_set_bit(bit, possible_idx); + for (count = 0; count < ICE_MAX_FV_WORDS; count++) + ice_set_bit(count, possible_idx); /* For each profile we are going to associate the recipe with, add the * recipes that are associated with that profile. This will give us - * the set of recipes that our recipe may collide with. + * the set of recipes that our recipe may collide with. Also, determine + * what possible result indexes are usable given this set of profiles. */ bit = 0; while (ICE_MAX_NUM_PROFILES > (bit = ice_find_next_bit(profiles, ICE_MAX_NUM_PROFILES, bit))) { ice_or_bitmap(recipes, recipes, profile_to_recipe[bit], ICE_MAX_NUM_RECIPES); - + ice_and_bitmap(possible_idx, possible_idx, + hw->switch_info->prof_res_bm[bit], + ICE_MAX_FV_WORDS); bit++; } @@ -4981,14 +4967,16 @@ ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles, * which indexes have been used. */ for (bit = 0; bit < ICE_MAX_NUM_RECIPES; bit++) - if (ice_is_bit_set(recipes, bit)) + if (ice_is_bit_set(recipes, bit)) { ice_or_bitmap(used_idx, used_idx, hw->switch_info->recp_list[bit].res_idxs, ICE_MAX_FV_WORDS); + } ice_xor_bitmap(free_idx, used_idx, possible_idx, ICE_MAX_FV_WORDS); /* return number of free indexes */ + count = 0; bit = 0; while (ICE_MAX_FV_WORDS > (bit = ice_find_next_bit(free_idx, ICE_MAX_FV_WORDS, bit))) { @@ -5029,6 +5017,9 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm, ice_zero_bitmap(result_idx_bm, ICE_MAX_FV_WORDS); free_res_idx = ice_find_free_recp_res_idx(hw, profiles, result_idx_bm); + ice_debug(hw, ICE_DBG_SW, "Result idx slots: %d, need %d\n", + free_res_idx, rm->n_grp_count); + if (rm->n_grp_count > 1) { if (rm->n_grp_count > free_res_idx) return ICE_ERR_MAX_LIMIT; @@ -6081,6 +6072,12 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u32 act = 0; u8 q_rgn; + /* Initialize profile to result index bitmap */ + if (!hw->switch_info->prof_res_bm_init) { + hw->switch_info->prof_res_bm_init = 1; + ice_init_prof_result_bm(hw); + } + if (!lkups_cnt) return ICE_ERR_PARAM; diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index 0f0a1e98e..61083738a 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -222,7 +222,6 @@ struct ice_sw_recipe { /* Profiles this recipe should be associated with */ struct LIST_HEAD_TYPE fv_list; -#define ICE_MAX_NUM_PROFILES 256 /* Profiles this recipe is associated with */ u8 num_profs, *prof_ids; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 8322d88a0..a8e4229a1 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -730,6 +730,9 @@ struct ice_port_info { struct ice_switch_info { struct LIST_HEAD_TYPE vsi_list_map_head; struct ice_sw_recipe *recp_list; + u16 prof_res_bm_init; + + ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); }; /* Port hardware description */ From patchwork Mon Sep 23 07:44:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59596 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 924D81BF3F; Mon, 23 Sep 2019 09:44:01 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 21FDE1BE0C for ; Mon, 23 Sep 2019 09:42:40 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445716" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:38 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Junfeng Guo , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:42 +0800 Message-Id: <20190923074448.7847-25-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 24/30] net/ice/base: fix 4 bytes alignment for pppoe dummy packet X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add two bytes to meet the requirement of 4 bytes alignment for dummy packet for creating switch rule for PPPoE. Fixes: 032b6c617a96 ("net/ice/base: add support for GTP and PPPoE protocols") Signed-off-by: Junfeng Guo Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_switch.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 9681d9590..7681ba38b 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -441,6 +441,8 @@ dummy_pppoe_packet[] = { 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ }; /* this is a recipe to profile association bitmap */ From patchwork Mon Sep 23 07:44:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59597 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 29B111BF47; Mon, 23 Sep 2019 09:44:05 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 805971BE0C for ; Mon, 23 Sep 2019 09:42:42 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445719" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:40 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:43 +0800 Message-Id: <20190923074448.7847-26-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 25/30] net/ice/base: remove unnecessary error log X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove the error log message when attempting to download a package that has an unsupported version. Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flex_pipe.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 318168910..11601f2c2 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1284,7 +1284,6 @@ static void ice_init_pkg_regs(struct ice_hw *hw) /** * ice_chk_pkg_version - check package version for compatibility with driver - * @hw: pointer to the hardware structure * @pkg_ver: pointer to a version structure to check * * Check to make sure that the package about to be downloaded is compatible with @@ -1292,18 +1291,11 @@ static void ice_init_pkg_regs(struct ice_hw *hw) * version must match our ICE_PKG_SUPP_VER_MAJ and ICE_PKG_SUPP_VER_MNR * definitions. */ -static enum ice_status -ice_chk_pkg_version(struct ice_hw *hw, struct ice_pkg_ver *pkg_ver) +static enum ice_status ice_chk_pkg_version(struct ice_pkg_ver *pkg_ver) { if (pkg_ver->major != ICE_PKG_SUPP_VER_MAJ || - pkg_ver->minor != ICE_PKG_SUPP_VER_MNR) { - ice_info(hw, "ERROR: Incompatible package: %d.%d.%d.%d - requires package version: %d.%d.*.*\n", - pkg_ver->major, pkg_ver->minor, pkg_ver->update, - pkg_ver->draft, ICE_PKG_SUPP_VER_MAJ, - ICE_PKG_SUPP_VER_MNR); - + pkg_ver->minor != ICE_PKG_SUPP_VER_MNR) return ICE_ERR_NOT_SUPPORTED; - } return ICE_SUCCESS; } @@ -1358,7 +1350,7 @@ enum ice_status ice_init_pkg(struct ice_hw *hw, u8 *buf, u32 len) /* before downloading the package, check package version for * compatibility with driver */ - status = ice_chk_pkg_version(hw, &hw->pkg_ver); + status = ice_chk_pkg_version(&hw->pkg_ver); if (status) return status; @@ -1384,7 +1376,7 @@ enum ice_status ice_init_pkg(struct ice_hw *hw, u8 *buf, u32 len) if (!status) { status = ice_get_pkg_info(hw); if (!status) - status = ice_chk_pkg_version(hw, &hw->active_pkg_ver); + status = ice_chk_pkg_version(&hw->active_pkg_ver); } if (!status) { From patchwork Mon Sep 23 07:44:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59598 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2255A1BF4C; Mon, 23 Sep 2019 09:44:09 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 223941BEDB for ; Mon, 23 Sep 2019 09:42:43 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445723" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:42 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Bruce Allan , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:44 +0800 Message-Id: <20190923074448.7847-27-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 26/30] net/ice/base: use bitmap copy where appropriate X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" ice_cp_bitmap() already exists and should be used instead of using ice_memcpy(). Note, there are a couple comments that suggest using a bitmap-specific copy function, but those are not correct since the source block of memory is not a bitmap. Signed-off-by: Bruce Allan Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_switch.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 7681ba38b..10dfc720a 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -615,8 +615,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid, goto err_unroll; /* Copy result indexes */ - ice_memcpy(recps[rid].res_idxs, result_bm, sizeof(recps[rid].res_idxs), - ICE_NONDMA_TO_NONDMA); + ice_cp_bitmap(recps[rid].res_idxs, result_bm, ICE_MAX_FV_WORDS); recps[rid].recp_created = true; err_unroll: @@ -645,8 +644,8 @@ ice_get_recp_to_prof_map(struct ice_hw *hw) ice_zero_bitmap(r_bitmap, ICE_MAX_NUM_RECIPES); if (ice_aq_get_recipe_to_profile(hw, i, (u8 *)r_bitmap, NULL)) continue; - ice_memcpy(profile_to_recipe[i], r_bitmap, - sizeof(profile_to_recipe[i]), ICE_NONDMA_TO_NONDMA); + ice_cp_bitmap(profile_to_recipe[i], r_bitmap, + ICE_MAX_NUM_RECIPES); for (j = 0; j < ICE_MAX_NUM_RECIPES; j++) if (ice_is_bit_set(r_bitmap, j)) ice_set_bit(i, recipe_to_profile[j]); @@ -5586,8 +5585,8 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, goto err_unroll; /* Update profile to recipe bitmap array */ - ice_memcpy(profile_to_recipe[fvit->profile_id], r_bitmap, - sizeof(r_bitmap), ICE_NONDMA_TO_NONDMA); + ice_cp_bitmap(profile_to_recipe[fvit->profile_id], r_bitmap, + ICE_MAX_NUM_RECIPES); /* Update recipe to profile bitmap array */ for (j = 0; j < ICE_MAX_NUM_RECIPES; j++) From patchwork Mon Sep 23 07:44:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59599 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 11C341BF57; Mon, 23 Sep 2019 09:44:13 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 20B041BEE4; Mon, 23 Sep 2019 09:42:45 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445728" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:43 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , stable@dpdk.org, Tony Nguyen , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:45 +0800 Message-Id: <20190923074448.7847-28-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 27/30] net/ice/base: fix alignment isue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As title says, fix an alignment issue. Fixes: 51d04e4933e3 ("net/ice/base: add flexible pipeline module") Cc: stable@dpdk.org Signed-off-by: Tony Nguyen Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flex_pipe.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 11601f2c2..0357fbd4e 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -131,8 +131,9 @@ static struct ice_buf_table *ice_find_buf_table(struct ice_seg *ice_seg) { struct ice_nvm_table *nvms; - nvms = (struct ice_nvm_table *)(ice_seg->device_table + - LE32_TO_CPU(ice_seg->device_table_count)); + nvms = (struct ice_nvm_table *) + (ice_seg->device_table + + LE32_TO_CPU(ice_seg->device_table_count)); return (_FORCE_ struct ice_buf_table *) (nvms->vers + LE32_TO_CPU(nvms->table_count)); From patchwork Mon Sep 23 07:44:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59600 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B5F9F1BF56; Mon, 23 Sep 2019 09:44:16 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id ED72C1BE8B for ; Mon, 23 Sep 2019 09:42:47 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445742" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:45 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Zhirun Yan , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:46 +0800 Message-Id: <20190923074448.7847-29-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 28/30] net/ice/base: fix PTYPE bitmap X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Before this patch, IPv4 and UDP inner hash rule will be over written by later rules after RSS initialization phase. This is because the PTYPE bitmap table cover some PTYPEs belong to another PTGs. And some PTYPEs are reserved. Remove these PTYPEs in TCP, UDP, SCTP and ipv4 bitmap table. Fixes: aa1cd410fa64 ("net/ice/base: add flow module") Signed-off-by: Zhirun Yan Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index f9c65d6a2..e03c5d0e7 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -177,9 +177,9 @@ static const u32 ice_ptypes_ipv4_ofos[] = { /* Packet types for packets with an Innermost/Last IPv4 header */ static const u32 ice_ptypes_ipv4_il[] = { - 0xE0000000, 0xB807700E, 0x8001DC03, 0xE01DC03B, - 0x0007700E, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x000FF800, 0x00000000, + 0xE0000000, 0xB807700E, 0x80000003, 0xE01DC03B, + 0x0000000E, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x001FF800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -227,8 +227,8 @@ static const u32 ice_ptypes_arp_of[] = { * packets with inner UDP. */ static const u32 ice_ptypes_udp_il[] = { - 0x81000000, 0x20204040, 0x04081010, 0x80810102, - 0x00204040, 0x00000000, 0x00000000, 0x00000000, + 0x81000000, 0x20204040, 0x04000010, 0x80810102, + 0x00200040, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00410000, 0x10842000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -239,7 +239,7 @@ static const u32 ice_ptypes_udp_il[] = { /* Packet types for packets with an Innermost/Last TCP header */ static const u32 ice_ptypes_tcp_il[] = { - 0x04000000, 0x80810102, 0x10204040, 0x02040408, + 0x04000000, 0x80810102, 0x10000040, 0x02040408, 0x00810102, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00820000, 0x21084000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -251,7 +251,7 @@ static const u32 ice_ptypes_tcp_il[] = { /* Packet types for packets with an Innermost/Last SCTP header */ static const u32 ice_ptypes_sctp_il[] = { - 0x08000000, 0x01020204, 0x20408081, 0x04080810, + 0x08000000, 0x01020204, 0x20000081, 0x04080810, 0x01020204, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01040000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, From patchwork Mon Sep 23 07:44:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59601 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 158F31BF5F; Mon, 23 Sep 2019 09:44:20 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 8867D1BE8B for ; Mon, 23 Sep 2019 09:42:49 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445746" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:47 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Junfeng Guo , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:47 +0800 Message-Id: <20190923074448.7847-30-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 29/30] net/ice/base: add switch support for IPv6 tc field X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for IPv6 traffic class (tc) field for switch rule. Correct ice_ipv6_hdr based on the IPv6 Protocol using bitfields. Add big/little endian convert for tc field before it is inserted, since tc is only one byte and also does not have a byte-aligned offset. Signed-off-by: Junfeng Guo Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_protocol_type.h | 6 +++--- drivers/net/ice/base/ice_switch.c | 13 +++++++++++++ 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index 98185c9de..f61345a7f 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -183,9 +183,9 @@ struct ice_ipv4_hdr { }; struct ice_ipv6_hdr { - u8 version; - u8 tc; - u16 flow_label; + u32 version:4; + u32 tc:8; + u32 flow_label:20; u16 payload_len; u8 next_hdr; u8 hop_limit; diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 10dfc720a..80afa74cd 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -5785,6 +5785,19 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, break; case ICE_IPV6_OFOS: case ICE_IPV6_IL: + /* Based on the same mechanism below, if tc (Traffic + * Class) for IPv6 has mask, it means tc field is set. + * Since tc is only one byte, we have to handle the + * big/little endian issue before it can be inserted. + */ + if (lkups[i].m_u.ipv6_hdr.tc) { + ((u16 *)&lkups[i].h_u)[0] = + (((u16 *)&lkups[i].h_u)[0] << 8) | + (((u16 *)&lkups[i].h_u)[0] >> 8); + ((u16 *)&lkups[i].m_u)[0] = + (((u16 *)&lkups[i].m_u)[0] << 8) | + (((u16 *)&lkups[i].m_u)[0] >> 8); + } len = sizeof(struct ice_ipv6_hdr); break; case ICE_TCP_IL: From patchwork Mon Sep 23 07:44:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 59602 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 552E11BF67; Mon, 23 Sep 2019 09:44:22 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 2997F1BE8B for ; Mon, 23 Sep 2019 09:42:51 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 00:42:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="182445753" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:49 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Paul M Stillwell Jr Date: Mon, 23 Sep 2019 15:44:48 +0800 Message-Id: <20190923074448.7847-31-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190923074448.7847-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190923074448.7847-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 30/30] net/ice/base: remove unused code X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove unused code. Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 4 ---- drivers/net/ice/base/ice_common.h | 2 -- drivers/net/ice/base/ice_flex_pipe.c | 1 - drivers/net/ice/base/ice_flow.h | 3 --- 4 files changed, 10 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 16b91dc12..48ba160f7 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1068,7 +1068,6 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); } -#if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER) /** * ice_clear_rxq_ctx * @hw: pointer to the hardware structure @@ -1089,7 +1088,6 @@ enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) return ICE_SUCCESS; } -#endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */ /* LAN Tx Queue Context */ const struct ice_ctx_ele ice_tlan_ctx_info[] = { @@ -1125,7 +1123,6 @@ const struct ice_ctx_ele ice_tlan_ctx_info[] = { { 0 } }; -#if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER) /** * ice_copy_tx_cmpltnq_ctx_to_hw * @hw: pointer to the hardware structure @@ -1306,7 +1303,6 @@ ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) return ICE_SUCCESS; } -#endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */ /* FW Admin Queue command wrappers */ diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index bcb0a999d..c73184499 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -74,7 +74,6 @@ void ice_set_safe_mode_caps(struct ice_hw *hw); enum ice_status ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, u32 rxq_index); -#if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER) enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); enum ice_status ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); @@ -88,7 +87,6 @@ enum ice_status ice_write_tx_drbell_q_ctx(struct ice_hw *hw, struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, u32 tx_drbell_q_index); -#endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */ enum ice_status ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut, diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 0357fbd4e..75bb87079 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -2701,7 +2701,6 @@ ice_find_prof_id_with_mask(struct ice_hw *hw, enum ice_block blk, for (i = 0; i < es->count; i++) { u16 off = i * es->fvw; - u16 j; if (memcmp(&es->t[off], fv, es->fvw * sizeof(*fv))) continue; diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index 6f26f3935..326ff6f81 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -362,9 +362,6 @@ struct ice_flow_action { } data; }; -/* TDD esp in the linux code doesn't like prototypes, so - * ifdef them all out, so they stop conflicting with our mocks - */ u64 ice_flow_find_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir, struct ice_flow_seg_info *segs, u8 segs_cnt);