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Also add version map file and maintainers file to claim responsibility. Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- MAINTAINERS | 7 ++++++ config/common_base | 8 ++++++ drivers/crypto/Makefile | 1 + drivers/crypto/cpt/Makefile | 40 ++++++++++++++++++++++++++++++ drivers/crypto/cpt/rte_pmd_cpt_version.map | 4 +++ mk/rte.app.mk | 2 +- 6 files changed, 61 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/cpt/Makefile create mode 100644 drivers/crypto/cpt/rte_pmd_cpt_version.map diff --git a/MAINTAINERS b/MAINTAINERS index 4667fa7..1b4a8eb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -504,6 +504,13 @@ F: drivers/net/octeontx/ F: doc/guides/nics/octeontx.rst F: doc/guides/nics/features/octeontx.ini +Cavium CPT +M: Ankur Dwivedi +M: Nithin Dabilpuram +M: Murthy NSSR +F: drivers/crypto/cpt/ +F: doc/guides/cryptodevs/cpt.rst + Chelsio cxgbe M: Rahul Lakkireddy F: drivers/net/cxgbe/ diff --git a/config/common_base b/config/common_base index 6b0d1cb..85e03a8 100644 --- a/config/common_base +++ b/config/common_base @@ -631,6 +631,14 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n # +# Compile PMD for Cavium CPT Crypto device +# +CONFIG_RTE_LIBRTE_PMD_CPT=n +CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_INIT=n +CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_RX=n +CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_TX=n + +# # Compile raw device support # EXPERIMENTAL: API may change without prior notice # diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 1d0c88e..a0515f3 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -22,5 +22,6 @@ ifeq ($(CONFIG_RTE_LIBRTE_DPAA_BUS),y) DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_SEC) += dpaa_sec endif DIRS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += virtio +DIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt include $(RTE_SDK)/mk/rte.subdir.mk diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile new file mode 100644 index 0000000..b2d950d --- /dev/null +++ b/drivers/crypto/cpt/Makefile @@ -0,0 +1,40 @@ + +include $(RTE_SDK)/mk/rte.vars.mk + +# library name +LIB = librte_pmd_cptvf.a + +# library version +LIBABIVER := 1 + +# build flags +CFLAGS += $(WERROR_FLAGS) + +# external library include paths +CFLAGS += -I$(LIBCRYPTO_THUNDERX_PATH)/include +LDLIBS += -L$(LIBCRYPTO_THUNDERX_PATH) -lcrypto +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring +LDLIBS += -lrte_cryptodev +LDLIBS += -lrte_pci -lrte_bus_pci + +VPATH += $(RTE_SDK)/drivers/crypto/cpt/base + +CFLAGS += -O3 +#CFLAGS += -DAUTH_SOFT_COMPUTE_IPAD_OPAD +#CFLAGS += -DCPT_DEBUG + +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += + +# export include files +SYMLINK-y-include += + +# versioning export map +EXPORT_MAP := rte_pmd_cpt_version.map + +# library dependencies +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_eal +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_cryptodev +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_mempool lib/librte_mbuf +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_malloc + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/crypto/cpt/rte_pmd_cpt_version.map b/drivers/crypto/cpt/rte_pmd_cpt_version.map new file mode 100644 index 0000000..9b9ab1a --- /dev/null +++ b/drivers/crypto/cpt/rte_pmd_cpt_version.map @@ -0,0 +1,4 @@ +DPDK_18.05 { + + local: *; +}; diff --git a/mk/rte.app.mk b/mk/rte.app.mk index 1e32c83..158066d 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -209,7 +209,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_SEC) += -lrte_pmd_dpaa_sec endif # CONFIG_RTE_LIBRTE_DPAA_BUS _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += -lrte_pmd_virtio_crypto endif # CONFIG_RTE_LIBRTE_CRYPTODEV - +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += -lrte_pmd_cptvf ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y) _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lrte_pmd_isal_comp _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lisal From patchwork Fri Jun 8 16:45:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 40863 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 54DFE7ED7; Fri, 8 Jun 2018 18:48:52 +0200 (CEST) Received: from NAM04-SN1-obe.outbound.protection.outlook.com (mail-eopbgr700056.outbound.protection.outlook.com [40.107.70.56]) by dpdk.org (Postfix) with ESMTP id 2871D7ED7 for ; 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Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/base/cpt_hw_types.h | 836 ++++++++++++++++++++++++++++++++ drivers/crypto/cpt/base/mcode_defines.h | 215 ++++++++ 2 files changed, 1051 insertions(+) create mode 100644 drivers/crypto/cpt/base/cpt_hw_types.h create mode 100644 drivers/crypto/cpt/base/mcode_defines.h diff --git a/drivers/crypto/cpt/base/cpt_hw_types.h b/drivers/crypto/cpt/base/cpt_hw_types.h new file mode 100644 index 0000000..b4b2af1 --- /dev/null +++ b/drivers/crypto/cpt/base/cpt_hw_types.h @@ -0,0 +1,836 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef __CPT_HW_TYPES_H +#define __CPT_HW_TYPES_H + +#include +#include +#include +#include +#include + +#define CPT_INST_SIZE (64) +#define CPT_VQ_CHUNK_ALIGN (128) /**< 128 byte align */ +#define CPT_NEXT_CHUNK_PTR_SIZE (8) +#define CPT_INST_CHUNK_MAX_SIZE (1023) + +#define CPT_PF_VF_MAILBOX_SIZE (2) + +#define CPT_VF_INTR_MBOX_MASK (1<<0) +#define CPT_VF_INTR_DOVF_MASK (1<<1) +#define CPT_VF_INTR_IRDE_MASK (1<<2) +#define CPT_VF_INTR_NWRP_MASK (1<<3) +#define CPT_VF_INTR_SWERR_MASK (1<<4) +#define CPT_VF_INTR_HWERR_MASK (1<<5) +#define CPT_VF_INTR_FAULT_MASK (1<<6) + +/* + * CPT_INST_S software command definitions + * Words EI (0-3) + */ +typedef union { + uint64_t u64; + struct { + uint16_t opcode; + uint16_t param1; + uint16_t param2; + uint16_t dlen; + } s; +} vq_cmd_word0_t; + +typedef union { + uint64_t u64; + struct { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + uint64_t grp : 3; + uint64_t cptr : 61; +#else + uint64_t cptr : 61; + uint64_t grp : 3; +#endif + } s; +} vq_cmd_word3_t; + +typedef struct cpt_vq_command { + vq_cmd_word0_t cmd; + uint64_t dptr; + uint64_t rptr; + vq_cmd_word3_t cptr; +} cpt_vq_cmd_t; + +/** + * Structure cpt_inst_s + * + * CPT Instruction Structure + * This structure specifies the instruction layout. + * Instructions are stored in memory + * as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set. + */ +typedef union cpt_inst_s { + uint64_t u[8]; + struct cpt_inst_s_s { +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */ + uint64_t reserved_17_63 : 47; + uint64_t doneint : 1; + /*< [ 16: 16] Done interrupt. + * 0 = No interrupts related to this instruction. + * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE] + * will be incremented, and based on the rules described + * there an interrupt may occur. + */ + uint64_t reserved_0_15 : 16; +#else /* Word 0 - Little Endian */ + uint64_t reserved_0_15 : 16; + uint64_t doneint : 1; + /*< [ 16: 16] Done interrupt. + * 0 = No interrupts related to this instruction. + * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE] + * will be incremented, and based on the rules described + * there aninterrupt may occur. + */ + uint64_t reserved_17_63 : 47; +#endif /* Word 0 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 1 - Big Endian */ + uint64_t res_addr : 64; + /*< [127: 64] Result IOVA. + * If nonzero, specifies where to write CPT_RES_S. + * If zero, no result structure will be written. + * Address must be 16-byte aligned. + + * Bits <63:49> are ignored by hardware; software should + *use a sign-extended bit <48> for forward compatibility. + */ +#else /* Word 1 - Little Endian */ + uint64_t res_addr : 64; + /*< [127: 64] Result IOVA. + * If nonzero, specifies where to write CPT_RES_S. + * If zero, no result structure will be written. + * Address must be 16-byte aligned. + + * Bits <63:49> are ignored by hardware; software should + *use a sign-extended bit <48> for forward compatibility. + */ +#endif /* Word 1 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 2 - Big Endian */ + uint64_t reserved_172_191 : 20; + uint64_t grp : 10; + /*< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to + * use when CPT submits work to SSO. + * For the SSO to not discard the add-work request, FPA_PF_MAP() + * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid. + */ + uint64_t tt : 2; + /*< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use + * when CPT submits work to SSO. + */ + uint64_t tag : 32; + /*< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when + * CPT submits work to SSO. + */ +#else /* Word 2 - Little Endian */ + uint64_t tag : 32; + /**< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when + * CPT submits work to SSO. + */ + uint64_t tt : 2; + /**< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use + * when CPT submits work to SSO. + */ + uint64_t grp : 10; + /**< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to + * use when CPT submits work to SSO. + * For the SSO to not discard the add-work request, FPA_PF_MAP() + * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid. + **/ + uint64_t reserved_172_191 : 20; +#endif /* Word 2 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 3 - Big Endian */ + uint64_t wq_ptr : 64; + /**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a + * work-queue entry that CPT submits work to SSO after all + * context, output data, and result write operations are + * visible to other CNXXXX units and the cores. + * Bits <2:0> must be zero. + * Bits <63:49> are ignored by hardware; software should use a + * sign-extended bit <48> for forward compatibility. + * Internal:Bits <63:49>, <2:0> are ignored by hardware, + * treated as always 0x0. + **/ +#else /* Word 3 - Little Endian */ + uint64_t wq_ptr : 64; + /**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a + * work-queue entry that CPT submits work to SSO after all + * context, output data, and result write operations are + * visible to other CNXXXX units and the cores. + * Bits <2:0> must be zero. + * Bits <63:49> are ignored by hardware; software should use a + * sign-extended bit <48> for forward compatibility. + * Internal: Bits <63:49>, <2:0> are ignored by hardware, + * treated as always 0x0. + **/ +#endif /* Word 3 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 4 - Big Endian */ + union { + uint64_t ei0 : 64; + /**< [319:256] Engine instruction word 0. Passed to the + * AE/SE. + **/ + vq_cmd_word0_t vq_cmd_w0; + }; +#else /* Word 4 - Little Endian */ + union { + uint64_t ei0 : 64; + /**< [319:256] Engine instruction word 0. Passed to the + * AE/SE. + **/ + vq_cmd_word0_t vq_cmd_w0; + }; +#endif /* Word 4 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 5 - Big Endian */ + union { + uint64_t ei1 : 64; + /**< [383:320] Engine instruction word 1. Passed to the + * AE/SE. + **/ + uint64_t dptr; + }; +#else /* Word 5 - Little Endian */ + union { + uint64_t ei1 : 64; + /**< [383:320] Engine instruction word 1. Passed to the + * AE/SE. + **/ + uint64_t dptr; + }; +#endif /* Word 5 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 6 - Big Endian */ + union { + uint64_t ei2 : 64; + /**< [447:384] Engine instruction word 2. Passed to the + * AE/SE. + **/ + uint64_t rptr; + }; +#else /* Word 6 - Little Endian */ + union { + uint64_t ei2 : 64; + /**< [447:384] Engine instruction word 2. Passed to the + * AE/SE. + **/ + uint64_t rptr; + }; +#endif /* Word 6 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 7 - Big Endian */ + union { + uint64_t ei3 : 64; + /**< [511:448] Engine instruction word 3. Passed to the + * AE/SE. + **/ + vq_cmd_word3_t vq_cmd_w3; + }; +#else /* Word 7 - Little Endian */ + union { + uint64_t ei3 : 64; + /**< [511:448] Engine instruction word 3. Passed to the + * AE/SE. + **/ + vq_cmd_word3_t vq_cmd_w3; + }; +#endif /* Word 7 - End */ + } s; + struct cpt_inst_s_cn { +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */ + uint64_t reserved_17_63 : 47; + uint64_t doneint : 1; + /**< [ 16: 16] Done interrupt. + * 0 = No interrupts related to this instruction. + * 1 = When the instruction completes, CPT()_VQ()_DONE[DONE] + * will be incremented,and based on the rules described there + * an interrupt may occur. + **/ + uint64_t reserved_8_15 : 8; + uint64_t reserved_0_7 : 8; +#else /* Word 0 - Little Endian */ + uint64_t reserved_0_7 : 8; + uint64_t reserved_8_15 : 8; + uint64_t doneint : 1; + /**< [ 16: 16] Done interrupt. + * 0 = No interrupts related to this instruction. + * 1 = When the instruction completes, CPT()_VQ()_DONE[DONE] + * will be incremented,and based on the rules described there + * an interrupt may occur. + **/ + uint64_t reserved_17_63 : 47; +#endif /* Word 0 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 1 - Big Endian */ + uint64_t res_addr : 64; + /**< [127: 64] Result IOVA. + * If nonzero, specifies where to write CPT_RES_S. + * If zero, no result structure will be written. + * Address must be 16-byte aligned. + * + * Bits <63:49> are ignored by hardware; software should + * use a sign-extended bit <48> for forward compatibility. + **/ +#else /* Word 1 - Little Endian */ + uint64_t res_addr : 64; + /**< [127: 64] Result IOVA. + * If nonzero, specifies where to write CPT_RES_S. + * If zero, no result structure will be written. + * Address must be 16-byte aligned. + * + * Bits <63:49> are ignored by hardware; software should + * use a sign-extended bit <48> for forward compatibility. + **/ +#endif /* Word 1 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 2 - Big Endian */ + uint64_t reserved_172_191 : 20; + uint64_t grp : 10; + /**< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to + * use when CPT submits work to SSO. For the SSO to not discard + * the add-work request, FPA_PF_MAP() must map [GRP] and + * CPT()_PF_Q()_GMCTL[GMID] as valid. + **/ + uint64_t tt : 2; + /**< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use + * when CPT submits work to SSO. + **/ + uint64_t tag : 32; + /**< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use + * when CPT submits work to SSO. + **/ +#else /* Word 2 - Little Endian */ + uint64_t tag : 32; + /**< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use + * when CPT submits work to SSO. + **/ + uint64_t tt : 2; + /**< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use + * when CPT submits work to SSO. + **/ + uint64_t grp : 10; + /**< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to + * use when CPT submits work to SSO. For the SSO to not discard + * the add-work request, FPA_PF_MAP() must map [GRP] and + * CPT()_PF_Q()_GMCTL[GMID] as valid. + **/ + uint64_t reserved_172_191 : 20; +#endif /* Word 2 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 3 - Big Endian */ + uint64_t wq_ptr : 64; + /**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a work + * -queue entry that CPT submits work to SSO after all context, + * output data, and result write operations are visible to other + * CNXXXX units and the cores. + + Bits <2:0> must be zero. Bits <63:49> are ignored by hardware; + software should use a sign-extended bit <48> for forward + compatibility. + +Internal: +Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0. + */ +#else /* Word 3 - Little Endian */ + uint64_t wq_ptr : 64; + /**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a work + * -queue entry that CPT submits work to SSO after all context, + * output data, and result write operations are visible to other + * CNXXXX units and the cores. + + Bits <2:0> must be zero. Bits <63:49> are ignored by hardware; + software should use a sign-extended bit <48> for forward + compatibility. + +Internal: +Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0. + */ +#endif /* Word 3 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 4 - Big Endian */ + uint64_t ei0 : 64; + /**< [319:256] Engine instruction word 0. Passed to the AE/SE.*/ +#else /* Word 4 - Little Endian */ + uint64_t ei0 : 64; + /**< [319:256] Engine instruction word 0. Passed to the AE/SE.*/ +#endif /* Word 4 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 5 - Big Endian */ + uint64_t ei1 : 64; + /**< [383:320] Engine instruction word 1. Passed to the AE/SE.*/ +#else /* Word 5 - Little Endian */ + uint64_t ei1 : 64; + /**< [383:320] Engine instruction word 1. Passed to the AE/SE.*/ +#endif /* Word 5 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 6 - Big Endian */ + uint64_t ei2 : 64; + /**< [447:384] Engine instruction word 2. Passed to the AE/SE.*/ +#else /* Word 6 - Little Endian */ + uint64_t ei2 : 64; + /**< [447:384] Engine instruction word 2. Passed to the AE/SE.*/ +#endif /* Word 6 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 7 - Big Endian */ + uint64_t ei3 : 64; + /**< [511:448] Engine instruction word 3. Passed to the AE/SE.*/ +#else /* Word 7 - Little Endian */ + uint64_t ei3 : 64; + /**< [511:448] Engine instruction word 3. Passed to the AE/SE.*/ +#endif /* Word 7 - End */ + } cn; +} cpt_inst_s_t; + +/** + * Structure cpt_res_s + * + * CPT Result Structure + * The CPT coprocessor writes the result structure after it completes a + * CPT_INST_S instruction. The result structure is exactly 16 bytes, and each + * instruction completion produces exactly one result structure. + * + * This structure is stored in memory as little-endian unless + * CPT()_PF_Q()_CTL[INST_BE] is set. + */ +typedef union cpt_res_s { + uint64_t u[2]; + struct cpt_res_s_s { +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */ + uint64_t reserved_17_63 : 47; + uint64_t doneint : 1; + /**< [ 16: 16] Done interrupt. This bit is copied from the + * corresponding instruction's CPT_INST_S[DONEINT]. + **/ + uint64_t reserved_8_15 : 8; + uint64_t compcode : 8; + /**< [ 7: 0] Indicates completion/error status of the CPT + * coprocessor for the associated instruction, as enumerated by + * CPT_COMP_E. Core software may write the memory location + * containing [COMPCODE] to 0x0 before ringing the doorbell, and + * then poll for completion by checking for a nonzero value. + + Once the core observes a nonzero [COMPCODE] value in this case, + the CPT coprocessor will have also completed L2/DRAM write + operations. + */ +#else /* Word 0 - Little Endian */ + uint64_t compcode : 8; + /**< [ 7: 0] Indicates completion/error status of the CPT + * coprocessor for the associated instruction, as enumerated by + * CPT_COMP_E. Core software may write the memory location + * containing [COMPCODE] to 0x0 before ringing the doorbell, and + * then poll for completion by checking for a nonzero value. + + Once the core observes a nonzero [COMPCODE] value in this case, + the CPT coprocessor will have also completed L2/DRAM write + operations. + */ + uint64_t reserved_8_15 : 8; + uint64_t doneint : 1; + /**< [ 16: 16] Done interrupt. This bit is copied from the + * corresponding instruction's CPT_INST_S[DONEINT]. + **/ + uint64_t reserved_17_63 : 47; +#endif /* Word 0 - End */ +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 1 - Big Endian */ + uint64_t reserved_64_127 : 64; +#else /* Word 1 - Little Endian */ + uint64_t reserved_64_127 : 64; +#endif /* Word 1 - End */ + } s; + /* struct cpt_res_s_s cn; */ +} cpt_res_s_t; + +/** + * Register (NCB) cpt#_vq#_ctl + * + * CPT VF Queue Control Registers + * This register configures queues. This register should be changed (other than + * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]). + */ +typedef union { + uint64_t u; + struct cptx_vqx_ctl_s { +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */ + uint64_t reserved_1_63 : 63; + uint64_t ena : 1; + /**< [ 0: 0](R/W/H) Enables the logical instruction queue. + * See also CPT()_PF_Q()_CTL[CONT_ERR] and + * CPT()_VQ()_INPROG[INFLIGHT]. + * 1 = Queue is enabled. + * 0 = Queue is disabled. + **/ +#else /* Word 0 - Little Endian */ + uint64_t ena : 1; + /**< [ 0: 0](R/W/H) Enables the logical instruction queue. + * See also CPT()_PF_Q()_CTL[CONT_ERR] and + * CPT()_VQ()_INPROG[INFLIGHT]. + * 1 = Queue is enabled. + * 0 = Queue is disabled. + **/ + uint64_t reserved_1_63 : 63; +#endif /* Word 0 - End */ + } s; + /* struct cptx_vqx_ctl_s cn; */ +} cptx_vqx_ctl_t; + +/** + * Register (NCB) cpt#_vq#_done + * + * CPT Queue Done Count Registers + * These registers contain the per-queue instruction done count. + */ +typedef union { + uint64_t u; + struct cptx_vqx_done_s { +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */ + uint64_t reserved_20_63 : 44; + uint64_t done : 20; + /**< [ 19: 0](R/W/H) Done count. When CPT_INST_S[DONEINT] set + * and that instruction completes,CPT()_VQ()_DONE[DONE] is + * incremented when the instruction finishes. Write to this + * field are for diagnostic use only; instead software writes + * CPT()_VQ()_DONE_ACK with the number of decrements for this + * field. + + Interrupts are sent as follows: + + * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending, + * the interrupt coalescing timer is held to zero, and an + * interrupt is not sent. + + * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt + * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE + * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ() + * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough + * results have arrived, then the interrupt is sent. Otherwise, + * it is not sent due to coalescing. + + * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is + * written but this is not typical), the interrupt coalescing + * timer restarts. Note after decrementing this interrupt + * equation is recomputed, for example if CPT()_VQ()_DONE[DONE] + * >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is + * zero, the interrupt will be resent immediately. (This covers + * the race case between software acknowledging an interrupt and + * a result returning.) + + * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not + * sent, but the counting described above still occurs. + + Since CPT instructions complete out-of-order, if software is + using completion interrupts the suggested scheme is to request a + DONEINT on each request, and when an interrupt arrives perform a + "greedy" scan for completions; even if a later command is + acknowledged first this will not result in missing a completion. + + Software is responsible for making sure [DONE] does not overflow + ; for example by insuring there are not more than 2^20-1 + instructions in flight that may request interrupts. + */ +#else /* Word 0 - Little Endian */ + uint64_t done : 20; + /**< [ 19: 0](R/W/H) Done count. When CPT_INST_S[DONEINT] set + * and that instruction completes,CPT()_VQ()_DONE[DONE] is + * incremented when the instruction finishes. Write to this + * field are for diagnostic use only; instead software writes + * CPT()_VQ()_DONE_ACK with the number of decrements for this + * field. + + Interrupts are sent as follows: + + * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending, + * the interrupt coalescing timer is held to zero, and an + * interrupt is not sent. + + * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt + * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE + * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ() + * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough + * results have arrived, then the interrupt is sent. Otherwise, + * it is not sent due to coalescing. + + * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is + * written but this is not typical), the interrupt coalescing + * timer restarts. Note after decrementing this interrupt + * equation is recomputed, for example if CPT()_VQ()_DONE[DONE] + * >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is + * zero, the interrupt will be resent immediately. (This covers + * the race case between software acknowledging an interrupt and + * a result returning.) + + * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not + * sent, but the counting described above still occurs. + + Since CPT instructions complete out-of-order, if software is + using completion interrupts the suggested scheme is to request a + DONEINT on each request, and when an interrupt arrives perform a + "greedy" scan for completions; even if a later command is + acknowledged first this will not result in missing a completion. + + Software is responsible for making sure [DONE] does not overflow + ; for example by insuring there are not more than 2^20-1 + instructions in flight that may request interrupts. + */ + uint64_t reserved_20_63 : 44; +#endif /* Word 0 - End */ + } s; + /* struct cptx_vqx_done_s cn; */ +} cptx_vqx_done_t; + +/** + * Register (NCB) cpt#_vq#_done_ack + * + * CPT Queue Done Count Ack Registers + * This register is written by software to acknowledge interrupts. + */ +typedef union { + uint64_t u; + struct cptx_vqx_done_ack_s { +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */ + uint64_t reserved_20_63 : 44; + uint64_t done_ack : 20; + /**< [ 19: 0](R/W/H) Number of decrements to CPT()_VQ()_DONE + * [DONE]. Reads CPT()_VQ()_DONE[DONE]. + + Written by software to acknowledge interrupts. If CPT()_VQ()_ + DONE[DONE] is still nonzero the interrupt will be re-sent if the + conditions described in CPT()_VQ()_DONE[DONE] are satisfied. + */ +#else /* Word 0 - Little Endian */ + uint64_t done_ack : 20; + /**< [ 19: 0](R/W/H) Number of decrements to CPT()_VQ()_DONE + * [DONE]. Reads CPT()_VQ()_DONE[DONE]. + + Written by software to acknowledge interrupts. If CPT()_VQ()_ + DONE[DONE] is still nonzero the interrupt will be re-sent if the + conditions described in CPT()_VQ()_DONE[DONE] are satisfied. + */ + uint64_t reserved_20_63 : 44; +#endif /* Word 0 - End */ + } s; + /* struct cptx_vqx_done_ack_s cn; */ +} cptx_vqx_done_ack_t; + +/** + * Register (NCB) cpt#_vq#_done_wait + * + * CPT Queue Done Interrupt Coalescing Wait Registers + * Specifies the per queue interrupt coalescing settings. + */ +typedef union { + uint64_t u; + struct cptx_vqx_done_wait_s { +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */ + uint64_t reserved_48_63 : 16; + uint64_t time_wait : 16; + /**< [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] = + * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When + * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing + * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is + * disabled. + **/ + uint64_t reserved_20_31 : 12; + uint64_t num_wait : 20; + /**< [ 19: 0](R/W) Number of messages hold-off. When + * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing + * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as + * 0x1. + **/ +#else /* Word 0 - Little Endian */ + uint64_t num_wait : 20; + /**< [ 19: 0](R/W) Number of messages hold-off. When + * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing + * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as + * 0x1. + **/ + uint64_t reserved_20_31 : 12; + uint64_t time_wait : 16; + /**< [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] = + * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When + * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing + * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is + * disabled. + **/ + uint64_t reserved_48_63 : 16; +#endif /* Word 0 - End */ + } s; + /* struct cptx_vqx_done_wait_s cn; */ +} cptx_vqx_done_wait_t; + +/** + * Register (NCB) cpt#_vq#_doorbell + * + * CPT Queue Doorbell Registers + * Doorbells for the CPT instruction queues. + */ +typedef union { + uint64_t u; + struct cptx_vqx_doorbell_s { +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */ + uint64_t reserved_20_63 : 44; + uint64_t dbell_cnt : 20; + /**< [ 19: 0](R/W/H) Number of instruction queue 64-bit words + * to add to the CPT instruction doorbell count. Readback value + * is the the current number of pending doorbell requests. + + If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set. + + To reset the count back to zero, write one to clear + CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value of + 2^20 minus the read [DBELL_CNT], then write one to + CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and + CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF]. + + Must be a multiple of 8. All CPT instructions are 8 words and + require a doorbell count of multiple of 8. + */ +#else /* Word 0 - Little Endian */ + uint64_t dbell_cnt : 20; + /**< [ 19: 0](R/W/H) Number of instruction queue 64-bit words + * to add to the CPT instruction doorbell count. Readback value + * is the the current number of pending doorbell requests. + + If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set. + + To reset the count back to zero, write one to clear + CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value of + 2^20 minus the read [DBELL_CNT], then write one to + CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and + CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF]. + + Must be a multiple of 8. All CPT instructions are 8 words and + require a doorbell count of multiple of 8. + */ + uint64_t reserved_20_63 : 44; +#endif /* Word 0 - End */ + } s; + /* struct cptx_vqx_doorbell_s cn; */ +} cptx_vqx_doorbell_t; + +/** + * Register (NCB) cpt#_vq#_inprog + * + * CPT Queue In Progress Count Registers + * These registers contain the per-queue instruction in flight registers. + */ +typedef union { + uint64_t u; + struct cptx_vqx_inprog_s { +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */ + uint64_t reserved_8_63 : 56; + uint64_t inflight : 8; + /**< [ 7: 0](RO/H) Inflight count. Counts the number of + * instructions for the VF for which CPT is fetching, executing + * or responding to instructions. However this does not include + * any interrupts that are awaiting software handling + * (CPT()_VQ()_DONE[DONE] != 0x0). + + A queue may not be reconfigured until: + 1. CPT()_VQ()_CTL[ENA] is cleared by software. + 2. [INFLIGHT] is polled until equals to zero. + */ +#else /* Word 0 - Little Endian */ + uint64_t inflight : 8; + /**< [ 7: 0](RO/H) Inflight count. Counts the number of + * instructions for the VF for which CPT is fetching, executing + * or responding to instructions. However this does not include + * any interrupts that are awaiting software handling + * (CPT()_VQ()_DONE[DONE] != 0x0). + + A queue may not be reconfigured until: + 1. CPT()_VQ()_CTL[ENA] is cleared by software. + 2. [INFLIGHT] is polled until equals to zero. + */ + uint64_t reserved_8_63 : 56; +#endif /* Word 0 - End */ + } s; + /* struct cptx_vqx_inprog_s cn; */ +} cptx_vqx_inprog_t; + +/** + * Register (NCB) cpt#_vq#_misc_int + * + * CPT Queue Misc Interrupt Register + * These registers contain the per-queue miscellaneous interrupts. + */ +typedef union { + uint64_t u; + struct cptx_vqx_misc_int_s { +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */ + uint64_t reserved_7_63 : 57; + uint64_t fault : 1; + /**< [ 6: 6](R/W1C/H) Translation fault detected. */ + uint64_t hwerr : 1; + /**< [ 5: 5](R/W1C/H) Hardware error from engines. */ + uint64_t swerr : 1; + /**< [ 4: 4](R/W1C/H) Software error from engines. */ + uint64_t nwrp : 1; + /**< [ 3: 3](R/W1C/H) NCB result write response error. */ + uint64_t irde : 1; + /**< [ 2: 2](R/W1C/H) Instruction NCB read response error. */ + uint64_t dovf : 1; + /**< [ 1: 1](R/W1C/H) Doorbell overflow. */ + uint64_t mbox : 1; + /**< [ 0: 0](R/W1C/H) PF to VF mailbox interrupt. Set when + * CPT()_VF()_PF_MBOX(0) is written. + **/ +#else /* Word 0 - Little Endian */ + uint64_t mbox : 1; + /**< [ 0: 0](R/W1C/H) PF to VF mailbox interrupt. Set when + * CPT()_VF()_PF_MBOX(0) is written. + **/ + uint64_t dovf : 1; + /**< [ 1: 1](R/W1C/H) Doorbell overflow. */ + uint64_t irde : 1; + /**< [ 2: 2](R/W1C/H) Instruction NCB read response error. */ + uint64_t nwrp : 1; + /**< [ 3: 3](R/W1C/H) NCB result write response error. */ + uint64_t swerr : 1; + /**< [ 4: 4](R/W1C/H) Software error from engines. */ + uint64_t hwerr : 1; + /**< [ 5: 5](R/W1C/H) Hardware error from engines. */ + uint64_t fault : 1; + /**< [ 6: 6](R/W1C/H) Translation fault detected. */ + uint64_t reserved_5_63 : 59; +#endif /* Word 0 - End */ + } s; + /* struct cptx_vqx_misc_int_s cn; */ +} cptx_vqx_misc_int_t; + +/** + * Register (NCB) cpt#_vq#_saddr + * + * CPT Queue Starting Buffer Address Registers + * These registers set the instruction buffer starting address. + */ +typedef union { + uint64_t u; + struct cptx_vqx_saddr_s { +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */ + uint64_t reserved_49_63 : 15; + uint64_t ptr : 43; + /**< [ 48: 6](R/W/H) Instruction buffer IOVA <48:6> + * (64-byte aligned). When written, it is the initial buffer + * starting address; when read, it is the next read pointer to + * be requested from L2C. The PTR field is overwritten with the + * next pointer each time that the command buffer segment is + * exhausted. New commands will then be read from the newly + * specified command buffer pointer. + **/ + uint64_t reserved_0_5 : 6; +#else /* Word 0 - Little Endian */ + uint64_t reserved_0_5 : 6; + uint64_t ptr : 43; + /**< [ 48: 6](R/W/H) Instruction buffer IOVA <48:6> + * (64-byte aligned). When written, it is the initial buffer + * starting address; when read, it is the next read pointer to + * be requested from L2C. The PTR field is overwritten with the + * next pointer each time that the command buffer segment is + * exhausted. New commands will then be read from the newly + * specified command buffer pointer. + **/ + uint64_t reserved_49_63 : 15; +#endif /* Word 0 - End */ + } s; + /* struct cptx_vqx_saddr_s cn; */ +} cptx_vqx_saddr_t; + +#endif /*__CPT_HW_TYPES_H*/ diff --git a/drivers/crypto/cpt/base/mcode_defines.h b/drivers/crypto/cpt/base/mcode_defines.h new file mode 100644 index 0000000..15e7e60 --- /dev/null +++ b/drivers/crypto/cpt/base/mcode_defines.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef _MCODE_DEFINES_H_ +#define _MCODE_DEFINES_H_ + +#include +#include + +/*SE opcodes*/ +#define MAJOR_OP_FC 0x33 +#define MAJOR_OP_HASH 0x34 +#define MAJOR_OP_HMAC 0x35 +#define MAJOR_OP_ZUC_SNOW3G 0x37 +#define MAJOR_OP_KASUMI 0x38 + +#define BYTE_16 16 +#define BYTE_24 24 +#define BYTE_32 32 +#define MAX_BUF_CNT 1024 +#define MAX_SG_IN_OUT_CNT 16 +#define MAX_SG_CNT (MAX_SG_IN_OUT_CNT/2) + +#define ENCRYPT 1 +#define DECRYPT 0 +#define OFFSET_CONTROL_BYTES 8 + +#define DMA_MODE (1 << 7) /* Default support is with SG */ + +#define FROM_CTX 0 +#define FROM_DPTR 1 + +typedef enum { + MD5_TYPE = 1, + SHA1_TYPE = 2, + SHA2_SHA224 = 3, + SHA2_SHA256 = 4, + SHA2_SHA384 = 5, + SHA2_SHA512 = 6, + GMAC_TYPE = 7, + XCBC_TYPE = 8, + SHA3_SHA224 = 10, + SHA3_SHA256 = 11, + SHA3_SHA384 = 12, + SHA3_SHA512 = 13, + SHA3_SHAKE256 = 14, + SHA3_SHAKE512 = 15, + + /* These are only for software use */ + ZUC_EIA3 = 0x90, + SNOW3G_UIA2 = 0x91, + KASUMI_F9_CBC = 0x92, + KASUMI_F9_ECB = 0x93, +} mc_hash_type_t; + +typedef enum { + /* + * These are defined by MC for Flexi crypto + * for field of 4 bits + */ + DES3_CBC = 0x1, + DES3_ECB = 0x2, + AES_CBC = 0x3, + AES_ECB = 0x4, + AES_CFB = 0x5, + AES_CTR = 0x6, + AES_GCM = 0x7, + AES_XTS = 0x8, + + /* These are only for software use */ + ZUC_EEA3 = 0x90, + SNOW3G_UEA2 = 0x91, + KASUMI_F8_CBC = 0x92, + KASUMI_F8_ECB = 0x93, +} mc_cipher_type_t; + +typedef enum { + AES_128_BIT = 0x1, + AES_192_BIT = 0x2, + AES_256_BIT = 0x3 +} mc_aes_type_t; + +typedef enum { + /*Microcode errors*/ + NO_ERR = 0x00, + ERR_OPCODE_UNSUPPORTED = 0x01, + + /*SCATTER GATHER*/ + ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02, + ERR_SCATTER_GATHER_LIST = 0x03, + ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04, + + /*SE GC*/ + ERR_GC_LENGTH_INVALID = 0x41, + ERR_GC_RANDOM_LEN_INVALID = 0x42, + ERR_GC_DATA_LEN_INVALID = 0x43, + ERR_GC_DRBG_TYPE_INVALID = 0x44, + ERR_GC_CTX_LEN_INVALID = 0x45, + ERR_GC_CIPHER_UNSUPPORTED = 0x46, + ERR_GC_AUTH_UNSUPPORTED = 0x47, + ERR_GC_OFFSET_INVALID = 0x48, + ERR_GC_HASH_MODE_UNSUPPORTED = 0x49, + ERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a, + ERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b, + ERR_GC_ICV_MISCOMPARE = 0x4c, + ERR_GC_DATA_UNALIGNED = 0x4d, + + /* API Layer */ + ERR_BAD_ALT_CCODE = 0xfd, + ERR_REQ_PENDING = 0xfe, + ERR_REQ_TIMEOUT = 0xff, + + ERR_BAD_INPUT_LENGTH = (0x40000000 | 384), /* 0x40000180 */ + ERR_BAD_KEY_LENGTH, + ERR_BAD_KEY_HANDLE, + ERR_BAD_CONTEXT_HANDLE, + ERR_BAD_SCALAR_LENGTH, + ERR_BAD_DIGEST_LENGTH, + ERR_BAD_INPUT_ARG, + ERR_BAD_RECORD_PADDING, + ERR_NB_REQUEST_PENDING, + ERR_EIO, + ERR_ENODEV, +} mc_error_code_t; + +/* FC offset_control at start of DPTR in bytes */ +#define OFF_CTRL_LEN 8 /* bytes */ +#define SHA1_BLOCK_SIZE 64 + +typedef union { + uint64_t flags; + struct { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + uint64_t enc_cipher : 4; + uint64_t reserved1 : 1; + uint64_t aes_key : 2; + uint64_t iv_source : 1; + uint64_t hash_type : 4; + uint64_t reserved2 : 3; + uint64_t auth_input_type : 1; + uint64_t mac_len : 8; + uint64_t reserved3 : 8; + uint64_t encr_offset : 16; + uint64_t iv_offset : 8; + uint64_t auth_offset : 8; +#else + uint64_t auth_offset : 8; + uint64_t iv_offset : 8; + uint64_t encr_offset : 16; + uint64_t reserved3 : 8; + uint64_t mac_len : 8; + uint64_t auth_input_type : 1; + uint64_t reserved2 : 3; + uint64_t hash_type : 4; + uint64_t iv_source : 1; + uint64_t aes_key : 2; + uint64_t reserved1 : 1; + uint64_t enc_cipher : 4; +#endif + } e; +} encr_ctrl_t; + +typedef struct { + encr_ctrl_t enc_ctrl; + uint8_t encr_key[32]; + uint8_t encr_iv[16]; +} mc_enc_context_t; + +typedef struct { + uint8_t ipad[64]; + uint8_t opad[64]; +} mc_fc_hmac_context_t; + +typedef struct { + mc_enc_context_t enc; + mc_fc_hmac_context_t hmac; +} mc_fc_context_t; + +typedef struct { + uint8_t encr_auth_iv[16]; + uint8_t ci_key[16]; + uint8_t zuc_const[32]; +} mc_zuc_snow3g_ctx_t; + +typedef struct { + uint8_t reg_A[8]; + uint8_t ci_key[16]; +} mc_kasumi_ctx_t; + +#define ENC_CTRL(fctx) fctx.enc.enc_ctrl.e +#define AUTH_CTRL(fctx) fctx.auth.auth_ctrl +#define P_ENC_CTRL(fctx) fctx->enc.enc_ctrl.e + +#define MAX_IVLEN 16 +#define MAX_KEYLEN 32 + +/** + * Enumeration cpt_comp_e + * + * CPT Completion Enumeration + * Enumerates the values of CPT_RES_S[COMPCODE]. + */ +typedef enum { + CPT_COMP_E_NOTDONE = (0x00), + CPT_COMP_E_GOOD = (0x01), + CPT_COMP_E_FAULT = (0x02), + CPT_COMP_E_SWERR = (0x03), + CPT_COMP_E_HWERR = (0x04), + CPT_COMP_E_LAST_ENTRY = (0xFF) +} cpt_comp_e_t; + +/** @endcond */ + +#endif /* _MCODE_DEFINES_H_ */ From patchwork Fri Jun 8 16:45:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 40864 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 10A911B76D; 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Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/base/cpt8xxx_device.c | 200 ++++++++++++++++ drivers/crypto/cpt/base/cpt8xxx_device.h | 85 +++++++ drivers/crypto/cpt/base/cpt_debug.h | 231 +++++++++++++++++++ drivers/crypto/cpt/base/cpt_device.c | 383 +++++++++++++++++++++++++++++++ drivers/crypto/cpt/base/cpt_device.h | 162 +++++++++++++ drivers/crypto/cpt/base/cpt_vf_mbox.c | 176 ++++++++++++++ drivers/crypto/cpt/base/cpt_vf_mbox.h | 60 +++++ 7 files changed, 1297 insertions(+) create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.c create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.h create mode 100644 drivers/crypto/cpt/base/cpt_debug.h create mode 100644 drivers/crypto/cpt/base/cpt_device.c create mode 100644 drivers/crypto/cpt/base/cpt_device.h create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.c create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.h diff --git a/drivers/crypto/cpt/base/cpt8xxx_device.c b/drivers/crypto/cpt/base/cpt8xxx_device.c new file mode 100644 index 0000000..cdce96f --- /dev/null +++ b/drivers/crypto/cpt/base/cpt8xxx_device.c @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#include "cpt8xxx_device.h" + +/* + * VF HAL functions + * Access its own BAR0/4 registers by passing VF number as 0. + * OS/PCI maps them accordingly. + */ + +/* Send a mailbox message to PF + * @vf: vf from which this message to be sent + * @mbx: Message to be sent + */ +void cptvf_send_msg_to_pf(struct cpt_vf *cptvf, cpt_mbox_t *mbx) +{ + /* Writing mbox(1) causes interrupt */ + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VFX_PF_MBOXX(0, 0, 0), mbx->msg); + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VFX_PF_MBOXX(0, 0, 1), mbx->data); +} + +/* Read Interrupt status of the VF + * @vf: vf number + */ +uint64_t cptvf_read_vf_misc_intr_status(struct cpt_vf *cptvf) +{ + return CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), CPTX_VQX_MISC_INT(0, 0)); +} + +/* Clear mailbox interrupt of the VF + * @vf: vf number + */ +void cptvf_clear_mbox_intr(struct cpt_vf *cptvf) +{ + cptx_vqx_misc_int_t vqx_misc_int; + + vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0)); + /* W1C for the VF */ + vqx_misc_int.s.mbox = 1; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u); +} + +/* Clear swerr interrupt of the VF + * @vf: vf number + */ +void cptvf_clear_swerr_intr(struct cpt_vf *cptvf) +{ + cptx_vqx_misc_int_t vqx_misc_int; + + vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0)); + /* W1C for the VF */ + vqx_misc_int.s.swerr = 1; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u); +} + +/* Clear doorbell overflow interrupt of the VF + * @vf: vf number + */ +void cptvf_clear_dovf_intr(struct cpt_vf *cptvf) +{ + cptx_vqx_misc_int_t vqx_misc_int; + + vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0)); + /* W1C for the VF */ + vqx_misc_int.s.dovf = 1; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u); +} + +/* Clear instruction NCB read error interrupt of the VF + * @vf: vf number + */ +void cptvf_clear_irde_intr(struct cpt_vf *cptvf) +{ + cptx_vqx_misc_int_t vqx_misc_int; + + vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0)); + /* W1C for the VF */ + vqx_misc_int.s.irde = 1; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u); +} + +/* Clear NCB result write response error interrupt of the VF + * @vf: vf number + */ +void cptvf_clear_nwrp_intr(struct cpt_vf *cptvf) +{ + cptx_vqx_misc_int_t vqx_misc_int; + + vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0)); + /* W1C for the VF */ + vqx_misc_int.s.nwrp = 1; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u); +} + +/* Clear hwerr interrupt of the VF + * @vf: vf number + */ +void cptvf_clear_hwerr_intr(struct cpt_vf *cptvf) +{ + cptx_vqx_misc_int_t vqx_misc_int; + + vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0)); + /* W1C for the VF */ + vqx_misc_int.s.hwerr = 1; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u); +} + +/* Clear translation fault interrupt of the VF + * @vf: vf number + */ +void cptvf_clear_fault_intr(struct cpt_vf *cptvf) +{ + cptx_vqx_misc_int_t vqx_misc_int; + + vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0)); + /* W1C for the VF */ + vqx_misc_int.s.fault = 1; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u); +} + +/* Write to VQX_CTL register + */ +void cptvf_write_vq_ctl(struct cpt_vf *cptvf, bool val) +{ + cptx_vqx_ctl_t vqx_ctl; + + vqx_ctl.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_CTL(0, 0)); + vqx_ctl.s.ena = val; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_CTL(0, 0), vqx_ctl.u); +} + +/* Write to VQX_INPROG register + */ +void cptvf_write_vq_inprog(struct cpt_vf *cptvf, uint8_t val) +{ + cptx_vqx_inprog_t vqx_inprg; + + vqx_inprg.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_INPROG(0, 0)); + vqx_inprg.s.inflight = val; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_INPROG(0, 0), vqx_inprg.u); +} + +/* Write to VQX_DONE_WAIT NUMWAIT register + */ +void cptvf_write_vq_done_numwait(struct cpt_vf *cptvf, uint32_t val) +{ + cptx_vqx_done_wait_t vqx_dwait; + + vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_DONE_WAIT(0, 0)); + vqx_dwait.s.num_wait = val; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u); +} + +/* Write to VQX_DONE_WAIT NUM_WAIT register + */ +void cptvf_write_vq_done_timewait(struct cpt_vf *cptvf, uint16_t val) +{ + cptx_vqx_done_wait_t vqx_dwait; + + vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_DONE_WAIT(0, 0)); + vqx_dwait.s.time_wait = val; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u); +} + +/* Write to VQX_SADDR register + */ +void cptvf_write_vq_saddr(struct cpt_vf *cptvf, uint64_t val) +{ + cptx_vqx_saddr_t vqx_saddr; + + vqx_saddr.u = val; + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_SADDR(0, 0), vqx_saddr.u); +} diff --git a/drivers/crypto/cpt/base/cpt8xxx_device.h b/drivers/crypto/cpt/base/cpt8xxx_device.h new file mode 100644 index 0000000..b7d7dcd --- /dev/null +++ b/drivers/crypto/cpt/base/cpt8xxx_device.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef __CPT81XX_DEVICE_H +#define __CPT81XX_DEVICE_H + +#include "cpt_device.h" +#include "cpt_vf_mbox.h" +/* + * CPT Registers map for 81xx + */ + +/* VF registers */ +#define CPTX_VQX_CTL(a, b) (0x0000100ll + 0x1000000000ll * \ + ((a) & 0x0) + 0x100000ll * (b)) +#define CPTX_VQX_SADDR(a, b) (0x0000200ll + 0x1000000000ll * \ + ((a) & 0x0) + 0x100000ll * (b)) +#define CPTX_VQX_DONE_WAIT(a, b) (0x0000400ll + 0x1000000000ll * \ + ((a) & 0x0) + 0x100000ll * (b)) +#define CPTX_VQX_INPROG(a, b) (0x0000410ll + 0x1000000000ll * \ + ((a) & 0x0) + 0x100000ll * (b)) +#define CPTX_VQX_DONE(a, b) (0x0000420ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b)) +#define CPTX_VQX_DONE_ACK(a, b) (0x0000440ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b)) +#define CPTX_VQX_DONE_INT_W1S(a, b) (0x0000460ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b)) +#define CPTX_VQX_DONE_INT_W1C(a, b) (0x0000468ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b)) +#define CPTX_VQX_DONE_ENA_W1S(a, b) (0x0000470ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b)) +#define CPTX_VQX_DONE_ENA_W1C(a, b) (0x0000478ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b)) +#define CPTX_VQX_MISC_INT(a, b) (0x0000500ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b)) +#define CPTX_VQX_MISC_INT_W1S(a, b) (0x0000508ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b)) +#define CPTX_VQX_MISC_ENA_W1S(a, b) (0x0000510ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b)) +#define CPTX_VQX_MISC_ENA_W1C(a, b) (0x0000518ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b)) +#define CPTX_VQX_DOORBELL(a, b) (0x0000600ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b)) +#define CPTX_VFX_PF_MBOXX(a, b, c) (0x0001000ll + 0x1000000000ll * \ + ((a) & 0x1) + 0x100000ll * (b) + \ + 8ll * ((c) & 0x1)) +/* VF HAL functions */ +void cptvf_send_msg_to_pf(struct cpt_vf *cptvf, cpt_mbox_t *mbx); +void cptvf_clear_mbox_intr(struct cpt_vf *cptvf); +void cptvf_clear_swerr_intr(struct cpt_vf *cptvf); +void cptvf_clear_dovf_intr(struct cpt_vf *cptvf); +void cptvf_clear_irde_intr(struct cpt_vf *cptvf); +void cptvf_clear_nwrp_intr(struct cpt_vf *cptvf); +void cptvf_clear_fault_intr(struct cpt_vf *cptvf); +void cptvf_clear_hwerr_intr(struct cpt_vf *cptvf); +void cptvf_write_vq_ctl(struct cpt_vf *cptvf, bool val); +void cptvf_write_vq_saddr(struct cpt_vf *cptvf, uint64_t val); +void cptvf_write_vq_done_timewait(struct cpt_vf *cptvf, uint16_t val); +void cptvf_write_vq_done_numwait(struct cpt_vf *cptvf, uint32_t val); +void cptvf_write_vq_inprog(struct cpt_vf *cptvf, uint8_t val); +uint64_t cptvf_read_vf_misc_intr_status(struct cpt_vf *cptvf); + +/* Write to VQX_DOORBELL register + */ +static inline void cptvf_write_vq_doorbell(struct cpt_vf *cptvf, uint32_t val) +{ + cptx_vqx_doorbell_t vqx_dbell; + + vqx_dbell.u = 0; + vqx_dbell.s.dbell_cnt = val * 8; /* Num of Instructions * 8 words */ + CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_DOORBELL(0, 0), vqx_dbell.u); +} + +static inline uint32_t cptvf_read_vq_doorbell(struct cpt_vf *cptvf) +{ + cptx_vqx_doorbell_t vqx_dbell; + + vqx_dbell.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VQX_DOORBELL(0, 0)); + return vqx_dbell.s.dbell_cnt; +} + +#endif /* __CPT81XX_DEVICE_H */ diff --git a/drivers/crypto/cpt/base/cpt_debug.h b/drivers/crypto/cpt/base/cpt_debug.h new file mode 100644 index 0000000..afa05df --- /dev/null +++ b/drivers/crypto/cpt/base/cpt_debug.h @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef __CPT_DEBUG_H +#define __CPT_DEBUG_H +#include +#include +#include "cpt_request_mgr.h" +#include + +#ifdef CPT_DEBUG +static inline void * +os_iova2va(phys_addr_t physaddr) +{ + return rte_mem_iova2virt(physaddr); +} + +static inline void __cpt_dump_buffer(const char *prefix_str, + void *buf, size_t len, int rowsize) +{ + size_t i = 0; + unsigned char *ptr = (unsigned char *)buf; + + PRINT("\n%s[%p]", prefix_str, buf); + PRINT("\n%.8lx: ", i); + + if (buf == NULL) { + PRINT("\n!!!NULL ptr\n"); + abort(); + } + + for (i = 0; i < len; i++) { + if (i && !(i % rowsize)) + PRINT("\n%.8lx: ", i); + PRINT("%02x ", ptr[i]); + } + PRINT("\n\n"); +} + +static inline void cpt_dump_buffer(const char *prefix_str, + void *buf, size_t len) +{ + __cpt_dump_buffer(prefix_str, buf, len, 8); +} + +#define cpt_fn_trace(fmt, ...) \ + do { \ + if (msg_req_trace(debug)) \ + cpt_info(fmt, ##__VA_ARGS__); \ + } while (0) + +static inline void dump_cpt_request_info(struct cpt_request_info *req, + cpt_inst_s_t *inst) +{ + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + uint16_t opcode, param1, param2, dlen; + + vq_cmd_w0.u64 = be64toh(inst->s.ei0); + opcode = be16toh(vq_cmd_w0.s.opcode); + param1 = be16toh(vq_cmd_w0.s.param1); + param2 = be16toh(vq_cmd_w0.s.param2); + dlen = be16toh(vq_cmd_w0.s.dlen); + vq_cmd_w3.u64 = inst->s.ei3; + + PRINT("\ncpt Request Info...\n"); + PRINT("\tdma_mode: %u\n", req->dma_mode); + PRINT("\tis_se : %u\n", req->se_req); + PRINT("\tgrp : 0\n"); + + PRINT("\nRequest Info...\n"); + PRINT("\topcode: 0x%0x\n", opcode); + PRINT("\tparam1: 0x%0x\n", param1); + PRINT("\tparam2: 0x%0x\n", param2); + PRINT("\tdlen: %u\n", dlen); + PRINT("\tctx_handle vaddr %p, dma 0x%lx\n", + os_iova2va((uint64_t)vq_cmd_w3.s.cptr), + (uint64_t)vq_cmd_w3.s.cptr); +} + +static inline void +dump_cpt_request_sglist(cpt_inst_s_t *inst, + const char *header, bool data, + bool glist) +{ + int i; + char suffix[64]; + vq_cmd_word0_t vq_cmd_w0; + uint16_t opcode, dlen; + const char *list = glist ? "glist" : "slist"; + + vq_cmd_w0.u64 = be64toh(inst->s.ei0); + opcode = be16toh(vq_cmd_w0.s.opcode); + dlen = be16toh(vq_cmd_w0.s.dlen); + + if (opcode & DMA_MODE) { + uint8_t *in_buffer = os_iova2va(inst->s.ei1); + uint16_t list_cnt, components; + struct sglist_comp *sg_ptr = NULL; + struct { + void *vaddr; + phys_addr_t dma_addr; + uint32_t size; + } list_ptr[MAX_SG_CNT]; + + PRINT("%s: DMA Mode\n", header); + snprintf(suffix, sizeof(suffix), + "DPTR: vaddr %p, dma 0x%lx len %u: ", + in_buffer, inst->s.ei1, dlen); + + cpt_dump_buffer(suffix, + in_buffer, + dlen); + + sg_ptr = (void *)(in_buffer + 8); + list_cnt = be16toh((((uint16_t *)in_buffer)[2])); + if (!glist) { + components = list_cnt / 4; + if (list_cnt % 4) + components++; + sg_ptr += components; + list_cnt = be16toh((((uint16_t *)in_buffer)[3])); + } + PRINT("current %s: %u\n", list, list_cnt); + if (!(list_cnt <= MAX_SG_CNT)) + abort(); + + components = list_cnt / 4; + + for (i = 0; i < components; i++) { + list_ptr[i*4+0].size = be16toh(sg_ptr->u.s.len[0]); + list_ptr[i*4+1].size = be16toh(sg_ptr->u.s.len[1]); + list_ptr[i*4+2].size = be16toh(sg_ptr->u.s.len[2]); + list_ptr[i*4+3].size = be16toh(sg_ptr->u.s.len[3]); + list_ptr[i*4+0].dma_addr = be64toh(sg_ptr->ptr[0]); + list_ptr[i*4+1].dma_addr = be64toh(sg_ptr->ptr[1]); + list_ptr[i*4+2].dma_addr = be64toh(sg_ptr->ptr[2]); + list_ptr[i*4+3].dma_addr = be64toh(sg_ptr->ptr[3]); + + list_ptr[i*4+0].vaddr = + os_iova2va(list_ptr[i*4+0].dma_addr); + list_ptr[i*4+1].vaddr = + os_iova2va(list_ptr[i*4+1].dma_addr); + list_ptr[i*4+2].vaddr = + os_iova2va(list_ptr[i*4+2].dma_addr); + list_ptr[i*4+3].vaddr = + os_iova2va(list_ptr[i*4+3].dma_addr); + sg_ptr++; + } + components = list_cnt % 4; + + switch (components) { + case 3: + list_ptr[i*4+2].size = be16toh(sg_ptr->u.s.len[2]); + list_ptr[i*4+2].dma_addr = be64toh(sg_ptr->ptr[2]); + list_ptr[i*4+2].vaddr = + os_iova2va(list_ptr[i*4+2].dma_addr); + /* fall through */ + case 2: + list_ptr[i*4+1].size = be16toh(sg_ptr->u.s.len[1]); + list_ptr[i*4+1].dma_addr = be64toh(sg_ptr->ptr[1]); + list_ptr[i*4+1].vaddr = + os_iova2va(list_ptr[i*4+1].dma_addr); + /* fall through */ + case 1: + list_ptr[i*4+0].size = be16toh(sg_ptr->u.s.len[0]); + list_ptr[i*4+0].dma_addr = be64toh(sg_ptr->ptr[0]); + list_ptr[i*4+0].vaddr = + os_iova2va(list_ptr[i*4+0].dma_addr); + break; + default: + break; + } + + for (i = 0; i < list_cnt; i++) { + snprintf(suffix, sizeof(suffix), + "%s[%d]: vaddr %p, dma 0x%lx len %u: ", + list, i, list_ptr[i].vaddr, + list_ptr[i].dma_addr, + list_ptr[i].size); + if (data) + cpt_dump_buffer(suffix, + list_ptr[i].vaddr, + list_ptr[i].size); + else + PRINT("%s\n", suffix); + } + } else { + PRINT("%s: Direct Mode\n", header); + + if (glist) { + snprintf(suffix, sizeof(suffix), + "DPTR: vaddr %p, dma 0x%lx len %u: ", + os_iova2va(inst->s.ei1), + inst->s.ei1, dlen); + if (data) + cpt_dump_buffer(suffix, + os_iova2va(inst->s.ei1), + dlen); + else + PRINT("%s\n", suffix); + } else { + snprintf(suffix, sizeof(suffix), + "RPTR: vaddr %p, dma 0x%lx len %u+..: ", + os_iova2va(inst->s.ei2), + inst->s.ei2, dlen); + /* + * In direct mode, we don't have rlen + * to dump exactly, so dump dlen + 32 + */ + if (data) + cpt_dump_buffer(suffix, + os_iova2va(inst->s.ei2), + dlen + 32); + else + PRINT("%s\n", suffix); + } + } +} + + +#else + +#define cpt_dump_buffer(__str, __buf, __len) +#define cpt_fn_trace(fmt, ...) +#define dump_cpt_request_info(req, ist) +#define dump_cpt_request_sglist(ist, header, data, flag) +#endif /* CPT_DEBUG */ + +#endif /* __CPT_DEBUG_H */ diff --git a/drivers/crypto/cpt/base/cpt_device.c b/drivers/crypto/cpt/base/cpt_device.c new file mode 100644 index 0000000..b7cd5b5 --- /dev/null +++ b/drivers/crypto/cpt/base/cpt_device.c @@ -0,0 +1,383 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#include "cpt_device.h" +#include "cpt_debug.h" +#include "cpt8xxx_device.h" +#include "cpt_vf_mbox.h" +#include "cpt_request_mgr.h" + +#include + +static void cptvf_vfvq_init(struct cpt_vf *cptvf) +{ + uint64_t base_addr = 0; + + /* Disable the VQ */ + cptvf_write_vq_ctl(cptvf, 0); + + /* Reset the doorbell */ + cptvf_write_vq_doorbell(cptvf, 0); + /* Clear inflight */ + cptvf_write_vq_inprog(cptvf, 0); + + /* Write VQ SADDR */ + base_addr = (uint64_t)(cptvf->cqueue.chead[0].dma_addr); + cptvf_write_vq_saddr(cptvf, base_addr); + + /* Configure timerhold / coalescence */ + cptvf_write_vq_done_timewait(cptvf, CPT_TIMER_THOLD); + cptvf_write_vq_done_numwait(cptvf, CPT_COUNT_THOLD); + + /* Enable the VQ */ + cptvf_write_vq_ctl(cptvf, 1); + + /* Flag the VF ready */ + cptvf->flags |= CPT_FLAG_DEVICE_READY; +} + +static int cpt_vf_init(struct cpt_vf *cptvf) +{ + int err = -1; + + /* Mark as VF driver */ + cptvf->flags |= CPT_FLAG_VF_DRIVER; + + /* Check ready with PF */ + /* Gets chip ID / device Id from PF if ready */ + err = cptvf_check_pf_ready(cptvf); + if (err) { + PMD_DRV_LOG(ERR, "%s: PF not responding to READY msg\n", + cptvf->dev_name); + err = -EBUSY; + goto cptvf_err; + } + + PMD_DRV_LOG(DEBUG, "%s: cpt_vf_init() done\n", cptvf->dev_name); + return 0; + +cptvf_err: + return err; +} + +static int cpt_vq_init(struct cpt_vf *cptvf, uint8_t group) +{ + int err; + + /* Convey VQ LEN to PF */ + err = cptvf_send_vq_size_msg(cptvf); + if (err) { + PMD_DRV_LOG(ERR, "%s: PF not responding to QLEN msg\n", + cptvf->dev_name); + err = -EBUSY; + goto cleanup; + } + + /* CPT VF device initialization */ + cptvf_vfvq_init(cptvf); + + /* Send msg to PF to assign currnet Q to required group */ + cptvf->vfgrp = group; + err = cptvf_send_vf_to_grp_msg(cptvf, group); + if (err) { + PMD_DRV_LOG(ERR, "%s: PF not responding to VF_GRP msg\n", + cptvf->dev_name); + err = -EBUSY; + goto cleanup; + } + + PMD_DRV_LOG(DEBUG, "%s: cpt_vq_init() done\n", cptvf->dev_name); + return 0; + +cleanup: + return err; +} + +void cptvf_poll_misc(void *dev) +{ + uint64_t intr; + struct cpt_vf *cptvf = dev; + + intr = cptvf_read_vf_misc_intr_status(cptvf); + + if (!intr) + return; + + /*Check for MISC interrupt types*/ + if (likely(intr & CPT_VF_INTR_MBOX_MASK)) { + PMD_DRV_LOG(DEBUG, "%s: Mailbox interrupt 0x%lx on CPT VF %d\n", + cptvf->dev_name, intr, cptvf->vfid); + cptvf_handle_mbox_intr(cptvf); + cptvf_clear_mbox_intr(cptvf); + } else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) { + cptvf_clear_irde_intr(cptvf); + PMD_DRV_LOG(DEBUG, "%s: Instruction NCB read error interrupt" + " 0x%lx on CPT VF %d\n", cptvf->dev_name, intr, + cptvf->vfid); + } else if (unlikely(intr & CPT_VF_INTR_NWRP_MASK)) { + cptvf_clear_nwrp_intr(cptvf); + PMD_DRV_LOG(DEBUG, "%s: NCB response write error interrupt" + " 0x%lx on CPT VF %d\n", cptvf->dev_name, intr, cptvf->vfid); + } else if (unlikely(intr & CPT_VF_INTR_SWERR_MASK)) { + cptvf_clear_swerr_intr(cptvf); + PMD_DRV_LOG(DEBUG, "%s: Software error interrupt 0x%lx on" + " CPT VF %d\n", cptvf->dev_name, intr, cptvf->vfid); + } else if (unlikely(intr & CPT_VF_INTR_HWERR_MASK)) { + cptvf_clear_hwerr_intr(cptvf); + PMD_DRV_LOG(DEBUG, "%s: Hardware error interrupt 0x%lx on" + " CPT VF %d\n", cptvf->dev_name, intr, cptvf->vfid); + } else if (unlikely(intr & CPT_VF_INTR_FAULT_MASK)) { + cptvf_clear_fault_intr(cptvf); + PMD_DRV_LOG(DEBUG, "%s: Translation fault interrupt 0x%lx on" + " CPT VF %d\n", cptvf->dev_name, intr, cptvf->vfid); + } else + PMD_DRV_LOG(ERR, "%s: Unhandled interrupt 0x%lx in CPT VF %d\n", + cptvf->dev_name, intr, cptvf->vfid); +} + +int cptvf_deinit_device(struct cpt_vf *dev) +{ + struct cpt_vf *cptvf = (struct cpt_vf *)dev; + + /* Do misc work one last time */ + cptvf_poll_misc(cptvf); + + /* TODO anything else ?? */ + + return 0; +} + +int cptvf_init_device(struct cpt_vf *cptvf, + void *pdev, + void *reg_base, + char *name, + uint32_t flags) +{ + (void) flags; + + memset(cptvf, 0, sizeof(struct cpt_vf)); + + /* Bar0 base address */ + cptvf->reg_base = reg_base; + strncpy(cptvf->dev_name, name, 32); + + cptvf->nr_queues = 1; + cptvf->max_queues = 1; + cptvf->pdev = pdev; + + /* To clear if there are any pending mbox msgs */ + cptvf_poll_misc(cptvf); + + if (cpt_vf_init(cptvf)) { + PMD_DRV_LOG(ERR, "Failed to initialize CPT VF device\n"); + return -1; + } + + return 0; +} + + +int cptvf_get_resource(struct cpt_vf *dev, + uint8_t group, cpt_instance_t **instance) +{ + int ret = -ENOENT, len, qlen, i; + int chunk_len, chunks, chunk_size; + struct cpt_vf *cptvf = dev; + cpt_instance_t *cpt_instance; + struct command_chunk *chunk_head = NULL, *chunk_prev = NULL; + struct command_chunk *chunk = NULL; + uint8_t *mem; + const struct rte_memzone *rz; + uint64_t dma_addr = 0, alloc_len, used_len; + uint64_t *next_ptr; + uint64_t pg_sz = sysconf(_SC_PAGESIZE); + + PMD_DRV_LOG(DEBUG, "Initializing csp resource %s\n", cptvf->dev_name); + + cpt_instance = &cptvf->instance; + + memset(&cptvf->cqueue, 0, sizeof(cptvf->cqueue)); + memset(&cptvf->pqueue, 0, sizeof(cptvf->pqueue)); + + /* Chunks are of fixed size buffers */ + chunks = DEFAULT_CMD_QCHUNKS; + chunk_len = DEFAULT_CMD_QCHUNK_SIZE; + + qlen = chunks * chunk_len; + /* Chunk size includes 8 bytes of next chunk ptr */ + chunk_size = chunk_len * CPT_INST_SIZE + CPT_NEXT_CHUNK_PTR_SIZE; + + /* For command chunk structures */ + len = chunks * RTE_ALIGN(sizeof(struct command_chunk), 8); + + /* For pending queue */ + len += qlen * RTE_ALIGN(sizeof(rid_t), 8); + + /* So that instruction queues start as pg size aligned */ + len = RTE_ALIGN(len, pg_sz); + + /* For Instruction queues */ + len += chunks * RTE_ALIGN(chunk_size, 128); + + /* Wastage after instruction queues */ + len = RTE_ALIGN(len, pg_sz); + + rz = rte_memzone_reserve_aligned(cptvf->dev_name, len, cptvf->node, + RTE_MEMZONE_SIZE_HINT_ONLY | + RTE_MEMZONE_256MB, + RTE_CACHE_LINE_SIZE); + if (!rz) { + ret = rte_errno; + goto cleanup; + } + + mem = rz->addr; + dma_addr = rz->phys_addr; + alloc_len = len; + + memset(mem, 0, len); + + cpt_instance->rsvd = (uint64_t)rz; + + /* Pending queue setup */ + cptvf->pqueue.rid_queue = (rid_t *)mem; + cptvf->pqueue.soft_qlen = qlen; + cptvf->pqueue.enq_tail = 0; + cptvf->pqueue.deq_head = 0; + cptvf->pqueue.pending_count = 0; + + mem += qlen * RTE_ALIGN(sizeof(rid_t), 8); + len -= qlen * RTE_ALIGN(sizeof(rid_t), 8); + dma_addr += qlen * RTE_ALIGN(sizeof(rid_t), 8); + + /* Alignement wastage */ + used_len = alloc_len - len; + mem += RTE_ALIGN(used_len, pg_sz) - used_len; + len -= RTE_ALIGN(used_len, pg_sz) - used_len; + dma_addr += RTE_ALIGN(used_len, pg_sz) - used_len; + + /* Init instruction queues */ + chunk_head = &cptvf->cqueue.chead[0]; + i = qlen; + + chunk_prev = NULL; + for (i = 0; i < DEFAULT_CMD_QCHUNKS; i++) { + int csize; + + chunk = &cptvf->cqueue.chead[i]; + chunk->head = mem; + chunk->dma_addr = dma_addr; + + csize = RTE_ALIGN(chunk_size, 128); + mem += csize; + dma_addr += csize; + len -= csize; + + if (chunk_prev) { + next_ptr = (uint64_t *)(chunk_prev->head + + chunk_size - 8); + *next_ptr = (uint64_t)chunk->dma_addr; + } + chunk_prev = chunk; + } + /* Circular loop */ + next_ptr = (uint64_t *)(chunk_prev->head + chunk_size - 8); + *next_ptr = (uint64_t)chunk_head->dma_addr; + + assert(!len); + + cptvf->qlen = qlen; + /* This is used for CPT(0)_PF_Q(0..15)_CTL.size config */ + cptvf->qsize = chunk_size / 8; + cptvf->cqueue.qhead = chunk_head->head; + cptvf->cqueue.idx = 0; + cptvf->cqueue.cchunk = 0; + + if (cpt_vq_init(cptvf, group)) { + PMD_DRV_LOG(ERR, "Failed to initialize CPT VQ of device %s\n", + cptvf->dev_name); + ret = -EBUSY; + goto cleanup; + } + + *instance = cpt_instance; + + PMD_DRV_LOG(DEBUG, "Crypto device (%s) initialized\n", + cptvf->dev_name); + + return 0; +cleanup: + rte_memzone_free(rz); + *instance = NULL; + return ret; +} + +int cptvf_put_resource(cpt_instance_t *instance) +{ + struct cpt_vf *cptvf = (struct cpt_vf *)instance; + struct rte_memzone *rz; + + if (!cptvf) { + PMD_DRV_LOG(ERR, "Invalid CPTVF handle\n"); + return -EINVAL; + } + + PMD_DRV_LOG(DEBUG, "Releasing csp device %s\n", cptvf->dev_name); + + rz = (struct rte_memzone *)instance->rsvd; + rte_memzone_free(rz); + return 0; +} + +int cptvf_start_device(struct cpt_vf *cptvf) +{ + int rc; + + rc = cptvf_send_vf_up(cptvf); + if (rc) { + PMD_DRV_LOG(ERR, "Failed to mark CPT VF device %s UP, rc = %d\n" + , cptvf->dev_name, rc); + return -EFAULT; + } + + if ((cptvf->vftype != SE_TYPE) && + (cptvf->vftype != AE_TYPE)) { + PMD_DRV_LOG(ERR, "Fatal error, unexpected vf type %u, for CPT" + " VF device %s\n", cptvf->vftype, cptvf->dev_name); + return -ENOENT; + } + + return 0; +} + +void cptvf_stop_device(struct cpt_vf *cptvf) +{ + int rc; + uint32_t pending, retries = 5; + + /* Wait for pending entries to complete */ + pending = cptvf_read_vq_doorbell(cptvf); + while (pending) { + PRINT("%s: Waiting for pending %u cmds to complete\n", + cptvf->dev_name, pending); + sleep(1); + pending = cptvf_read_vq_doorbell(cptvf); + retries--; + if (!retries) + break; + } + + if (!retries && pending) { + PMD_DRV_LOG(ERR, "%s: Timeout waiting for commands(%u)\n", + cptvf->dev_name, pending); + return; + } + + rc = cptvf_send_vf_down(cptvf); + if (rc) { + PMD_DRV_LOG(ERR, "Failed to bring down vf %s, rc %d\n", + cptvf->dev_name, rc); + return; + } +} diff --git a/drivers/crypto/cpt/base/cpt_device.h b/drivers/crypto/cpt/base/cpt_device.h new file mode 100644 index 0000000..951c7ae --- /dev/null +++ b/drivers/crypto/cpt/base/cpt_device.h @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef __CPT_DEVICE_H +#define __CPT_DEVICE_H + +#include "cpt.h" +#include "cpt_hw_types.h" +#include +#include +#include +#include + +/* Device ID */ +#define PCI_VENDOR_ID_CAVIUM 0x177d +#define CPT_81XX_PCI_VF_DEVICE_ID 0xa041 + +#define CPT_NUM_QS_PER_VF (1) + +#define CPT_MBOX_MSG_TIMEOUT 2000 /* In Milli Seconds */ + +/**< flags to indicate the features supported */ +#define CPT_FLAG_VF_DRIVER (uint16_t)(1 << 3) +#define CPT_FLAG_DEVICE_READY (uint16_t)(1 << 4) + +#ifndef ROUNDUP4 +#define ROUNDUP4(val) (((val) + 3) & 0xfffffffc) +#endif + +#ifndef ROUNDUP8 +#define ROUNDUP8(val) (((val) + 7) & 0xfffffff8) +#endif + +#ifndef ROUNDUP16 +#define ROUNDUP16(val) (((val) + 15) & 0xfffffff0) +#endif + +/* Default command queue length */ +#define DEFAULT_CMD_QCHUNKS 2 +#define DEFAULT_CMD_QCHUNK_SIZE 1023 +#define DEFAULT_CMD_QLEN (DEFAULT_CMD_QCHUNK_SIZE * DEFAULT_CMD_QCHUNKS) + +/* Default command timeout in seconds */ +#define DEFAULT_COMMAND_TIMEOUT 4 + +#define CPT_COUNT_THOLD 32 +#define CPT_TIMER_THOLD 0x3F + + +#define AE_TYPE 1 +#define SE_TYPE 2 + +typedef enum { + CPT_81XX = 1, + CPT_AE_83XX, + CPT_SE_83XX, + INVALID_CPT +} cpt_pf_type_t; + +typedef struct rid { + uint64_t rid; /* Request id of a crypto operation */ +/* void *op; */ /* Opaque operation handle returned */ +} rid_t; /* Array of pending request's */ + +typedef struct pending_queue { + uint16_t enq_tail; + uint16_t deq_head; + uint16_t soft_qlen; /* Software expected queue length */ + uint16_t p_doorbell; + rid_t *rid_queue; /* Array of pending request's */ + uint64_t pending_count; /* Pending requests count */ +} pending_queue_t; + +struct command_chunk { + uint8_t *head; /**< 128-byte aligned real_vaddr */ + phys_addr_t dma_addr; /**< 128-byte aligned real_dma_addr */ +}; + +/** + * comamnd queue structure + */ +struct command_queue { + uint32_t idx; + /**< Command queue host write idx */ + uint32_t cchunk; + uint8_t *qhead; + /**< Command queue head, instructions are inserted here */ + struct command_chunk chead[DEFAULT_CMD_QCHUNKS]; + /**< Command chunk list head */ +}; + +/** + * CPT VF device structure + */ +struct cpt_vf { + cpt_instance_t instance; + + /* base address where BAR is mapped */ + uint8_t *reg_base; /**< Register start address */ + + /* Command and Pending queues */ + struct command_queue cqueue;/**< Command queue information */ + struct pending_queue pqueue;/**< Pending queue information */ + + /* Below fields are accessed only in control path */ + + /* + * This points to environment specific pdev that + * represents the pci dev + */ + void *pdev; + uint32_t qlen; + /* + * Qsize * CPT_INST_SIZE + + * alignment size(CPT_INST_SIZE + + * next chunk pointer size (8) + */ + uint32_t qsize; + /**< Calculated queue size */ + uint32_t nr_queues; + uint32_t max_queues; + + uint32_t chip_id; + /**< CPT Device ID */ + uint16_t flags; + /**< Flags to hold device status bits */ + uint8_t vfid; + /**< Device Index (0...CPT_MAX_VQ_NUM */ + uint8_t vftype; + /**< VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */ + uint8_t vfgrp; + /**< VF group (0 - 8) */ + uint8_t node; + /**< Operating node: Bits (46:44) in BAR0 address */ + + /* VF-PF mailbox communication */ + bool pf_acked; + bool pf_nacked; + char dev_name[32]; +} ____cacheline_aligned_in_smp; + +#define CPT_CSR_REG_BASE(cpt) ((cpt)->reg_base) + +#define CPT_READ_CSR(__hw_addr, __offset) \ + rte_read64_relaxed((uint8_t *)__hw_addr + __offset) +#define CPT_WRITE_CSR(__hw_addr, __offset, __val) \ + rte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset)) + +void cptvf_poll_misc(void *dev); +int cptvf_deinit_device(struct cpt_vf *dev); +int cptvf_init_device(struct cpt_vf *cptvf, + void *pdev, + void *reg_base, + char *name, + uint32_t flags); +int cptvf_get_resource(struct cpt_vf *dev, + uint8_t group, cpt_instance_t **instance); +int cptvf_put_resource(cpt_instance_t *instance); +int cptvf_start_device(struct cpt_vf *cptvf); +void cptvf_stop_device(struct cpt_vf *cptvf); +#endif /* __CPT_DEVICE_H */ diff --git a/drivers/crypto/cpt/base/cpt_vf_mbox.c b/drivers/crypto/cpt/base/cpt_vf_mbox.c new file mode 100644 index 0000000..00d98bb --- /dev/null +++ b/drivers/crypto/cpt/base/cpt_vf_mbox.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#include "cpt8xxx_device.h" +#include "cpt_vf_mbox.h" +#include + +/* Poll handler to handle mailbox messages from VFs */ +void cptvf_handle_mbox_intr(struct cpt_vf *cptvf) +{ + cpt_mbox_t mbx = {0, 0}; + + /* + * MBOX[0] contains msg + * MBOX[1] contains data + */ + mbx.msg = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VFX_PF_MBOXX(0, 0, 0)); + mbx.data = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), + CPTX_VFX_PF_MBOXX(0, 0, 1)); + + PMD_DRV_LOG(DEBUG, "%s: Mailbox msg 0x%lx from PF\n", + cptvf->dev_name, mbx.msg); + switch (mbx.msg) { + case CPT_MSG_READY: + { + cpt_chipid_vfid_t cid; + + cid.u64 = mbx.data; + cptvf->pf_acked = true; + cptvf->vfid = cid.s.vfid; + cptvf->chip_id = cid.s.chip_id; + PMD_DRV_LOG(DEBUG, "%s: Received VFID %d chip_id %d\n", + cptvf->dev_name, + cptvf->vfid, cid.s.chip_id); + } + break; + case CPT_MSG_QBIND_GRP: + cptvf->pf_acked = true; + cptvf->vftype = mbx.data; + PMD_DRV_LOG(DEBUG, "%s: VF %d type %s group %d\n", + cptvf->dev_name, cptvf->vfid, + ((mbx.data == SE_TYPE) ? "SE" : "AE"), + cptvf->vfgrp); + break; + case CPT_MBOX_MSG_TYPE_ACK: + cptvf->pf_acked = true; + break; + case CPT_MBOX_MSG_TYPE_NACK: + cptvf->pf_nacked = true; + break; + default: + PMD_DRV_LOG(DEBUG, "%s: Invalid msg from PF, msg 0x%lx\n", + cptvf->dev_name, mbx.msg); + break; + } +} + +static int32_t +cptvf_send_msg_to_pf_timeout(struct cpt_vf *cptvf, cpt_mbox_t *mbx) +{ + int timeout = CPT_MBOX_MSG_TIMEOUT; + int sleep_ms = 10; + + cptvf->pf_acked = false; + cptvf->pf_nacked = false; + + cptvf_send_msg_to_pf(cptvf, mbx); + + /* Wait for previous message to be acked, timeout 2sec */ + while (!cptvf->pf_acked) { + if (cptvf->pf_nacked) + return -EINVAL; + usleep(sleep_ms * 1000); + cptvf_poll_misc(cptvf); + if (cptvf->pf_acked) + break; + timeout -= sleep_ms; + if (!timeout) { + PMD_DRV_LOG(ERR, "%s: PF didn't ack mbox msg %lx(vfid " + "%u)\n", + cptvf->dev_name, + (mbx->msg & 0xFF), cptvf->vfid); + return -EBUSY; + } + } + return 0; +} + +/* + * Checks if VF is able to comminicate with PF + * and also gets the CPT number this VF is associated to. + */ +int cptvf_check_pf_ready(struct cpt_vf *cptvf) +{ + cpt_mbox_t mbx = {0, 0}; + + mbx.msg = CPT_MSG_READY; + if (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) { + PMD_DRV_LOG(ERR, "%s: PF didn't respond to READY msg\n", + cptvf->dev_name); + return 1; + } + return 0; +} + +/* + * Communicate VQs size to PF to program CPT(0)_PF_Q(0-15)_CTL of the VF. + * Must be ACKed. + */ +int cptvf_send_vq_size_msg(struct cpt_vf *cptvf) +{ + cpt_mbox_t mbx = {0, 0}; + + mbx.msg = CPT_MSG_QLEN; + + mbx.data = cptvf->qsize; + if (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) { + PMD_DRV_LOG(ERR, "%s: PF didn't respond to vq_size msg\n", + cptvf->dev_name); + return 1; + } + return 0; +} + +/* + * Communicate VF group required to PF and get the VQ binded to that group + */ +int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf, uint32_t group) +{ + cpt_mbox_t mbx = {0, 0}; + + mbx.msg = CPT_MSG_QBIND_GRP; + + /* Convey group of the VF */ + mbx.data = group; + if (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) { + PMD_DRV_LOG(ERR, "%s: PF didn't respond to vf_type msg\n", + cptvf->dev_name); + return 1; + } + return 0; +} + +/* + * Communicate to PF that VF is UP and running + */ +int cptvf_send_vf_up(struct cpt_vf *cptvf) +{ + cpt_mbox_t mbx = {0, 0}; + + mbx.msg = CPT_MSG_VF_UP; + if (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) { + PMD_DRV_LOG(ERR, "%s: PF didn't respond to UP msg\n", + cptvf->dev_name); + return 1; + } + return 0; +} + +/* + * Communicate to PF that VF is DOWN and running + */ +int cptvf_send_vf_down(struct cpt_vf *cptvf) +{ + cpt_mbox_t mbx = {0, 0}; + + mbx.msg = CPT_MSG_VF_DOWN; + if (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) { + PMD_DRV_LOG(ERR, "%s: PF didn't respond to DOWN msg\n", + cptvf->dev_name); + return 1; + } + return 0; +} diff --git a/drivers/crypto/cpt/base/cpt_vf_mbox.h b/drivers/crypto/cpt/base/cpt_vf_mbox.h new file mode 100644 index 0000000..8e7a05f --- /dev/null +++ b/drivers/crypto/cpt/base/cpt_vf_mbox.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef __CPTVF_MBOX_H +#define __CPTVF_MBOX_H + +#include "cpt.h" +#include "cpt_device.h" + +#define CPT_MBOX_MSG_TYPE_REQ 0 +#define CPT_MBOX_MSG_TYPE_ACK 1 +#define CPT_MBOX_MSG_TYPE_NACK 2 +#define CPT_MBOX_MSG_TYPE_NOP 3 + +typedef enum { + CPT_MSG_VF_UP = 1, + CPT_MSG_VF_DOWN, + CPT_MSG_READY, + CPT_MSG_QLEN, + CPT_MSG_QBIND_GRP, + CPT_MSG_VQ_PRIORITY, + CPT_MSG_PF_TYPE, +} cpt_mbox_opcode_t; + +/* CPT mailbox structure */ +typedef struct { + uint64_t msg; /* Message type MBOX[0] */ + uint64_t data;/* Data MBOX[1] */ +} cpt_mbox_t; + +typedef union { + uint64_t u64; + struct { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + uint32_t chip_id; + uint8_t vfid; + uint8_t reserved[3]; +#else + uint8_t reserved[3]; + uint8_t vfid; + uint32_t chip_id; +#endif + } s; +} cpt_chipid_vfid_t; + + +void cptvf_mbox_send_ack(struct cpt_vf *cptvf, cpt_mbox_t *mbx); +void cptvf_mbox_send_nack(struct cpt_vf *cptvf, cpt_mbox_t *mbx); +int cptvf_check_pf_ready(struct cpt_vf *cptvf); +int cptvf_send_vq_size_msg(struct cpt_vf *cptvf); +int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf, uint32_t group); +int cptvf_send_vf_priority_msg(struct cpt_vf *cptvf, uint32_t priority); +int cptvf_send_vf_down(struct cpt_vf *cptvf); +int cptvf_send_vf_up(struct cpt_vf *cptvf); +void cptvf_handle_mbox_intr(struct cpt_vf *cptvf); +/* Synchronous raw operation to get vf cfg */ +int cptvf_get_pf_type_raw(char *dev_name, void *reg_base, + cpt_pf_type_t *pf_type); +#endif /* __CPTVF_MBOX_H */ From patchwork Fri Jun 8 16:45:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 40865 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0E8641BB0F; Fri, 8 Jun 2018 18:49:00 +0200 (CEST) Received: from NAM04-SN1-obe.outbound.protection.outlook.com (mail-eopbgr700086.outbound.protection.outlook.com [40.107.70.86]) by dpdk.org (Postfix) with ESMTP id 73DC51BA9A for ; Fri, 8 Jun 2018 18:48:58 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h3U64+nfhDzEAitmABYPlzXMXkJ5u03IoChIh2ut9f0=; b=hXZOlaw3/+/0Slv0mkstqwlMNQvS/RBuqnA1QinAXKBdtSaXqr51TbZAE7jPsvO/EQyakpmrg52idMpD7qKBgOBH8bV3bEB+h0cj0VUHgvuED22yvEJKRi8xBoBbb2bSsF9DsKBHB2sRTQXC6x1CGfVIHHGJl47b2CvfaaJ8GFg= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Anoob.Joseph@cavium.com; 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Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/base/cpt.h | 102 +++++++ drivers/crypto/cpt/base/cpt_device.c | 4 +- drivers/crypto/cpt/base/cpt_request_mgr.c | 424 ++++++++++++++++++++++++++++++ drivers/crypto/cpt/base/cpt_request_mgr.h | 75 ++++++ 4 files changed, 603 insertions(+), 2 deletions(-) create mode 100644 drivers/crypto/cpt/base/cpt.h create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.c create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.h diff --git a/drivers/crypto/cpt/base/cpt.h b/drivers/crypto/cpt/base/cpt.h new file mode 100644 index 0000000..11407ae --- /dev/null +++ b/drivers/crypto/cpt/base/cpt.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef __BASE_CPT_H__ +#define __BASE_CPT_H__ + +/* Linux Includes */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* DPDK includes */ +#include +#include +#include +#include +#include + +#include "../cpt_pmd_logs.h" +#include "mcode_defines.h" + +/** @cond __INTERNAL_DOCUMENTATION__ */ + +/* Declarations */ +typedef struct cpt_instance cpt_instance_t; + +/* + * Generic Defines + */ + +/* Buffer pointer */ +typedef struct buf_ptr { + void *vaddr; + phys_addr_t dma_addr; + uint32_t size; + uint32_t resv; +} buf_ptr_t; + +/* IOV Pointer */ +typedef struct{ + int buf_cnt; + buf_ptr_t bufs[0]; +} iov_ptr_t; + +typedef struct app_data { + uint64_t pktout; + void *marker; +} app_data_t; + +/* Instance operations */ + +/* Enqueue an SE/AE request */ +int cpt_enqueue_req(cpt_instance_t *inst, void *req, uint8_t flags, + void *event, uint64_t event_flags); + +/* Dequeue completed SE requests as burst */ +int32_t cpt_dequeue_burst(cpt_instance_t *instance, uint16_t cnt, + void *resp[], uint8_t cc[]); + +/* Marks event as done in event driven mode */ +int32_t cpt_event_mark_done(void *marker, uint8_t *op_error); + +/* Checks queue full condition */ +uint16_t cpt_queue_full(cpt_instance_t *instance); + +/* Misc */ +uint32_t cpt_get_instance_count(void); + +#define ENQ_FLAG_SYNC 0x01 +#define ENQ_FLAG_EVENT 0x02 +#define ENQ_FLAG_NODOORBELL 0x04 +#define ENQ_FLAG_ONLY_DOORBELL 0x08 + + +#define OCTTX_EVENT_TAG(__flags) (__flags & 0xffffffff) +#define OCTTX_EVENT_GRP(__flags) ((__flags >> 32) & 0xffff) +#define OCTTX_EVENT_TT(__flags) ((__flags >> 48) & 0xff) + +#define OCTTX_EVENT_FLAGS(__tag, __grp, __tt) \ + (((uint64_t)__tag & 0xffffffff) | \ + (((uint64_t)__grp & 0xffff) << 32) | \ + (((uint64_t)__tt & 0xff) << 48)) + + +/* cpt instance */ +struct cpt_instance { + /* 0th cache line */ + uint32_t queue_id; + uint64_t rsvd; +}; + +#define __hot __attribute__((hot)) +/** @endcond */ + +#endif /* __BASE_CPT_H__ */ diff --git a/drivers/crypto/cpt/base/cpt_device.c b/drivers/crypto/cpt/base/cpt_device.c index b7cd5b5..a50e5b8 100644 --- a/drivers/crypto/cpt/base/cpt_device.c +++ b/drivers/crypto/cpt/base/cpt_device.c @@ -193,7 +193,7 @@ int cptvf_get_resource(struct cpt_vf *dev, uint64_t *next_ptr; uint64_t pg_sz = sysconf(_SC_PAGESIZE); - PMD_DRV_LOG(DEBUG, "Initializing csp resource %s\n", cptvf->dev_name); + PMD_DRV_LOG(DEBUG, "Initializing cpt resource %s\n", cptvf->dev_name); cpt_instance = &cptvf->instance; @@ -323,7 +323,7 @@ int cptvf_put_resource(cpt_instance_t *instance) return -EINVAL; } - PMD_DRV_LOG(DEBUG, "Releasing csp device %s\n", cptvf->dev_name); + PMD_DRV_LOG(DEBUG, "Releasing cpt device %s\n", cptvf->dev_name); rz = (struct rte_memzone *)instance->rsvd; rte_memzone_free(rz); diff --git a/drivers/crypto/cpt/base/cpt_request_mgr.c b/drivers/crypto/cpt/base/cpt_request_mgr.c new file mode 100644 index 0000000..8b9b1ff --- /dev/null +++ b/drivers/crypto/cpt/base/cpt_request_mgr.c @@ -0,0 +1,424 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#include "cpt_request_mgr.h" +#include "cpt_debug.h" +#include + +#define MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++) + +#define __hot __attribute__((hot)) + +static inline uint64_t cpu_cycles(void) +{ + return rte_get_timer_cycles(); +} + +static inline uint64_t cpu_cycles_freq(void) +{ + return rte_get_timer_hz(); +} + +static inline void * +get_cpt_inst(struct command_queue *cqueue, void *req) +{ + (void)req; + PMD_TX_LOG(DEBUG, "CPT queue idx %u, req %p\n", cqueue->idx, req); + return &cqueue->qhead[cqueue->idx * CPT_INST_SIZE]; +} + +static inline void +mark_cpt_inst(struct cpt_vf *cptvf, + struct command_queue *queue, + uint32_t ring_door_bell) +{ +#ifdef CMD_DEBUG + /* DEBUG */ + { + uint32_t i = queue->idx * CPT_INST_SIZE; + cpt_inst_s_t *cmd = (void *)&queue->qhead[i]; + uint64_t *p = (void *)&queue->qhead[i]; + + PRINT("\nQUEUE parameters:"); + PRINT("Queue index = %u\n", + queue->idx); + PRINT("Queue HEAD = %p\n", + queue->qhead); + PRINT("Command Entry = %p\n", + cmd); + + PRINT("\nCPT_INST_S format:"); + PRINT("cmd->s.doneint = %x\n", cmd->s.doneint); + PRINT("cmd->s.res_addr = %lx\n", cmd->s.res_addr); + PRINT("cmd->s.grp = %x\n", cmd->s.grp); + PRINT("cmd->s.tag = %x\n", cmd->s.tag); + PRINT("cmd->s.tt = %x\n", cmd->s.tt); + PRINT("cmd->s.wq_ptr = %lx\n", cmd->s.wq_ptr); + PRINT("cmd->s.ei0 = %lx\n", cmd->s.ei0); + PRINT("cmd->s.ei1 = %lx\n", cmd->s.ei1); + PRINT("cmd->s.ei2 = %lx\n", cmd->s.ei2); + PRINT("cmd->s.ei3 = %lx\n", cmd->s.ei3); + + PRINT("\nCommand dump from queue HEAD:"); + for (i = 0; i < CPT_INST_SIZE / 8; i++) + PRINT("%lx\n", p[i]); + } +#endif + if (unlikely(++queue->idx >= DEFAULT_CMD_QCHUNK_SIZE)) { + uint32_t cchunk = queue->cchunk; + MOD_INC(cchunk, DEFAULT_CMD_QCHUNKS); + queue->qhead = queue->chead[cchunk].head; + queue->idx = 0; + queue->cchunk = cchunk; + } + + if (ring_door_bell) { + /* Memory barrier to flush pending writes */ + rte_smp_wmb(); + cptvf_write_vq_doorbell(cptvf, ring_door_bell); + } +} + +static inline uint8_t +check_nb_command_id(cpt_request_info_t *user_req, struct cpt_vf *cptvf) +{ + uint8_t ret = ERR_REQ_PENDING; + volatile cpt_res_s_t *cptres; + + cptres = (volatile cpt_res_s_t *)user_req->completion_addr; + + if (unlikely(cptres->s.compcode == CPT_COMP_E_NOTDONE)) { + /* + * Wait for some time for this command to get completed + * before timing out + */ + if (cpu_cycles() < user_req->time_out) + return ret; + /* + * TODO: See if alternate caddr can be used to not loop + * longer than needed. + */ + if ((cptres->s.compcode == CPT_COMP_E_NOTDONE) && + (user_req->extra_time < TIME_IN_RESET_COUNT)) { + user_req->extra_time++; + return ret; + } + + if (cptres->s.compcode != CPT_COMP_E_NOTDONE) + goto complete; + + ret = ERR_REQ_TIMEOUT; + PMD_DRV_LOG_RAW(ERR, "Request %p timedout\n", user_req); + cptvf_poll_misc(cptvf); + dump_cpt_request_sglist(&user_req->dbg_inst, + "Response Packet Gather in", 1, 1); + goto exit; + } + +complete: + if (likely(cptres->s.compcode == CPT_COMP_E_GOOD)) { + ret = 0; /* success */ + PMD_RX_LOG(DEBUG, "MC status %.8x\n", + *((volatile uint32_t *)user_req->alternate_caddr)); + PMD_RX_LOG(DEBUG, "HW status %.8x\n", + *((volatile uint32_t *)user_req->completion_addr)); + } else if ((cptres->s.compcode == CPT_COMP_E_SWERR) || + (cptres->s.compcode == CPT_COMP_E_FAULT)) { + ret = (uint8_t)*user_req->alternate_caddr; + if (!ret) + ret = ERR_BAD_ALT_CCODE; + PMD_RX_LOG(DEBUG, "Request %p : failed with %s : err code :" + "%x\n", user_req, + (cptres->s.compcode == CPT_COMP_E_FAULT) ? + "DMA Fault" : "Software error", ret); + } else { + PMD_DRV_LOG_RAW(ERR, "Request %p : unexpected completion code" + " %d\n", + user_req, cptres->s.compcode); + ret = (uint8_t)*user_req->alternate_caddr; + } + +exit: + dump_cpt_request_sglist(&user_req->dbg_inst, + "Response Packet Scatter Out", 1, 0); + return ret; +} + + +/* + * cpt_enqueue_req() + * + * SE & AE request enqueue function + */ +int32_t __hot +cpt_enqueue_req(cpt_instance_t *instance, void *req, uint8_t flags, + void *event, uint64_t event_flags) +{ + struct pending_queue *pqueue; + struct cpt_vf *cptvf; + cpt_inst_s_t *cpt_ist_p = NULL; + cpt_request_info_t *user_req = (cpt_request_info_t *)req; + struct command_queue *cqueue; + int32_t ret = 0; + +#ifdef CPTVF_STRICT_PARAM_CHECK + if (unlikely(!instance)) { + PMD_DRV_LOG_RAW(ERR, "Invalid inputs (instance: %p, req: %p)\n", + instance, req); + return -EINVAL; + } +#endif + + cptvf = (struct cpt_vf *)instance; + pqueue = &cptvf->pqueue; + + if (unlikely(!req)) { + /* ring only pending doorbells */ + if ((flags & ENQ_FLAG_ONLY_DOORBELL) && pqueue->p_doorbell) { + /* Memory barrier to flush pending writes */ + rte_smp_wmb(); + cptvf_write_vq_doorbell(cptvf, pqueue->p_doorbell); + pqueue->p_doorbell = 0; + } + return 0; + } + +#if defined(ATOMIC_THROTTLING_COUNTER) + /* Ask the application to try again later */ + if (unlikely(cpt_pmd_pcount_load(&pqueue->pending_count) >= + DEFAULT_CMD_QLEN)) { + return -EAGAIN; + } +#else + if (unlikely(pqueue->pending_count >= DEFAULT_CMD_QLEN)) + return -EAGAIN; +#endif + cqueue = &cptvf->cqueue; + cpt_ist_p = get_cpt_inst(cqueue, req); + rte_prefetch_non_temporal(cpt_ist_p); + + /* EI0, EI1, EI2, EI3 are already prepared */ + /* HW W0 */ + cpt_ist_p->u[0] = 0; + /* HW W1 */ + cpt_ist_p->s.res_addr = user_req->comp_baddr; + /* HW W2 */ + cpt_ist_p->u[2] = 0; + /* HW W3 */ + cpt_ist_p->s.wq_ptr = 0; + + /* MC EI0 */ + cpt_ist_p->s.ei0 = user_req->ist.ei0; + /* MC EI1 */ + cpt_ist_p->s.ei1 = user_req->ist.ei1; + /* MC EI2 */ + cpt_ist_p->s.ei2 = user_req->ist.ei2; + /* MC EI3 */ + cpt_ist_p->s.ei3 = user_req->ist.ei3; + + PMD_TX_LOG(DEBUG, "req: %p op: %p dma_mode 0x%x se_req %u\n", + req, + user_req->op, + user_req->dma_mode, + user_req->se_req); + +#ifdef CPT_DEBUG + { + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + + vq_cmd_w3.u64 = cpt_ist_p->s.ei3; + vq_cmd_w0.u64 = be64toh(cpt_ist_p->s.ei0); + user_req->dbg_inst = *cpt_ist_p; + + if (vq_cmd_w3.s.cptr) { + PMD_TX_LOG(DEBUG, "Context Handle: 0x%016lx\n", + (uint64_t)vq_cmd_w3.s.cptr); + /* Dump max context i.e 448 bytes */ + cpt_dump_buffer("CONTEXT", + os_iova2va((uint64_t)vq_cmd_w3.s.cptr), + 448); + } + + dump_cpt_request_info(user_req, cpt_ist_p); + dump_cpt_request_sglist(cpt_ist_p, "Request (src)", 1, 1); + dump_cpt_request_sglist(cpt_ist_p, "Request (dst)", 0, 0); + cpt_dump_buffer("VQ command word0", &cpt_ist_p->u[4], + sizeof(vq_cmd_w0)); + cpt_dump_buffer("VQ command word1", &cpt_ist_p->u[5], + sizeof(uint64_t)); + cpt_dump_buffer("VQ command word2", &cpt_ist_p->u[6], + sizeof(uint64_t)); + cpt_dump_buffer("VQ command word3", &cpt_ist_p->u[7], + sizeof(vq_cmd_w3)); + } +#endif + + if (likely(!(flags & ENQ_FLAG_SYNC))) { + void *op = user_req->op; + + if (unlikely(flags & ENQ_FLAG_EVENT)) { + app_data_t *app_data = op; + + /* Event based completion */ + cpt_ist_p->s.tag = OCTTX_EVENT_TAG(event_flags); + cpt_ist_p->s.grp = OCTTX_EVENT_GRP(event_flags); + cpt_ist_p->s.tt = OCTTX_EVENT_TT(event_flags); + cpt_ist_p->s.wq_ptr = (uint64_t)event; + +#if defined(ATOMIC_THROTTLING_COUNTER) + app_data->marker = user_req; + __atomic_fetch_add(&pqueue->pending_count, + 1, __ATOMIC_RELAXED); +#else + rid_t *rid_e; + /* + * Mark it as in progress in pending queue, software + * will mark it when completion is received + */ + rid_e = &pqueue->rid_queue[pqueue->enq_tail]; + rid_e->rid = (uint64_t)user_req; + /* rid_e->op = op; */ + MOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN); + app_data->marker = rid_e; +#endif + + cpt_dump_buffer("CPT Instruction with wqe", cpt_ist_p, + sizeof(*cpt_ist_p)); + + mark_cpt_inst(cptvf, cqueue, 1); + + } else { + uint32_t doorbell = 0; + + if (likely(flags & ENQ_FLAG_NODOORBELL)) + pqueue->p_doorbell++; + else + doorbell = ++pqueue->p_doorbell; + + /* Fill time_out cycles */ + user_req->time_out = cpu_cycles() + + DEFAULT_COMMAND_TIMEOUT * cpu_cycles_freq(); + user_req->extra_time = 0; + + cpt_dump_buffer("CPT Instruction", cpt_ist_p, + sizeof(*cpt_ist_p)); + + /* Default mode of software queue */ + mark_cpt_inst(cptvf, cqueue, doorbell); + + pqueue->p_doorbell -= doorbell; + pqueue->rid_queue[pqueue->enq_tail].rid = + (uint64_t)user_req; + /* pqueue->rid_queue[pqueue->enq_tail].op = op; */ + /* We will use soft queue length here to limit + * requests + */ + MOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN); + pqueue->pending_count += 1; + } + + PMD_TX_LOG(DEBUG, "Submitted NB cmd with request: %p op: %p\n", + user_req, op); + } else { + /* + * Synchronous operation, + * hold until completion / timeout + */ + /* Fill time_out cycles */ + user_req->time_out = cpu_cycles() + + DEFAULT_COMMAND_TIMEOUT * cpu_cycles_freq(); + user_req->extra_time = 0; + + cpt_dump_buffer("CPT Instruction", cpt_ist_p, + sizeof(*cpt_ist_p)); + + /* Default mode of software queue */ + mark_cpt_inst(cptvf, cqueue, 1); + + do { + /* TODO: should we pause */ + ret = check_nb_command_id(user_req, cptvf); + cptvf_poll_misc(cptvf); +#if 0 + PMD_TX_LOG(DEBUG, "Doorbell count for cptvf %s: %u\n", + cptvf->dev_name, + cptvf_read_vq_doorbell(cptvf)); +#endif + } while (ret == ERR_REQ_PENDING); + + PMD_TX_LOG(DEBUG, "Completed blocking cmd req: 0x%016llx, rc " + "0x%x\n", (unsigned long long)user_req, ret); + } + + return ret; +} + + +int32_t __hot +cpt_dequeue_burst(cpt_instance_t *instance, uint16_t cnt, + void *resp[], uint8_t cc[]) +{ + struct cpt_vf *cptvf = (struct cpt_vf *)instance; + struct pending_queue *pqueue = &cptvf->pqueue; + cpt_request_info_t *user_req; + rid_t *rid_e; + int i, count, pcount; + uint8_t ret; + + pcount = pqueue->pending_count; + count = (cnt > pcount) ? pcount : cnt; + + for (i = 0; i < count; i++) { + rid_e = &pqueue->rid_queue[pqueue->deq_head]; + user_req = (cpt_request_info_t *)(rid_e->rid); + + if (likely((i+1) < count)) + rte_prefetch_non_temporal((void *)rid_e[1].rid); + + ret = check_nb_command_id(user_req, cptvf); + + if (unlikely(ret == ERR_REQ_PENDING)) { + /* Stop checking for completions */ + break; + } + + /* Return completion code and op handle */ + cc[i] = (uint8_t)ret; + resp[i] = user_req->op; + PMD_RX_LOG(DEBUG, "Request %p Op %p completed with code %d", + user_req, user_req->op, ret); + + MOD_INC(pqueue->deq_head, DEFAULT_CMD_QLEN); + pqueue->pending_count -= 1; + } + + return i; +} + +uint16_t __hot +cpt_queue_full(cpt_instance_t *instance) +{ + struct cpt_vf *cptvf; + struct pending_queue *pqueue; + uint16_t avail; + + cptvf = (struct cpt_vf *)instance; + pqueue = &cptvf->pqueue; +#if defined(ATOMIC_THROTTLING_COUNTER) + avail = DEFAULT_CMD_QLEN - cpt_pmd_pcount_load(&pqueue->pending_count); + /* Ask the application to try again later */ + if (avail <= 0) + return 0; + + return avail; +#else + avail = DEFAULT_CMD_QLEN - pqueue->pending_count; + /* + * This will be NULL if instruction + * that was sent earlier which this entry was complete + */ + return avail; +#endif +} diff --git a/drivers/crypto/cpt/base/cpt_request_mgr.h b/drivers/crypto/cpt/base/cpt_request_mgr.h new file mode 100644 index 0000000..dfa4046 --- /dev/null +++ b/drivers/crypto/cpt/base/cpt_request_mgr.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef __REQUEST_MANGER_H +#define __REQUEST_MANGER_H + +#include "cpt8xxx_device.h" + +#define TIME_IN_RESET_COUNT 5 +#define COMPLETION_CODE_SIZE 8 +#define COMPLETION_CODE_INIT 0 + +#define SG_LIST_HDR_SIZE (8u) +#define SG_ENTRY_SIZE sizeof(sg_comp_t) + +#define AE_CORE_REQ 0 +#define SE_CORE_REQ 1 + +#define CTRL_DMA_MODE_SGIO 2 /* DMA Mode but SGIO is already setup */ + +#define MRS(reg) \ + ({ \ + uint64_t val; \ + __asm volatile("mrs %0, " #reg : "=r" (val)); \ + val; \ + }) + +int calculate_pad(uint8_t *ipad, uint8_t *opad, auth_type_t hash_type, + uint8_t *key, uint32_t keylen); + +typedef union opcode_info { + uint16_t flags; + struct { + uint8_t major; + uint8_t minor; + } s; +} opcode_info_t; + +typedef struct sglist_comp { + union { + uint64_t len; + struct { + uint16_t len[4]; + } s; + } u; + uint64_t ptr[4]; +} sg_comp_t; + +struct cpt_request_info { + /* fast path fields */ + uint64_t dma_mode : 2; /**< DMA mode */ + uint64_t se_req : 1; /**< To SE core */ + uint64_t comp_baddr : 61; + volatile uint64_t *completion_addr; + volatile uint64_t *alternate_caddr; + void *op; /** Reference to operation */ + struct { + uint64_t ei0; + uint64_t ei1; + uint64_t ei2; + uint64_t ei3; + } ist; + + /* slow path fields */ + uint64_t time_out; + uint8_t extra_time; +#ifdef CPT_DEBUG + cpt_inst_s_t dbg_inst; +#endif + +}; + +typedef struct cpt_request_info cpt_request_info_t; +#endif From patchwork Fri Jun 8 16:45:14 2018 Content-Type: text/plain; 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Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/base/cpt_ops.c | 308 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 308 insertions(+) create mode 100644 drivers/crypto/cpt/base/cpt_ops.c diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c new file mode 100644 index 0000000..e340006 --- /dev/null +++ b/drivers/crypto/cpt/base/cpt_ops.c @@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#include "cpt_request_mgr.h" + +#define __hot __attribute__((hot)) + +#define FC_GEN 0x1 +#define ZUC_SNOW3G 0x2 +#define KASUMI 0x3 +#define HASH_HMAC 0x4 + +struct cpt_ctx { + /* Below fields are accessed by sw */ + uint64_t enc_cipher :8; + uint64_t hash_type :8; + uint64_t mac_len :8; + uint64_t auth_key_len :8; + uint64_t fc_type :4; + uint64_t hmac :1; + uint64_t zsk_flags :3; + uint64_t k_ecb :1; + uint64_t snow3g :1; /* Set if it is snow3g and not ZUC */ + uint64_t rsvd :22; + /* Below fields are accessed by hardware */ + union { + mc_fc_context_t fctx; + mc_zuc_snow3g_ctx_t zs_ctx; + mc_kasumi_ctx_t k_ctx; + }; + uint8_t auth_key[64]; +}; + +static uint8_t zuc_d[32] = { + 0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E, + 0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF, + 0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1, + 0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC +}; + +static void gen_key_snow3g(uint8_t *ck, uint32_t *keyx) +{ + int i, base; + + for (i = 0; i < 4; i++) { + base = 4 * i; + keyx[3 - i] = (ck[base] << 24) | (ck[base + 1] << 16) | + (ck[base + 2] << 8) | (ck[base + 3]); + keyx[3 - i] = htobe32(keyx[3 - i]); + } +} + +#define MAX_IV_LEN 16 + +int cpt_fc_get_op_meta_len(void) +{ + uint32_t len = 0; + + len += sizeof(cpt_request_info_t); + len += OFFSET_CONTROL_BYTES + MAX_IV_LEN; + len += ROUNDUP8(SG_LIST_HDR_SIZE + + (ROUNDUP4(MAX_SG_IN_OUT_CNT) >> 2) * SG_ENTRY_SIZE); + len += 2 * COMPLETION_CODE_SIZE; + len += 2 * sizeof(cpt_res_s_t); + return len; +} + +/* Provides meta length required when it is + * direct mode i.e single buf inplace + */ +int32_t cpt_fc_get_op_sb_meta_len(void) +{ + uint32_t len = 0; + + /* Request structure */ + len = sizeof(cpt_request_info_t); + /* CPT HW result structure plus extra as it is aligned */ + len += 2*sizeof(cpt_res_s_t); + + return len; +} + +int32_t cpt_fc_get_ctx_len(void) +{ + return sizeof(struct cpt_ctx); +} + +int +cpt_fc_ciph_set_key(cpt_instance_t *instance, + void *ctx, cipher_type_t type, uint8_t *key, + uint16_t key_len, uint8_t *salt) +{ + struct cpt_ctx *cpt_ctx = ctx; + mc_fc_context_t *fctx = &cpt_ctx->fctx; + mc_aes_type_t aes_key_type = 0; + uint64_t *ctrl_flags; + + (void) instance; + + if (!type) { + /* to support passthrough case */ + + cpt_ctx->fc_type = FC_GEN; + ctrl_flags = (uint64_t *)&(fctx->enc.enc_ctrl.flags); + cpt_ctx->enc_cipher = 0; + + *ctrl_flags = be64toh(*ctrl_flags); + P_ENC_CTRL(fctx).enc_cipher = 0; + *ctrl_flags = htobe64(*ctrl_flags); + + return 0; + } + + if ((type >= ZUC_EEA3) && (type <= KASUMI_F8_ECB)) { + uint32_t keyx[4]; + + if (key_len != 16) + return -1; + + /* No support for AEAD yet */ + if (cpt_ctx->hash_type) + return -1; + + /* For ZUC/SNOW3G/Kasumi */ + switch (type) { + case SNOW3G_UEA2: + cpt_ctx->snow3g = 1; + gen_key_snow3g(key, keyx); + memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len); + cpt_ctx->fc_type = ZUC_SNOW3G; + cpt_ctx->zsk_flags = 0; + break; + case ZUC_EEA3: + cpt_ctx->snow3g = 0; + memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len); + memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32); + cpt_ctx->fc_type = ZUC_SNOW3G; + cpt_ctx->zsk_flags = 0; + break; + case KASUMI_F8_ECB: + /* Kasumi ECB mode */ + cpt_ctx->k_ecb = 1; + memcpy(cpt_ctx->k_ctx.ci_key, key, key_len); + cpt_ctx->zsk_flags = 0; + cpt_ctx->fc_type = KASUMI; + break; + case KASUMI_F8_CBC: + memcpy(cpt_ctx->k_ctx.ci_key, key, key_len); + cpt_ctx->zsk_flags = 0; + cpt_ctx->fc_type = KASUMI; + break; + default: + return -1; + } + cpt_ctx->enc_cipher = type; + return 0; + } + + fctx = &cpt_ctx->fctx; + /* Even though iv source is from dptr, + * aes_gcm salt is taken from ctx + */ + if (salt && (type == AES_GCM)) { + memcpy(fctx->enc.encr_iv, salt, 4); + /* Assuming it was just salt update + * and nothing else + */ + if (!key) + return 0; + } + + cpt_ctx->fc_type = FC_GEN; + ctrl_flags = (uint64_t *)&(fctx->enc.enc_ctrl.flags); + *ctrl_flags = be64toh(*ctrl_flags); + + cpt_ctx->enc_cipher = type; + /* For GMAC auth, cipher must be NULL */ + if (cpt_ctx->hash_type != GMAC_TYPE) + P_ENC_CTRL(fctx).enc_cipher = type; + + if (type == AES_XTS) + key_len = key_len / 2; + + /* key len only for AES */ + if ((type != DES3_CBC) && + (type != DES3_ECB)) { + switch (key_len) { + case BYTE_16: + aes_key_type = AES_128_BIT; + break; + case BYTE_24: + aes_key_type = AES_192_BIT; + if (type == AES_XTS) { + PMD_DRV_LOG(ERR, "Invalid AES key len for" + " XTS\n"); + return -1; + } + break; + case BYTE_32: + aes_key_type = AES_256_BIT; + break; + default: + PMD_DRV_LOG(ERR, "Invalid AES key len\n"); + return -1; + } + + P_ENC_CTRL(fctx).aes_key = aes_key_type; + } + /* + * We need to always say iv is from DPTR as user can + * sometimes override IV per operation + */ + P_ENC_CTRL(fctx).iv_source = FROM_DPTR; + + memcpy(fctx->enc.encr_key, key, key_len); + if (type == AES_XTS) { + /* Copy key2 for XTS into ipad */ + memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad)); + memcpy(fctx->hmac.ipad, &key[key_len], key_len); + } + + *ctrl_flags = htobe64(*ctrl_flags); + + return 0; +} + +int +cpt_fc_auth_set_key(cpt_instance_t *instance, + void *ctx, auth_type_t type, uint8_t *key, + uint16_t key_len, uint16_t mac_len) +{ + struct cpt_ctx *cpt_ctx = ctx; + mc_fc_context_t *fctx = &cpt_ctx->fctx; + uint64_t *ctrl_flags = NULL; + + (void) instance; + + if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) { + uint32_t keyx[4]; + + if (key_len != 16) + return -1; + /* No support for AEAD yet */ + if (cpt_ctx->enc_cipher) + return -1; + /* For ZUC/SNOW3G/Kasumi */ + switch (type) { + case SNOW3G_UIA2: + cpt_ctx->snow3g = 1; + gen_key_snow3g(key, keyx); + memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len); + cpt_ctx->fc_type = ZUC_SNOW3G; + cpt_ctx->zsk_flags = 0x1; + break; + case ZUC_EIA3: + cpt_ctx->snow3g = 0; + memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len); + memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32); + cpt_ctx->fc_type = ZUC_SNOW3G; + cpt_ctx->zsk_flags = 0x1; + break; + case KASUMI_F9_ECB: + /* Kasumi ECB mode */ + cpt_ctx->k_ecb = 1; + memcpy(cpt_ctx->k_ctx.ci_key, key, key_len); + cpt_ctx->fc_type = KASUMI; + cpt_ctx->zsk_flags = 0x1; + break; + case KASUMI_F9_CBC: + memcpy(cpt_ctx->k_ctx.ci_key, key, key_len); + cpt_ctx->fc_type = KASUMI; + cpt_ctx->zsk_flags = 0x1; + break; + default: + return -1; + } + cpt_ctx->mac_len = 4; + cpt_ctx->hash_type = type; + return 0; + } + + if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher) + cpt_ctx->fc_type = HASH_HMAC; + + ctrl_flags = (uint64_t *)&fctx->enc.enc_ctrl.flags; + *ctrl_flags = be64toh(*ctrl_flags); + + /* For GMAC auth, cipher must be NULL */ + if (type == GMAC_TYPE) + P_ENC_CTRL(fctx).enc_cipher = 0; + + P_ENC_CTRL(fctx).hash_type = cpt_ctx->hash_type = type; + P_ENC_CTRL(fctx).mac_len = cpt_ctx->mac_len = mac_len; + + if (key_len) { + cpt_ctx->hmac = 1; + memset(cpt_ctx->auth_key, 0, sizeof(cpt_ctx->auth_key)); + memcpy(cpt_ctx->auth_key, key, key_len); + cpt_ctx->auth_key_len = key_len; + memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad)); + memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad)); + memcpy(fctx->hmac.opad, key, key_len); + P_ENC_CTRL(fctx).auth_input_type = 1; + } + *ctrl_flags = htobe64(*ctrl_flags); + return 0; +} From patchwork Fri Jun 8 16:45:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 40867 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 34D5A1BAF5; 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Fri, 8 Jun 2018 16:49:01 +0000 From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon Cc: Ankur Dwivedi , Jerin Jacob , Murthy NSSR , Narayana Prasad , Nithin Dabilpuram , Ragothaman Jayaraman , Srisivasubramanian Srinivasan , dev@dpdk.org Date: Fri, 8 Jun 2018 22:15:15 +0530 Message-Id: <1528476325-15585-7-git-send-email-anoob.joseph@caviumnetworks.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com> References: <1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com> MIME-Version: 1.0 X-Originating-IP: [115.113.156.2] X-ClientProxiedBy: BM1PR01CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::11) To SN6PR07MB4911.namprd07.prod.outlook.com (2603:10b6:805:3c::29) X-MS-PublicTrafficType: Email X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(5600026)(4534165)(7168020)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020); SRVR:SN6PR07MB4911; X-Microsoft-Exchange-Diagnostics: 1; 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This includes all supported algos except Kasumi, Snow3G, Zuc, HMAC_ONLY and HASH_ONLY cases. Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/base/cpt.h | 129 +++++ drivers/crypto/cpt/base/cpt_ops.c | 1021 +++++++++++++++++++++++++++++++++++++ 2 files changed, 1150 insertions(+) diff --git a/drivers/crypto/cpt/base/cpt.h b/drivers/crypto/cpt/base/cpt.h index 11407ae..54b1cb6 100644 --- a/drivers/crypto/cpt/base/cpt.h +++ b/drivers/crypto/cpt/base/cpt.h @@ -54,6 +54,135 @@ void *marker; } app_data_t; +/* + * Parameters for Flexi Crypto + * requests + */ +#define VALID_AAD_BUF 0x01 +#define VALID_MAC_BUF 0x02 +#define VALID_IV_BUF 0x04 +#define SINGLE_BUF_INPLACE 0x08 +#define SINGLE_BUF_HEADTAILROOM 0x10 + +#define ENCR_IV_OFFSET(__d_offs) ((__d_offs >> 32) & 0xffff) +#define ENCR_OFFSET(__d_offs) ((__d_offs >> 16) & 0xffff) +#define AUTH_OFFSET(__d_offs) (__d_offs & 0xffff) +#define ENCR_DLEN(__d_lens) (__d_lens >> 32) +#define AUTH_DLEN(__d_lens) (__d_lens & 0xffffffff) + +typedef struct fc_params { + /* 0th cache line */ + union { + buf_ptr_t bufs[1]; + struct { + iov_ptr_t *src_iov; + iov_ptr_t *dst_iov; + }; + }; + void *iv_buf; + void *auth_iv_buf; + buf_ptr_t meta_buf; + buf_ptr_t ctx_buf; + uint64_t rsvd2; + + /* 1st cache line */ + buf_ptr_t aad_buf; + buf_ptr_t mac_buf; + +} fc_params_t; + +/* + * Parameters for digest + * generate requests + * Only src_iov, op, ctx_buf, mac_buf, prep_req + * meta_buf, auth_data_len are used for digest gen. + */ +typedef struct fc_params digest_params_t; + +/* Cipher Algorithms */ +typedef mc_cipher_type_t cipher_type_t; + +/* Auth Algorithms */ +typedef mc_hash_type_t auth_type_t; + +/* Flexi Crypto Operations */ +/* + * Encr | Encr + Hmac | HASH-HMAC generation + */ +/* + * ZUC/SNOW3g enc cipher/cipher+auth/auth-gen operation + */ +/* + * kasumi enc cipher/cipher+auth/auth-gen operation + * F8 iv_buf: 64 bits Bigendian format + * COUNT[63-32] || BEARER[31-27] || + * DIRECTION[26] || 0...0[25-0] + * F9 mac gen auth_iv_buf: 64 bits BE + 8 bits + * COUNT[63-32] || FRESH[31-0] + * 0...0[7-1] || DIRECTION[0] + */ +void *cpt_fc_enc_hmac_prep(uint32_t flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + int *ret); +/* + * Decr | Decr + Hmac + */ +/* + * ZUC/SNOW3g dec cipher/cipher+auth operation + */ +/* + * kasumi dec cipher/cipher+auth/ operation + * F8 iv_buf: 64 bits Bigendian format + * COUNT[63-32] || BEARER[31-27] || + * DIRECTION[26] || 0...0[25-0] + */ +void *cpt_fc_dec_hmac_prep(uint32_t flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + int *ret); + +/* Flexi Crypto Ctrl Operations */ +int32_t cpt_fc_ciph_set_key(cpt_instance_t *inst, + void *ctx, + cipher_type_t type, + uint8_t *key, + uint16_t key_len, + uint8_t *salt); + +int32_t cpt_fc_ciph_set_iv(cpt_instance_t *inst, + void *ctx, + uint8_t *iv, + uint16_t iv_len); + +int32_t cpt_fc_auth_set_key(cpt_instance_t *inst, + void *ctx, + auth_type_t type, + uint8_t *key, + uint16_t key_len, + uint16_t mac_len); + +void +cpt_fc_salt_update(void *ctx, + uint8_t *salt); +/* + * Get's size of contiguous meta buffer + * to be allocated per op + */ +int32_t cpt_fc_get_op_meta_len(void); + +/* Get context length for a session */ +int32_t cpt_fc_get_ctx_len(void); + +/* Provides meta length required when it is + * direct mode i.e single buf inplace + */ +int32_t cpt_fc_get_op_sb_meta_len(void); + /* Instance operations */ /* Enqueue an SE/AE request */ diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c index e340006..31f8064 100644 --- a/drivers/crypto/cpt/base/cpt_ops.c +++ b/drivers/crypto/cpt/base/cpt_ops.c @@ -86,6 +86,14 @@ int32_t cpt_fc_get_ctx_len(void) return sizeof(struct cpt_ctx); } +inline void +cpt_fc_salt_update(void *ctx, + uint8_t *salt) +{ + struct cpt_ctx *cpt_ctx = ctx; + memcpy(&cpt_ctx->fctx.enc.encr_iv, salt, 4); +} + int cpt_fc_ciph_set_key(cpt_instance_t *instance, void *ctx, cipher_type_t type, uint8_t *key, @@ -306,3 +314,1016 @@ int32_t cpt_fc_get_ctx_len(void) *ctrl_flags = htobe64(*ctrl_flags); return 0; } + +static inline uint32_t +fill_sg_comp(sg_comp_t *list, + uint32_t i, + phys_addr_t dma_addr, + void *vaddr, + uint32_t size) +{ + sg_comp_t *to = &list[i>>2]; + + to->u.s.len[i%4] = htobe16(size); + to->ptr[i%4] = htobe64(dma_addr); + (void) vaddr; + i++; + return i; +} + +static inline uint32_t +fill_sg_comp_from_buf(sg_comp_t *list, + uint32_t i, + buf_ptr_t *from) +{ + sg_comp_t *to = &list[i>>2]; + + to->u.s.len[i%4] = htobe16(from->size); + to->ptr[i%4] = htobe64(from->dma_addr); + i++; + return i; +} + +static inline uint32_t +fill_sg_comp_from_buf_min(sg_comp_t *list, + uint32_t i, + buf_ptr_t *from, + uint32_t *psize) +{ + sg_comp_t *to = &list[i >> 2]; + uint32_t size = *psize; + uint32_t e_len; + + e_len = (size > from->size) ? from->size : size; + to->u.s.len[i % 4] = htobe16(e_len); + to->ptr[i % 4] = htobe64(from->dma_addr); + *psize -= e_len; + i++; + return i; +} + +/* + * This fills the MC expected SGIO list + * from IOV given by user. + */ +static inline uint32_t +fill_sg_comp_from_iov(sg_comp_t *list, + uint32_t i, + iov_ptr_t *from, uint32_t from_offset, + uint32_t *psize, buf_ptr_t *extra_buf, + uint32_t extra_offset) +{ + int32_t j; + uint32_t extra_len = extra_buf ? extra_buf->size : 0; + uint32_t size = *psize - extra_len; + buf_ptr_t *bufs; + + bufs = from->bufs; + for (j = 0; (j < from->buf_cnt) && size; j++) { + phys_addr_t e_dma_addr; + uint32_t e_len; + sg_comp_t *to = &list[i >> 2]; + + if (!bufs[j].size) + continue; + + if (unlikely(from_offset)) { + if (from_offset >= bufs[j].size) { + from_offset -= bufs[j].size; + continue; + } + e_dma_addr = bufs[j].dma_addr + from_offset; + e_len = (size > (bufs[j].size - from_offset)) ? + (bufs[j].size - from_offset) : size; + from_offset = 0; + } else { + e_dma_addr = bufs[j].dma_addr; + e_len = (size > bufs[j].size) ? + bufs[j].size : size; + } + + to->u.s.len[i % 4] = htobe16(e_len); + to->ptr[i % 4] = htobe64(e_dma_addr); + + if (extra_len && (e_len >= extra_offset)) { + /* Break the data at given offset */ + uint32_t next_len = e_len - extra_offset; + phys_addr_t next_dma = e_dma_addr + extra_offset; + + if (!extra_offset) { + i--; + } else { + e_len = extra_offset; + size -= e_len; + to->u.s.len[i % 4] = htobe16(e_len); + } + + /* Insert extra data ptr */ + if (extra_len) { + i++; + to = &list[i >> 2]; + to->u.s.len[i % 4] = htobe16(extra_buf->size); + to->ptr[i % 4] = htobe64(extra_buf->dma_addr); + + /* size already decremented by extra len */ + } + + /* insert the rest of the data */ + if (next_len) { + i++; + to = &list[i >> 2]; + to->u.s.len[i % 4] = htobe16(next_len); + to->ptr[i % 4] = htobe64(next_dma); + size -= next_len; + } + extra_len = 0; + + } else { + size -= e_len; + } + if (extra_offset) + extra_offset -= size; + i++; + } + + *psize = size; + return (uint32_t)i; +} + +static inline int __attribute__((always_inline)) +cpt_enc_hmac_prep(uint32_t flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *fc_params, + void *op, + void **prep_req) +{ + uint32_t iv_offset = 0; + int32_t inputlen, outputlen, enc_dlen, auth_dlen; + struct cpt_ctx *cpt_ctx; + uint32_t cipher_type, hash_type; + uint32_t mac_len, size; + uint8_t iv_len = 16; + cpt_request_info_t *req; + buf_ptr_t *meta_p, *aad_buf = NULL; + uint32_t encr_offset, auth_offset; + uint32_t encr_data_len, auth_data_len, aad_len = 0; + uint32_t passthrough_len = 0; + void *m_vaddr, *offset_vaddr; + uint64_t m_dma, offset_dma, ctx_dma; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + void *c_vaddr; + uint64_t c_dma; + int32_t m_size; + opcode_info_t opcode; + + meta_p = &fc_params->meta_buf; +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!fc_params || !meta_p->vaddr || !meta_p->size) + return ERR_BAD_INPUT_ARG; +#endif + m_vaddr = meta_p->vaddr; + m_dma = meta_p->dma_addr; + m_size = meta_p->size; + + encr_offset = ENCR_OFFSET(d_offs); + auth_offset = AUTH_OFFSET(d_offs); + encr_data_len = ENCR_DLEN(d_lens); + auth_data_len = AUTH_DLEN(d_lens); + if (unlikely(flags & VALID_AAD_BUF)) { + /* + * We dont support both aad + * and auth data separately + */ + auth_data_len = 0; + auth_offset = 0; + aad_len = fc_params->aad_buf.size; + aad_buf = &fc_params->aad_buf; + } + cpt_ctx = fc_params->ctx_buf.vaddr; + cipher_type = cpt_ctx->enc_cipher; + hash_type = cpt_ctx->hash_type; + mac_len = cpt_ctx->mac_len; + + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* start cpt request info struct at 8 byte boundary */ + size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) - + (uint8_t *)m_vaddr; + + req = (cpt_request_info_t *)((uint8_t *)m_vaddr + size); + + size += sizeof(cpt_request_info_t); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + if (hash_type == GMAC_TYPE) + encr_data_len = 0; + + if (unlikely(!(flags & VALID_IV_BUF))) { + iv_len = 0; + iv_offset = ENCR_IV_OFFSET(d_offs); + } + + if (unlikely(flags & VALID_AAD_BUF)) { + /* + * When AAD is given, data above encr_offset is pass through + * Since AAD is given as separate pointer and not as offset, + * this is a special case as we need to fragment input data + * into passthrough + encr_data and then insert AAD in between. + */ + if (hash_type != GMAC_TYPE) { + passthrough_len = encr_offset; + auth_offset = passthrough_len + iv_len; + encr_offset = passthrough_len + aad_len + iv_len; + auth_data_len = aad_len + encr_data_len; + } else { + passthrough_len = 16 + aad_len; + auth_offset = passthrough_len + iv_len; + auth_data_len = aad_len; + } + } else { + encr_offset += iv_len; + auth_offset += iv_len; + } + + /* Initialising ctrl and opcode + * fields in cpt request structure + */ + + req->se_req = SE_CORE_REQ; + /* + * We are using DMA mode but indicate that + * SGIO list is already populated. + */ + req->dma_mode = CTRL_DMA_MODE_SGIO; + + /* Encryption */ + opcode.s.major = MAJOR_OP_FC; + opcode.s.minor = 0; + + auth_dlen = auth_offset + auth_data_len; + enc_dlen = encr_data_len + encr_offset; + if (unlikely(encr_data_len & 0xf)) { + if ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB)) + enc_dlen = ROUNDUP8(encr_data_len) + encr_offset; + else if (likely((cipher_type == AES_CBC) || + (cipher_type == AES_ECB))) + enc_dlen = ROUNDUP16(encr_data_len) + encr_offset; + } + + /* TODO: MC issue */ + if (unlikely(hash_type == GMAC_TYPE)) { + encr_offset = auth_dlen; + enc_dlen = 0; + } + + if (unlikely(auth_dlen > enc_dlen)) { + inputlen = auth_dlen; + outputlen = auth_dlen + mac_len; + } else { + inputlen = enc_dlen; + outputlen = enc_dlen + mac_len; + } + + /*GP op header */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = htobe16(encr_data_len); + vq_cmd_w0.s.param2 = htobe16(auth_data_len); + /* + * In 83XX since we have a limitation of + * IV & Offset control word not part of instruction + * and need to be part of Data Buffer, we check if + * head room is there and then only do the Direct mode processing + */ + if (likely((flags & SINGLE_BUF_INPLACE) && + (flags & SINGLE_BUF_HEADTAILROOM))) { + void *dm_vaddr = fc_params->bufs[0].vaddr; + uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr; + /* + * This flag indicates that there is 24 bytes head room and + * 8 bytes tail room available, so that we get to do + * DIRECT MODE with limitation + */ + + offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len; + offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len; + + /* DPTR */ + req->ist.ei1 = offset_dma; + /* RPTR should just exclude offset control word */ + req->ist.ei2 = dm_dma_addr - iv_len; + req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr + + outputlen - iv_len); + /* *req->alternate_caddr = ((uint64_t)0xdeadbeefdeadbeef) */ + + vq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN); + + vq_cmd_w0.s.opcode = htobe16(opcode.flags); + + if (likely(iv_len)) { + uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr + + OFF_CTRL_LEN); + uint64_t *src = fc_params->iv_buf; + dest[0] = src[0]; + dest[1] = src[1]; + } + + *(uint64_t *)offset_vaddr = + htobe64(((uint64_t)encr_offset << 16) | + ((uint64_t)iv_offset << 8) | + ((uint64_t)auth_offset)); + + } else { + uint32_t i, g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + uint8_t *in_buffer; + + /* This falls under strict SG mode */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + size = OFF_CTRL_LEN + iv_len; + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + opcode.s.major |= DMA_MODE; + + vq_cmd_w0.s.opcode = htobe16(opcode.flags); + + if (likely(iv_len)) { + uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr + + OFF_CTRL_LEN); + uint64_t *src = fc_params->iv_buf; + dest[0] = src[0]; + dest[1] = src[1]; + } + + *(uint64_t *)offset_vaddr = + htobe64(((uint64_t)encr_offset << 16) | + ((uint64_t)iv_offset << 8) | + ((uint64_t)auth_offset)); + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + + i = 0; + + /* Offset control word that includes iv */ + i = fill_sg_comp(gather_comp, i, offset_dma, + offset_vaddr, OFF_CTRL_LEN + iv_len); + + /* Add input data */ + size = inputlen - iv_len; + if (likely(size)) { + uint32_t aad_offset = aad_len ? passthrough_len : 0; + + if (unlikely(flags & SINGLE_BUF_INPLACE)) { + i = fill_sg_comp_from_buf_min(gather_comp, i, + fc_params->bufs, + &size); + } else { + + i = fill_sg_comp_from_iov(gather_comp, i, + fc_params->src_iov, + 0, &size, + aad_buf, aad_offset); + } + + if (unlikely(size)) { + PMD_TX_LOG(ERR, "Insufficient buffer space," + " size %d need\n", size); + return ERR_BAD_INPUT_ARG; + } + } + ((uint16_t *)in_buffer)[2] = htobe16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter list + */ + i = 0; + scatter_comp = + (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + /* Add IV */ + if (likely(iv_len)) { + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, + (uint8_t *)offset_vaddr + OFF_CTRL_LEN, + iv_len); + } + + /* output data or output data + digest*/ + if (unlikely(flags & VALID_MAC_BUF)) { + size = outputlen - iv_len - mac_len; + if (size) { + uint32_t aad_offset = + aad_len ? passthrough_len : 0; + + if (unlikely(flags & SINGLE_BUF_INPLACE)) { + i = fill_sg_comp_from_buf_min( + scatter_comp, + i, + fc_params->bufs, + &size); + } else { + i = fill_sg_comp_from_iov(scatter_comp, + i, + fc_params->dst_iov, + 0, + &size, + aad_buf, + aad_offset); + } + if (size) + return ERR_BAD_INPUT_ARG; + } + /* mac_data */ + if (mac_len) { + i = fill_sg_comp_from_buf(scatter_comp, i, + &fc_params->mac_buf); + } + } else { + /* Output including mac */ + size = outputlen - iv_len; + if (likely(size)) { + uint32_t aad_offset = + aad_len ? passthrough_len : 0; + + if (unlikely(flags & SINGLE_BUF_INPLACE)) { + i = fill_sg_comp_from_buf_min( + scatter_comp, + i, + fc_params->bufs, + &size); + } else { + i = fill_sg_comp_from_iov(scatter_comp, + i, + fc_params->dst_iov, + 0, + &size, + aad_buf, + aad_offset); + } + if (unlikely(size)) { + PMD_TX_LOG(ERR, "Insufficient buffer" + " space, size %d need\n", size); + return ERR_BAD_INPUT_ARG; + } + } + } + ((uint16_t *)in_buffer)[3] = htobe16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = htobe16(size); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + } + + /* First 16-bit swap then 64-bit swap */ + /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions + * to eliminate all the swapping + */ + vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64); + + ctx_dma = fc_params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, fctx); + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = ctx_dma; + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!(m_size >= 0)) { + PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n", + m_size); + abort(); + } +#endif + *prep_req = req; + return 0; +} + +static inline int +cpt_dec_hmac_prep(uint32_t flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *fc_params, + void *op, + void **prep_req) +{ + uint32_t iv_offset = 0, size; + int32_t inputlen, outputlen, enc_dlen, auth_dlen; + struct cpt_ctx *cpt_ctx; + int32_t hash_type, mac_len, m_size; + uint8_t iv_len = 16; + cpt_request_info_t *req; + buf_ptr_t *meta_p, *aad_buf = NULL; + uint32_t encr_offset, auth_offset; + uint32_t encr_data_len, auth_data_len, aad_len = 0; + uint32_t passthrough_len = 0; + void *m_vaddr, *offset_vaddr; + uint64_t m_dma, offset_dma, ctx_dma; + opcode_info_t opcode; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + void *c_vaddr; + uint64_t c_dma; + + meta_p = &fc_params->meta_buf; +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!fc_params || !meta_p->vaddr || !meta_p->size) + return ERR_BAD_INPUT_ARG; +#endif + m_vaddr = meta_p->vaddr; + m_dma = meta_p->dma_addr; + m_size = meta_p->size; + + encr_offset = ENCR_OFFSET(d_offs); + auth_offset = AUTH_OFFSET(d_offs); + encr_data_len = ENCR_DLEN(d_lens); + auth_data_len = AUTH_DLEN(d_lens); + + if (unlikely(flags & VALID_AAD_BUF)) { + /* + * We dont support both aad + * and auth data separately + */ + auth_data_len = 0; + auth_offset = 0; + aad_len = fc_params->aad_buf.size; + aad_buf = &fc_params->aad_buf; + } + + cpt_ctx = fc_params->ctx_buf.vaddr; + hash_type = cpt_ctx->hash_type; + mac_len = cpt_ctx->mac_len; + + if (hash_type == GMAC_TYPE) + encr_data_len = 0; + + if (unlikely(!(flags & VALID_IV_BUF))) { + iv_len = 0; + iv_offset = ENCR_IV_OFFSET(d_offs); + } + + if (unlikely(flags & VALID_AAD_BUF)) { + /* + * When AAD is given, data above encr_offset is pass through + * Since AAD is given as separate pointer and not as offset, + * this is a special case as we need to fragment input data + * into passthrough + encr_data and then insert AAD in between. + */ + if (hash_type != GMAC_TYPE) { + passthrough_len = encr_offset; + auth_offset = passthrough_len + iv_len; + encr_offset = passthrough_len + aad_len + iv_len; + auth_data_len = aad_len + encr_data_len; + } else { + passthrough_len = 16 + aad_len; + auth_offset = passthrough_len + iv_len; + auth_data_len = aad_len; + } + } else { + encr_offset += iv_len; + auth_offset += iv_len; + } + + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* start cpt request info structure at 8 byte alignment */ + size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) - + (uint8_t *)m_vaddr; + + req = (cpt_request_info_t *)((uint8_t *)m_vaddr + size); + + size += sizeof(cpt_request_info_t); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Initialising ctrl and opcode + * fields in cpt request structure + */ + + req->se_req = SE_CORE_REQ; + /* + * We are using DMA mode but indicate that + * SGIO list is already populated. + */ + req->dma_mode = CTRL_DMA_MODE_SGIO; + + /* Decryption */ + opcode.s.major = MAJOR_OP_FC; + opcode.s.minor = 1; + + enc_dlen = encr_offset + encr_data_len; + auth_dlen = auth_offset + auth_data_len; + + if (auth_dlen > enc_dlen) { + inputlen = auth_dlen + mac_len; + outputlen = auth_dlen; + } else { + inputlen = enc_dlen + mac_len; + outputlen = enc_dlen; + } + + if (hash_type == GMAC_TYPE) + encr_offset = inputlen; + + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = htobe16(encr_data_len); + vq_cmd_w0.s.param2 = htobe16(auth_data_len); + + /* + * In 83XX since we have a limitation of + * IV & Offset control word not part of instruction + * and need to be part of Data Buffer, we check if + * head room is there and then only do the Direct mode processing + */ + if (likely((flags & SINGLE_BUF_INPLACE) && + (flags & SINGLE_BUF_HEADTAILROOM))) { + void *dm_vaddr = fc_params->bufs[0].vaddr; + uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr; + /* + * This flag indicates that there is 24 bytes head room and + * 8 bytes tail room available, so that we get to do + * DIRECT MODE with limitation + */ + + offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len; + offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len; + req->ist.ei1 = offset_dma; + + /* RPTR should just exclude offset control word */ + req->ist.ei2 = dm_dma_addr - iv_len; + + /* In direct mode,changing the alternate completion code address + * to start of rptr,the assumption is that most auth iv failure + * are reported at first byte only.This will not give the + * correct alternate completion code the auth iv fail is + * reported after some bytes. + * FIXME + */ + req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr - + iv_len); + /* since this is decryption, + * don't touch the content of + * alternate ccode space as it contains + * hmac. + */ + + vq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN); + + vq_cmd_w0.s.opcode = htobe16(opcode.flags); + + if (likely(iv_len)) { + uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr + + OFF_CTRL_LEN); + uint64_t *src = fc_params->iv_buf; + dest[0] = src[0]; + dest[1] = src[1]; + } + + *(uint64_t *)offset_vaddr = + htobe64(((uint64_t)encr_offset << 16) | + ((uint64_t)iv_offset << 8) | + ((uint64_t)auth_offset)); + + } else { + uint64_t dptr_dma, rptr_dma; + uint32_t g_size_bytes, s_size_bytes; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + uint8_t *in_buffer; + uint8_t i = 0; + + /* This falls under strict SG mode */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + size = OFF_CTRL_LEN + iv_len; + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + opcode.s.major |= DMA_MODE; + + vq_cmd_w0.s.opcode = htobe16(opcode.flags); + + if (likely(iv_len)) { + uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr + + OFF_CTRL_LEN); + uint64_t *src = fc_params->iv_buf; + dest[0] = src[0]; + dest[1] = src[1]; + } + + *(uint64_t *)offset_vaddr = + htobe64(((uint64_t)encr_offset << 16) | + ((uint64_t)iv_offset << 8) | + ((uint64_t)auth_offset)); + + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word that includes iv */ + i = fill_sg_comp(gather_comp, i, offset_dma, + offset_vaddr, OFF_CTRL_LEN + iv_len); + + /* Add input data */ + if (flags & VALID_MAC_BUF) { + size = inputlen - iv_len - mac_len; + if (size) { + /* input data only */ + if (unlikely(flags & SINGLE_BUF_INPLACE)) { + i = fill_sg_comp_from_buf_min( + gather_comp, i, + fc_params->bufs, + &size); + } else { + uint32_t aad_offset = aad_len ? + passthrough_len : 0; + + i = fill_sg_comp_from_iov(gather_comp, + i, + fc_params->src_iov, + 0, &size, + aad_buf, + aad_offset); + } + if (size) + return ERR_BAD_INPUT_ARG; + } + + /* mac data */ + if (mac_len) { + i = fill_sg_comp_from_buf(gather_comp, i, + &fc_params->mac_buf); + } + } else { + /* input data + mac */ + size = inputlen - iv_len; + if (size) { + if (unlikely(flags & SINGLE_BUF_INPLACE)) { + i = fill_sg_comp_from_buf_min( + gather_comp, i, + fc_params->bufs, + &size); + } else { + uint32_t aad_offset = aad_len ? + passthrough_len : 0; + + if (!fc_params->src_iov) + return ERR_BAD_INPUT_ARG; + + i = fill_sg_comp_from_iov(gather_comp, i, + fc_params->src_iov, + 0, &size, + aad_buf, + aad_offset); + } + + if (size) + return ERR_BAD_INPUT_ARG; + } + } + ((uint16_t *)in_buffer)[2] = htobe16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = + (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + /* Add iv */ + if (iv_len) { + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, + (uint8_t *)offset_vaddr + OFF_CTRL_LEN, + iv_len); + } + + /* Add output data */ + size = outputlen - iv_len; + if (size) { + if (unlikely(flags & SINGLE_BUF_INPLACE)) { + /* handle single buffer here */ + i = fill_sg_comp_from_buf_min(scatter_comp, i, + fc_params->bufs, + &size); + } else { + uint32_t aad_offset = aad_len ? + passthrough_len : 0; + + if (!fc_params->dst_iov) + return ERR_BAD_INPUT_ARG; + + i = fill_sg_comp_from_iov(scatter_comp, i, + fc_params->dst_iov, 0, + &size, aad_buf, + aad_offset); + } + + if (unlikely(size)) + return ERR_BAD_INPUT_ARG; + } + + ((uint16_t *)in_buffer)[3] = htobe16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = htobe16(size); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + size += COMPLETION_CODE_SIZE; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + } + + /* First 16-bit swap then 64-bit swap */ + /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions + * to eliminate all the swapping + */ + vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64); + + ctx_dma = fc_params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, fctx); + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = ctx_dma; + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!(m_size >= 0)) { + PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n", + m_size); + abort(); + } +#endif + *prep_req = req; + return 0; +} + +void * +cpt_fc_dec_hmac_prep(uint32_t flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *fc_params, + void *op, int *ret_val) +{ + struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr; + uint8_t fc_type; + void *prep_req = NULL; + int ret; + + fc_type = ctx->fc_type; + + if (likely(fc_type == FC_GEN)) { + ret = cpt_dec_hmac_prep(flags, d_offs, d_lens, + fc_params, op, &prep_req); + } else { + /* + * For AUTH_ONLY case, + * MC only supports digest generation and verification + * should be done in software by memcmp() + */ + + ret = ERR_EIO; + } + + if (unlikely(!prep_req)) + *ret_val = ret; + return prep_req; +} + +void *__hot +cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, + fc_params_t *fc_params, void *op, int *ret_val) +{ + struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr; + uint8_t fc_type; + void *prep_req = NULL; + int ret; + + fc_type = ctx->fc_type; + + /* Common api for rest of the ops */ + if (likely(fc_type == FC_GEN)) { + ret = cpt_enc_hmac_prep(flags, d_offs, d_lens, + fc_params, op, &prep_req); + } else { + ret = ERR_EIO; + } + + if (unlikely(!prep_req)) + *ret_val = ret; + return prep_req; +} From patchwork Fri Jun 8 16:45:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 40868 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CECDD69D4; Fri, 8 Jun 2018 18:49:11 +0200 (CEST) Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on0040.outbound.protection.outlook.com [104.47.36.40]) by dpdk.org (Postfix) with ESMTP id 1B0625F17 for ; Fri, 8 Jun 2018 18:49:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yHQ9VcoE2gh7kJJy0Foitz9lEJLAEi9Us1kMzqQOjhc=; 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Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/base/cpt_ops.c | 667 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 667 insertions(+) diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c index 31f8064..ff7522a 100644 --- a/drivers/crypto/cpt/base/cpt_ops.c +++ b/drivers/crypto/cpt/base/cpt_ops.c @@ -1272,6 +1272,667 @@ static inline int __attribute__((always_inline)) return 0; } +static int +cpt_zuc_snow3g_enc_prep(uint32_t req_flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + void **prep_req) +{ + uint32_t size; + int32_t inputlen, outputlen; + struct cpt_ctx *cpt_ctx; + uint32_t mac_len = 0; + uint8_t snow3g, j; + cpt_request_info_t *req; + buf_ptr_t *buf_p; + uint32_t encr_offset = 0, auth_offset = 0; + uint32_t encr_data_len = 0, auth_data_len = 0; + int flags, iv_len = 16, m_size; + void *m_vaddr, *c_vaddr; + uint64_t m_dma, c_dma, offset_ctrl; + uint64_t *offset_vaddr, offset_dma; + uint32_t *iv_s, iv[4]; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + opcode_info_t opcode; + + buf_p = ¶ms->meta_buf; +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params || !buf_p->vaddr || !buf_p->size) + return ERR_BAD_INPUT_ARG; +#endif + m_vaddr = buf_p->vaddr; + m_dma = buf_p->dma_addr; + m_size = buf_p->size; + + cpt_ctx = params->ctx_buf.vaddr; + flags = cpt_ctx->zsk_flags; + mac_len = cpt_ctx->mac_len; + snow3g = cpt_ctx->snow3g; + + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Reserve memory for cpt request info */ + req = m_vaddr; + + size = sizeof(cpt_request_info_t); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Initialising ctrl and opcode + * fields for cpt request + */ + + req->se_req = SE_CORE_REQ; + req->dma_mode = CTRL_DMA_MODE_SGIO; + + opcode.s.major = MAJOR_OP_ZUC_SNOW3G; + + /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */ + opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) | + (0 << 3) | (flags & 0x7)); + + if (flags == 0x1) { + /* + * Microcode expects offsets in bytes + * TODO: Rounding off + */ + auth_data_len = AUTH_DLEN(d_lens); + + /* EIA3 or UIA2 */ + auth_offset = AUTH_OFFSET(d_offs); + auth_offset = auth_offset / 8; + + /* consider iv len */ + auth_offset += iv_len; + + inputlen = auth_offset + + (RTE_ALIGN(auth_data_len, 8) / 8); + outputlen = mac_len; + + offset_ctrl = htobe64((uint64_t)auth_offset); + + } else { + /* EEA3 or UEA2 */ + /* + * Microcode expects offsets in bytes + * TODO: Rounding off + */ + encr_data_len = ENCR_DLEN(d_lens); + + + encr_offset = ENCR_OFFSET(d_offs); + encr_offset = encr_offset / 8; + /* consider iv len */ + encr_offset += iv_len; + + inputlen = encr_offset + + (RTE_ALIGN(encr_data_len, 8) / 8); + outputlen = inputlen; + + /* iv offset is 0 */ + offset_ctrl = htobe64((uint64_t)encr_offset << 16); + } + + /* IV */ + iv_s = (flags == 0x1) ? params->auth_iv_buf : + params->iv_buf; + + if (snow3g) { + /* + * DPDK seems to provide it in form of IV3 IV2 IV1 IV0 + * and BigEndian, MC needs it as IV0 IV1 IV2 IV3 + */ + + for (j = 0; j < 4; j++) + iv[j] = iv_s[3 - j]; + } else { + /* ZUC doesn't need a swap */ + for (j = 0; j < 4; j++) + iv[j] = iv_s[j]; + } + + /* + * GP op header, lengths are expected in bits. + */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = htobe16(encr_data_len); + vq_cmd_w0.s.param2 = htobe16(auth_data_len); + + /* + * In 83XX since we have a limitation of + * IV & Offset control word not part of instruction + * and need to be part of Data Buffer, we check if + * head room is there and then only do the Direct mode processing + */ + if (likely((req_flags & SINGLE_BUF_INPLACE) && + (req_flags & SINGLE_BUF_HEADTAILROOM))) { + void *dm_vaddr = params->bufs[0].vaddr; + uint64_t dm_dma_addr = params->bufs[0].dma_addr; + /* + * This flag indicates that there is 24 bytes head room and + * 8 bytes tail room available, so that we get to do + * DIRECT MODE with limitation + */ + + offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr - + OFF_CTRL_LEN - iv_len); + offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len; + + /* DPTR */ + req->ist.ei1 = offset_dma; + /* RPTR should just exclude offset control word */ + req->ist.ei2 = dm_dma_addr - iv_len; + req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr + + outputlen - iv_len); + + vq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN); + + vq_cmd_w0.s.opcode = htobe16(opcode.flags); + + if (likely(iv_len)) { + uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr + + OFF_CTRL_LEN); + memcpy(iv_d, iv, 16); + } + + *offset_vaddr = offset_ctrl; + } else { + uint32_t i, g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + uint8_t *in_buffer; + uint32_t *iv_d; + + /*save space for iv */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + + m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len; + m_dma += OFF_CTRL_LEN + iv_len; + m_size -= OFF_CTRL_LEN + iv_len; + + opcode.s.major |= DMA_MODE; + + vq_cmd_w0.s.opcode = htobe16(opcode.flags); + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word followed by iv */ + + i = fill_sg_comp(gather_comp, i, offset_dma, + offset_vaddr, OFF_CTRL_LEN + iv_len); + + /* iv offset is 0 */ + *offset_vaddr = offset_ctrl; + + iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN); + memcpy(iv_d, iv, 16); + + /* input data */ + size = inputlen - iv_len; + if (size) { +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params->src_iov) + return ERR_BAD_INPUT_ARG; +#endif + + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, + 0, &size, NULL, 0); + if (size) + return ERR_BAD_INPUT_ARG; + } + ((uint16_t *)in_buffer)[2] = htobe16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = + (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + if (flags == 0x1) { + /* IV in SLIST only for EEA3 & UEA2 */ + iv_len = 0; + } + + if (iv_len) { + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, + (uint8_t *)offset_vaddr + OFF_CTRL_LEN, + iv_len); + } + + /* Add output data */ + if (req_flags & VALID_MAC_BUF) { + size = outputlen - iv_len - mac_len; + if (size) { +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params->dst_iov) + return ERR_BAD_INPUT_ARG; +#endif + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (size) + return ERR_BAD_INPUT_ARG; + } + + /* mac data */ + if (mac_len) { + i = fill_sg_comp_from_buf(scatter_comp, i, + ¶ms->mac_buf); + } + } else { + /* Output including mac */ + size = outputlen - iv_len; + if (size) { +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params->dst_iov) + return ERR_BAD_INPUT_ARG; +#endif + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (size) + return ERR_BAD_INPUT_ARG; + } + } + ((uint16_t *)in_buffer)[3] = htobe16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = htobe16(size); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + } + + /* First 16-bit swap then 64-bit swap */ + /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions + * to eliminate all the swapping + */ + vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64); + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, zs_ctx); + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!(m_size >= 0)) { + PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n", + m_size); + abort(); + } +#endif + *prep_req = req; + return 0; +} + +static inline int +cpt_zuc_snow3g_dec_prep(uint32_t req_flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + void **prep_req) +{ + uint32_t size; + int32_t inputlen = 0, outputlen; + struct cpt_ctx *cpt_ctx; + uint8_t snow3g, iv_len = 16; + cpt_request_info_t *req; + buf_ptr_t *buf_p; + uint32_t encr_offset; + uint32_t encr_data_len; + int flags, m_size; + void *m_vaddr, *c_vaddr; + uint64_t m_dma, c_dma; + uint64_t *offset_vaddr, offset_dma; + uint32_t *iv_s, iv[4], j; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + opcode_info_t opcode; + + (void)req_flags; + buf_p = ¶ms->meta_buf; +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params || !buf_p->vaddr || !buf_p->size) + return ERR_BAD_INPUT_ARG; +#endif + m_vaddr = buf_p->vaddr; + m_dma = buf_p->dma_addr; + m_size = buf_p->size; + + /* + * Microcode expects offsets in bytes + * TODO: Rounding off + */ + encr_offset = ENCR_OFFSET(d_offs) / 8; + encr_data_len = ENCR_DLEN(d_lens); + + cpt_ctx = params->ctx_buf.vaddr; + flags = cpt_ctx->zsk_flags; + snow3g = cpt_ctx->snow3g; +#ifdef CPTVF_STRICT_PARAM_CHECK + if (flags != 0) { + /* Dec not supported for EIA3 or UIA2 */ + return ERR_BAD_INPUT_ARG; + } +#endif + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Reserve memory for cpt request info */ + req = m_vaddr; + + size = sizeof(cpt_request_info_t); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Initialising ctrl and opcode + * fields for cpt request + */ + + req->se_req = SE_CORE_REQ; + req->dma_mode = CTRL_DMA_MODE_SGIO; + + opcode.s.major = MAJOR_OP_ZUC_SNOW3G; + + /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */ + opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) | + (0 << 3) | (flags & 0x7)); + + /* consider iv len */ + encr_offset += iv_len; + + inputlen = encr_offset + + (RTE_ALIGN(encr_data_len, 8) / 8); + outputlen = inputlen; + + /* IV */ + iv_s = params->iv_buf; + if (snow3g) { + /* + * DPDK seems to provide it in form of IV3 IV2 IV1 IV0 + * and BigEndian, MC needs it as IV0 IV1 IV2 IV3 + */ + + for (j = 0; j < 4; j++) + iv[j] = iv_s[3 - j]; + } else { + /* ZUC doesn't need a swap */ + for (j = 0; j < 4; j++) + iv[j] = iv_s[j]; + } + + /* + * GP op header, lengths are expected in bits. + */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = htobe16(encr_data_len); + + /* + * In 83XX since we have a limitation of + * IV & Offset control word not part of instruction + * and need to be part of Data Buffer, we check if + * head room is there and then only do the Direct mode processing + */ + if (likely((req_flags & SINGLE_BUF_INPLACE) && + (req_flags & SINGLE_BUF_HEADTAILROOM))) { + void *dm_vaddr = params->bufs[0].vaddr; + uint64_t dm_dma_addr = params->bufs[0].dma_addr; + /* + * This flag indicates that there is 24 bytes head room and + * 8 bytes tail room available, so that we get to do + * DIRECT MODE with limitation + */ + + offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr - + OFF_CTRL_LEN - iv_len); + offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len; + + /* DPTR */ + req->ist.ei1 = offset_dma; + /* RPTR should just exclude offset control word */ + req->ist.ei2 = dm_dma_addr - iv_len; + req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr + + outputlen - iv_len); + /* *req->alternate_caddr = ((uint64_t)0xdeadbeefdeadbeef) */ + + vq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN); + + vq_cmd_w0.s.opcode = htobe16(opcode.flags); + + if (likely(iv_len)) { + uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr + + OFF_CTRL_LEN); + memcpy(iv_d, iv, 16); + } + + /* iv offset is 0 */ + *offset_vaddr = htobe64((uint64_t)encr_offset << 16); + } else { + uint32_t i, g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + uint8_t *in_buffer; + uint32_t *iv_d; + + /* save space for offset and iv... */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + + m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len; + m_dma += OFF_CTRL_LEN + iv_len; + m_size -= OFF_CTRL_LEN + iv_len; + + opcode.s.major |= DMA_MODE; + + vq_cmd_w0.s.opcode = htobe16(opcode.flags); + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word */ + + /* iv offset is 0 */ + *offset_vaddr = htobe64((uint64_t)encr_offset << 16); + + i = fill_sg_comp(gather_comp, i, offset_dma, offset_vaddr, + OFF_CTRL_LEN + iv_len); + + iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN); + memcpy(iv_d, iv, 16); + + /* Add input data */ + size = inputlen - iv_len; + if (size) { +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params->src_iov) + return ERR_BAD_INPUT_ARG; +#endif + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, + 0, &size, NULL, 0); + if (size) + return ERR_BAD_INPUT_ARG; + } + ((uint16_t *)in_buffer)[2] = htobe16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = + (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + /* IV */ + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, + (uint8_t *)offset_vaddr + OFF_CTRL_LEN, + iv_len); + + /* Add output data */ + size = outputlen - iv_len; + if (size) { +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params->dst_iov) + return ERR_BAD_INPUT_ARG; +#endif + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (size) + return ERR_BAD_INPUT_ARG; + } + ((uint16_t *)in_buffer)[3] = htobe16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = htobe16(size); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + } + + /* First 16-bit swap then 64-bit swap */ + /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions + * to eliminate all the swapping + */ + vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64); + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, zs_ctx); + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!(m_size >= 0)) { + PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n", + m_size); + abort(); + } +#endif + *prep_req = req; + return 0; +} + void * cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, @@ -1289,6 +1950,9 @@ static inline int __attribute__((always_inline)) if (likely(fc_type == FC_GEN)) { ret = cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, op, &prep_req); + } else if (fc_type == ZUC_SNOW3G) { + ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, + fc_params, op, &prep_req); } else { /* * For AUTH_ONLY case, @@ -1319,6 +1983,9 @@ static inline int __attribute__((always_inline)) if (likely(fc_type == FC_GEN)) { ret = cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, op, &prep_req); + } else if (fc_type == ZUC_SNOW3G) { + ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, + fc_params, op, &prep_req); } else { ret = ERR_EIO; } From patchwork Fri Jun 8 16:45:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 40869 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EB8D21BB7F; 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SN6PR07MB4911; 6:yS8YfueQgEvBCPahVNPL1uGlxYQOvhbCG/G/7iJO0FAbNpRALMHWCU7jwKtRqL65aFJq74p8vOI6vdI5ei55rR7q537RQhogvbIpDmvvXBsXph96W0/czM3Why4adaeUtJ1Ef/0U7uKIoo/MGalsu2zidrSJSeTxRFHFUJRF8mtnlh9+3p01cPLNvHyUDNR6RaZfwpVdel+4ggjsMcQhg0Yrwb1lMK2nqWoIqsVNAPEoXm3KpdYpg+WVW70Fb3Bf7mJXyZheMvaXW435x8phUgBB/Syxh+hrrbiMacUgw5M01uK/4rsab5NjtkcTXZzfwcLB54FLGle9ZBggXrhvxRf2w94o1sdnCoTOnIchE7pIO4iK3Mf62rwlhrFrMSYqxQXjsNcAMiRPCw+BAGhAI9X0iX9McYDQs40bhBUmV/dUMIfmXh0FpHSj16HcigAJ12Wu2dAQWvxhh56AdRXfqQ==; 5:lZYUABTu41FsiAEJvKeF0cYqUzhmIIqLlkpf/V/Awcox/zQR06sWobcD15dVQfhNqvTbC183+WgpRZZEbFudRwZ6Wpg+dxxHFu4sG5whz6TLQwVClb5e9ZHWxG7sCQSeVJ5029jY1/hule6x6rzCCa375ClHR/ijxyMLOo0iIgM=; 24:PnK+ixKDu1gtdfisK7KLzkuDExTj9osYLS2sVwj/P4YJXAfU8LzCMA47qwP6sq4yeJ9tNaH5tWZKNn9ertS6Hg6WrT/UK7SqJwy1jyWWoR4= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; SN6PR07MB4911; 7:sNRt6gvb2QwBHhUGYv7m0HUgFflkme6LZ9+e8/fGjdHYP1sicd1ZQna5krZoLswsFp0poWFNBktZnp+M7DpWeP4jq3jGygKxCOaZDAXu1IgEvCH/EcNRoZ1++gAUpOf8DMRwWVgg1YSBUMFFo+Ev/FWbjTC4PPq1+ZLWH3qx/tPtpnyD6O9h2Tc/dI9cjV14ES09z8pBoBTVVh+sI1V47+bHMM+Zkdd5s2bk19uPPbnPe4mwAwPQ02U8aACHqSSD X-MS-Office365-Filtering-Correlation-Id: 2024047b-88dd-4cd9-0940-08d5cd5fc3f8 X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2018 16:49:10.0965 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2024047b-88dd-4cd9-0940-08d5cd5fc3f8 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR07MB4911 Subject: [dpdk-dev] [PATCH 08/16] crypto/cpt/base: add request prepare API for Kasumi X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Murthy NSSR These functions help in preparing symmetric crypto request for Kasumi of both cipher and auth but not cipher+auth in single xform. Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/base/cpt_ops.c | 545 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 545 insertions(+) diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c index ff7522a..15c3413 100644 --- a/drivers/crypto/cpt/base/cpt_ops.c +++ b/drivers/crypto/cpt/base/cpt_ops.c @@ -1933,6 +1933,545 @@ static inline int __attribute__((always_inline)) return 0; } +static int +cpt_kasumi_enc_prep(uint32_t req_flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + void **prep_req) +{ + uint32_t size; + int32_t inputlen = 0, outputlen = 0; + struct cpt_ctx *cpt_ctx; + uint32_t mac_len = 0; + uint8_t i = 0; + cpt_request_info_t *req; + buf_ptr_t *buf_p; + uint32_t encr_offset, auth_offset; + uint32_t encr_data_len, auth_data_len; + int flags, m_size; + uint8_t *iv_s, *iv_d, iv_len = 8; + uint8_t dir = 0; + void *m_vaddr, *c_vaddr; + uint64_t m_dma, c_dma; + uint64_t *offset_vaddr, offset_dma; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + opcode_info_t opcode; + uint8_t *in_buffer; + uint32_t g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + + buf_p = ¶ms->meta_buf; +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params || !buf_p->vaddr || !buf_p->size) + return ERR_BAD_INPUT_ARG; +#endif + m_vaddr = buf_p->vaddr; + m_dma = buf_p->dma_addr; + m_size = buf_p->size; + + encr_offset = ENCR_OFFSET(d_offs) / 8; + auth_offset = AUTH_OFFSET(d_offs) / 8; + encr_data_len = ENCR_DLEN(d_lens); + auth_data_len = AUTH_DLEN(d_lens); + + cpt_ctx = params->ctx_buf.vaddr; + flags = cpt_ctx->zsk_flags; + mac_len = cpt_ctx->mac_len; + +#ifdef CPTVF_STRICT_PARAM_CHECK + if (flags == 0x0) { + /* F8 Mode */ + if (auth_offset || auth_data_len) + return ERR_BAD_INPUT_ARG; + + if (!params->iv_buf) + return ERR_BAD_INPUT_ARG; + } else if (flags == 0x1) { + /* F9 mode */ + if (encr_offset || encr_data_len) + return ERR_BAD_INPUT_ARG; + + if (!params->auth_iv_buf) + return ERR_BAD_INPUT_ARG; + } else { + return ERR_EIO; + } +#endif + if (flags == 0x0) + iv_s = params->iv_buf; + else + iv_s = params->auth_iv_buf; + + dir = iv_s[8] & 0x1; + + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Reserve memory for cpt request info */ + req = m_vaddr; + + size = sizeof(cpt_request_info_t); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Initialising ctrl and opcode + * fields for cpt request + */ + + req->se_req = SE_CORE_REQ; + req->dma_mode = CTRL_DMA_MODE_SGIO; + + opcode.s.major = MAJOR_OP_KASUMI | DMA_MODE; + + /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */ + opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) | + (dir << 4) | (0 << 3) | (flags & 0x7)); + + /* + * GP op header, lengths are expected in bits. + */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = htobe16(encr_data_len); + vq_cmd_w0.s.param2 = htobe16(auth_data_len); + vq_cmd_w0.s.opcode = htobe16(opcode.flags); + + /* consider iv len */ + if (flags == 0x0) { + encr_offset += iv_len; + auth_offset += iv_len; + } + + /* save space for offset ctrl and iv */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + + m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len; + m_dma += OFF_CTRL_LEN + iv_len; + m_size -= OFF_CTRL_LEN + iv_len; + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word followed by iv */ + + if (flags == 0x0) { + inputlen = encr_offset + + (RTE_ALIGN(encr_data_len, 8) / 8); + outputlen = inputlen; + /* iv offset is 0 */ + *offset_vaddr = htobe64((uint64_t)encr_offset << 16); + } else { + inputlen = auth_offset + + (RTE_ALIGN(auth_data_len, 8) / 8); + outputlen = mac_len; + /* iv offset is 0 */ + *offset_vaddr = htobe64((uint64_t)auth_offset); + } + + i = fill_sg_comp(gather_comp, i, offset_dma, + offset_vaddr, OFF_CTRL_LEN + iv_len); + + /* IV */ + iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN; + memcpy(iv_d, iv_s, iv_len); + + /* input data */ + size = inputlen - iv_len; + if (size) { +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params->src_iov) + return ERR_BAD_INPUT_ARG; +#endif + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, 0, + &size, NULL, 0); + + if (size) + return ERR_BAD_INPUT_ARG; + } + ((uint16_t *)in_buffer)[2] = htobe16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = + (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + if (flags == 0x1) { + /* IV in SLIST only for F8 */ + iv_len = 0; + } + + /* IV */ + if (iv_len) { + + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, + (uint8_t *)offset_vaddr + OFF_CTRL_LEN, + iv_len); + } + + /* Add output data */ + if (req_flags & VALID_MAC_BUF) { + size = outputlen - iv_len - mac_len; + if (size) { +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params->dst_iov) + return ERR_BAD_INPUT_ARG; +#endif + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (size) + return ERR_BAD_INPUT_ARG; + } + + /* mac data */ + if (mac_len) { + i = fill_sg_comp_from_buf(scatter_comp, i, + ¶ms->mac_buf); + } + } else { + /* Output including mac */ + size = outputlen - iv_len; + if (size) { +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params->dst_iov) + return ERR_BAD_INPUT_ARG; +#endif + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (size) + return ERR_BAD_INPUT_ARG; + } + } + ((uint16_t *)in_buffer)[3] = htobe16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = htobe16(size); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + + /* First 16-bit swap then 64-bit swap */ + /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions + * to eliminate all the swapping + */ + vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64); + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, k_ctx); + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!(m_size >= 0)) { + PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n", + m_size); + abort(); + } +#endif + *prep_req = req; + return 0; +} + + +static inline int +cpt_kasumi_dec_prep(uint32_t req_flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + void **prep_req) +{ + uint32_t size; + int32_t inputlen = 0, outputlen; + struct cpt_ctx *cpt_ctx; + uint8_t i = 0, iv_len = 8; + cpt_request_info_t *req; + buf_ptr_t *buf_p; + uint32_t encr_offset; + uint32_t encr_data_len; + int flags, m_size; + uint8_t dir = 0; + void *m_vaddr, *c_vaddr; + uint64_t m_dma, c_dma; + uint64_t *offset_vaddr, offset_dma; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + opcode_info_t opcode; + uint8_t *in_buffer; + uint32_t g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + + (void)req_flags; + buf_p = ¶ms->meta_buf; +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params || !buf_p->vaddr || !buf_p->size) + return ERR_BAD_INPUT_ARG; +#endif + m_vaddr = buf_p->vaddr; + m_dma = buf_p->dma_addr; + m_size = buf_p->size; + + encr_offset = ENCR_OFFSET(d_offs) / 8; + encr_data_len = ENCR_DLEN(d_lens); + + cpt_ctx = params->ctx_buf.vaddr; + flags = cpt_ctx->zsk_flags; +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params->iv_buf) + return ERR_BAD_INPUT_ARG; +#endif +#ifdef CPTVF_STRICT_PARAM_CHECK + if (flags != 0) { + /* Dec not supported for F9 */ + return ERR_BAD_INPUT_ARG; + } +#endif + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Reserve memory for cpt request info */ + req = m_vaddr; + + size = sizeof(cpt_request_info_t); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Initialising ctrl and opcode + * fields for cpt req + */ + + req->se_req = SE_CORE_REQ; + req->dma_mode = CTRL_DMA_MODE_SGIO; + + opcode.s.major = MAJOR_OP_KASUMI | DMA_MODE; + + /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */ + opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) | + (dir << 4) | (0 << 3) | (flags & 0x7)); + + /* + * GP op header, lengths are expected in bits. + */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = htobe16(encr_data_len); + vq_cmd_w0.s.opcode = htobe16(opcode.flags); + + /* consider iv len */ + encr_offset += iv_len; + + inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8); + outputlen = inputlen; + + /* save space for offset ctrl & iv */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + + m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len; + m_dma += OFF_CTRL_LEN + iv_len; + m_size -= OFF_CTRL_LEN + iv_len; + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word followed by iv */ + *offset_vaddr = htobe64((uint64_t)encr_offset << 16); + + i = fill_sg_comp(gather_comp, i, offset_dma, offset_vaddr, + OFF_CTRL_LEN + iv_len); + + + /* IV */ + memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN, + params->iv_buf, iv_len); + + /* Add input data */ + size = inputlen - iv_len; + if (size) { +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params->src_iov) + return ERR_BAD_INPUT_ARG; +#endif + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, + 0, &size, NULL, 0); + if (size) + return ERR_BAD_INPUT_ARG; + } + ((uint16_t *)in_buffer)[2] = htobe16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = + (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + /* IV */ + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, + (uint8_t *)offset_vaddr + OFF_CTRL_LEN, + iv_len); + + /* Add output data */ + size = outputlen - iv_len; + if (size) { +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!params->dst_iov) + return ERR_BAD_INPUT_ARG; +#endif + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + if (size) + return ERR_BAD_INPUT_ARG; + } + ((uint16_t *)in_buffer)[3] = htobe16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = htobe16(size); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + + /* First 16-bit swap then 64-bit swap */ + /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions + * to eliminate all the swapping + */ + vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64); + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, k_ctx); + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!(m_size >= 0)) + abort(); +#endif + *prep_req = req; + return 0; +} + void * cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, @@ -1953,6 +2492,9 @@ static inline int __attribute__((always_inline)) } else if (fc_type == ZUC_SNOW3G) { ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params, op, &prep_req); + } else if (fc_type == KASUMI) { + ret = cpt_kasumi_dec_prep(flags, d_offs, d_lens, + fc_params, op, &prep_req); } else { /* * For AUTH_ONLY case, @@ -1986,6 +2528,9 @@ static inline int __attribute__((always_inline)) } else if (fc_type == ZUC_SNOW3G) { ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params, op, &prep_req); + } else if (fc_type == KASUMI) { + ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens, + fc_params, op, &prep_req); } else { ret = ERR_EIO; } From patchwork Fri Jun 8 16:45:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 40870 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BC57B47CD; Fri, 8 Jun 2018 18:49:21 +0200 (CEST) Received: from NAM04-SN1-obe.outbound.protection.outlook.com (mail-eopbgr700054.outbound.protection.outlook.com [40.107.70.54]) by dpdk.org (Postfix) with ESMTP id 8DDF11BA9E for ; Fri, 8 Jun 2018 18:49:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; 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Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/base/cpt_ops.c | 215 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+) diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c index 15c3413..eb25607 100644 --- a/drivers/crypto/cpt/base/cpt_ops.c +++ b/drivers/crypto/cpt/base/cpt_ops.c @@ -450,6 +450,218 @@ int32_t cpt_fc_get_ctx_len(void) return (uint32_t)i; } +static int +cpt_digest_gen_prep(uint32_t flags, + uint64_t d_offs, + uint64_t d_lens, + digest_params_t *params, + void *op, + void **prep_req) +{ + cpt_request_info_t *req; + uint32_t size, i; + int32_t m_size; + uint16_t data_len, mac_len, key_len; + auth_type_t hash_type; + buf_ptr_t *meta_p; + struct cpt_ctx *ctx; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + uint8_t *in_buffer; + uint32_t g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + void *c_vaddr, *m_vaddr; + uint64_t c_dma, m_dma; + opcode_info_t opcode; + + if (!params || !params->ctx_buf.vaddr) + return ERR_BAD_INPUT_ARG; + + (void)d_offs; + ctx = params->ctx_buf.vaddr; + meta_p = ¶ms->meta_buf; + + if (!meta_p->vaddr || !meta_p->dma_addr) + return ERR_BAD_INPUT_ARG; + + if (meta_p->size < sizeof(cpt_request_info_t)) + return ERR_BAD_INPUT_ARG; + + m_vaddr = meta_p->vaddr; + m_dma = meta_p->dma_addr; + m_size = meta_p->size; + + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + req = m_vaddr; + + size = sizeof(cpt_request_info_t); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Initialising ctrl and opcode fields */ + + req->dma_mode = CTRL_DMA_MODE_SGIO; + req->se_req = SE_CORE_REQ; + + hash_type = ctx->hash_type; + mac_len = ctx->mac_len; + key_len = ctx->auth_key_len; + data_len = AUTH_DLEN(d_lens); + + /*GP op header */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param2 = htobe16(((uint16_t)hash_type << 8)); + if (ctx->hmac) { + opcode.s.major = MAJOR_OP_HMAC | DMA_MODE; + vq_cmd_w0.s.param1 = htobe16(key_len); + vq_cmd_w0.s.dlen = htobe16((data_len + ROUNDUP8(key_len))); + } else { + opcode.s.major = MAJOR_OP_HASH | DMA_MODE; + vq_cmd_w0.s.param1 = 0; + vq_cmd_w0.s.dlen = htobe16(data_len); + } + + opcode.s.minor = 0; + + vq_cmd_w0.s.opcode = htobe16(opcode.flags); + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input gather list + */ + + i = 0; + + if (ctx->hmac) { + uint64_t k_dma = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, auth_key); + /* Key */ + i = fill_sg_comp(gather_comp, i, k_dma, + ctx->auth_key, ROUNDUP8(key_len)); + } + + /* input data */ + size = data_len; + if (size) { + i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov, + 0, &size, NULL, 0); + if (size) { + PMD_TX_LOG(DEBUG, "Insufficient dst IOV size, short by" + " %dB\n", size); + return ERR_BAD_INPUT_ARG; + } + } else { + /* + * Looks like we need to support zero data + * gather ptr in case of hash & hmac + */ + i++; + } + ((uint16_t *)in_buffer)[2] = htobe16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + + /* + * Output Gather list + */ + + i = 0; + scatter_comp = + (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + if (flags & VALID_MAC_BUF) { + if (params->mac_buf.size < mac_len) + return ERR_BAD_INPUT_ARG; + + size = mac_len; + i = fill_sg_comp_from_buf_min(scatter_comp, i, + ¶ms->mac_buf, &size); + } else { + size = mac_len; + i = fill_sg_comp_from_iov(scatter_comp, i, + params->src_iov, data_len, + &size, NULL, 0); + if (size) { + PMD_TX_LOG(DEBUG, "Insufficient dst IOV size, short by" + " %dB\n", size); + return ERR_BAD_INPUT_ARG; + } + } + + ((uint16_t *)in_buffer)[3] = htobe16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = htobe16(size); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + /* First 16-bit swap then 64-bit swap */ + /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions + * to eliminate all the swapping + */ + vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64); + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + +#ifdef CPTVF_STRICT_PARAM_CHECK + if (!(m_size >= 0)) + abort(); +#endif + *prep_req = req; + return 0; +} + static inline int __attribute__((always_inline)) cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, @@ -2531,6 +2743,9 @@ static inline int __attribute__((always_inline)) } else if (fc_type == KASUMI) { ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens, fc_params, op, &prep_req); + } else if (fc_type == HASH_HMAC) { + ret = cpt_digest_gen_prep(flags, d_offs, d_lens, + fc_params, op, &prep_req); } else { ret = ERR_EIO; } From patchwork Fri Jun 8 16:45:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 40871 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 589D75F30; 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Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/Makefile | 9 +- drivers/crypto/cpt/cpt_pmd_cryptodev.c | 270 +++++++++++++++++++++++++++++++++ drivers/crypto/cpt/cpt_pmd_logs.h | 50 ++++++ 3 files changed, 328 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/cpt/cpt_pmd_cryptodev.c create mode 100644 drivers/crypto/cpt/cpt_pmd_logs.h diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile index b2d950d..40ec9e2 100644 --- a/drivers/crypto/cpt/Makefile +++ b/drivers/crypto/cpt/Makefile @@ -23,7 +23,14 @@ CFLAGS += -O3 #CFLAGS += -DAUTH_SOFT_COMPUTE_IPAD_OPAD #CFLAGS += -DCPT_DEBUG -SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += +# PMD code +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_pmd_cryptodev.c + +# Base code +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_device.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_ops.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt8xxx_device.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_vf_mbox.c # export include files SYMLINK-y-include += diff --git a/drivers/crypto/cpt/cpt_pmd_cryptodev.c b/drivers/crypto/cpt/cpt_pmd_cryptodev.c new file mode 100644 index 0000000..addddd8 --- /dev/null +++ b/drivers/crypto/cpt/cpt_pmd_cryptodev.c @@ -0,0 +1,270 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "base/cpt_device.h" +#include "cpt_pmd_logs.h" + +#define CSP_INTR_POLL_INTERVAL_MS 50 + +static int global_init_done; +uint8_t cryptodev_cpt_driver_id; +struct rte_mempool *cpt_meta_pool; +int cpt_op_mlen; +int cpt_op_sb_mlen; + +static void +cpt_pmd_alarm_cb(void *arg) +{ + struct cpt_vf *cptvf = arg; + cptvf_poll_misc(cptvf); + rte_eal_alarm_set(CSP_INTR_POLL_INTERVAL_MS * 1000, + cpt_pmd_alarm_cb, cptvf); +} + +static int +cpt_pmd_periodic_alarm_start(void *arg) +{ + return rte_eal_alarm_set(CSP_INTR_POLL_INTERVAL_MS * 1000, + cpt_pmd_alarm_cb, arg); +} + +static int +cpt_pmd_periodic_alarm_stop(void *arg) +{ + return rte_eal_alarm_cancel(cpt_pmd_alarm_cb, arg); +} + +static struct rte_cryptodev_ops cptvf_ops = { + /* Device related operations */ + .dev_configure = NULL, + .dev_start = NULL, + .dev_stop = NULL, + .dev_close = NULL, + .dev_infos_get = NULL, + + .stats_get = NULL, + .stats_reset = NULL, + .queue_pair_setup = NULL, + .queue_pair_release = NULL, + .queue_pair_start = NULL, + .queue_pair_stop = NULL, + .queue_pair_count = NULL, + + /* Crypto related operations */ + .session_get_size = NULL, + .session_configure = NULL, + .session_clear = NULL +}; + +static int init_global_resources(void) +{ + /* In future consider rte_security and asym. 4B extra for app use */ + cpt_op_mlen = cpt_fc_get_op_meta_len() + 4 * sizeof(uint64_t); + cpt_meta_pool = rte_mempool_create("cpt_metabuf-pool", 4096 * 16, + cpt_op_mlen, 512, 0, + NULL, NULL, NULL, NULL, + SOCKET_ID_ANY, 0); + if (!cpt_meta_pool) { + PMD_DRV_LOG(ERR, "cpt metabuf pool not created\n"); + return -ENOMEM; + } + cpt_op_sb_mlen = cpt_fc_get_op_sb_meta_len() + 4 * sizeof(uint64_t); + + return 0; +} + +static int +cptvf_dev_init(struct rte_pci_driver *c_drv __rte_unused, + struct rte_cryptodev *c_dev) +{ + struct rte_pci_device *pdev = RTE_DEV_TO_PCI(c_dev->device); + struct cpt_vf *cptvf = c_dev->data->dev_private; + void *reg_base; + char dev_name[32]; + int ret; + + PMD_DRV_LOG(DEBUG, ">>>"); + + if (pdev->mem_resource[0].phys_addr == 0ULL) + return -EIO; + + /* for secondary processes, we don't initialise any further as primary + * has already done this work. + */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + snprintf(dev_name, 32, "%02x:%02x.%x", + pdev->addr.bus, pdev->addr.devid, pdev->addr.function); + PMD_DRV_LOG(DEBUG, "Found CPT device %s", dev_name); + + reg_base = pdev->mem_resource[0].addr; + if (!reg_base) { + PMD_DRV_LOG(ERR, "Failed to map BAR0 of %s", dev_name); + ret = -ENODEV; + goto fail; + } + + ret = cptvf_init_device(cptvf, pdev, reg_base, dev_name, 0); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to init cptvf %s", dev_name); + return -EIO; + } + + /* Start off timer for mailbox interrupts */ + cpt_pmd_periodic_alarm_start(cptvf); + /* TODO Do we really need this to poll for mbox ?? */ + /* cptvf_enable_mbox_interrupts(cptvf); */ + + if (!global_init_done) { + /* cpt_set_debug_level(debug); */ + ret = init_global_resources(); + if (ret) + goto init_fail; + global_init_done = 1; + } + + c_dev->dev_ops = &cptvf_ops; + + c_dev->enqueue_burst = NULL; + c_dev->dequeue_burst = NULL; + + c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | + RTE_CRYPTODEV_FF_HW_ACCELERATED | + RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING; + + return 0; + +init_fail: + cpt_pmd_periodic_alarm_stop(cptvf); + cptvf_deinit_device(cptvf); + return ret; + +fail: + return ret; +} + +static int +rte_cptdev_pci_probe(struct rte_pci_driver *pci_drv, + struct rte_pci_device *pci_dev) +{ + struct rte_cryptodev *cryptodev; + + char cryptodev_name[RTE_CRYPTODEV_NAME_MAX_LEN]; + + int retval; + + if (pci_drv == NULL) + return -ENODEV; + + rte_pci_device_name(&pci_dev->addr, cryptodev_name, + sizeof(cryptodev_name)); + + cryptodev = rte_cryptodev_pmd_allocate(cryptodev_name, rte_socket_id()); + if (cryptodev == NULL) + return -ENOMEM; + + if (rte_eal_process_type() == RTE_PROC_PRIMARY) { + cryptodev->data->dev_private = + rte_zmalloc_socket( + "cryptodev private structure", + sizeof(struct cpt_vf), + RTE_CACHE_LINE_SIZE, + rte_socket_id()); + + if (cryptodev->data->dev_private == NULL) + rte_panic("Cannot allocate memzone for private " + "device data"); + } + + cryptodev->device = &pci_dev->device; + cryptodev->device->driver = &pci_drv->driver; + cryptodev->driver_id = cryptodev_cpt_driver_id; + + /* init user callbacks */ + TAILQ_INIT(&(cryptodev->link_intr_cbs)); + + /* Invoke PMD device initialization function */ + retval = cptvf_dev_init(pci_drv, cryptodev); + if (retval == 0) + return 0; + + PMD_DRV_LOG(ERR, "driver %s: crypto_dev_init(vendor_id=0x%x device_id=" + "0x%x) failed", pci_drv->driver.name, + (unsigned int) pci_dev->id.vendor_id, + (unsigned int) pci_dev->id.device_id); + + if (rte_eal_process_type() == RTE_PROC_PRIMARY) + rte_free(cryptodev->data->dev_private); + + cryptodev->attached = RTE_CRYPTODEV_DETACHED; + + return -ENXIO; +} + +static int +rte_cptdev_pci_remove(struct rte_pci_device *pci_dev) +{ + struct rte_cryptodev *cryptodev; + char cryptodev_name[RTE_CRYPTODEV_NAME_MAX_LEN]; + + if (pci_dev == NULL) + return -EINVAL; + + rte_pci_device_name(&pci_dev->addr, cryptodev_name, + sizeof(cryptodev_name)); + + cryptodev = rte_cryptodev_pmd_get_named_dev(cryptodev_name); + if (cryptodev == NULL) + return -ENODEV; + + if (pci_dev->driver == NULL) + return -ENODEV; + + /* free crypto device */ + rte_cryptodev_pmd_release_device(cryptodev); + + if (rte_eal_process_type() == RTE_PROC_PRIMARY) + rte_free(cryptodev->data->dev_private); + + cryptodev->device = NULL; + cryptodev->device->driver = NULL; + cryptodev->data = NULL; + + return 0; +} +static struct rte_pci_id pci_id_cpt_table[] = { + { + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CPT_81XX_PCI_VF_DEVICE_ID), + }, + /* sentinel */ + { + .device_id = 0 + }, +}; + +static struct rte_pci_driver cptvf_pmd = { + .id_table = pci_id_cpt_table, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, + .probe = rte_cptdev_pci_probe, + .remove = rte_cptdev_pci_remove, +}; +static struct cryptodev_driver cpt_crypto_drv; + +#define CRYPTODEV_NAME_CPT_SYM_PMD crypto_cpt +/* Cavium CPT Symmetric Crypto PMD device name */ + +RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_CPT_SYM_PMD, cptvf_pmd); +RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_CPT_SYM_PMD, pci_id_cpt_table); +RTE_PMD_REGISTER_CRYPTO_DRIVER(cpt_crypto_drv, cptvf_pmd.driver, + cryptodev_cpt_driver_id); diff --git a/drivers/crypto/cpt/cpt_pmd_logs.h b/drivers/crypto/cpt/cpt_pmd_logs.h new file mode 100644 index 0000000..d245d62 --- /dev/null +++ b/drivers/crypto/cpt/cpt_pmd_logs.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef _CPT_PMD_LOGS_H_ +#define _CPT_PMD_LOGS_H_ + +#include + +#define PMD_DRV_LOG_RAW(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, RTE_LOGTYPE_PMD, \ + "PMD: %s(): " fmt "\n", __func__, ##args) + +#ifdef RTE_LIBRTE_PMD_CPT_DEBUG_INIT + +#define PMD_INIT_FUNC_TRACE() PMD_DRV_LOG_RAW(DEBUG, " >>") +#define PMD_DRV_LOG(level, args...) \ + PMD_DRV_LOG_RAW(level, ##args) +#else + +#define PMD_DRV_LOG(...) do { } while (0) +#define PMD_INIT_FUNC_TRACE() do { } while (0) +#endif + +#ifdef RTE_LIBRTE_PMD_CPT_DEBUG_RX + +#define CPT_DEBUG +#define CPTVF_STRICT_PARAM_CHECK +#define PMD_RX_LOG(level, args...) \ + PMD_DRV_LOG_RAW(level, ##args) +#else + +#define PMD_RX_LOG(...) do { } while (0) +#endif + +#ifdef RTE_LIBRTE_PMD_CPT_DEBUG_TX + +#define CPT_DEBUG +#define CPTVF_STRICT_PARAM_CHECK + +#define PMD_TX_LOG(level, args...) \ + PMD_DRV_LOG_RAW(level, ##args) +#else + +#define PMD_TX_LOG(...) do { } while (0) +#endif + +#define PRINT printf + +#endif From patchwork Fri Jun 8 16:45:20 2018 Content-Type: text/plain; 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Adds the basic device operation functions for the cpt vf. 2. The probe/remove functions are staic so no need to declare in the header file. 3. Removing extra declaration for cpt_dev_periodic_alarm_stop in the header file. Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/Makefile | 1 + drivers/crypto/cpt/cpt_pmd_cryptodev.c | 13 +- drivers/crypto/cpt/cpt_pmd_ops.c | 544 +++++++++++++++++++++++++++++++++ drivers/crypto/cpt/cpt_pmd_ops.h | 64 ++++ 4 files changed, 616 insertions(+), 6 deletions(-) create mode 100644 drivers/crypto/cpt/cpt_pmd_ops.c create mode 100644 drivers/crypto/cpt/cpt_pmd_ops.h diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile index 40ec9e2..bf22c2b 100644 --- a/drivers/crypto/cpt/Makefile +++ b/drivers/crypto/cpt/Makefile @@ -25,6 +25,7 @@ CFLAGS += -O3 # PMD code SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_pmd_cryptodev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_pmd_ops.c # Base code SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_device.c diff --git a/drivers/crypto/cpt/cpt_pmd_cryptodev.c b/drivers/crypto/cpt/cpt_pmd_cryptodev.c index addddd8..3939b5e 100644 --- a/drivers/crypto/cpt/cpt_pmd_cryptodev.c +++ b/drivers/crypto/cpt/cpt_pmd_cryptodev.c @@ -13,6 +13,7 @@ #include "base/cpt_device.h" #include "cpt_pmd_logs.h" +#include "cpt_pmd_ops.h" #define CSP_INTR_POLL_INTERVAL_MS 50 @@ -38,7 +39,7 @@ cpt_pmd_alarm_cb, arg); } -static int +int cpt_pmd_periodic_alarm_stop(void *arg) { return rte_eal_alarm_cancel(cpt_pmd_alarm_cb, arg); @@ -46,11 +47,11 @@ static struct rte_cryptodev_ops cptvf_ops = { /* Device related operations */ - .dev_configure = NULL, - .dev_start = NULL, - .dev_stop = NULL, - .dev_close = NULL, - .dev_infos_get = NULL, + .dev_configure = cpt_pmd_dev_config, + .dev_start = cpt_pmd_dev_start, + .dev_stop = cpt_pmd_dev_stop, + .dev_close = cpt_pmd_dev_close, + .dev_infos_get = cptvf_dev_info_get, .stats_get = NULL, .stats_reset = NULL, diff --git a/drivers/crypto/cpt/cpt_pmd_ops.c b/drivers/crypto/cpt/cpt_pmd_ops.c new file mode 100644 index 0000000..2f066cb --- /dev/null +++ b/drivers/crypto/cpt/cpt_pmd_ops.c @@ -0,0 +1,544 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#include +#include +#include + +#include "cpt_pmd_logs.h" +#include "cpt_pmd_ops.h" +#include "base/cpt.h" +#include "base/cpt_device.h" + +struct cpt_sess_misc { + uint16_t cpt_op:4; + uint16_t zsk_flag:4; + uint16_t aes_gcm:1; + uint16_t aes_ctr:1; + uint16_t dir_dma_supp:1; /* Single frag DMA supported? */ + uint16_t is_gmac:1; + uint16_t aad_length; + uint8_t mac_len; + uint8_t iv_length; /**< IV length in bytes */ + uint8_t auth_iv_length; /**< Auth IV length in bytes */ + uint8_t rsvd1; + uint16_t iv_offset; /**< IV offset in bytes */ + uint16_t auth_iv_offset; /**< Auth IV offset in bytes */ + uint32_t salt; + phys_addr_t ctx_dma_addr; +}; + +/* Helper macros */ + +#define SRC_IOV_SIZE \ + (sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * MAX_SG_CNT)) +#define DST_IOV_SIZE \ + (sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * MAX_SG_CNT)) + +#define SESS_PRIV(__sess) \ + (void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc)) + +#define BYTE_LEN 8 + +/* #define CPT_ALWAYS_USE_SG_MODE */ +#define CPT_ALWAYS_USE_SEPARATE_BUF + +/* TODO: Add all other capabilities */ +static const struct rte_cryptodev_capabilities cpt_capabilities[] = { + { /* SHA1 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA1_HMAC, + .block_size = 64, + .key_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + .digest_size = { + .min = 1, + .max = 20, + .increment = 1 + }, + .aad_size = { 0 } + }, } + }, } + }, + { /* SHA224 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA224_HMAC, + .block_size = 64, + .key_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + .digest_size = { + .min = 1, + .max = 28, + .increment = 1 + }, + .aad_size = { 0 } + }, } + }, } + }, + { /* SHA256 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA256_HMAC, + .block_size = 64, + .key_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + .digest_size = { + .min = 1, + .max = 32, + .increment = 1 + }, + .aad_size = { 0 } + }, } + }, } + }, + { /* SHA384 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA384_HMAC, + .block_size = 64, + .key_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + .digest_size = { + .min = 1, + .max = 48, + .increment = 1 + }, + .aad_size = { 0 } + }, } + }, } + }, + { /* SHA512 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA512_HMAC, + .block_size = 128, + .key_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + .digest_size = { + .min = 1, + .max = 64, + .increment = 1 + }, + .aad_size = { 0 } + }, } + }, } + }, + { /* MD5 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_MD5_HMAC, + .block_size = 64, + .key_size = { + .min = 8, + .max = 64, + .increment = 8 + }, + .digest_size = { + .min = 1, + .max = 16, + .increment = 1 + }, + .aad_size = { 0 } + }, } + }, } + }, + { /* AES GCM */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD, + {.aead = { + .algo = RTE_CRYPTO_AEAD_AES_GCM, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .digest_size = { + .min = 8, + .max = 16, + .increment = 4 + }, + .aad_size = { + .min = 0, + .max = 1024, + .increment = 1 + }, + .iv_size = { + .min = 12, + .max = 12, + .increment = 0 + } + }, } + }, } + }, + { /* AES GMAC (AUTH) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_AES_GMAC, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .digest_size = { + .min = 8, + .max = 16, + .increment = 4 + }, + .aad_size = { + .min = 1, + .max = 65535, + .increment = 1 + } + }, } + }, } + }, + { /* SNOW 3G (UIA2) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .digest_size = { + .min = 4, + .max = 4, + .increment = 0 + }, + .aad_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* AES CBC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_AES_CBC, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* SNOW 3G (UEA2) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* AES CTR */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_AES_CTR, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* NULL (AUTH) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_NULL, + .block_size = 1, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .digest_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .aad_size = { 0 } + }, }, + }, }, + }, + { /* NULL (CIPHER) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_NULL, + .block_size = 1, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .iv_size = { + .min = 0, + .max = 0, + .increment = 0 + } + }, }, + }, } + }, + { /* KASUMI (F8) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_KASUMI_F8, + .block_size = 8, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .iv_size = { + .min = 8, + .max = 8, + .increment = 0 + } + }, } + }, } + }, + { /* ZUC (EIA3) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_ZUC_EIA3, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .digest_size = { + .min = 4, + .max = 4, + .increment = 0 + }, + .aad_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* ZUC (EEA3) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_ZUC_EEA3, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* KASUMI (F9) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_KASUMI_F9, + .block_size = 8, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .digest_size = { + .min = 4, + .max = 4, + .increment = 0 + }, + .aad_size = { + .min = 8, + .max = 8, + .increment = 0 + } + }, } + }, } + }, + { /* 3DES CBC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_3DES_CBC, + .block_size = 8, + .key_size = { + .min = 24, + .max = 24, + .increment = 0 + }, + .iv_size = { + .min = 8, + .max = 16, + .increment = 8 + } + }, } + }, } + }, + RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() +}; + +int cpt_pmd_dev_config(struct rte_cryptodev *dev __rte_unused, + struct rte_cryptodev_config *config __rte_unused) +{ + PMD_INIT_FUNC_TRACE(); + return 0; +} + +int cpt_pmd_dev_start(struct rte_cryptodev *c_dev __rte_unused) +{ + struct cpt_vf *cptvf = c_dev->data->dev_private; + + PMD_INIT_FUNC_TRACE(); + + return cptvf_start_device(cptvf); +} + +void cpt_pmd_dev_stop(struct rte_cryptodev *c_dev __rte_unused) +{ + struct cpt_vf *cptvf = c_dev->data->dev_private; + + PMD_INIT_FUNC_TRACE(); + + cptvf_stop_device(cptvf); +} + +int cpt_pmd_dev_close(struct rte_cryptodev *c_dev) +{ + struct cpt_vf *cptvf = c_dev->data->dev_private; + int i, ret; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < c_dev->data->nb_queue_pairs; i++) { + ret = cpt_pmd_que_pair_release(c_dev, i); + if (ret) + return ret; + } + cpt_pmd_periodic_alarm_stop(cptvf); + cptvf_deinit_device(cptvf); + + return 0; +} + +void +cptvf_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info) +{ + PMD_INIT_FUNC_TRACE(); + if (info != NULL) { + info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF; + info->feature_flags = dev->feature_flags; + info->capabilities = cpt_capabilities; + /* TODO: Hardcoding as of now */ + info->sym.max_nb_sessions = 128; + info->driver_id = cryptodev_cpt_driver_id; + } +} + +int +cpt_pmd_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id) +{ + cpt_instance_t *instance = dev->data->queue_pairs[que_pair_id]; + int ret; + + PMD_INIT_FUNC_TRACE(); + + ret = cptvf_put_resource(instance); + if (ret != 0) { + PMD_DRV_LOG(ERR, "Error putting instance handle" + " of device %s : ret = %d\n", dev->data->name, ret); + return ret; + } + + dev->data->queue_pairs[que_pair_id] = NULL; + + return 0; +} diff --git a/drivers/crypto/cpt/cpt_pmd_ops.h b/drivers/crypto/cpt/cpt_pmd_ops.h new file mode 100644 index 0000000..015b4a2 --- /dev/null +++ b/drivers/crypto/cpt/cpt_pmd_ops.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef __CPT_PMD_OPS_H_ +#define __CPT_PMD_OPS_H_ + +#include "base/cpt.h" + +#define CAVIUM_VENDOR_ID 0x177d +#define NITROXIII_DEV_ID 0x11 + +#define CSP_OP_CIPHER_ENCRYPT 0x1 +#define CSP_OP_CIPHER_DECRYPT 0x2 +#define CSP_OP_CIPHER_MASK 0x3 + +#define CSP_OP_AUTH_VERIFY 0x4 +#define CSP_OP_AUTH_GENERATE 0x8 +#define CSP_OP_AUTH_MASK 0xC + +#define CSP_OP_ENCODE (CSP_OP_CIPHER_ENCRYPT | CSP_OP_AUTH_GENERATE) +#define CSP_OP_DECODE (CSP_OP_CIPHER_DECRYPT | CSP_OP_AUTH_VERIFY) + +#define MAX_CIPHER_KEY_LEN 32 +#define MAX_AUTH_KEY_LEN 32 +#define DEFAULT_BLOCK_SIZE 64 + +#define CSP_DDMA_AUTH (1 << 1) +#define CSP_DDMA_ENC (1 << 2) +#define CSP_DDMA_SUPPORTED (CSP_DDMA_AUTH | CSP_DDMA_ENC) + +/* + * Space needed in packet for direct-dma operation. + * UCODE result & padding - 16 bytes max + * Result - 16 bytes + * struct cb_info size + */ +#define CSP_DDMA_EXTRA_SPACE (32 + sizeof(struct cpt_cb_info)) + +#define ZS_EA 0x1 +#define ZS_IA 0x2 +#define K_F8 0x4 +#define K_F9 0x8 + +extern uint8_t cryptodev_cpt_driver_id; +extern int cpt_pmd_periodic_alarm_stop(void *arg); +extern struct rte_mempool *cpt_meta_pool; +extern int cpt_op_mlen; +extern int cpt_op_sb_mlen; + +int cpt_pmd_dev_config(struct rte_cryptodev *dev __rte_unused, + struct rte_cryptodev_config *config __rte_unused); +int cpt_pmd_dev_start(struct rte_cryptodev *dev); + +void cpt_pmd_dev_stop(struct rte_cryptodev *dev); + +int cpt_pmd_dev_close(struct rte_cryptodev *dev); + +void cptvf_dev_info_get(struct rte_cryptodev *dev, + struct rte_cryptodev_info *inf); + +int cpt_pmd_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id); + +#endif From patchwork Fri Jun 8 16:45:21 2018 Content-Type: text/plain; charset="utf-8" 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24:Q0cxzoJs0pYGYyNQplq57nxrLgH+cBvA/feIaRri+uPu+SHII/3HWJUV3plfvqaGnLaCvjVjJKWncmYhyC4ZGuVlj4xC8YRovbxOX1NPY8s= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; SN6PR07MB4911; 7:wmBwksKqpJWIt8ONK5DYn4pADTebjbSDiE9AaAjNW67YiUJ6rS9ztSWUvVj1VDv/ysWaQtO2SHiLhbNosChadKr4S9QvxAunDHFlAoto0K+bT+/4Qjuky5XRrOg7VL4uyFREUoZTl6aG/wsYYcRbiHq/UpQjMriBHYxpGAUV7EOleuMUMCREHusn0rrM7JUD6M2TEdvVWYsSIoSzLVSBwhGRFpx5YbTigcFfFCZU4MerWW3PrYIAwB5vxcC8+Ipq X-MS-Office365-Filtering-Correlation-Id: 97e1f936-7df3-4973-4ea4-08d5cd5fcdd2 X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2018 16:49:26.5894 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97e1f936-7df3-4973-4ea4-08d5cd5fcdd2 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR07MB4911 Subject: [dpdk-dev] [PATCH 12/16] crypto/cpt: adds some more callback functions for CPT X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Srisivasubramanian Srinivasan This patch does the following: 1. Adds the stats callback functions for the cpt vf. 2. Adds the queue pair setup and queue pair release callback functions for cpt vf. Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/cpt_pmd_cryptodev.c | 8 ++--- drivers/crypto/cpt/cpt_pmd_ops.c | 63 ++++++++++++++++++++++++++++++++++ drivers/crypto/cpt/cpt_pmd_ops.h | 11 ++++++ 3 files changed, 78 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/cpt/cpt_pmd_cryptodev.c b/drivers/crypto/cpt/cpt_pmd_cryptodev.c index 3939b5e..3961ec8 100644 --- a/drivers/crypto/cpt/cpt_pmd_cryptodev.c +++ b/drivers/crypto/cpt/cpt_pmd_cryptodev.c @@ -53,10 +53,10 @@ .dev_close = cpt_pmd_dev_close, .dev_infos_get = cptvf_dev_info_get, - .stats_get = NULL, - .stats_reset = NULL, - .queue_pair_setup = NULL, - .queue_pair_release = NULL, + .stats_get = cpt_pmd_stats_get, + .stats_reset = cpt_pmd_stats_reset, + .queue_pair_setup = cpt_pmd_que_pair_setup, + .queue_pair_release = cpt_pmd_que_pair_release, .queue_pair_start = NULL, .queue_pair_stop = NULL, .queue_pair_count = NULL, diff --git a/drivers/crypto/cpt/cpt_pmd_ops.c b/drivers/crypto/cpt/cpt_pmd_ops.c index 2f066cb..1c60191 100644 --- a/drivers/crypto/cpt/cpt_pmd_ops.c +++ b/drivers/crypto/cpt/cpt_pmd_ops.c @@ -523,6 +523,69 @@ int cpt_pmd_dev_close(struct rte_cryptodev *c_dev) } } +void +cpt_pmd_stats_get(struct rte_cryptodev *dev __rte_unused, + struct rte_cryptodev_stats *stats __rte_unused) +{ + PMD_INIT_FUNC_TRACE(); +} + +void cpt_pmd_stats_reset(struct rte_cryptodev *dev __rte_unused) +{ + PMD_INIT_FUNC_TRACE(); +} + +int +cpt_pmd_que_pair_setup(struct rte_cryptodev *dev, + uint16_t que_pair_id, + const struct rte_cryptodev_qp_conf *qp_conf, + int socket_id __rte_unused, + struct rte_mempool *session_pool __rte_unused) +{ + struct cpt_vf *cptvf = dev->data->dev_private; + cpt_instance_t *instance = NULL; + struct rte_pci_device *pci_dev; + int ret = -1; + + PMD_INIT_FUNC_TRACE(); + + if (dev->data->queue_pairs[que_pair_id] != NULL) { + ret = cpt_pmd_que_pair_release(dev, que_pair_id); + if (ret) + return ret; + } + + if (qp_conf->nb_descriptors > DEFAULT_CMD_QLEN) { + PMD_DRV_LOG(INFO, "Number of descriptors too big %d," + " using default queue length of %d\n", + qp_conf->nb_descriptors, DEFAULT_CMD_QLEN); + } + + pci_dev = RTE_DEV_TO_PCI(dev->device); + + if (pci_dev->mem_resource[0].addr == NULL) { + PMD_DRV_LOG(ERR, "PCI mem address null"); + return -EIO; + } + + /* + * FIXME: We always setup a queue with DEFAULT_CMD_QLEN size + * in get_hw_resource. + */ + ret = cptvf_get_resource(cptvf, 0, &instance); + if (ret != 0) { + PMD_DRV_LOG(ERR, "Error getting instance handle" + " from device %s : ret = %d\n", + dev->data->name, ret); + return ret; + } + + instance->queue_id = que_pair_id; + dev->data->queue_pairs[que_pair_id] = instance; + + return 0; +} + int cpt_pmd_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id) { diff --git a/drivers/crypto/cpt/cpt_pmd_ops.h b/drivers/crypto/cpt/cpt_pmd_ops.h index 015b4a2..db2024b 100644 --- a/drivers/crypto/cpt/cpt_pmd_ops.h +++ b/drivers/crypto/cpt/cpt_pmd_ops.h @@ -58,7 +58,18 @@ int cpt_pmd_dev_config(struct rte_cryptodev *dev __rte_unused, void cptvf_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *inf); +int +cpt_pmd_que_pair_setup(struct rte_cryptodev *dev, + uint16_t que_pair_id, + const struct rte_cryptodev_qp_conf *qp_conf, + int socket_id, + struct rte_mempool *session_pool); int cpt_pmd_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id); +void cpt_pmd_stats_get(struct rte_cryptodev *dev, + struct rte_cryptodev_stats *stats); + +void cpt_pmd_stats_reset(struct rte_cryptodev *dev); + #endif From patchwork Fri Jun 8 16:45:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 40874 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B999F1BB82; Fri, 8 Jun 2018 18:49:38 +0200 (CEST) Received: from NAM04-SN1-obe.outbound.protection.outlook.com (mail-eopbgr700073.outbound.protection.outlook.com [40.107.70.73]) by dpdk.org (Postfix) with ESMTP id 0743E1BB82 for ; Fri, 8 Jun 2018 18:49:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=e8N+gFqXyyKGgp4qhnQv4GcJBS7tnikqC3Nc0sJrDcw=; b=oKmLAy0LHQv7xDvupIt6PKyK3w0O1Cl11nyj1etH3tfwweIUMeuoXM+bjP4xY/o3Hr5rrsH+wCyW/iVS/b9gC3yKAifl9kcYiokCVSapu2O4DqVKfs51e1wtvZyR+N24VQDIKkfByXAxwvzqKoHBGzDeqDEop6fDV5yJtvuOLfg= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Anoob.Joseph@cavium.com; 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The cipher keys, auth keys and aead keys are set during the session configure. Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/cpt_pmd_cryptodev.c | 6 +- drivers/crypto/cpt/cpt_pmd_ops.c | 470 +++++++++++++++++++++++++++++++++ drivers/crypto/cpt/cpt_pmd_ops.h | 11 + 3 files changed, 484 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/cpt/cpt_pmd_cryptodev.c b/drivers/crypto/cpt/cpt_pmd_cryptodev.c index 3961ec8..939f31b 100644 --- a/drivers/crypto/cpt/cpt_pmd_cryptodev.c +++ b/drivers/crypto/cpt/cpt_pmd_cryptodev.c @@ -62,9 +62,9 @@ .queue_pair_count = NULL, /* Crypto related operations */ - .session_get_size = NULL, - .session_configure = NULL, - .session_clear = NULL + .session_get_size = cpt_pmd_get_session_size, + .session_configure = cpt_pmd_session_cfg, + .session_clear = cpt_pmd_session_clear }; static int init_global_resources(void) diff --git a/drivers/crypto/cpt/cpt_pmd_ops.c b/drivers/crypto/cpt/cpt_pmd_ops.c index 1c60191..37808ce 100644 --- a/drivers/crypto/cpt/cpt_pmd_ops.c +++ b/drivers/crypto/cpt/cpt_pmd_ops.c @@ -605,3 +605,473 @@ void cpt_pmd_stats_reset(struct rte_cryptodev *dev __rte_unused) return 0; } + +unsigned int +cpt_pmd_get_session_size(struct rte_cryptodev *dev __rte_unused) +{ + return (sizeof(struct cpt_sess_misc) + + RTE_ALIGN_CEIL(cpt_fc_get_ctx_len(), 8)); +} + +static int +fill_sess_aead(cpt_instance_t *instance, struct rte_crypto_sym_xform *xform, + struct cpt_sess_misc *sess) +{ + struct rte_crypto_aead_xform *aead_form; + cipher_type_t enc_type = 0; /* NULL Cipher type */ + auth_type_t auth_type = 0; /* NULL Auth type */ + uint32_t cipher_key_len = 0; + uint8_t zsk_flag = 0, aes_gcm = 0; + aead_form = &xform->aead; + if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT && + aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) { + sess->cpt_op |= CSP_OP_CIPHER_ENCRYPT; + sess->cpt_op |= CSP_OP_AUTH_GENERATE; + } else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT && + aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) { + sess->cpt_op |= CSP_OP_CIPHER_DECRYPT; + sess->cpt_op |= CSP_OP_AUTH_VERIFY; + } else { + PMD_DRV_LOG(ERR, "Unknown cipher operation\n"); + return -1; + } + if (aead_form->key.length < cipher_key_len) { + PMD_DRV_LOG(ERR, "Invalid cipher params keylen %lu\n", + (unsigned int long)aead_form->key.length); + return -1; + } + switch (aead_form->algo) { + case RTE_CRYPTO_AEAD_AES_GCM: + enc_type = AES_GCM; + cipher_key_len = 16; + aes_gcm = 1; + break; + case RTE_CRYPTO_AEAD_AES_CCM: + PMD_DRV_LOG(ERR, "Crypto: Unsupported cipher alg %u", + aead_form->algo); + return -1; + default: + PMD_DRV_LOG(ERR, "Crypto: Undefined cipher algo %u specified", + aead_form->algo); + return -1; + } + sess->zsk_flag = zsk_flag; + sess->aes_gcm = aes_gcm; + sess->mac_len = aead_form->digest_length; + sess->iv_offset = aead_form->iv.offset; + sess->iv_length = aead_form->iv.length; + sess->aad_length = aead_form->aad_length; + cpt_fc_ciph_set_key(instance, + (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)), + enc_type, + aead_form->key.data, + aead_form->key.length, + NULL); + + cpt_fc_auth_set_key(instance, + (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)), + auth_type, + NULL, + 0, + aead_form->digest_length); + + return 0; +} +static int +fill_sess_cipher(cpt_instance_t *instance, struct rte_crypto_sym_xform *xform, + struct cpt_sess_misc *sess) +{ + struct rte_crypto_cipher_xform *c_form; + cipher_type_t enc_type = 0; /* NULL Cipher type */ + uint32_t cipher_key_len = 0; + uint8_t zsk_flag = 0, aes_gcm = 0, aes_ctr = 0; + + if (xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER) + return -1; + + c_form = &xform->cipher; + + if (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) + sess->cpt_op |= CSP_OP_CIPHER_ENCRYPT; + else if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT) + sess->cpt_op |= CSP_OP_CIPHER_DECRYPT; + else { + PMD_DRV_LOG(ERR, "Unknown cipher operation\n"); + return -1; + } + + switch (c_form->algo) { + case RTE_CRYPTO_CIPHER_AES_CBC: + enc_type = AES_CBC; + cipher_key_len = 16; + sess->dir_dma_supp |= CSP_DDMA_ENC; + break; + case RTE_CRYPTO_CIPHER_3DES_CBC: + enc_type = DES3_CBC; + cipher_key_len = 24; + break; + case RTE_CRYPTO_CIPHER_AES_CTR: + enc_type = AES_CTR; + cipher_key_len = 16; + aes_ctr = 1; + break; + case RTE_CRYPTO_CIPHER_NULL: + enc_type = 0; + break; + case RTE_CRYPTO_CIPHER_KASUMI_F8: + enc_type = KASUMI_F8_ECB; + cipher_key_len = 16; + zsk_flag = K_F8; + break; + case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: + enc_type = SNOW3G_UEA2; + cipher_key_len = 16; + zsk_flag = ZS_EA; + break; + case RTE_CRYPTO_CIPHER_ZUC_EEA3: + enc_type = ZUC_EEA3; + cipher_key_len = 16; + zsk_flag = ZS_EA; + break; + case RTE_CRYPTO_CIPHER_AES_XTS: + enc_type = AES_XTS; + cipher_key_len = 16; + break; + case RTE_CRYPTO_CIPHER_3DES_ECB: + enc_type = DES3_ECB; + cipher_key_len = 24; + break; + case RTE_CRYPTO_CIPHER_AES_ECB: + enc_type = AES_ECB; + cipher_key_len = 16; + break; + case RTE_CRYPTO_CIPHER_3DES_CTR: + case RTE_CRYPTO_CIPHER_AES_F8: + case RTE_CRYPTO_CIPHER_ARC4: + PMD_DRV_LOG(ERR, "Crypto: Unsupported cipher alg %u", + c_form->algo); + return -1; + default: + PMD_DRV_LOG(ERR, "Crypto: Undefined cipher algo %u specified", + c_form->algo); + return -1; + } + + if (c_form->key.length < cipher_key_len) { + PMD_DRV_LOG(ERR, "Invalid cipher params keylen %lu\n", + (unsigned long) c_form->key.length); + return -1; + } + + sess->zsk_flag = zsk_flag; + sess->aes_gcm = aes_gcm; + sess->aes_ctr = aes_ctr; + sess->iv_offset = c_form->iv.offset; + sess->iv_length = c_form->iv.length; + cpt_fc_ciph_set_key(instance, + SESS_PRIV(sess), + enc_type, + c_form->key.data, + c_form->key.length, + NULL); + + return 0; +} + +static int +fill_sess_auth(cpt_instance_t *instance, struct rte_crypto_sym_xform *xform, + struct cpt_sess_misc *sess) +{ + struct rte_crypto_auth_xform *a_form; + auth_type_t auth_type = 0; /* NULL Auth type */ + uint8_t zsk_flag = 0, aes_gcm = 0; + + if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH) + goto error_out; + + a_form = &xform->auth; + + if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY) + sess->cpt_op |= CSP_OP_AUTH_VERIFY; + else if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE) + sess->cpt_op |= CSP_OP_AUTH_GENERATE; + else { + PMD_DRV_LOG(ERR, "Unknown auth operation\n"); + return -1; + } + + if (a_form->key.length > 64) { + PMD_DRV_LOG(ERR, "Auth key length is big\n"); + return -1; + } + + switch (a_form->algo) { + case RTE_CRYPTO_AUTH_SHA1_HMAC: + sess->dir_dma_supp |= CSP_DDMA_AUTH; + /* Fall through */ + case RTE_CRYPTO_AUTH_SHA1: + auth_type = SHA1_TYPE; + break; + case RTE_CRYPTO_AUTH_SHA256_HMAC: + case RTE_CRYPTO_AUTH_SHA256: + auth_type = SHA2_SHA256; + break; + case RTE_CRYPTO_AUTH_SHA512_HMAC: + case RTE_CRYPTO_AUTH_SHA512: + auth_type = SHA2_SHA512; + break; + case RTE_CRYPTO_AUTH_AES_GMAC: + auth_type = GMAC_TYPE; + aes_gcm = 1; + break; + case RTE_CRYPTO_AUTH_SHA224_HMAC: + case RTE_CRYPTO_AUTH_SHA224: + auth_type = SHA2_SHA224; + break; + case RTE_CRYPTO_AUTH_SHA384_HMAC: + case RTE_CRYPTO_AUTH_SHA384: + auth_type = SHA2_SHA384; + break; + case RTE_CRYPTO_AUTH_MD5_HMAC: + case RTE_CRYPTO_AUTH_MD5: + auth_type = MD5_TYPE; + break; + case RTE_CRYPTO_AUTH_KASUMI_F9: + auth_type = KASUMI_F9_ECB; + /* + * Indicate that direction needs to be taken out + * from end of src + */ + zsk_flag = K_F9; + break; + case RTE_CRYPTO_AUTH_SNOW3G_UIA2: + auth_type = SNOW3G_UIA2; + zsk_flag = ZS_IA; + break; + case RTE_CRYPTO_AUTH_ZUC_EIA3: + auth_type = ZUC_EIA3; + zsk_flag = ZS_IA; + break; + case RTE_CRYPTO_AUTH_AES_XCBC_MAC: + case RTE_CRYPTO_AUTH_AES_CMAC: + case RTE_CRYPTO_AUTH_AES_CBC_MAC: + case RTE_CRYPTO_AUTH_NULL: + PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u", + a_form->algo); + goto error_out; + default: + PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified", + a_form->algo); + goto error_out; + } + + sess->zsk_flag = zsk_flag; + sess->aes_gcm = aes_gcm; + sess->mac_len = a_form->digest_length; + if (zsk_flag) { + sess->auth_iv_offset = a_form->iv.offset; + sess->auth_iv_length = a_form->iv.length; + } + cpt_fc_auth_set_key(instance, + SESS_PRIV(sess), + auth_type, + a_form->key.data, + a_form->key.length, + a_form->digest_length); + + return 0; + +error_out: + return -1; +} +static int +fill_sess_gmac(cpt_instance_t *instance, struct rte_crypto_sym_xform *xform, + struct cpt_sess_misc *sess) +{ + struct rte_crypto_auth_xform *a_form; + cipher_type_t enc_type = 0; /* NULL Cipher type */ + auth_type_t auth_type = 0; /* NULL Auth type */ + uint8_t zsk_flag = 0, aes_gcm = 0; + + if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH) + return -1; + + a_form = &xform->auth; + + if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE) + sess->cpt_op |= CSP_OP_ENCODE; + else if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY) + sess->cpt_op |= CSP_OP_DECODE; + else { + PMD_DRV_LOG(ERR, "Unknown auth operation\n"); + return -1; + } + + switch (a_form->algo) { + case RTE_CRYPTO_AUTH_AES_GMAC: + enc_type = AES_GCM; + auth_type = GMAC_TYPE; + break; + default: + PMD_DRV_LOG(ERR, "Crypto: Undefined cipher algo %u specified", + a_form->algo); + return -1; + } + + sess->zsk_flag = zsk_flag; + sess->aes_gcm = aes_gcm; + sess->is_gmac = 1; + sess->iv_offset = a_form->iv.offset; + sess->iv_length = a_form->iv.length; + sess->mac_len = a_form->digest_length; + cpt_fc_ciph_set_key(instance, + (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)), + enc_type, + a_form->key.data, + a_form->key.length, + NULL); + cpt_fc_auth_set_key(instance, + (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)), + auth_type, + NULL, + 0, + a_form->digest_length); + + return 0; +} + +static void +cpt_pmd_session_init(struct rte_mempool *mp __rte_unused, void *sym_sess, + uint8_t driver_id) +{ + struct rte_cryptodev_sym_session *sess = sym_sess; + struct cpt_sess_misc *cpt_sess = + (struct cpt_sess_misc *) get_session_private_data(sess, driver_id); + + PMD_INIT_FUNC_TRACE(); + cpt_sess->ctx_dma_addr = rte_mempool_virt2iova(cpt_sess) + + sizeof(struct cpt_sess_misc); +} + + +int cpt_pmd_session_cfg(struct rte_cryptodev *dev, + struct rte_crypto_sym_xform *xform, + struct rte_cryptodev_sym_session *sess, + struct rte_mempool *mempool) +{ + struct rte_crypto_sym_xform *chain; + void *sess_private_data; + + PMD_INIT_FUNC_TRACE(); + + /* + * Microcode only supports the following combination. + * Encryption followed by authentication + * Authentication followed by decryption + * Also zuc, kasumi and snow3g are not supported in + * aead mode(ie. cipher+auth), but only cipher or auth. + */ + if (xform->next) { + if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH) { + if ((xform->auth.algo == RTE_CRYPTO_AUTH_SNOW3G_UIA2) || + (xform->auth.algo == RTE_CRYPTO_AUTH_ZUC_EIA3) || + (xform->auth.algo == RTE_CRYPTO_AUTH_KASUMI_F9)) { + PMD_DRV_LOG(ERR, "Requested auth algorithm in " + "combination with cipher unsupported\n"); + goto err; + } + if ((xform->next->type == + RTE_CRYPTO_SYM_XFORM_CIPHER) && + (xform->next->cipher.op == + RTE_CRYPTO_CIPHER_OP_ENCRYPT)) { + PMD_DRV_LOG(ERR, "Unsupported combination by " + "microcode\n"); + goto err; + /* Unsupported as of now by microcode */ + } + } + if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) { + if ((xform->cipher.algo == + RTE_CRYPTO_CIPHER_SNOW3G_UEA2) || + (xform->cipher.algo == + RTE_CRYPTO_CIPHER_ZUC_EEA3) || + (xform->cipher.algo == + RTE_CRYPTO_CIPHER_KASUMI_F8)) { + PMD_DRV_LOG(ERR, "Requested cipher algorithm " + "in combination with auth unsupported\n"); + goto err; + } + if ((xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) && + (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT)) { + /* For GMAC auth there is no cipher operation */ + if ((xform->aead.algo != + RTE_CRYPTO_AEAD_AES_GCM) || + (xform->next->auth.algo != + RTE_CRYPTO_AUTH_AES_GMAC)) { + PMD_DRV_LOG(ERR, "Unsupported " + "combination by microcode\n"); + goto err; + /* Unsupported as of now by microcode */ + } + } + } + } + + if (unlikely(sess == NULL)) { + PMD_DRV_LOG(ERR, "invalid session struct"); + return -EINVAL; + } + + if (rte_mempool_get(mempool, &sess_private_data)) { + PMD_DRV_LOG(ERR, "Could not allocate sess_private_data\n"); + return -ENOMEM; + } + + chain = xform; + ((struct cpt_sess_misc *) sess_private_data)->dir_dma_supp = 0; + /* TODO: Need to restrict this loop to 2 chain elements? */ + while (chain) { + if (chain->type == RTE_CRYPTO_SYM_XFORM_AEAD) { + if (fill_sess_aead(NULL, chain, sess_private_data)) + goto err; + } else { + if (chain->type == RTE_CRYPTO_SYM_XFORM_CIPHER) { + if (fill_sess_cipher(NULL, chain, sess_private_data)) + goto err; + } else if (chain->type == RTE_CRYPTO_SYM_XFORM_AUTH) { + if (chain->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) { + if (fill_sess_gmac(NULL, chain, + sess_private_data)) + goto err; + } else { + if (fill_sess_auth(NULL, chain, sess_private_data)) + goto err; + } + } + } + chain = chain->next; + } + set_session_private_data(sess, dev->driver_id, sess_private_data); + cpt_pmd_session_init(NULL, sess, dev->driver_id); + return 0; + +err: + /* TODO: rte_mempool_put(); */ + return -EPERM; +} + +void +cpt_pmd_session_clear(struct rte_cryptodev *dev, + struct rte_cryptodev_sym_session *sess) +{ + void *session_private = get_session_private_data(sess, dev->driver_id); + + PMD_INIT_FUNC_TRACE(); + if (session_private) { + memset(session_private, 0, cpt_pmd_get_session_size(dev)); + struct rte_mempool *sess_mp = + rte_mempool_from_obj(session_private); + set_session_private_data(sess, dev->driver_id, NULL); + rte_mempool_put(sess_mp, session_private); + } +} diff --git a/drivers/crypto/cpt/cpt_pmd_ops.h b/drivers/crypto/cpt/cpt_pmd_ops.h index db2024b..314b2b1 100644 --- a/drivers/crypto/cpt/cpt_pmd_ops.h +++ b/drivers/crypto/cpt/cpt_pmd_ops.h @@ -72,4 +72,15 @@ void cpt_pmd_stats_get(struct rte_cryptodev *dev, void cpt_pmd_stats_reset(struct rte_cryptodev *dev); +unsigned int +cpt_pmd_get_session_size(struct rte_cryptodev *dev); + +int cpt_pmd_session_cfg(struct rte_cryptodev *dev, + struct rte_crypto_sym_xform *xform, + struct rte_cryptodev_sym_session *sess, + struct rte_mempool *mempool); + +void +cpt_pmd_session_clear(struct rte_cryptodev *dev, + struct rte_cryptodev_sym_session *sess); #endif From patchwork Fri Jun 8 16:45:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 40875 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 53D9C1BB0E; Fri, 8 Jun 2018 18:49:45 +0200 (CEST) Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on0045.outbound.protection.outlook.com [104.47.36.45]) by dpdk.org (Postfix) with ESMTP id B32801BB0E for ; Fri, 8 Jun 2018 18:49:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eiGo7RaG8qB3pVKcOrdElJOaAlgUEyioBfLa3KQDsUo=; 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Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/Makefile | 1 + drivers/crypto/cpt/cpt_pmd_cryptodev.c | 4 +- drivers/crypto/cpt/cpt_pmd_ops.c | 859 +++++++++++++++++++++++++++++++++ drivers/crypto/cpt/cpt_pmd_ops.h | 10 + 4 files changed, 872 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile index bf22c2b..63553e0 100644 --- a/drivers/crypto/cpt/Makefile +++ b/drivers/crypto/cpt/Makefile @@ -29,6 +29,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_pmd_ops.c # Base code SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_device.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_request_mgr.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_ops.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt8xxx_device.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_vf_mbox.c diff --git a/drivers/crypto/cpt/cpt_pmd_cryptodev.c b/drivers/crypto/cpt/cpt_pmd_cryptodev.c index 939f31b..45e052f 100644 --- a/drivers/crypto/cpt/cpt_pmd_cryptodev.c +++ b/drivers/crypto/cpt/cpt_pmd_cryptodev.c @@ -137,8 +137,8 @@ static int init_global_resources(void) c_dev->dev_ops = &cptvf_ops; - c_dev->enqueue_burst = NULL; - c_dev->dequeue_burst = NULL; + c_dev->enqueue_burst = cpt_pmd_pkt_enqueue; + c_dev->dequeue_burst = cpt_pmd_pkt_dequeue; c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | diff --git a/drivers/crypto/cpt/cpt_pmd_ops.c b/drivers/crypto/cpt/cpt_pmd_ops.c index 37808ce..d10caf5 100644 --- a/drivers/crypto/cpt/cpt_pmd_ops.c +++ b/drivers/crypto/cpt/cpt_pmd_ops.c @@ -1060,6 +1060,70 @@ int cpt_pmd_session_cfg(struct rte_cryptodev *dev, return -EPERM; } +static void *instance_session_cfg(cpt_instance_t *instance, + struct rte_crypto_sym_xform *xform, void *sess) +{ + struct rte_crypto_sym_xform *chain; + + PMD_INIT_FUNC_TRACE(); + + /* + * Microcode only supports the following combination. + * Encryption followed by authentication + * Authentication followed by decryption + */ + if (xform->next) { + if ((xform->type == RTE_CRYPTO_SYM_XFORM_AUTH) && + (xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) && + (xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)) { + PMD_DRV_LOG(ERR, "Unsupported combination by " + "microcode\n"); + goto err; + /* Unsupported as of now by microcode */ + } + if ((xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) && + (xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) && + (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT)) { + /* For GMAC auth there is no cipher operation */ + if (xform->aead.algo != RTE_CRYPTO_AEAD_AES_GCM || + xform->next->auth.algo != + RTE_CRYPTO_AUTH_AES_GMAC) { + PMD_DRV_LOG(ERR, "Unsupported combination by " + "microcode\n"); + goto err; + /* Unsupported as of now by microcode */ + } + } + } + + chain = xform; + while (chain) { + if (chain->type == RTE_CRYPTO_SYM_XFORM_AEAD) { + if (fill_sess_aead(instance, chain, sess)) + goto err; + } else { + if (chain->type == RTE_CRYPTO_SYM_XFORM_CIPHER) { + if (fill_sess_cipher(instance, chain, sess)) + goto err; + } else if (chain->type == RTE_CRYPTO_SYM_XFORM_AUTH) { + if (chain->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) { + if (fill_sess_gmac(NULL, chain, sess)) + goto err; + } else { + if (fill_sess_auth(instance, chain, sess)) + goto err; + } + } + } + chain = chain->next; + } + + return sess; + +err: + return NULL; +} + void cpt_pmd_session_clear(struct rte_cryptodev *dev, struct rte_cryptodev_sym_session *sess) @@ -1075,3 +1139,798 @@ int cpt_pmd_session_cfg(struct rte_cryptodev *dev, rte_mempool_put(sess_mp, session_private); } } + +static inline void * +alloc_op_meta(struct rte_mbuf *m_src, + buf_ptr_t *buf, + int32_t len) +{ + uint8_t *mdata; + +#ifndef CPT_ALWAYS_USE_SEPARATE_BUF + if (likely(m_src && (m_src->nb_segs == 1))) { + int32_t tailroom; + phys_addr_t mphys; + + /* Check if tailroom is sufficient to hold meta data */ + tailroom = rte_pktmbuf_tailroom(m_src); + if (likely(tailroom > len + 8)) { + mdata = (uint8_t *)m_src->buf_addr + m_src->buf_len; + mphys = m_src->buf_physaddr + m_src->buf_len; + mdata -= len; + mphys -= len; + buf->vaddr = mdata; + buf->dma_addr = mphys; + buf->size = len; + /* Indicate that this is a mbuf allocated mdata */ + mdata = (uint8_t *)((uint64_t)mdata | 1ull); + return mdata; + } + } +#else + (void) m_src; +#endif + + if (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0)) + return NULL; + + buf->vaddr = mdata; + buf->dma_addr = rte_mempool_virt2iova(mdata); + buf->size = len; + + return mdata; +} + +/** + * cpt_free_metabuf - free metabuf to mempool. + * @param instance: pointer to instance. + * @param objp: pointer to the metabuf. + */ +static inline void free_op_meta(void *mdata) +{ + bool nofree = ((uint64_t)mdata & 1ull); + + if (likely(nofree)) + return; + rte_mempool_put(cpt_meta_pool, mdata); +} + +static inline uint32_t +prepare_iov_from_pkt(struct rte_mbuf *pkt, + iov_ptr_t *iovec, uint32_t start_offset) +{ + uint16_t index = 0; + void *seg_data = NULL; + phys_addr_t seg_phys; + int32_t seg_size = 0; + + if (!pkt) { + iovec->buf_cnt = 0; + return 0; + } + + if (!start_offset) { + seg_data = rte_pktmbuf_mtod(pkt, void *); + seg_phys = rte_pktmbuf_mtophys(pkt); + seg_size = pkt->data_len; + } else { + while (start_offset >= pkt->data_len) { + start_offset -= pkt->data_len; + pkt = pkt->next; + } + + seg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset); + seg_phys = rte_pktmbuf_mtophys_offset(pkt, start_offset); + seg_size = pkt->data_len - start_offset; + if (!seg_size) + return 1; + } + + /* first seg */ + iovec->bufs[index].vaddr = seg_data; + iovec->bufs[index].dma_addr = seg_phys; + iovec->bufs[index].size = seg_size; + index++; + pkt = pkt->next; + + while (unlikely(pkt != NULL)) { + seg_data = rte_pktmbuf_mtod(pkt, void *); + seg_phys = rte_pktmbuf_mtophys(pkt); + seg_size = pkt->data_len; + if (!seg_size) + break; + + iovec->bufs[index].vaddr = seg_data; + iovec->bufs[index].dma_addr = seg_phys; + iovec->bufs[index].size = seg_size; + + index++; + + /* FIXME: Not depending on wqe.w0.s.bufs to break */ + pkt = pkt->next; + } + + iovec->buf_cnt = index; + return 0; +} + +static inline uint32_t +prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt, + fc_params_t *param, + uint32_t *flags) +{ + uint16_t index = 0; + void *seg_data = NULL; + phys_addr_t seg_phys; + uint32_t seg_size = 0; + iov_ptr_t *iovec; + + seg_data = rte_pktmbuf_mtod(pkt, void *); + seg_phys = rte_pktmbuf_mtophys(pkt); + seg_size = pkt->data_len; + + /* first seg */ + if (likely(!pkt->next)) { + uint32_t headroom, tailroom; + + *flags |= SINGLE_BUF_INPLACE; + headroom = rte_pktmbuf_headroom(pkt); + tailroom = rte_pktmbuf_tailroom(pkt); + if (likely((headroom >= 24) && + (tailroom >= 8))) { + /* In 83XX this is prerequivisit for Direct mode */ + *flags |= SINGLE_BUF_HEADTAILROOM; + } + param->bufs[0].vaddr = seg_data; + param->bufs[0].dma_addr = seg_phys; + param->bufs[0].size = seg_size; + return 0; + } + iovec = param->src_iov; + iovec->bufs[index].vaddr = seg_data; + iovec->bufs[index].dma_addr = seg_phys; + iovec->bufs[index].size = seg_size; + index++; + pkt = pkt->next; + + while (unlikely(pkt != NULL)) { + seg_data = rte_pktmbuf_mtod(pkt, void *); + seg_phys = rte_pktmbuf_mtophys(pkt); + seg_size = pkt->data_len; + + if (!seg_size) + break; + + iovec->bufs[index].vaddr = seg_data; + iovec->bufs[index].dma_addr = seg_phys; + iovec->bufs[index].size = seg_size; + + index++; + + pkt = pkt->next; + } + + iovec->buf_cnt = index; + return 0; +} + +static void +find_kasumif9_direction_and_length(uint8_t *src, + uint32_t counter_num_bytes, + uint32_t *addr_length_in_bits, + uint8_t *addr_direction) +{ + uint8_t found = 0; + while (!found && counter_num_bytes > 0) { + counter_num_bytes--; + if (src[counter_num_bytes] == 0x00) + continue; + if (src[counter_num_bytes] == 0x80) { + *addr_direction = src[counter_num_bytes - 1] & 0x1; + *addr_length_in_bits = counter_num_bytes * 8 - 1; + found = 1; + } else { + int i = 0; + uint8_t last_byte = src[counter_num_bytes]; + for (i = 0; i < 8 && found == 0; i++) { + if (last_byte & (1 << i)) { + *addr_direction = (last_byte >> (i+1)) + & 0x1; + if (i != 6) + *addr_length_in_bits = + counter_num_bytes * 8 + + (8 - (i + 2)); + else + *addr_length_in_bits = + counter_num_bytes * 8; + + found = 1; + } + } + } + } +} +/* + * This handles all auth only except AES_GMAC + */ +static void * +fill_digest_params(struct rte_crypto_op *cop, + struct cpt_sess_misc *sess, + void **mdata_ptr, + int *op_ret) +{ + uint32_t space = 0; + struct rte_crypto_sym_op *sym_op = cop->sym; + void *mdata; + phys_addr_t mphys; + uint64_t *op; + uint32_t auth_range_off; + uint32_t flags = 0; + uint64_t d_offs = 0, d_lens; + void *prep_req = NULL; + struct rte_mbuf *m_src, *m_dst; + uint16_t auth_op = sess->cpt_op & CSP_OP_AUTH_MASK; + uint8_t zsk_flag = sess->zsk_flag; + uint16_t mac_len = sess->mac_len; + fc_params_t params; + char src[SRC_IOV_SIZE]; + uint8_t iv_buf[16]; + + m_src = sym_op->m_src; + + /* For just digest lets force mempool alloc */ + mdata = alloc_op_meta(NULL, ¶ms.meta_buf, cpt_op_mlen); + if (mdata == NULL) { + PMD_DRV_LOG(ERR, "Error allocating meta buffer for request\n"); + *op_ret = -ENOMEM; + return NULL; + } + + mphys = params.meta_buf.dma_addr; + + op = mdata; + op[0] = (uint64_t)mdata; + op[1] = (uint64_t)cop; + op[2] = op[3] = 0; /* Used to indicate auth verify */ + space += 4 * sizeof(uint64_t); + + auth_range_off = sym_op->auth.data.offset; + + flags = VALID_MAC_BUF; + params.src_iov = (void *)src; + if (unlikely(zsk_flag)) { + /* + * Since for Zuc, Kasumi, Snow3g offsets are in bits + * we will send pass through even for auth only case, + * let MC handle it + */ + d_offs = auth_range_off; + auth_range_off = 0; + params.auth_iv_buf = rte_crypto_op_ctod_offset(cop, + uint8_t *, sess->auth_iv_offset); + if (zsk_flag == K_F9) { + uint32_t length_in_bits, num_bytes; + uint8_t *src, direction = 0; + uint32_t counter_num_bytes; + + memcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src, + uint8_t *), 8); + /* + * This is kasumi f9, take direction from + * source buffer + */ + length_in_bits = cop->sym->auth.data.length; + num_bytes = (length_in_bits >> 3); + counter_num_bytes = num_bytes; + src = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *); + find_kasumif9_direction_and_length(src, + counter_num_bytes, + &length_in_bits, + &direction); + length_in_bits -= 64; + cop->sym->auth.data.offset += 64; + d_offs = cop->sym->auth.data.offset; + auth_range_off = d_offs / 8; + cop->sym->auth.data.length = length_in_bits; + + /* Store it at end of auth iv */ + iv_buf[8] = direction; + params.auth_iv_buf = iv_buf; + } + } + + d_lens = sym_op->auth.data.length; + + params.ctx_buf.vaddr = SESS_PRIV(sess); + params.ctx_buf.dma_addr = sess->ctx_dma_addr; + + if (auth_op == CSP_OP_AUTH_GENERATE) { + if (sym_op->auth.digest.data) { + /* + * Digest to be generated + * in separate buffer + */ + params.mac_buf.size = + sess->mac_len; + params.mac_buf.vaddr = + sym_op->auth.digest.data; + params.mac_buf.dma_addr = + sym_op->auth.digest.phys_addr; + } else { + uint32_t off = sym_op->auth.data.offset + + sym_op->auth.data.length; + int32_t dlen, space; + + m_dst = sym_op->m_dst ? + sym_op->m_dst : sym_op->m_src; + dlen = rte_pktmbuf_pkt_len(m_dst); + + space = off + mac_len - dlen; + if (space > 0) + if (!rte_pktmbuf_append(m_dst, space)) { + PMD_DRV_LOG(ERR, "Failed to extend " + "mbuf by %uB\n", space); + goto err; + } + + params.mac_buf.vaddr = + rte_pktmbuf_mtod_offset(m_dst, + void *, off); + params.mac_buf.dma_addr = + rte_pktmbuf_mtophys_offset(m_dst, off); + params.mac_buf.size = mac_len; + } + } else { + /* Need space for storing generated mac */ + params.mac_buf.vaddr = + (uint8_t *)mdata + space; + params.mac_buf.dma_addr = mphys + space; + params.mac_buf.size = mac_len; + space += RTE_ALIGN_CEIL(mac_len, 8); + op[2] = (uint64_t)params.mac_buf.vaddr; + op[3] = mac_len; + + } + + params.meta_buf.vaddr = (uint8_t *)mdata + space; + params.meta_buf.dma_addr = mphys + space; + params.meta_buf.size -= space; + + /* Out of place processing */ + params.src_iov = (void *)src; + + /*Store SG I/O in the api for reuse */ + if (prepare_iov_from_pkt(m_src, params.src_iov, + auth_range_off)) { + PMD_DRV_LOG(ERR, "Prepare src iov failed\n"); + *op_ret = -1; + goto err; + } + + prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, + ¶ms, op, op_ret); + *mdata_ptr = mdata; + return prep_req; +err: + if (unlikely(!prep_req)) + free_op_meta(mdata); + return NULL; +} + +static inline void * +fill_fc_params(struct rte_crypto_op *cop, + struct cpt_sess_misc *sess_misc, + void **mdata_ptr, + int *op_ret) +{ + uint32_t space = 0; + struct rte_crypto_sym_op *sym_op = cop->sym; + void *mdata; + uint64_t *op; + uint32_t mc_hash_off; + uint32_t flags = 0; + uint64_t d_offs, d_lens; + void *prep_req; + struct rte_mbuf *m_src, *m_dst; + uint8_t cpt_op = sess_misc->cpt_op; + uint8_t zsk_flag = sess_misc->zsk_flag; + uint8_t aes_gcm = sess_misc->aes_gcm; + uint16_t mac_len = sess_misc->mac_len; +#ifdef CPT_ALWAYS_USE_SG_MODE + uint8_t inplace = 0; +#else + uint8_t inplace = 1; +#endif + fc_params_t fc_params; + char src[SRC_IOV_SIZE]; + char dst[SRC_IOV_SIZE]; + uint32_t iv_buf[4]; + + if (likely(sess_misc->iv_length)) { + flags |= VALID_IV_BUF; + fc_params.iv_buf = rte_crypto_op_ctod_offset(cop, + uint8_t *, sess_misc->iv_offset); + if (sess_misc->aes_ctr && + unlikely(sess_misc->iv_length != 16)) { + memcpy((uint8_t *)iv_buf, + rte_crypto_op_ctod_offset(cop, + uint8_t *, sess_misc->iv_offset), 12); + iv_buf[3] = htobe32(0x1); + fc_params.iv_buf = iv_buf; + } + } + + if (zsk_flag) { + fc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop, + uint8_t *, + sess_misc->auth_iv_offset); + if (zsk_flag == K_F9) { + PMD_DRV_LOG(ERR, "Should not reach here for " + "kasumi F9\n"); + } + if (zsk_flag != ZS_EA) + inplace = 0; + } + m_src = sym_op->m_src; + m_dst = sym_op->m_dst; + + if (aes_gcm) { + uint8_t *salt; + uint8_t *aad_data; + uint16_t aad_len; + + d_offs = sym_op->aead.data.offset; + d_lens = sym_op->aead.data.length; + mc_hash_off = sym_op->aead.data.offset + + sym_op->aead.data.length; + + aad_data = sym_op->aead.aad.data; + aad_len = sess_misc->aad_length; + if (likely((aad_data + aad_len) == + rte_pktmbuf_mtod_offset(m_src, + uint8_t *, + sym_op->aead.data.offset))) { + d_offs = (d_offs - aad_len) | (d_offs << 16); + d_lens = (d_lens + aad_len) | (d_lens << 32); + } else { + fc_params.aad_buf.vaddr = sym_op->aead.aad.data; + fc_params.aad_buf.dma_addr = sym_op->aead.aad.phys_addr; + fc_params.aad_buf.size = aad_len; + flags |= VALID_AAD_BUF; + inplace = 0; + d_offs = d_offs << 16; + d_lens = d_lens << 32; + } + + salt = fc_params.iv_buf; + if (unlikely(*(uint32_t *)salt != sess_misc->salt)) { + cpt_fc_salt_update(SESS_PRIV(sess_misc), salt); + sess_misc->salt = *(uint32_t *)salt; + } + fc_params.iv_buf = salt + 4; + if (likely(mac_len)) { + struct rte_mbuf *m = (cpt_op & CSP_OP_ENCODE) ? m_dst : + m_src; + + if (!m) + m = m_src; + + /* hmac immediately following data is best case */ + if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) + + mc_hash_off != + (uint8_t *)sym_op->aead.digest.data)) { + flags |= VALID_MAC_BUF; + fc_params.mac_buf.size = sess_misc->mac_len; + fc_params.mac_buf.vaddr = + sym_op->aead.digest.data; + fc_params.mac_buf.dma_addr = + sym_op->aead.digest.phys_addr; + inplace = 0; + } + } + } else { + d_offs = sym_op->cipher.data.offset; + d_lens = sym_op->cipher.data.length; + mc_hash_off = sym_op->cipher.data.offset + + sym_op->cipher.data.length; + d_offs = (d_offs << 16) | sym_op->auth.data.offset; + d_lens = (d_lens << 32) | sym_op->auth.data.length; + + if (mc_hash_off < (sym_op->auth.data.offset + + sym_op->auth.data.length)){ + mc_hash_off = (sym_op->auth.data.offset + + sym_op->auth.data.length); + } + /* for gmac, salt should be updated like in gcm */ + if (unlikely(sess_misc->is_gmac)) { + uint8_t *salt; + salt = fc_params.iv_buf; + if (unlikely(*(uint32_t *)salt != sess_misc->salt)) { + cpt_fc_salt_update(SESS_PRIV(sess_misc), salt); + sess_misc->salt = *(uint32_t *)salt; + } + fc_params.iv_buf = salt + 4; + } + /* */ + if (likely(mac_len)) { + struct rte_mbuf *m = + (cpt_op & CSP_OP_ENCODE) ? m_dst : m_src; + + if (!m) + m = m_src; + + /* hmac immediately following data is best case */ + if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) + + mc_hash_off != + (uint8_t *)sym_op->auth.digest.data)) { + flags |= VALID_MAC_BUF; + fc_params.mac_buf.size = + sess_misc->mac_len; + fc_params.mac_buf.vaddr = + sym_op->auth.digest.data; + fc_params.mac_buf.dma_addr = + sym_op->auth.digest.phys_addr; + inplace = 0; + } + } + } + fc_params.ctx_buf.vaddr = SESS_PRIV(sess_misc); + fc_params.ctx_buf.dma_addr = sess_misc->ctx_dma_addr; + + if (likely(!m_dst && inplace)) { + /* Case of single buffer without AAD buf or + * separate mac buf in place and + * not air crypto + */ + fc_params.dst_iov = fc_params.src_iov = (void *)src; + + if (unlikely(prepare_iov_from_pkt_inplace(m_src, + &fc_params, + &flags))) { + PMD_DRV_LOG(ERR, "Prepare inplace src iov failed\n"); + *op_ret = -1; + return NULL; + } + + } else { + /* Out of place processing */ + fc_params.src_iov = (void *)src; + fc_params.dst_iov = (void *)dst; + + /*Store SG I/O in the api for reuse */ + if (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) { + PMD_DRV_LOG(ERR, "Prepare src iov failed\n"); + *op_ret = -1; + return NULL; + } + + if (unlikely(m_dst != NULL)) { + uint32_t pkt_len; + + /* Try to make room as much as src has */ + m_dst = sym_op->m_dst; + pkt_len = rte_pktmbuf_pkt_len(m_dst); + + if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) { + pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len; + if (!rte_pktmbuf_append(m_dst, pkt_len)) { + PMD_DRV_LOG(ERR, "Not enough space in " + "m_dst %p, need %u more\n", + m_dst, pkt_len); + return NULL; + } + } + + if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) { + PMD_DRV_LOG(ERR, "Prepare dst iov failed for " + "m_dst %p\n", m_dst); + return NULL; + } + } else { + fc_params.dst_iov = (void *)src; + } + + } + + if (likely(flags & SINGLE_BUF_HEADTAILROOM)) + mdata = alloc_op_meta(m_src, + &fc_params.meta_buf, + cpt_op_sb_mlen); + else + mdata = alloc_op_meta(NULL, + &fc_params.meta_buf, + cpt_op_mlen); + + if (unlikely(mdata == NULL)) { + PMD_DRV_LOG(ERR, "Error allocating meta buffer for request\n"); + return NULL; + } + + op = (uint64_t *)((uint64_t)mdata & ~1ull); + op[0] = (uint64_t)mdata; + op[1] = (uint64_t)cop; + op[2] = op[3] = 0; /* Used to indicate auth verify */ + space += 4 * sizeof(uint64_t); + + fc_params.meta_buf.vaddr = (uint8_t *)op + space; + fc_params.meta_buf.dma_addr += space; + fc_params.meta_buf.size -= space; + + /* Finally prepare the instruction */ + if (cpt_op & CSP_OP_ENCODE) + prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, + &fc_params, op, op_ret); + else + prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens, + &fc_params, op, op_ret); + + if (unlikely(!prep_req)) + free_op_meta(mdata); + *mdata_ptr = mdata; + return prep_req; +} + +static inline void +compl_auth_verify(struct rte_crypto_op *op, + uint8_t *gen_mac, + uint64_t mac_len) +{ + uint8_t *mac; + struct rte_crypto_sym_op *sym_op = op->sym; + + if (sym_op->auth.digest.data) + mac = sym_op->auth.digest.data; + else + mac = rte_pktmbuf_mtod_offset(sym_op->m_src, + uint8_t *, + sym_op->auth.data.length + + sym_op->auth.data.offset); + if (!mac) { + op->status = RTE_CRYPTO_OP_STATUS_ERROR; + return; + } + + if (memcmp(mac, gen_mac, mac_len)) + op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED; + else + op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; +} + + +static inline int __hot +cpt_pmd_crypto_operation(cpt_instance_t *instance, + struct rte_crypto_op *op, + bool last_op) +{ + struct cpt_sess_misc *sess = NULL; + struct rte_crypto_sym_op *sym_op = op->sym; + void *prep_req, *mdata = NULL; + int ret = 0; + uint64_t cpt_op; + uint8_t flags = last_op ? 0 : ENQ_FLAG_NODOORBELL; + + + if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) { + void *ptr = NULL; + int sess_len; + + sess_len = cpt_pmd_get_session_size(NULL); + + sess = rte_calloc(__func__, 1, sess_len, 8); + if (!sess) + return -ENOMEM; + + sess->ctx_dma_addr = rte_malloc_virt2iova(sess) + + sizeof(struct cpt_sess_misc); + + ptr = instance_session_cfg(instance, + sym_op->xform, (void *)sess); + if (ptr == NULL) + return -EINVAL; + } else { + sess = (struct cpt_sess_misc *) + get_session_private_data(sym_op->session, + cryptodev_cpt_driver_id); + } + + cpt_op = sess->cpt_op; + + if (likely(cpt_op & CSP_OP_CIPHER_MASK)) + prep_req = fill_fc_params(op, sess, &mdata, &ret); + else + prep_req = fill_digest_params(op, sess, &mdata, &ret); + + if (unlikely(!prep_req)) { + PMD_DRV_LOG_RAW(ERR, "prep cryto req : op %p, cpt_op 0x%x ret " + "0x%x\n", op, (unsigned int)cpt_op, ret); + goto req_fail; + } + + /* Enqueue prepared instruction to HW */ + ret = cpt_enqueue_req(instance, prep_req, + flags, NULL, 0); + + if (unlikely(ret)) { + if (unlikely(ret == -EAGAIN)) + goto req_fail; + PMD_DRV_LOG(ERR, "Error enqueing crypto request : error code " + "%d\n", ret); + goto req_fail; + } + + /* TODO: Stats here */ + + return 0; + +req_fail: + if (mdata) + free_op_meta(mdata); + return ret; +} + + + +uint16_t +cpt_pmd_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) +{ + cpt_instance_t *instance = (cpt_instance_t *)qptr; + uint16_t count = 0; + int ret; + + count = cpt_queue_full(instance); + if (nb_ops > count) + nb_ops = count; + + count = 0; + while (likely(count < nb_ops)) { + bool last_op = (count + 1 == nb_ops); + ret = cpt_pmd_crypto_operation(instance, ops[count], last_op); + if (unlikely(ret)) + break; + count++; + } + return count; +} + +uint16_t +cpt_pmd_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) +{ + cpt_instance_t *instance = (cpt_instance_t *)qptr; + uint16_t nb_completed, i = 0; + uint8_t compcode[nb_ops]; + + nb_completed = cpt_dequeue_burst(instance, nb_ops, + (void **)ops, compcode); + while (likely(i < nb_completed)) { + struct rte_crypto_op *cop; + void *metabuf; + uint64_t *rsp; + uint8_t status; + + rsp = (void *)ops[i]; + status = compcode[i]; + if (likely((i + 1) < nb_completed)) + rte_prefetch0(ops[i+1]); + metabuf = (void *)rsp[0]; + cop = (void *)rsp[1]; + + ops[i] = cop; + + if (likely(status == 0)) { + if (likely(!rsp[2])) + cop->status = + RTE_CRYPTO_OP_STATUS_SUCCESS; + else + compl_auth_verify(cop, (uint8_t *)rsp[2], + rsp[3]); + } else if (status == ERR_GC_ICV_MISCOMPARE) { + /*auth data mismatch */ + cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED; + } else { + cop->status = RTE_CRYPTO_OP_STATUS_ERROR; + } + free_op_meta(metabuf); + i++; + } + return nb_completed; +} diff --git a/drivers/crypto/cpt/cpt_pmd_ops.h b/drivers/crypto/cpt/cpt_pmd_ops.h index 314b2b1..17b3a09 100644 --- a/drivers/crypto/cpt/cpt_pmd_ops.h +++ b/drivers/crypto/cpt/cpt_pmd_ops.h @@ -83,4 +83,14 @@ int cpt_pmd_session_cfg(struct rte_cryptodev *dev, void cpt_pmd_session_clear(struct rte_cryptodev *dev, struct rte_cryptodev_sym_session *sess); + +uint16_t +cpt_pmd_pkt_enqueue(void *qptr, + struct rte_crypto_op **ops, + uint16_t nb_ops); + +uint16_t +cpt_pmd_pkt_dequeue(void *qptr, + struct rte_crypto_op **ops, + uint16_t nb_ops); #endif From patchwork Fri Jun 8 16:45:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 40876 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0F1841CDFB; Fri, 8 Jun 2018 18:49:48 +0200 (CEST) Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on0065.outbound.protection.outlook.com [104.47.36.65]) by dpdk.org (Postfix) with ESMTP id F37441BBB4 for ; Fri, 8 Jun 2018 18:49:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=k0H6AIjpAFT6/iF9cxm9J/L3PeuTz2glYiD6nrldCnQ=; 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It also contains the compilation steps and how to execute an examples application. Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- doc/guides/cryptodevs/cpt.rst | 112 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 doc/guides/cryptodevs/cpt.rst diff --git a/doc/guides/cryptodevs/cpt.rst b/doc/guides/cryptodevs/cpt.rst new file mode 100644 index 0000000..262ce9e --- /dev/null +++ b/doc/guides/cryptodevs/cpt.rst @@ -0,0 +1,112 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2017 Cavium, Inc + +***************************** +Cavium's CPT Poll Mode Driver +****************************** + +The CPT poll mode driver provides support for offloading cryptographic +operations on the Cavium's cryptographic accelerator unit(CPT) coprocessor +hardware. This coprocessor is present on the Cavium's thunder boards(CN8xxx). +The CPT poll mode driver enqueues the crypto request to this coprocessor and +dequeues the response once the operation is completed. + +Supported Algorithms +##################### + +Cipher Algorithms +****************** + +* ``RTE_CRYPTO_CIPHER_AES_CBC`` +* ``RTE_CRYPTO_CIPHER_AES_CTR`` +* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2`` +* ``RTE_CRYPTO_CIPHER_KASUMI_F8`` +* ``RTE_CRYPTO_CIPHER_ZUC_EEA3`` +* ``RTE_CRYPTO_CIPHER_3DES_CBC`` +* ``RTE_CRYPTO_CIPHER_NULL`` + +Hash Algorithms +**************** + +* ``RTE_CRYPTO_AUTH_SHA1_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA224_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA256_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA384_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA512_HMAC`` +* ``RTE_CRYPTO_AUTH_MD5_HMAC`` +* ``RTE_CRYPTO_AUTH_AES_GMAC`` +* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2`` +* ``RTE_CRYPTO_AUTH_NULL`` +* ``RTE_CRYPTO_AUTH_ZUC_EIA3`` +* ``RTE_CRYPTO_AUTH_KASUMI_F9`` + +AEAD Algorithms +**************** + +* ``RTE_CRYPTO_AEAD_AES_GCM`` + +Compilation +############ + +The thunder board must be running the linux kernel based on sdk-6.2.0 patch 2. +In this the cpt pf driver is already built in. Also install the openssl package, +because the cpt driver depends on the crypto library. + +For compiling the cpt poll mode driver, the CONFIG_RTE_LIBRTE_PMD_CPT setting +should be made as `y` in config/common_base file. By default it is set to `n`. + +* ``CONFIG_RTE_LIBRTE_PMD_CPT=y`` + +The following are the steps to compile the cpt poll mode driver: + +.. code-block:: console + + cd + make config T=arm64-thunderx-linuxapp-gcc + make + +The example applications can be compiled using the following: + +.. code-block:: console + + cd + export RTE_SDK=$PWD + export RTE_TARGET=build + cd examples/ + make + +Execution +########## + +The sriov_numvfs should be assigned for the cpt pf driver using the following: + +.. code-block:: console + + echo > /sys/bus/pci/devices//sriov_numvfs + +The device number can be ascertained by running the dpdk-devbind.py scripts in +the dpdk sources. + +Then the corresponding vf should be binded to the vfio-pci driver using the +following: + +.. code-block:: console + + cd + ./usertools/dpdk-devbind.py -u + ./usertools/dpdk-devbind.py -bvfio-pci + +Appropriate huge page need to be setup in order to run the examples dpdk +application. + +.. code-block:: console + + echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages + mkdir /mnt/huge + mount -t hugetlbfs nodev /mnt/huge + +After that the example dpdk application can be executed on the hardware. + +.. code-block:: console + ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config + "(0,0,0),(1,0,0)" -f ep0.cfg From patchwork Fri Jun 8 16:45:25 2018 Content-Type: text/plain; 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Signed-off-by: Ankur Dwivedi Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian Srinivasan --- drivers/crypto/cpt/meson.build | 16 ++++++++++++++++ drivers/crypto/meson.build | 2 +- 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/cpt/meson.build diff --git a/drivers/crypto/cpt/meson.build b/drivers/crypto/cpt/meson.build new file mode 100644 index 0000000..d298587 --- /dev/null +++ b/drivers/crypto/cpt/meson.build @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Cavium, Inc +if host_machine.system() != 'linux' + build = false +endif + +sources = files('cpt_pmd_cryptodev.c', + 'cpt_pmd_ops.c', + 'base/cpt_device.c', + 'base/cpt_request_mgr.c', + 'base/cpt_ops.c', + 'base/cpt8xxx_device.c', + 'base/cpt_vf_mbox.c') + +deps += ['bus_pci'] +pkgconfig_extra_libs += '-lcrypto' diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build index d64ca41..6a7923f 100644 --- a/drivers/crypto/meson.build +++ b/drivers/crypto/meson.build @@ -1,7 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -drivers = ['ccp', 'dpaa_sec', 'dpaa2_sec', 'mvsam', +drivers = ['cpt', 'ccp', 'dpaa_sec', 'dpaa2_sec', 'mvsam', 'null', 'openssl', 'qat', 'virtio'] std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps