From patchwork Sun Jun 30 16:21:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 55669 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2CB1D1B955; Sun, 30 Jun 2019 18:21:45 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 34DC91B945 for ; Sun, 30 Jun 2019 18:21:42 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B06FCFC; Sun, 30 Jun 2019 09:21:41 -0700 (PDT) Received: from net-arm-thunderx2.shanghai.arm.com (net-arm-thunderx2.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 97B063F718; Sun, 30 Jun 2019 09:21:39 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: thomas@monjalon.net, jerinj@marvell.com, hemant.agrawal@nxp.com, bruce.richardson@intel.com, chaozhu@linux.vnet.ibm.com, Honnappa.Nagarahalli@arm.com, nd@arm.com, gavin.hu@arm.com Date: Mon, 1 Jul 2019 00:21:12 +0800 Message-Id: <1561911676-37718-2-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [RFC 1/5] eal: add the APIs to wait until equal X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The rte_wait_until_equal_xxx APIs abstract the functionality of 'polling for a memory location to become equal to a given value'. Signed-off-by: Gavin Hu Reviewed-by: Ruifeng Wang Reviewed-by: Steve Capper Reviewed-by: Ola Liljedahl Reviewed-by: Honnappa Nagarahalli --- .../common/include/arch/arm/rte_pause_64.h | 143 +++++++++++++++++++++ lib/librte_eal/common/include/generic/rte_pause.h | 20 +++ 2 files changed, 163 insertions(+) diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h index 93895d3..0095da6 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h @@ -17,6 +17,149 @@ static inline void rte_pause(void) asm volatile("yield" ::: "memory"); } +#ifdef RTE_USE_WFE +#define rte_wait_until_equal_relaxed(addr, expected) do {\ + typeof(*addr) tmp; \ + if (__builtin_constant_p((expected))) \ + do { \ + if (sizeof(*(addr)) == 16)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxrh %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 32)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxr %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 64)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxr %x0, %1\n" \ + "cmp %x0, %x2\n" \ + "bne 1b\n" \ + : "=&r" (tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + } while (0); \ + else \ + do { \ + if (sizeof(*(addr)) == 16)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxrh %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 32)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxr %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 64)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxr %x0, %1\n" \ + "cmp %x0, %x2\n" \ + "bne 1b\n" \ + : "=&r" (tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + } while (0); \ +} while (0) + +#define rte_wait_until_equal_acquire(addr, expected) do {\ + typeof(*addr) tmp; \ + if (__builtin_constant_p((expected))) \ + do { \ + if (sizeof(*(addr)) == 16)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxrh %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 32)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxr %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 64)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxr %x0, %1\n" \ + "cmp %x0, %x2\n" \ + "bne 1b\n" \ + : "=&r" (tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + } while (0); \ + else \ + do { \ + if (sizeof(*(addr)) == 16)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxrh %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 32)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxr %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 64)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxr %x0, %1\n" \ + "cmp %x0, %x2\n" \ + "bne 1b\n" \ + : "=&r" (tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + } while (0); \ +} while (0) + +#endif + #ifdef __cplusplus } #endif diff --git a/lib/librte_eal/common/include/generic/rte_pause.h b/lib/librte_eal/common/include/generic/rte_pause.h index 52bd4db..c115b61 100644 --- a/lib/librte_eal/common/include/generic/rte_pause.h +++ b/lib/librte_eal/common/include/generic/rte_pause.h @@ -20,4 +20,24 @@ */ static inline void rte_pause(void); +#if !defined(RTE_USE_WFE) +#define rte_wait_until_equal_relaxed(addr, expected) do {\ + rte_pause(); \ + } while (*(addr) != (expected)) + +#ifdef RTE_USE_C11_MEM_MODEL +#define rte_wait_until_equal_acquire(addr, expected) do {\ + rte_pause(); \ + } while (__atomic_load_n((addr), __ATOMIC_ACQUIRE) != (expected)) +#else +#define rte_wait_until_equal_acquire(addr, expected) do {\ + do {\ + rte_pause(); \ + } while (*(addr) != (expected)); \ + rte_smp_rmb(); \ + } while (0) +#endif +#endif + + #endif /* _RTE_PAUSE_H_ */ From patchwork Sun Jun 30 16:21:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 55670 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 469251B974; Sun, 30 Jun 2019 18:21:47 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 369E21B952 for ; Sun, 30 Jun 2019 18:21:44 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B88F213A1; Sun, 30 Jun 2019 09:21:43 -0700 (PDT) Received: from net-arm-thunderx2.shanghai.arm.com (net-arm-thunderx2.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CB9DC3F718; Sun, 30 Jun 2019 09:21:41 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: thomas@monjalon.net, jerinj@marvell.com, hemant.agrawal@nxp.com, bruce.richardson@intel.com, chaozhu@linux.vnet.ibm.com, Honnappa.Nagarahalli@arm.com, nd@arm.com, gavin.hu@arm.com Date: Mon, 1 Jul 2019 00:21:13 +0800 Message-Id: <1561911676-37718-3-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [RFC 2/5] ticketlock: use new API to reduce contention on aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" While using ticket lock, cores repeatedly poll the lock variable. This is replaced by rte_wait_until_equal API. Running ticketlock_autotest on ThunderX2, with different numbers of cores and depths of rings, 3%~8% performance gains were measured. Signed-off-by: Gavin Hu Reviewed-by: Honnappa Nagarahalli --- lib/librte_eal/common/include/generic/rte_ticketlock.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/librte_eal/common/include/generic/rte_ticketlock.h b/lib/librte_eal/common/include/generic/rte_ticketlock.h index 191146f..6820f01 100644 --- a/lib/librte_eal/common/include/generic/rte_ticketlock.h +++ b/lib/librte_eal/common/include/generic/rte_ticketlock.h @@ -64,8 +64,8 @@ static inline __rte_experimental void rte_ticketlock_lock(rte_ticketlock_t *tl) { uint16_t me = __atomic_fetch_add(&tl->s.next, 1, __ATOMIC_RELAXED); - while (__atomic_load_n(&tl->s.current, __ATOMIC_ACQUIRE) != me) - rte_pause(); + if (__atomic_load_n(&tl->s.current, __ATOMIC_ACQUIRE) != me) + rte_wait_until_equal_acquire(&tl->s.current, me); } /** From patchwork Sun Jun 30 16:21:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 55671 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F2A8A1B998; Sun, 30 Jun 2019 18:21:50 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 6E97B1B96B for ; Sun, 30 Jun 2019 18:21:46 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EF47E13D5; Sun, 30 Jun 2019 09:21:45 -0700 (PDT) Received: from net-arm-thunderx2.shanghai.arm.com (net-arm-thunderx2.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 14F9F3F718; Sun, 30 Jun 2019 09:21:43 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: thomas@monjalon.net, jerinj@marvell.com, hemant.agrawal@nxp.com, bruce.richardson@intel.com, chaozhu@linux.vnet.ibm.com, Honnappa.Nagarahalli@arm.com, nd@arm.com, gavin.hu@arm.com Date: Mon, 1 Jul 2019 00:21:14 +0800 Message-Id: <1561911676-37718-4-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [RFC 3/5] ring: use wfe to wait for ring tail update on aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of polling for tail to be updated, use wfe instruction. 50%~70% performance gain was measured by running ring_perf_autotest on ThunderX2. Signed-off-by: Gavin Hu Reviewed-by: Ruifeng Wang Reviewed-by: Steve Capper Reviewed-by: Ola Liljedahl Reviewed-by: Honnappa Nagarahalli --- lib/librte_ring/rte_ring_c11_mem.h | 5 +++-- lib/librte_ring/rte_ring_generic.h | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/lib/librte_ring/rte_ring_c11_mem.h b/lib/librte_ring/rte_ring_c11_mem.h index 0fb73a3..f1de79c 100644 --- a/lib/librte_ring/rte_ring_c11_mem.h +++ b/lib/librte_ring/rte_ring_c11_mem.h @@ -2,6 +2,7 @@ * * Copyright (c) 2017,2018 HXT-semitech Corporation. * Copyright (c) 2007-2009 Kip Macy kmacy@freebsd.org + * Copyright (c) 2019 Arm Limited * All rights reserved. * Derived from FreeBSD's bufring.h * Used as BSD-3 Licensed with permission from Kip Macy. @@ -21,8 +22,8 @@ update_tail(struct rte_ring_headtail *ht, uint32_t old_val, uint32_t new_val, * we need to wait for them to complete */ if (!single) - while (unlikely(ht->tail != old_val)) - rte_pause(); + if (unlikely(ht->tail != old_val)) + rte_wait_until_equal_relaxed(&ht->tail, old_val); __atomic_store_n(&ht->tail, new_val, __ATOMIC_RELEASE); } diff --git a/lib/librte_ring/rte_ring_generic.h b/lib/librte_ring/rte_ring_generic.h index 953cdbb..bb0dce0 100644 --- a/lib/librte_ring/rte_ring_generic.h +++ b/lib/librte_ring/rte_ring_generic.h @@ -23,8 +23,8 @@ update_tail(struct rte_ring_headtail *ht, uint32_t old_val, uint32_t new_val, * we need to wait for them to complete */ if (!single) - while (unlikely(ht->tail != old_val)) - rte_pause(); + if (unlikely(ht->tail != old_val)) + rte_wait_until_equal_relaxed(&ht->tail, old_val); ht->tail = new_val; } From patchwork Sun Jun 30 16:21:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 55672 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2D1991B99C; Sun, 30 Jun 2019 18:21:53 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id B03171B995 for ; Sun, 30 Jun 2019 18:21:48 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 30473344; Sun, 30 Jun 2019 09:21:48 -0700 (PDT) Received: from net-arm-thunderx2.shanghai.arm.com (net-arm-thunderx2.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4BA453F718; Sun, 30 Jun 2019 09:21:46 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: thomas@monjalon.net, jerinj@marvell.com, hemant.agrawal@nxp.com, bruce.richardson@intel.com, chaozhu@linux.vnet.ibm.com, Honnappa.Nagarahalli@arm.com, nd@arm.com, gavin.hu@arm.com Date: Mon, 1 Jul 2019 00:21:15 +0800 Message-Id: <1561911676-37718-5-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [RFC 4/5] spinlock: use wfe to reduce contention on aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In acquiring a spinlock, cores repeatedly poll the lock variable. This is replaced by rte_wait_until_equal API. 20% performance gain was measured by running spinlock_autotest on 14 isolated cores of ThunderX2. Signed-off-by: Gavin Hu Reviewed-by: Ruifeng Wang Reviewed-by: Phil Yang Reviewed-by: Steve Capper Reviewed-by: Ola Liljedahl Reviewed-by: Honnappa Nagarahalli --- .../common/include/arch/arm/rte_spinlock.h | 25 ++++++++++++++++++++++ .../common/include/generic/rte_spinlock.h | 2 +- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/lib/librte_eal/common/include/arch/arm/rte_spinlock.h b/lib/librte_eal/common/include/arch/arm/rte_spinlock.h index 1a6916b..b7e8521 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_spinlock.h +++ b/lib/librte_eal/common/include/arch/arm/rte_spinlock.h @@ -16,6 +16,31 @@ extern "C" { #include #include "generic/rte_spinlock.h" +/* armv7a does support WFE, but an explicit wake-up signal using SEV is + * required (must be preceded by DSB to drain the store buffer) and + * this is less performant, so keep armv7a implementation unchanged. + */ +#if defined(RTE_USE_WFE) && defined(RTE_ARCH_ARM64) +static inline void +rte_spinlock_lock(rte_spinlock_t *sl) +{ + unsigned int tmp; + /* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc. + * faqs/ka16809.html + */ + asm volatile( + "sevl\n" + "1: wfe\n" + "2: ldaxr %w0, %1\n" + "cbnz %w0, 1b\n" + "stxr %w0, %w2, %1\n" + "cbnz %w0, 2b\n" + : "=&r" (tmp), "+Q"(sl->locked) + : "r" (1) + : "cc", "memory"); +} +#endif + static inline int rte_tm_supported(void) { return 0; diff --git a/lib/librte_eal/common/include/generic/rte_spinlock.h b/lib/librte_eal/common/include/generic/rte_spinlock.h index 87ae7a4..cf4f15b 100644 --- a/lib/librte_eal/common/include/generic/rte_spinlock.h +++ b/lib/librte_eal/common/include/generic/rte_spinlock.h @@ -57,7 +57,7 @@ rte_spinlock_init(rte_spinlock_t *sl) static inline void rte_spinlock_lock(rte_spinlock_t *sl); -#ifdef RTE_FORCE_INTRINSICS +#if defined(RTE_FORCE_INTRINSICS) && !defined(RTE_USE_WFE) static inline void rte_spinlock_lock(rte_spinlock_t *sl) { From patchwork Sun Jun 30 16:21:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 55673 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 27A6B1B9A5; Sun, 30 Jun 2019 18:21:56 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id CC1511B996 for ; Sun, 30 Jun 2019 18:21:50 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 647E6CFC; Sun, 30 Jun 2019 09:21:50 -0700 (PDT) Received: from net-arm-thunderx2.shanghai.arm.com (net-arm-thunderx2.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 80AE43F718; Sun, 30 Jun 2019 09:21:48 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: thomas@monjalon.net, jerinj@marvell.com, hemant.agrawal@nxp.com, bruce.richardson@intel.com, chaozhu@linux.vnet.ibm.com, Honnappa.Nagarahalli@arm.com, nd@arm.com, gavin.hu@arm.com Date: Mon, 1 Jul 2019 00:21:16 +0800 Message-Id: <1561911676-37718-6-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [RFC 5/5] config: add WFE config entry for aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add the RTE_USE_WFE configuration entry for aarch64, disabled by default. It can be enabled selectively based on the performance benchmarking. Signed-off-by: Gavin Hu Reviewed-by: Ruifeng Wang Reviewed-by: Steve Capper Reviewed-by: Honnappa Nagarahalli --- config/arm/meson.build | 1 + config/common_armv8a_linux | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/config/arm/meson.build b/config/arm/meson.build index 6fa06a1..939d60e 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -116,6 +116,7 @@ impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic] impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic] dpdk_conf.set('RTE_FORCE_INTRINSICS', 1) +dpdk_conf.set('RTE_USE_WFE', 0) if not dpdk_conf.get('RTE_ARCH_64') dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) diff --git a/config/common_armv8a_linux b/config/common_armv8a_linux index 72091de..ae87a87 100644 --- a/config/common_armv8a_linux +++ b/config/common_armv8a_linux @@ -12,6 +12,12 @@ CONFIG_RTE_ARCH_64=y CONFIG_RTE_FORCE_INTRINSICS=y +# Use WFE instructions to implement the rte_wait_for_equal_xxx APIs, +# calling these APIs put the cores enter low power state while waiting +# for the memory address to be become equal to the expected value. +# This is supported only by aarch64. +CONFIG_RTE_USE_WFE=n + # Maximum available cache line size in arm64 implementations. # Setting to maximum available cache line size in generic config # to address minimum DMA alignment across all arm64 implementations.