From patchwork Mon Jun 24 15:40:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyu Min X-Patchwork-Id: 55249 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 94CC31BCB1; Mon, 24 Jun 2019 17:40:26 +0200 (CEST) Received: from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130]) by dpdk.org (Postfix) with ESMTP id 65C141BC70 for ; Mon, 24 Jun 2019 17:40:23 +0200 (CEST) From: Xiaoyu Min To: Adrien Mazarguil , John McNamara , Marko Kovacevic , Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko Cc: dev@dpdk.org Date: Mon, 24 Jun 2019 23:40:15 +0800 Message-Id: <20190624154018.128379-2-jackmin@mellanox.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190624154018.128379-1-jackmin@mellanox.com> References: <20190624154018.128379-1-jackmin@mellanox.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 1/4] ethdev: add GRE key field to flow API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add new rte_flow_item_gre_key in order to match the optional key field. Signed-off-by: Xiaoyu Min Acked-by: Ori Kam --- doc/guides/prog_guide/rte_flow.rst | 9 +++++++++ lib/librte_ethdev/rte_flow.c | 1 + lib/librte_ethdev/rte_flow.h | 27 +++++++++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index a34d012e55..e900a53e3c 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -980,6 +980,15 @@ Matches a GRE header. - ``protocol``: protocol type. - Default ``mask`` matches protocol only. +Item: ``GRE_KEY`` +^^^^^^^^^^^^^^^^^ + +Matches a GRE key field. +This should be preceded by item ``GRE`` + +- ``key``: key value. +- Default ``mask`` matches key only. + Item: ``FUZZY`` ^^^^^^^^^^^^^^^ diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c index 3277be1edb..1cd5f4d263 100644 --- a/lib/librte_ethdev/rte_flow.c +++ b/lib/librte_ethdev/rte_flow.c @@ -55,6 +55,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = { MK_FLOW_ITEM(NVGRE, sizeof(struct rte_flow_item_nvgre)), MK_FLOW_ITEM(MPLS, sizeof(struct rte_flow_item_mpls)), MK_FLOW_ITEM(GRE, sizeof(struct rte_flow_item_gre)), + MK_FLOW_ITEM(GRE_KEY, sizeof(struct rte_flow_item_gre_key)), MK_FLOW_ITEM(FUZZY, sizeof(struct rte_flow_item_fuzzy)), MK_FLOW_ITEM(GTP, sizeof(struct rte_flow_item_gtp)), MK_FLOW_ITEM(GTPC, sizeof(struct rte_flow_item_gtp)), diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h index f3a8fb103f..a708ccd53b 100644 --- a/lib/librte_ethdev/rte_flow.h +++ b/lib/librte_ethdev/rte_flow.h @@ -289,6 +289,13 @@ enum rte_flow_item_type { */ RTE_FLOW_ITEM_TYPE_GRE, + /** + * Matches a GRE optional key field. + * + * See struct rte_flow_item_gre_key. + */ + RTE_FLOW_ITEM_TYPE_GRE_KEY, + /** * [META] * @@ -856,6 +863,26 @@ static const struct rte_flow_item_gre rte_flow_item_gre_mask = { }; #endif +/** + * RTE_FLOW_ITEM_GRE_KEY. + * + * Matches the presence of a GRE key. + * + * Normally preceding by: + * + * - RTE_FLOW_ITEM_TYPE_GRE + */ +struct rte_flow_item_gre_key { + rte_be32_t key; /**< Application specific key value (K bit). */ +}; + +/** Default mask for RTE_FLOW_ITEM_TYPE_GRE_KEY. */ +#ifndef __cplusplus +static const struct rte_flow_item_gre_key rte_flow_item_gre_key_mask = { + .key = RTE_BE32(UINT32_MAX), +}; +#endif + /** * RTE_FLOW_ITEM_TYPE_FUZZY * From patchwork Mon Jun 24 15:40:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyu Min X-Patchwork-Id: 55250 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 89C5B1BCE3; Mon, 24 Jun 2019 17:40:29 +0200 (CEST) Received: from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130]) by dpdk.org (Postfix) with ESMTP id 8E9D81BC87 for ; Mon, 24 Jun 2019 17:40:24 +0200 (CEST) From: Xiaoyu Min To: Shahaf Shuler , Yongseok Koh Cc: dev@dpdk.org Date: Mon, 24 Jun 2019 23:40:16 +0800 Message-Id: <20190624154018.128379-3-jackmin@mellanox.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190624154018.128379-1-jackmin@mellanox.com> References: <20190624154018.128379-1-jackmin@mellanox.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 2/4] net/mlx5: support match GRE protocol on DR engine X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" DR engine support matching on GRE protocol field without MPLS supports. So bypassing the MPLS check when DR is enabled. Signed-off-by: Xiaoyu Min --- drivers/net/mlx5/mlx5_flow.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index c03eb4c376..4cb04c32ff 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1612,6 +1612,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item, sizeof(struct rte_flow_item_gre), error); if (ret < 0) return ret; +#ifndef HAVE_MLX5DV_DR #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT if (spec && (spec->protocol & mask->protocol)) return rte_flow_error_set(error, ENOTSUP, @@ -1619,6 +1620,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item, "without MPLS support the" " specification cannot be used for" " filtering"); +#endif #endif return 0; } From patchwork Mon Jun 24 15:40:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyu Min X-Patchwork-Id: 55251 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A08811BD26; Mon, 24 Jun 2019 17:40:31 +0200 (CEST) Received: from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130]) by dpdk.org (Postfix) with ESMTP id D10271BC87 for ; Mon, 24 Jun 2019 17:40:25 +0200 (CEST) From: Xiaoyu Min To: Shahaf Shuler , Yongseok Koh Cc: dev@dpdk.org Date: Mon, 24 Jun 2019 23:40:17 +0800 Message-Id: <20190624154018.128379-4-jackmin@mellanox.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190624154018.128379-1-jackmin@mellanox.com> References: <20190624154018.128379-1-jackmin@mellanox.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 3/4] net/mlx5: match GRE's key and present bits X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" support matching on the present bits (C,K,S) as well as the optional key field. If the rte_flow_item_gre_key is specified in pattern, it will set K present match automatically. Signed-off-by: Xiaoyu Min --- drivers/net/mlx5/mlx5_flow.c | 49 +++++++++++++++++++- drivers/net/mlx5/mlx5_flow.h | 5 +++ drivers/net/mlx5/mlx5_flow_dv.c | 80 +++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_prm.h | 6 ++- 4 files changed, 138 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 4cb04c32ff..4f0583eead 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1564,6 +1564,49 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, " defined"); return 0; } +/** + * Validate GRE Key item. + * + * @param[in] item + * Item specification. + * @param[in] item_flags + * Bit flags to mark detected items. + * @param[in] target_protocol + * The next protocol in the previous item. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, + uint64_t item_flags, + struct rte_flow_error *error) +{ + const struct rte_flow_item_gre_key *mask = item->mask; + int ret = 0; + + if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "Multiple GRE key not support"); + if (!(item_flags & MLX5_FLOW_LAYER_GRE)) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "No preceding GRE header"); + if (item_flags & MLX5_FLOW_LAYER_INNER) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "GRE key following a wrong item"); + if (!mask) + mask = &rte_flow_item_gre_key_mask; + ret = mlx5_flow_item_acceptable + (item, (const uint8_t *)mask, + (const uint8_t *)&rte_flow_item_gre_key_mask, + sizeof(struct rte_flow_item_gre_key), error); + return ret; +} /** * Validate GRE item. @@ -1589,6 +1632,10 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item, const struct rte_flow_item_gre *spec __rte_unused = item->spec; const struct rte_flow_item_gre *mask = item->mask; int ret; + const struct rte_flow_item_gre nic_mask = { + .c_rsvd0_ver = RTE_BE16(0xB000), + .protocol = RTE_BE16(UINT16_MAX), + }; if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) return rte_flow_error_set(error, EINVAL, @@ -1608,7 +1655,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item, mask = &rte_flow_item_gre_mask; ret = mlx5_flow_item_acceptable (item, (const uint8_t *)mask, - (const uint8_t *)&rte_flow_item_gre_mask, + (const uint8_t *)&nic_mask, sizeof(struct rte_flow_item_gre), error); if (ret < 0) return ret; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index b6654200cb..0d83539cc9 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -50,6 +50,8 @@ #define MLX5_FLOW_ITEM_METADATA (1u << 16) #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) +#define MLX5_FLOW_LAYER_GRE_KEY (1u << 18) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) @@ -480,6 +482,9 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, uint64_t item_flags, uint8_t target_protocol, struct rte_flow_error *error); +int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, + uint64_t item_flags, + struct rte_flow_error *error); int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, uint64_t item_flags, const struct rte_flow_item_ipv4 *acc_mask, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 933ad0b819..eca926d670 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -2177,6 +2177,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, return ret; last_item = MLX5_FLOW_LAYER_GRE; break; + case RTE_FLOW_ITEM_TYPE_GRE_KEY: + ret = mlx5_flow_validate_item_gre_key + (items, item_flags, error); + if (ret < 0) + return ret; + item_flags |= MLX5_FLOW_LAYER_GRE_KEY; + break; case RTE_FLOW_ITEM_TYPE_VXLAN: ret = mlx5_flow_validate_item_vxlan(items, item_flags, error); @@ -2922,6 +2929,43 @@ flow_dv_translate_item_udp(void *matcher, void *key, rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port)); } +/** + * Add GRE optional Key item to matcher and to the value. + * + * @param[in, out] matcher + * Flow matcher. + * @param[in, out] key + * Flow matcher value. + * @param[in] item + * Flow pattern to translate. + * @param[in] inner + * Item is inner pattern. + */ +static void +flow_dv_translate_item_gre_key(void *matcher, void *key, + const struct rte_flow_item *item) +{ + const struct rte_flow_item_gre_key *key_m = item->mask; + const struct rte_flow_item_gre_key *key_v = item->spec; + void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters); + void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters); + + if (!key_v) + return; + if (!key_m) + key_m = &rte_flow_item_gre_key_mask; + MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1); + MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1); + MLX5_SET(fte_match_set_misc, misc_m, gre_key_h, + rte_be_to_cpu_32(key_m->key) >> 8); + MLX5_SET(fte_match_set_misc, misc_v, gre_key_h, + rte_be_to_cpu_32(key_v->key & key_m->key) >> 8); + MLX5_SET(fte_match_set_misc, misc_m, gre_key_l, + rte_be_to_cpu_32(key_m->key) & 0xFF); + MLX5_SET(fte_match_set_misc, misc_v, gre_key_l, + rte_be_to_cpu_32(key_v->key & key_m->key) & 0xFF); +} + /** * Add GRE item to matcher and to the value. * @@ -2945,6 +2989,20 @@ flow_dv_translate_item_gre(void *matcher, void *key, void *headers_v; void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters); void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters); + struct { + union { + __extension__ + struct { + uint16_t version:3; + uint16_t rsvd0:9; + uint16_t s_present:1; + uint16_t k_present:1; + uint16_t rsvd_bit1:1; + uint16_t c_present:1; + }; + uint16_t value; + }; + } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v; if (inner) { headers_m = MLX5_ADDR_OF(fte_match_param, matcher, @@ -2965,6 +3023,23 @@ flow_dv_translate_item_gre(void *matcher, void *key, rte_be_to_cpu_16(gre_m->protocol)); MLX5_SET(fte_match_set_misc, misc_v, gre_protocol, rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol)); + gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver); + gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver); + MLX5_SET(fte_match_set_misc, misc_m, gre_c_present, + gre_crks_rsvd0_ver_m.c_present); + MLX5_SET(fte_match_set_misc, misc_v, gre_c_present, + gre_crks_rsvd0_ver_v.c_present & + gre_crks_rsvd0_ver_m.c_present); + MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, + gre_crks_rsvd0_ver_m.k_present); + MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, + gre_crks_rsvd0_ver_v.k_present & + gre_crks_rsvd0_ver_m.k_present); + MLX5_SET(fte_match_set_misc, misc_m, gre_s_present, + gre_crks_rsvd0_ver_m.s_present); + MLX5_SET(fte_match_set_misc, misc_v, gre_s_present, + gre_crks_rsvd0_ver_v.s_present & + gre_crks_rsvd0_ver_m.s_present); } /** @@ -3995,6 +4070,11 @@ flow_dv_translate(struct rte_eth_dev *dev, items, tunnel); last_item = MLX5_FLOW_LAYER_GRE; break; + case RTE_FLOW_ITEM_TYPE_GRE_KEY: + flow_dv_translate_item_gre_key(match_mask, + match_value, items); + item_flags |= MLX5_FLOW_LAYER_GRE_KEY; + break; case RTE_FLOW_ITEM_TYPE_NVGRE: flow_dv_translate_item_nvgre(match_mask, match_value, items, tunnel); diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h index 1a199580c5..4022770b7b 100644 --- a/drivers/net/mlx5/mlx5_prm.h +++ b/drivers/net/mlx5/mlx5_prm.h @@ -416,7 +416,11 @@ typedef uint8_t u8; #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) struct mlx5_ifc_fte_match_set_misc_bits { - u8 reserved_at_0[0x8]; + u8 gre_c_present[0x1]; + u8 reserved_at_1[0x1]; + u8 gre_k_present[0x1]; + u8 gre_s_present[0x1]; + u8 source_vhci_port[0x4]; u8 source_sqn[0x18]; u8 reserved_at_20[0x10]; u8 source_port[0x10]; From patchwork Mon Jun 24 15:40:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyu Min X-Patchwork-Id: 55252 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B36521BD64; Mon, 24 Jun 2019 17:40:33 +0200 (CEST) Received: from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130]) by dpdk.org (Postfix) with ESMTP id D91331BCD2 for ; Mon, 24 Jun 2019 17:40:27 +0200 (CEST) From: Xiaoyu Min To: Adrien Mazarguil , Wenzhuo Lu , Jingjing Wu , Bernard Iremonger , John McNamara , Marko Kovacevic Cc: dev@dpdk.org Date: Mon, 24 Jun 2019 23:40:18 +0800 Message-Id: <20190624154018.128379-5-jackmin@mellanox.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190624154018.128379-1-jackmin@mellanox.com> References: <20190624154018.128379-1-jackmin@mellanox.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 4/4] app/testpmd: match GRE's key and present bits X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" support matching on GRE key and present bits (C,K,S) example testpmd command could be: testpmd>flow create 0 ingress group 1 pattern eth / ipv4 / gre crksv is 0x2000 crksv mask 0xb000 / gre_key key is 0x12345678 / end actions rss queues 1 0 end / mark id 196 / end Which will match GRE packet with k present bit set and key value is 0x12345678. Signed-off-by: Xiaoyu Min --- app/test-pmd/cmdline_flow.c | 33 +++++++++++++++++++++ doc/guides/testpmd_app_ug/testpmd_funcs.rst | 4 +++ 2 files changed, 37 insertions(+) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 201bd9de56..c8e0785a41 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -148,6 +148,9 @@ enum index { ITEM_MPLS_LABEL, ITEM_GRE, ITEM_GRE_PROTO, + ITEM_GRE_CRKSV, + ITEM_GRE_KEY, + ITEM_GRE_KEY_KEY, ITEM_FUZZY, ITEM_FUZZY_THRESH, ITEM_GTP, @@ -595,6 +598,7 @@ static const enum index next_item[] = { ITEM_NVGRE, ITEM_MPLS, ITEM_GRE, + ITEM_GRE_KEY, ITEM_FUZZY, ITEM_GTP, ITEM_GTPC, @@ -755,6 +759,13 @@ static const enum index item_mpls[] = { static const enum index item_gre[] = { ITEM_GRE_PROTO, + ITEM_GRE_CRKSV, + ITEM_NEXT, + ZERO, +}; + +static const enum index item_gre_key[] = { + ITEM_GRE_KEY_KEY, ITEM_NEXT, ZERO, }; @@ -1898,6 +1909,28 @@ static const struct token token_list[] = { .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre, protocol)), }, + [ITEM_GRE_CRKSV] = { + .name = "crksv", + .help = "GRE's first word (bit0 - bit15)", + .next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre, + c_rsvd0_ver)), + }, + [ITEM_GRE_KEY] = { + .name = "gre_key", + .help = "match GRE Key", + .priv = PRIV_ITEM(GRE_KEY, + sizeof(struct rte_flow_item_gre_key)), + .next = NEXT(item_gre_key), + .call = parse_vc, + }, + [ITEM_GRE_KEY_KEY] = { + .name = "key", + .help = "GRE key", + .next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_key, + key)), + }, [ITEM_FUZZY] = { .name = "fuzzy", .help = "fuzzy pattern match, expect faster than default", diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst index cb83a3ce8a..fc3ba8a009 100644 --- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst +++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst @@ -3804,6 +3804,10 @@ This section lists supported pattern items and their attributes, if any. - ``protocol {unsigned}``: protocol type. +- ``gre_key``: match GRE optional key field. + + - ``key {unsigned}``: key value. + - ``fuzzy``: fuzzy pattern match, expect faster than default. - ``thresh {unsigned}``: accuracy threshold.