From patchwork Mon Jun 24 02:52:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 55224 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 041AD1BF6C; Mon, 24 Jun 2019 04:53:07 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 6F1CA1BEAD for ; Mon, 24 Jun 2019 04:53:01 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jun 2019 19:52:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,410,1557212400"; d="scan'208";a="183991184" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga004.fm.intel.com with ESMTP; 23 Jun 2019 19:52:59 -0700 From: Nicolas Chautru To: akhil.goyal@nxp.com, dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@intel.com, amr.mokhtar@intel.com, Nicolas Chautru Date: Sun, 23 Jun 2019 19:52:47 -0700 Message-Id: <1561344776-43990-2-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> References: <1561136352-32198-2-git-send-email-nicolas.chautru@intel.com> <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v4 01/10] baseband/turbo_sw: baseband/turbo_sw: dependency patch X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Not meant for review, purely for dependency for CI. This is a squash of the related serie which is not applied yet: option to build turbosw PMD without SDK https://patches.dpdk.org/project/dpdk/list/?series=5093 Signed-off-by: Nicolas Chautru Acked-by: Amr Mokhtar --- config/common_base | 3 +- doc/guides/bbdevs/turbo_sw.rst | 81 +++++++++++++----------- drivers/baseband/meson.build | 2 +- drivers/baseband/turbo_sw/Makefile | 13 ++-- drivers/baseband/turbo_sw/bbdev_turbo_software.c | 51 ++++++++++++++- drivers/baseband/turbo_sw/meson.build | 30 +++++++++ meson_options.txt | 2 + mk/rte.app.mk | 3 + 8 files changed, 138 insertions(+), 47 deletions(-) create mode 100644 drivers/baseband/turbo_sw/meson.build diff --git a/config/common_base b/config/common_base index e406e78..21ab606 100644 --- a/config/common_base +++ b/config/common_base @@ -528,6 +528,7 @@ CONFIG_RTE_PMD_PACKET_PREFETCH=y CONFIG_RTE_LIBRTE_BBDEV=y CONFIG_RTE_BBDEV_MAX_DEVS=128 CONFIG_RTE_BBDEV_OFFLOAD_COST=y +CONFIG_RTE_BBDEV_SDK_AVX2=n # # Compile PMD for NULL bbdev device @@ -537,7 +538,7 @@ CONFIG_RTE_LIBRTE_PMD_BBDEV_NULL=y # # Compile PMD for turbo software bbdev device # -CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=n +CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=y # # Compile generic crypto device library diff --git a/doc/guides/bbdevs/turbo_sw.rst b/doc/guides/bbdevs/turbo_sw.rst index 29f7ec9..455fa1d 100644 --- a/doc/guides/bbdevs/turbo_sw.rst +++ b/doc/guides/bbdevs/turbo_sw.rst @@ -4,23 +4,39 @@ SW Turbo Poll Mode Driver ========================= -The SW Turbo PMD (**baseband_turbo_sw**) provides a poll mode bbdev driver that utilizes -Intel optimized libraries for LTE Layer 1 workloads acceleration. This PMD -supports the functions: Turbo FEC, Rate Matching and CRC functions. +The SW Turbo PMD (**baseband_turbo_sw**) provides a software only poll mode bbdev +driver that can optionally utilize Intel optimized libraries for LTE Layer 1 +workloads acceleration. + +Note that the driver can also be built without any dependency with reduced +functionality for maintenance purpose. + +To enable linking to the SDK libraries see detailed installation section below. +One flag can be enabled depending on whether the target machine can support +AVX2 instructions sets and the related SDK libraries for vectorized +signal processing functions are installed : +- CONFIG_RTE_BBDEV_SDK_AVX2 + +By default this flag is disabled. For AVX2 machine and SDK +library installed then this flag can be enabled. + +This PMD supports the functions: FEC, Rate Matching and CRC functions detailed +in the Features section. Features -------- -SW Turbo PMD has support for the following capabilities: +SW Turbo PMD can support for the following capabilities when the SDK libraries +are used: -For the encode operation: +For the LTE encode operation: * ``RTE_BBDEV_TURBO_CRC_24A_ATTACH`` * ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` * ``RTE_BBDEV_TURBO_RATE_MATCH`` * ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS`` -For the decode operation: +For the LTE decode operation: * ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` * ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` @@ -41,14 +57,10 @@ Installation FlexRAN SDK Download ~~~~~~~~~~~~~~~~~~~~ -To build DPDK with the *baseband_turbo_sw* PMD the user is required to download -the export controlled ``FlexRAN SDK`` Libraries. An account at `Intel Resource -Design Center `_ -needs to be registered. +As an option it is possible to link this driver with FleXRAN SDK libraries +which can enable real time signal processing using AVX instructions. -Once registered, the user needs to log in, and look for -*Intel FlexRAN Software Release Package -18-09* to download or directly through -this `link `_. +These libraries are available through this link `link `_. After download is complete, the user needs to unpack and compile on their system before building DPDK. @@ -57,24 +69,24 @@ The following table maps DPDK versions with past FlexRAN SDK releases: .. _table_flexran_releases: -.. table:: DPDK and FlexRAN SDK releases compliance +.. table:: DPDK and FlexRAN FEC SDK releases compliance ===================== ============================ - DPDK version FlexRAN SDK release + DPDK version FlexRAN FEC SDK release ===================== ============================ - 18.02 1.3.0 - 18.05 1.4.0 - 18.08 1.6.0 - 19.02 18.09 + 19.08 19.04 ===================== ============================ FlexRAN SDK Installation ~~~~~~~~~~~~~~~~~~~~~~~~ +Note that the installation of these libraries is optional. + The following are pre-requisites for building FlexRAN SDK Libraries: - (a) An AVX2 supporting machine - (b) CentOS Linux release 7.2.1511 (Core) operating system - (c) Intel ICC 18.0.1 20171018 compiler installed + (a) An AVX2 or AVX512 supporting machine + (b) CentOS Linux release 7.2.1511 (Core) operating system is advised + (c) Intel ICC 18.0.1 20171018 compiler or more recent and related libraries + ICC is available with a free community license `link `_. The following instructions should be followed in this exact order: @@ -84,25 +96,18 @@ The following instructions should be followed in this exact order: source /linux/bin/compilervars.sh intel64 -platform linux -#. Extract the ``605167-flexran-18-09-tar.gz`` package: - - .. code-block:: console - - mkdir FlexRAN-18.09 - tar xvzf 605167-flexran-18-09-tar.gz -C FlexRAN-18.09/ - #. Run the SDK extractor script and accept the license: .. code-block:: console - cd /FlexRAN-18.09/ - ./SDK-18.09.sh + cd + ./FlexRAN-FEC-SDK-19-04.sh #. Generate makefiles based on system configuration: .. code-block:: console - cd /FlexRAN-18.09/SDK-18.09/sdk/ + cd /FlexRAN-FEC-SDK-19-04/sdk/ ./create-makefiles-linux.sh #. A build folder is generated in this form ``build--``, enter that @@ -129,12 +134,14 @@ Example: .. code-block:: console - export FLEXRAN_SDK=/FlexRAN-18.09/SDK-18.09/sdk/build-avx2-icc/install - export DIR_WIRELESS_SDK=/FlexRAN-18.09/SDK-18.09/sdk/ - + export FLEXRAN_SDK=/FlexRAN-FEC-SDK-19-04/sdk/build-avx2-icc/install + export DIR_WIRELESS_SDK=/FlexRAN-FEC-SDK-19-04/sdk/build-avx2-icc/ -* Set ``CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=y`` in DPDK common configuration - file ``config/common_base``. +* Set ``CONFIG_RTE_BBDEV_SDK_AVX2=y`` + in DPDK common configuration file ``config/common_base`` to be able to use + the SDK libraries as mentioned above. + If no flag are set the PMD driver will still build but its capabilities + will be limited accordingly. To use the PMD in an application, user must: diff --git a/drivers/baseband/meson.build b/drivers/baseband/meson.build index 52489df..40a87d2 100644 --- a/drivers/baseband/meson.build +++ b/drivers/baseband/meson.build @@ -1,7 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Luca Boccassi -drivers = ['null'] +drivers = ['null', 'turbo_sw'] config_flag_fmt = 'RTE_LIBRTE_@0@_PMD' driver_name_fmt = 'rte_pmd_@0@' diff --git a/drivers/baseband/turbo_sw/Makefile b/drivers/baseband/turbo_sw/Makefile index d364677..414d0d9 100644 --- a/drivers/baseband/turbo_sw/Makefile +++ b/drivers/baseband/turbo_sw/Makefile @@ -3,9 +3,6 @@ include $(RTE_SDK)/mk/rte.vars.mk -ifeq ($(FLEXRAN_SDK),) -$(error "Please define FLEXRAN_SDK environment variable") -endif # library name LIB = librte_pmd_bbdev_turbo_sw.a @@ -21,17 +18,21 @@ LDLIBS += -lrte_bus_vdev # versioning export map EXPORT_MAP := rte_pmd_bbdev_turbo_sw_version.map -# external library dependencies +# external library dependencies if available +ifeq ($(CONFIG_RTE_BBDEV_SDK_AVX2),y) +ifeq ($(FLEXRAN_SDK),) +$(error "Please define FLEXRAN_SDK environment variable") +endif CFLAGS += -I$(FLEXRAN_SDK)/lib_common CFLAGS += -I$(FLEXRAN_SDK)/lib_turbo CFLAGS += -I$(FLEXRAN_SDK)/lib_crc CFLAGS += -I$(FLEXRAN_SDK)/lib_rate_matching - LDLIBS += -L$(FLEXRAN_SDK)/lib_turbo -lturbo LDLIBS += -L$(FLEXRAN_SDK)/lib_crc -lcrc LDLIBS += -L$(FLEXRAN_SDK)/lib_rate_matching -lrate_matching LDLIBS += -L$(FLEXRAN_SDK)/lib_common -lcommon -LDLIBS += -lstdc++ -lirc -limf -lipps +LDLIBS += -lstdc++ -lirc -limf -lipps -lsvml +endif # library version LIBABIVER := 1 diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c index 5204a77..94aa536 100644 --- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c +++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c @@ -14,10 +14,11 @@ #include #include +#ifdef RTE_BBDEV_SDK_AVX2 #include #include #include -#include +#endif #define DRIVER_NAME baseband_turbo_sw @@ -83,6 +84,7 @@ struct turbo_sw_queue { enum rte_bbdev_op_type type; } __rte_cache_aligned; +#ifdef RTE_BBDEV_SDK_AVX2 static inline char * mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len) { @@ -128,6 +130,7 @@ struct turbo_sw_queue { return result; } +#endif /* Read flag value 0/1 from bitmap */ static inline bool @@ -143,6 +146,7 @@ struct turbo_sw_queue { struct bbdev_private *internals = dev->data->dev_private; static const struct rte_bbdev_op_cap bbdev_capabilities[] = { +#ifdef RTE_BBDEV_SDK_AVX2 { .type = RTE_BBDEV_OP_TURBO_DEC, .cap.turbo_dec = { @@ -172,6 +176,7 @@ struct turbo_sw_queue { .num_buffers_dst = RTE_BBDEV_MAX_CODE_BLOCKS, } }, +#endif RTE_BBDEV_END_OF_CAPABILITIES_LIST() }; @@ -179,7 +184,12 @@ struct turbo_sw_queue { .queue_size = RTE_BBDEV_QUEUE_SIZE_LIMIT, }; +#ifdef RTE_BBDEV_SDK_AVX2 static const enum rte_cpu_flag_t cpu_flag = RTE_CPUFLAG_SSE4_2; + dev_info->cpu_flag_reqs = &cpu_flag; +#else + dev_info->cpu_flag_reqs = NULL; +#endif default_queue_conf.socket = dev->data->socket_id; @@ -191,7 +201,6 @@ struct turbo_sw_queue { dev_info->max_ul_queue_priority = 0; dev_info->default_queue_conf = default_queue_conf; dev_info->capabilities = bbdev_capabilities; - dev_info->cpu_flag_reqs = &cpu_flag; dev_info->min_alignment = 64; rte_bbdev_log_debug("got device info from %u\n", dev->data->dev_id); @@ -410,6 +419,7 @@ struct turbo_sw_queue { .queue_release = q_release }; +#ifdef RTE_BBDEV_SDK_AVX2 /* Checks if the encoder input buffer is correct. * Returns 0 if it's valid, -1 otherwise. */ @@ -464,6 +474,7 @@ struct turbo_sw_queue { return 0; } +#endif static inline void process_enc_cb(struct turbo_sw_queue *q, struct rte_bbdev_enc_op *op, @@ -472,6 +483,7 @@ struct turbo_sw_queue { struct rte_mbuf *m_out, uint16_t in_offset, uint16_t out_offset, uint16_t in_length, struct rte_bbdev_stats *q_stats) { +#ifdef RTE_BBDEV_SDK_AVX2 int ret; int16_t k_idx; uint16_t m; @@ -724,6 +736,22 @@ struct turbo_sw_queue { } *tmp_out = 0; } +#else + RTE_SET_USED(q); + RTE_SET_USED(op); + RTE_SET_USED(r); + RTE_SET_USED(c); + RTE_SET_USED(k); + RTE_SET_USED(ncb); + RTE_SET_USED(e); + RTE_SET_USED(m_in); + RTE_SET_USED(m_out_head); + RTE_SET_USED(m_out); + RTE_SET_USED(in_offset); + RTE_SET_USED(out_offset); + RTE_SET_USED(in_length); + RTE_SET_USED(q_stats); +#endif } static inline void @@ -835,6 +863,7 @@ struct turbo_sw_queue { NULL); } +#ifdef RTE_BBDEV_SDK_AVX2 static inline void move_padding_bytes(const uint8_t *in, uint8_t *out, uint16_t k, uint16_t ncb) @@ -847,6 +876,7 @@ struct turbo_sw_queue { rte_memcpy(&out[nd + kpi + 64], &in[kpi], d); rte_memcpy(&out[(nd - 1) + 2 * (kpi + 64)], &in[2 * kpi], d); } +#endif static inline void process_dec_cb(struct turbo_sw_queue *q, struct rte_bbdev_dec_op *op, @@ -856,6 +886,7 @@ struct turbo_sw_queue { uint16_t crc24_overlap, uint16_t in_length, struct rte_bbdev_stats *q_stats) { +#ifdef RTE_BBDEV_SDK_AVX2 int ret; int32_t k_idx; int32_t iter_cnt; @@ -972,6 +1003,22 @@ struct turbo_sw_queue { rte_bbdev_log(ERR, "Turbo Decoder failed"); return; } +#else + RTE_SET_USED(q); + RTE_SET_USED(op); + RTE_SET_USED(c); + RTE_SET_USED(k); + RTE_SET_USED(kw); + RTE_SET_USED(m_in); + RTE_SET_USED(m_out_head); + RTE_SET_USED(m_out); + RTE_SET_USED(in_offset); + RTE_SET_USED(out_offset); + RTE_SET_USED(check_crc_24b); + RTE_SET_USED(crc24_overlap); + RTE_SET_USED(in_length); + RTE_SET_USED(q_stats); +#endif } static inline void diff --git a/drivers/baseband/turbo_sw/meson.build b/drivers/baseband/turbo_sw/meson.build new file mode 100644 index 0000000..438b5a7 --- /dev/null +++ b/drivers/baseband/turbo_sw/meson.build @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2019 Intel Corporation + +path = get_option('flexran_sdk') + +if dpdk_conf.has('RTE_BBDEV_SDK_AVX2') + lib = cc.find_library('libturbo', dirs: [path + '/lib_turbo'], required: false) + if not lib.found() + build = false + else + ext_deps += cc.find_library('libturbo', dirs: [path + '/lib_turbo'], required: true) + ext_deps += cc.find_library('libcrc', dirs: [path + '/lib_crc'], required: true) + ext_deps += cc.find_library('librate_matching', dirs: [path + '/lib_rate_matching'], required: true) + ext_deps += cc.find_library('libcommon', dirs: [path + '/lib_common'], required: true) + ext_deps += cc.find_library('libstdc++', required: true) + ext_deps += cc.find_library('libirc', required: true) + ext_deps += cc.find_library('libimf', required: true) + ext_deps += cc.find_library('libipps', required: true) + ext_deps += cc.find_library('libsvml', required: true) + includes += include_directories(path + '/lib_turbo') + includes += include_directories(path + '/lib_crc') + includes += include_directories(path + '/lib_rate_matching') + includes += include_directories(path + '/lib_common') + endif +endif + +deps += ['bbdev', 'bus_vdev', 'ring'] +name = 'bbdev_turbo_sw' +allow_experimental_apis = true +sources = files('bbdev_turbo_software.c') diff --git a/meson_options.txt b/meson_options.txt index 16d9f92..92d3e97 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -10,6 +10,8 @@ option('enable_kmods', type: 'boolean', value: true, description: 'build kernel modules') option('examples', type: 'string', value: '', description: 'Comma-separated list of examples to build by default') +option('flexran_sdk', type: 'string', value: '', + description: 'Path to FlexRAN SDK optional Libraries for BBDEV device') option('ibverbs_link', type: 'combo', choices : ['shared', 'dlopen'], value: 'shared', description: 'Linkage method (shared/dlopen) for Mellanox PMDs with ibverbs dependencies.') option('include_subdir_arch', type: 'string', value: '', diff --git a/mk/rte.app.mk b/mk/rte.app.mk index d0df0b0..2c3d07a 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -219,11 +219,14 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_NULL) += -lrte_pmd_bbdev_null # TURBO SOFTWARE PMD is dependent on the FLEXRAN library _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -lrte_pmd_bbdev_turbo_sw +ifeq ($(CONFIG_RTE_BBDEV_SDK_AVX2),y) +# Dependency on the FLEXRAN SDK library if available _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_crc -lcrc _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_turbo -lturbo _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_rate_matching -lrate_matching _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_common -lcommon _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -lirc -limf -lstdc++ -lipps +endif # CONFIG_RTE_BBDEV_SDK_AVX2 endif # CONFIG_RTE_LIBRTE_BBDEV ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y) From patchwork Mon Jun 24 02:52:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 55225 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 668D328EE; Mon, 24 Jun 2019 04:53:10 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 7C5731BF0A for ; Mon, 24 Jun 2019 04:53:01 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jun 2019 19:52:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,410,1557212400"; d="scan'208";a="183991187" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga004.fm.intel.com with ESMTP; 23 Jun 2019 19:52:59 -0700 From: Nicolas Chautru To: akhil.goyal@nxp.com, dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@intel.com, amr.mokhtar@intel.com, Nicolas Chautru Date: Sun, 23 Jun 2019 19:52:48 -0700 Message-Id: <1561344776-43990-3-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> References: <1561136352-32198-2-git-send-email-nicolas.chautru@intel.com> <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v4 02/10] baseband/fpga_lte_fec: dependency patch X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Not meant for review, purely for dependency for CI. This is a squash of the related serie which is not applied yet: adding driver for FEC on FPGA https://patches.dpdk.org/project/dpdk/list/?series=5017 Signed-off-by: Nicolas Chautru Acked-by: Amr Mokhtar --- config/common_base | 5 + doc/guides/bbdevs/fpga_lte_fec.rst | 318 +++ doc/guides/bbdevs/index.rst | 1 + drivers/baseband/Makefile | 2 + drivers/baseband/fpga_lte_fec/Makefile | 29 + drivers/baseband/fpga_lte_fec/fpga_lte_fec.c | 2674 ++++++++++++++++++++ drivers/baseband/fpga_lte_fec/fpga_lte_fec.h | 73 + drivers/baseband/fpga_lte_fec/meson.build | 7 + .../rte_pmd_bbdev_fpga_lte_fec_version.map | 3 + drivers/baseband/meson.build | 2 +- mk/rte.app.mk | 1 + 11 files changed, 3114 insertions(+), 1 deletion(-) create mode 100644 doc/guides/bbdevs/fpga_lte_fec.rst create mode 100644 drivers/baseband/fpga_lte_fec/Makefile create mode 100644 drivers/baseband/fpga_lte_fec/fpga_lte_fec.c create mode 100644 drivers/baseband/fpga_lte_fec/fpga_lte_fec.h create mode 100644 drivers/baseband/fpga_lte_fec/meson.build create mode 100644 drivers/baseband/fpga_lte_fec/rte_pmd_bbdev_fpga_lte_fec_version.map diff --git a/config/common_base b/config/common_base index 21ab606..cc13025 100644 --- a/config/common_base +++ b/config/common_base @@ -526,6 +526,7 @@ CONFIG_RTE_PMD_PACKET_PREFETCH=y # EXPERIMENTAL: API may change without prior notice # CONFIG_RTE_LIBRTE_BBDEV=y +CONFIG_RTE_LIBRTE_BBDEV_DEBUG=n CONFIG_RTE_BBDEV_MAX_DEVS=128 CONFIG_RTE_BBDEV_OFFLOAD_COST=y CONFIG_RTE_BBDEV_SDK_AVX2=n @@ -540,6 +541,10 @@ CONFIG_RTE_LIBRTE_PMD_BBDEV_NULL=y # CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=y +# Compile PMD for Intel FPGA LTE FEC bbdev device +# +CONFIG_RTE_LIBRTE_PMD_FPGA_LTE_FEC=y + # # Compile generic crypto device library # diff --git a/doc/guides/bbdevs/fpga_lte_fec.rst b/doc/guides/bbdevs/fpga_lte_fec.rst new file mode 100644 index 0000000..71b058c --- /dev/null +++ b/doc/guides/bbdevs/fpga_lte_fec.rst @@ -0,0 +1,318 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2018 Intel Corporation + +Intel(R) FPGA LTE FEC Poll Mode Driver +====================================== + +The BBDEV FPGA LTE FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN +Turbo Encode / Decode LTE wireless acceleration function, using Intel's PCI-e and FPGA +based Vista Creek device. + +Features +-------- + +FPGA LTE FEC PMD supports the following features: + +- Turbo Encode in the DL with total throughput of 4.5 Gbits/s +- Turbo Decode in the UL with total throughput of 1.5 Gbits/s assuming 8 decoder iterations +- 8 VFs per PF (physical device) +- Maximum of 32 UL queues per VF +- Maximum of 32 DL queues per VF +- PCIe Gen-3 x8 Interface +- MSI-X +- SR-IOV + + +FPGA LTE FEC PMD supports the following BBDEV capabilities: + +* For the turbo encode operation: + - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s) + - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match bypass + - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue interrupts + + +* For the turbo decode operation: + - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s) + - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock de-interleave + - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue interrupts + - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR encoder i/p is supported + - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits appended while decoding + + +Limitations +----------- + +FPGA LTE FEC does not support the following: + +- Scatter-Gather function + + +Installation +-------------- + +Section 3 of the DPDK manual provides instuctions on installing and compiling DPDK. The +default set of bbdev compile flags may be found in config/common_base, where for example +the flag to build the FPGA LTE FEC device, ``CONFIG_RTE_LIBRTE_PMD_FPGA_LTE_FEC``, is already +set. It is assumed DPDK has been compiled using for instance: + +.. code-block:: console + + make install T=x86_64-native-linuxapp-gcc + + +DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual. +The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The +hugepage configuration of a server may be examined using: + +.. code-block:: console + + grep Huge* /proc/meminfo + + +Initialization +-------------- + +When the device first powers up, its PCI Physical Functions (PF) can be listed through this command: + +.. code-block:: console + + sudo lspci -vd1172:5052 + +The physical and virtual functions are compatible with Linux UIO drivers: +``vfio`` and ``igb_uio``. However, in order to work the FPGA LTE FEC device firstly needs +to be bound to one of these linux drivers through DPDK. + + +Bind PF UIO driver(s) +~~~~~~~~~~~~~~~~~~~~~ + +Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use +``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver. + +The igb_uio driver may be bound to the PF PCI device using one of three methods: + + +1. PCI functions (physical or virtual, depending on the use case) can be bound to +the UIO driver by repeating this command for every function. + +.. code-block:: console + + cd + insmod ./build/kmod/igb_uio.ko + echo "1172 5052" > /sys/bus/pci/drivers/igb_uio/new_id + lspci -vd1172: + + +2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool + +.. code-block:: console + + cd + ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0 + +where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd1172: + + +3. A third way to bind is to use ``dpdk-setup.sh`` tool + +.. code-block:: console + + cd + ./usertools/dpdk-setup.sh + + select 'Bind Ethernet/Crypto/Baseband device to IGB UIO module' + or + select 'Bind Ethernet/Crypto/Baseband device to VFIO module' depending on driver required + enter PCI device ID + select 'Display current Ethernet/Crypto/Baseband device settings' to confirm binding + + +In the same way the FPGA LTE FEC PF can be bound with vfio, but vfio driver does not +support SR-IOV configuration right out of the box, so it will need to be patched. + + +Enable Virtual Functions +~~~~~~~~~~~~~~~~~~~~~~~~ + +Now, it should be visible in the printouts that PCI PF is under igb_uio control +"``Kernel driver in use: igb_uio``" + +To show the number of available VFs on the device, read ``sriov_totalvfs`` file.. + +.. code-block:: console + + cat /sys/bus/pci/devices/0000\:\:./sriov_totalvfs + + where 0000\:\:. is the PCI device ID + + +To enable VFs via igb_uio, echo the number of virtual functions intended to +enable to ``max_vfs`` file.. + +.. code-block:: console + + echo > /sys/bus/pci/devices/0000\:\:./max_vfs + + +Afterwards, all VFs must be bound to appropriate UIO drivers as required, same +way it was done with the physical function previously. + +Enabling SR-IOV via vfio driver is pretty much the same, except that the file +name is different: + +.. code-block:: console + + echo > /sys/bus/pci/devices/0000\:\:./sriov_numvfs + + +Configure the VFs through PF +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The PCI virtual functions must be configured before working or getting assigned +to VMs/Containers. The configuration involves allocating the number of hardware +queues, priorities, load balance, bandwidth and other settings necessary for the +device to perform FEC functions. + +This configuration needs to be executed at least once after reboot or PCI FLR and can +be achieved by using the function ``fpga_lte_fec_configure()``, which sets up the +parameters defined in ``fpga_lte_fec_conf`` structure: + +.. code-block:: c + + struct fpga_lte_fec_conf { + bool pf_mode_en; + uint8_t vf_ul_queues_number[FPGA_LTE_FEC_NUM_VFS]; + uint8_t vf_dl_queues_number[FPGA_LTE_FEC_NUM_VFS]; + uint8_t ul_bandwidth; + uint8_t dl_bandwidth; + uint8_t ul_load_balance; + uint8_t dl_load_balance; + uint16_t flr_time_out; + }; + +- ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and + VFs are mutually exclusive and cannot run simultaneously. + Set to 1 for PF mode enabled. + If PF mode is enabled all queues available in the device are assigned + exclusively to PF and 0 queues given to VFs. + +- ``vf_*l_queues_number``: defines the hardware queue mapping for every VF. + +- ``*l_bandwidth``: in case of congestion on PCIe interface. The device + allocates different bandwidth to UL and DL. The weight is configured by this + setting. The unit of weight is 3 code blocks. For example, if the code block + cbps (code block per second) ratio between UL and DL is 12:1, then the + configuration value should be set to 36:3. The schedule algorithm is based + on code block regardless the length of each block. + +- ``*l_load_balance``: hardware queues are load-balanced in a round-robin + fashion. Queues get filled first-in first-out until they reach a pre-defined + watermark level, if exceeded, they won't get assigned new code blocks.. + This watermark is defined by this setting. + + If all hardware queues exceeds the watermark, no code blocks will be + streamed in from UL/DL code block FIFO. + +- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The + time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for + the FLR time out then set this setting to 0x262=610. + + +An example configuration code calling the function ``fpga_lte_fec_configure()`` is shown +below: + +.. code-block:: c + + struct fpga_lte_fec_conf conf; + unsigned int i; + + memset(&conf, 0, sizeof(struct fpga_lte_fec_conf)); + conf.pf_mode_en = 1; + + for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) { + conf.vf_ul_queues_number[i] = 4; + conf.vf_dl_queues_number[i] = 4; + } + conf.ul_bandwidth = 12; + conf.dl_bandwidth = 5; + conf.dl_load_balance = 64; + conf.ul_load_balance = 64; + + /* setup FPGA PF */ + ret = fpga_lte_fec_configure(info->dev_name, &conf); + TEST_ASSERT_SUCCESS(ret, + "Failed to configure 4G FPGA PF for bbdev %s", + info->dev_name); + + +Test Application +---------------- + +BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing +the functionality of FPGA LTE FEC turbo encode and turbo decode, depending on the device's +capabilities. The test application is located under app->test-bbdev folder and has the +following options: + +.. code-block:: console + + "-p", "--testapp-path": specifies path to the bbdev test app. + "-e", "--eal-params" : EAL arguments which are passed to the test app. + "-t", "--timeout" : Timeout in seconds (default=300). + "-c", "--test-cases" : Defines test cases to run. Run all if not specified. + "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data). + "-n", "--num-ops" : Number of operations to process on device (default=32). + "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32). + "-l", "--num-lcores" : Number of lcores to run (default=16). + "-i", "--init-device" : Initialise PF device with default values. + + +To execute the test application tool using simple turbo decode or turbo encode data, +type one of the following: + +.. code-block:: console + + ./test-bbdev.py -c validation -n 64 -b 8 -v ./turbo_dec_default.data + ./test-bbdev.py -c validation -n 64 -b 8 -v ./turbo_enc_default.data + + +The test application ``test-bbdev.py``, supports the ability to configure the PF device with +a default set of values, if the "-i" or "- -init-device" option is included. The default values +are defined in test_bbdev_perf.c as: + +- VF_UL_QUEUE_VALUE 4 +- VF_DL_QUEUE_VALUE 4 +- UL_BANDWIDTH 3 +- DL_BANDWIDTH 3 +- UL_LOAD_BALANCE 128 +- DL_LOAD_BALANCE 128 +- FLR_TIMEOUT 610 + + +Test Vectors +~~~~~~~~~~~~ + +In addition to the simple turbo decoder and turbo encoder tests, bbdev also provides +a range of additional tests under the test_vectors folder, which may be useful. The results +of these tests will depend on the FPGA LTE FEC capabilities: + +* turbo decoder tests: + - ``turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_high_snr.data`` + - ``turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_low_snr.data`` + - ``turbo_dec_c1_k6144_r0_e34560_negllr.data`` + - ``turbo_dec_c1_k6144_r0_e34560_sbd_negllr.data`` + - ``turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data`` + - ``turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data`` + + +* turbo encoder tests: + - ``turbo_enc_c1_k40_r0_e1190_rm.data`` + - ``turbo_enc_c1_k40_r0_e1194_rm.data`` + - ``turbo_enc_c1_k40_r0_e1196_rm.data`` + - ``turbo_enc_c1_k40_r0_e272_rm.data`` + - ``turbo_enc_c1_k6144_r0_e18444.data`` + - ``turbo_enc_c1_k6144_r0_e32256_crc24b_rm.data`` + - ``turbo_enc_c2_k5952_r0_e17868_crc24b.data`` + - ``turbo_enc_c3_k4800_r2_e14412_crc24b.data`` + - ``turbo_enc_c4_k4800_r2_e14412_crc24b.data`` + + diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst index 93276ed..005b95e 100644 --- a/doc/guides/bbdevs/index.rst +++ b/doc/guides/bbdevs/index.rst @@ -10,3 +10,4 @@ Baseband Device Drivers null turbo_sw + fpga_lte_fec diff --git a/drivers/baseband/Makefile b/drivers/baseband/Makefile index 4ec83b0..ceffc7d 100644 --- a/drivers/baseband/Makefile +++ b/drivers/baseband/Makefile @@ -10,5 +10,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_NULL) += null DEPDIRS-null = $(core-libs) DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += turbo_sw DEPDIRS-turbo_sw = $(core-libs) +DIRS-$(CONFIG_RTE_LIBRTE_PMD_FPGA_LTE_FEC) += fpga_lte_fec +DEPDIRS-fpga_lte_fec = $(core-libs) include $(RTE_SDK)/mk/rte.subdir.mk diff --git a/drivers/baseband/fpga_lte_fec/Makefile b/drivers/baseband/fpga_lte_fec/Makefile new file mode 100644 index 0000000..a38a396 --- /dev/null +++ b/drivers/baseband/fpga_lte_fec/Makefile @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2019 Intel Corporation + +include $(RTE_SDK)/mk/rte.vars.mk + +# library name +LIB = librte_pmd_fpga_lte_fec.a + +# build flags +CFLAGS += -DALLOW_EXPERIMENTAL_API +CFLAGS += -O3 +CFLAGS += $(WERROR_FLAGS) +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring +LDLIBS += -lrte_bbdev +LDLIBS += -lrte_pci -lrte_bus_pci + +# versioning export map +EXPORT_MAP := rte_pmd_bbdev_fpga_lte_fec_version.map + +# library version +LIBABIVER := 1 + +# library source files +SRCS-$(CONFIG_RTE_LIBRTE_PMD_FPGA_LTE_FEC) += fpga_lte_fec.c + +# export include files +SYMLINK-$(CONFIG_RTE_LIBRTE_PMD_FPGA_LTE_FEC)-include += fpga_lte_fec.h + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c new file mode 100644 index 0000000..19e7689 --- /dev/null +++ b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c @@ -0,0 +1,2674 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Intel Corporation + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef RTE_BBDEV_OFFLOAD_COST +#include +#endif + +#include +#include + +#include "fpga_lte_fec.h" + +/* Turbo SW PMD logging ID */ +static int fpga_lte_fec_logtype; + +/* Helper macro for logging */ +#define rte_bbdev_log(level, fmt, ...) \ + rte_log(RTE_LOG_ ## level, fpga_lte_fec_logtype, fmt "\n", \ + ##__VA_ARGS__) + +#ifdef RTE_LIBRTE_BBDEV_DEBUG +#define rte_bbdev_log_debug(fmt, ...) \ + rte_bbdev_log(DEBUG, "fpga_lte_fec: " fmt, \ + ##__VA_ARGS__) +#else +#define rte_bbdev_log_debug(fmt, ...) +#endif + +/* FPGA LTE FEC driver names */ +#define FPGA_LTE_FEC_PF_DRIVER_NAME intel_fpga_lte_fec_pf +#define FPGA_LTE_FEC_VF_DRIVER_NAME intel_fpga_lte_fec_vf + +/* FPGA LTE FEC PCI vendor & device IDs */ +#define FPGA_LTE_FEC_VENDOR_ID (0x1172) +#define FPGA_LTE_FEC_PF_DEVICE_ID (0x5052) +#define FPGA_LTE_FEC_VF_DEVICE_ID (0x5050) + +/* Align DMA descriptors to 256 bytes - cache-aligned */ +#define FPGA_RING_DESC_ENTRY_LENGTH (8) +/* Ring size is in 256 bits (32 bytes) units */ +#define FPGA_RING_DESC_LEN_UNIT_BYTES (32) +/* Maximum size of queue */ +#define FPGA_RING_MAX_SIZE (1024) +#define FPGA_FLR_TIMEOUT_UNIT (16.384) + +#define FPGA_NUM_UL_QUEUES (32) +#define FPGA_NUM_DL_QUEUES (32) +#define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES) +#define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET) + +#define FPGA_INVALID_HW_QUEUE_ID (0xFFFFFFFF) + +#define FPGA_QUEUE_FLUSH_TIMEOUT_US (1000) +#define FPGA_TIMEOUT_CHECK_INTERVAL (5) + +/* FPGA LTE FEC Register mapping on BAR0 */ +enum { + FPGA_LTE_FEC_VERSION_ID = 0x00000000, /* len: 4B */ + FPGA_LTE_FEC_CONFIGURATION = 0x00000004, /* len: 2B */ + FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */ + FPGA_LTE_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */ + FPGA_LTE_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */ + FPGA_LTE_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */ + FPGA_LTE_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */ + FPGA_LTE_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */ + FPGA_LTE_FEC_VF0_DEBUG = 0x00000020, /* len: 4B */ + FPGA_LTE_FEC_VF1_DEBUG = 0x00000024, /* len: 4B */ + FPGA_LTE_FEC_VF2_DEBUG = 0x00000028, /* len: 4B */ + FPGA_LTE_FEC_VF3_DEBUG = 0x0000002c, /* len: 4B */ + FPGA_LTE_FEC_VF4_DEBUG = 0x00000030, /* len: 4B */ + FPGA_LTE_FEC_VF5_DEBUG = 0x00000034, /* len: 4B */ + FPGA_LTE_FEC_VF6_DEBUG = 0x00000038, /* len: 4B */ + FPGA_LTE_FEC_VF7_DEBUG = 0x0000003c, /* len: 4B */ + FPGA_LTE_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */ + FPGA_LTE_FEC_RING_CTRL_REGS = 0x00000200 /* len: 2048B */ +}; + +/* FPGA LTE FEC Ring Control Registers */ +enum { + FPGA_LTE_FEC_RING_HEAD_ADDR = 0x00000008, + FPGA_LTE_FEC_RING_SIZE = 0x00000010, + FPGA_LTE_FEC_RING_MISC = 0x00000014, + FPGA_LTE_FEC_RING_ENABLE = 0x00000015, + FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN = 0x00000016, + FPGA_LTE_FEC_RING_SHADOW_TAIL = 0x00000018, + FPGA_LTE_FEC_RING_HEAD_POINT = 0x0000001C +}; + +/* FPGA LTE FEC DESCRIPTOR ERROR */ +enum { + DESC_ERR_NO_ERR = 0x0, + DESC_ERR_K_OUT_OF_RANGE = 0x1, + DESC_ERR_K_NOT_NORMAL = 0x2, + DESC_ERR_KPAI_NOT_NORMAL = 0x3, + DESC_ERR_DESC_OFFSET_ERR = 0x4, + DESC_ERR_DESC_READ_FAIL = 0x8, + DESC_ERR_DESC_READ_TIMEOUT = 0x9, + DESC_ERR_DESC_READ_TLP_POISONED = 0xA, + DESC_ERR_CB_READ_FAIL = 0xC, + DESC_ERR_CB_READ_TIMEOUT = 0xD, + DESC_ERR_CB_READ_TLP_POISONED = 0xE +}; + +/* FPGA LTE FEC DMA Encoding Request Descriptor */ +struct __attribute__((__packed__)) fpga_dma_enc_desc { + uint32_t done:1, + rsrvd0:11, + error:4, + rsrvd1:16; + uint32_t ncb:16, + rsrvd2:14, + rv:2; + uint32_t bypass_rm:1, + irq_en:1, + crc_en:1, + rsrvd3:13, + offset:10, + rsrvd4:6; + uint16_t e; + uint16_t k; + uint32_t out_addr_lw; + uint32_t out_addr_hi; + uint32_t in_addr_lw; + uint32_t in_addr_hi; + + union { + struct { + /* Virtual addresses used to retrieve SW context info */ + void *op_addr; + /* Stores information about total number of Code Blocks + * in currently processed Transport Block + */ + uint64_t cbs_in_op; + }; + + uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES * + (FPGA_RING_DESC_ENTRY_LENGTH - 1)]; + }; +}; + +/* FPGA LTE FEC DMA Decoding Request Descriptor */ +struct __attribute__((__packed__)) fpga_dma_dec_desc { + uint32_t done:1, + iter:5, + rsrvd0:2, + crc_pass:1, + rsrvd1:3, + error:4, + crc_type:1, + rsrvd2:7, + max_iter:5, + rsrvd3:3; + uint32_t rsrvd4; + uint32_t bypass_rm:1, + irq_en:1, + drop_crc:1, + rsrvd5:13, + offset:10, + rsrvd6:6; + uint16_t k; + uint16_t in_len; + uint32_t out_addr_lw; + uint32_t out_addr_hi; + uint32_t in_addr_lw; + uint32_t in_addr_hi; + + union { + struct { + /* Virtual addresses used to retrieve SW context info */ + void *op_addr; + /* Stores information about total number of Code Blocks + * in currently processed Transport Block + */ + uint8_t cbs_in_op; + }; + + uint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)]; + }; +}; + +/* FPGA LTE DMA Descriptor */ +union fpga_dma_desc { + struct fpga_dma_enc_desc enc_req; + struct fpga_dma_dec_desc dec_req; +}; + +/* FPGA LTE FEC Ring Control Register */ +struct __attribute__((__packed__)) fpga_ring_ctrl_reg { + uint64_t ring_base_addr; + uint64_t ring_head_addr; + uint16_t ring_size:11; + uint16_t rsrvd0; + union { /* Miscellaneous register */ + uint8_t misc; + uint8_t max_ul_dec:5, + max_ul_dec_en:1, + rsrvd1:2; + }; + uint8_t enable; + uint8_t flush_queue_en; + uint8_t rsrvd2; + uint16_t shadow_tail; + uint16_t rsrvd3; + uint16_t head_point; + uint16_t rsrvd4; + +}; + +/* Private data structure for each FPGA FEC device */ +struct fpga_lte_fec_device { + /** Base address of MMIO registers (BAR0) */ + void *mmio_base; + /** Base address of memory for sw rings */ + void *sw_rings; + /** Physical address of sw_rings */ + rte_iova_t sw_rings_phys; + /** Number of bytes available for each queue in device. */ + uint32_t sw_ring_size; + /** Max number of entries available for each queue in device */ + uint32_t sw_ring_max_depth; + /** Base address of response tail pointer buffer */ + uint32_t *tail_ptrs; + /** Physical address of tail pointers */ + rte_iova_t tail_ptr_phys; + /** Queues flush completion flag */ + uint64_t *flush_queue_status; + /* Bitmap capturing which Queues are bound to the PF/VF */ + uint64_t q_bound_bit_map; + /* Bitmap capturing which Queues have already been assigned */ + uint64_t q_assigned_bit_map; + /** True if this is a PF FPGA FEC device */ + bool pf_device; +}; + +/* Structure associated with each queue. */ +struct __rte_cache_aligned fpga_queue { + struct fpga_ring_ctrl_reg ring_ctrl_reg; /* Ring Control Register */ + union fpga_dma_desc *ring_addr; /* Virtual address of software ring */ + uint64_t *ring_head_addr; /* Virtual address of completion_head */ + uint64_t shadow_completion_head; /* Shadow completion head value */ + uint16_t head_free_desc; /* Ring head */ + uint16_t tail; /* Ring tail */ + /* Mask used to wrap enqueued descriptors on the sw ring */ + uint32_t sw_ring_wrap_mask; + uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */ + uint8_t q_idx; /* Queue index */ + struct fpga_lte_fec_device *d; + /* MMIO register of shadow_tail used to enqueue descriptors */ + void *shadow_tail_addr; +}; + +/* Write to 16 bit MMIO register address */ +static inline void +mmio_write_16(void *addr, uint16_t value) +{ + *((volatile uint16_t *)(addr)) = rte_cpu_to_le_16(value); +} + +/* Write to 32 bit MMIO register address */ +static inline void +mmio_write_32(void *addr, uint32_t value) +{ + *((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value); +} + +/* Write to 64 bit MMIO register address */ +static inline void +mmio_write_64(void *addr, uint64_t value) +{ + *((volatile uint64_t *)(addr)) = rte_cpu_to_le_64(value); +} + +/* Write a 8 bit register of a FPGA LTE FEC device */ +static inline void +fpga_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload) +{ + void *reg_addr = RTE_PTR_ADD(mmio_base, offset); + *((volatile uint8_t *)(reg_addr)) = payload; +} + +/* Write a 16 bit register of a FPGA LTE FEC device */ +static inline void +fpga_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload) +{ + void *reg_addr = RTE_PTR_ADD(mmio_base, offset); + mmio_write_16(reg_addr, payload); +} + +/* Write a 32 bit register of a FPGA LTE FEC device */ +static inline void +fpga_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload) +{ + void *reg_addr = RTE_PTR_ADD(mmio_base, offset); + mmio_write_32(reg_addr, payload); +} + +/* Write a 64 bit register of a FPGA LTE FEC device */ +static inline void +fpga_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload) +{ + void *reg_addr = RTE_PTR_ADD(mmio_base, offset); + mmio_write_64(reg_addr, payload); +} + +/* Write a ring control register of a FPGA LTE FEC device */ +static inline void +fpga_ring_reg_write(void *mmio_base, uint32_t offset, + struct fpga_ring_ctrl_reg payload) +{ + fpga_reg_write_64(mmio_base, offset, payload.ring_base_addr); + fpga_reg_write_64(mmio_base, offset + FPGA_LTE_FEC_RING_HEAD_ADDR, + payload.ring_head_addr); + fpga_reg_write_16(mmio_base, offset + FPGA_LTE_FEC_RING_SIZE, + payload.ring_size); + fpga_reg_write_16(mmio_base, offset + FPGA_LTE_FEC_RING_HEAD_POINT, + payload.head_point); + fpga_reg_write_8(mmio_base, offset + FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN, + payload.flush_queue_en); + fpga_reg_write_16(mmio_base, offset + FPGA_LTE_FEC_RING_SHADOW_TAIL, + payload.shadow_tail); + fpga_reg_write_8(mmio_base, offset + FPGA_LTE_FEC_RING_MISC, + payload.misc); + fpga_reg_write_8(mmio_base, offset + FPGA_LTE_FEC_RING_ENABLE, + payload.enable); +} + +/* Read a register of FPGA LTE FEC device */ +static uint32_t +fpga_reg_read_32(void *mmio_base, uint32_t offset) +{ + void *reg_addr = RTE_PTR_ADD(mmio_base, offset); + uint32_t ret = *((volatile uint32_t *)(reg_addr)); + return rte_le_to_cpu_32(ret); +} + +#ifdef RTE_LIBRTE_BBDEV_DEBUG +/* Read a register of FPGA LTE FEC device */ +static uint8_t +fpga_reg_read_8(void *mmio_base, uint32_t offset) +{ + void *reg_addr = RTE_PTR_ADD(mmio_base, offset); + return *((volatile uint8_t *)(reg_addr)); +} + +/* Read a register of FPGA LTE FEC device */ +static uint16_t +fpga_reg_read_16(void *mmio_base, uint32_t offset) +{ + void *reg_addr = RTE_PTR_ADD(mmio_base, offset); + uint16_t ret = *((volatile uint16_t *)(reg_addr)); + return rte_le_to_cpu_16(ret); +} + +/* Read a register of FPGA LTE FEC device */ +static uint64_t +fpga_reg_read_64(void *mmio_base, uint32_t offset) +{ + void *reg_addr = RTE_PTR_ADD(mmio_base, offset); + uint64_t ret = *((volatile uint64_t *)(reg_addr)); + return rte_le_to_cpu_64(ret); +} + +/* Read Ring Control Register of FPGA LTE FEC device */ +static inline void +print_ring_reg_debug_info(void *mmio_base, uint32_t offset) +{ + rte_bbdev_log_debug( + "FPGA MMIO base address @ %p | Ring Control Register @ offset = 0x%08" + PRIx32, mmio_base, offset); + rte_bbdev_log_debug( + "RING_BASE_ADDR = 0x%016"PRIx64, + fpga_reg_read_64(mmio_base, offset)); + rte_bbdev_log_debug( + "RING_HEAD_ADDR = 0x%016"PRIx64, + fpga_reg_read_64(mmio_base, offset + + FPGA_LTE_FEC_RING_HEAD_ADDR)); + rte_bbdev_log_debug( + "RING_SIZE = 0x%04"PRIx16, + fpga_reg_read_16(mmio_base, offset + + FPGA_LTE_FEC_RING_SIZE)); + rte_bbdev_log_debug( + "RING_MISC = 0x%02"PRIx8, + fpga_reg_read_8(mmio_base, offset + + FPGA_LTE_FEC_RING_MISC)); + rte_bbdev_log_debug( + "RING_ENABLE = 0x%02"PRIx8, + fpga_reg_read_8(mmio_base, offset + + FPGA_LTE_FEC_RING_ENABLE)); + rte_bbdev_log_debug( + "RING_FLUSH_QUEUE_EN = 0x%02"PRIx8, + fpga_reg_read_8(mmio_base, offset + + FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN)); + rte_bbdev_log_debug( + "RING_SHADOW_TAIL = 0x%04"PRIx16, + fpga_reg_read_16(mmio_base, offset + + FPGA_LTE_FEC_RING_SHADOW_TAIL)); + rte_bbdev_log_debug( + "RING_HEAD_POINT = 0x%04"PRIx16, + fpga_reg_read_16(mmio_base, offset + + FPGA_LTE_FEC_RING_HEAD_POINT)); +} + +/* Read Static Register of FPGA LTE FEC device */ +static inline void +print_static_reg_debug_info(void *mmio_base) +{ + uint16_t config = fpga_reg_read_16(mmio_base, + FPGA_LTE_FEC_CONFIGURATION); + uint8_t qmap_done = fpga_reg_read_8(mmio_base, + FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE); + uint16_t lb_factor = fpga_reg_read_16(mmio_base, + FPGA_LTE_FEC_LOAD_BALANCE_FACTOR); + uint16_t ring_desc_len = fpga_reg_read_16(mmio_base, + FPGA_LTE_FEC_RING_DESC_LEN); + uint16_t flr_time_out = fpga_reg_read_16(mmio_base, + FPGA_LTE_FEC_FLR_TIME_OUT); + + rte_bbdev_log_debug("UL.DL Weights = %u.%u", + ((uint8_t)config), ((uint8_t)(config >> 8))); + rte_bbdev_log_debug("UL.DL Load Balance = %u.%u", + ((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8))); + rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s", + (qmap_done > 0) ? "READY" : "NOT-READY"); + rte_bbdev_log_debug("Ring Descriptor Size = %u bytes", + ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES); + rte_bbdev_log_debug("FLR Timeout = %f usec", + (float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT); +} + +/* Print decode DMA Descriptor of FPGA LTE FEC device */ +static void +print_dma_dec_desc_debug_info(union fpga_dma_desc *desc) +{ + rte_bbdev_log_debug("DMA response desc %p\n" + "\t-- done(%"PRIu32") | iter(%"PRIu32") | crc_pass(%"PRIu32")" + " | error (%"PRIu32") | crc_type(%"PRIu32")\n" + "\t-- max_iter(%"PRIu32") | bypass_rm(%"PRIu32") | " + "irq_en (%"PRIu32") | drop_crc(%"PRIu32") | offset(%"PRIu32")\n" + "\t-- k(%"PRIu32") | in_len (%"PRIu16") | op_add(%p)\n" + "\t-- cbs_in_op(%"PRIu32") | in_add (0x%08"PRIx32"%08"PRIx32") | " + "out_add (0x%08"PRIx32"%08"PRIx32")", + desc, + (uint32_t)desc->dec_req.done, + (uint32_t)desc->dec_req.iter, + (uint32_t)desc->dec_req.crc_pass, + (uint32_t)desc->dec_req.error, + (uint32_t)desc->dec_req.crc_type, + (uint32_t)desc->dec_req.max_iter, + (uint32_t)desc->dec_req.bypass_rm, + (uint32_t)desc->dec_req.irq_en, + (uint32_t)desc->dec_req.drop_crc, + (uint32_t)desc->dec_req.offset, + (uint32_t)desc->dec_req.k, + (uint16_t)desc->dec_req.in_len, + desc->dec_req.op_addr, + (uint32_t)desc->dec_req.cbs_in_op, + (uint32_t)desc->dec_req.in_addr_hi, + (uint32_t)desc->dec_req.in_addr_lw, + (uint32_t)desc->dec_req.out_addr_hi, + (uint32_t)desc->dec_req.out_addr_lw); +} +#endif + +static int +fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) +{ + /* Number of queues bound to a PF/VF */ + uint32_t hw_q_num = 0; + uint32_t ring_size, payload, address, q_id, offset; + rte_iova_t phys_addr; + struct fpga_ring_ctrl_reg ring_reg; + struct fpga_lte_fec_device *fpga_dev = dev->data->dev_private; + + address = FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE; + if (!(fpga_reg_read_32(fpga_dev->mmio_base, address) & 0x1)) { + rte_bbdev_log(ERR, + "Queue-PF/VF mapping is not set! Was PF configured for device (%s) ?", + dev->data->name); + return -EPERM; + } + + /* Clear queue registers structure */ + memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg)); + + /* Scan queue map. + * If a queue is valid and mapped to a calling PF/VF the read value is + * replaced with a queue ID and if it's not then + * FPGA_INVALID_HW_QUEUE_ID is returned. + */ + for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { + uint32_t hw_q_id = fpga_reg_read_32(fpga_dev->mmio_base, + FPGA_LTE_FEC_QUEUE_MAP + (q_id << 2)); + + rte_bbdev_log_debug("%s: queue ID: %u, registry queue ID: %u", + dev->device->name, q_id, hw_q_id); + + if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) { + fpga_dev->q_bound_bit_map |= (1ULL << q_id); + /* Clear queue register of found queue */ + offset = FPGA_LTE_FEC_RING_CTRL_REGS + + (sizeof(struct fpga_ring_ctrl_reg) * q_id); + fpga_ring_reg_write(fpga_dev->mmio_base, + offset, ring_reg); + ++hw_q_num; + } + } + if (hw_q_num == 0) { + rte_bbdev_log(ERR, + "No HW queues assigned to this device. Probably this is a VF configured for PF mode. Check device configuration!"); + return -ENODEV; + } + + if (num_queues > hw_q_num) { + rte_bbdev_log(ERR, + "Not enough queues for device %s! Requested: %u, available: %u", + dev->device->name, num_queues, hw_q_num); + return -EINVAL; + } + + ring_size = FPGA_RING_MAX_SIZE * sizeof(struct fpga_dma_dec_desc); + + /* Enforce 32 byte alignment */ + RTE_BUILD_BUG_ON((RTE_CACHE_LINE_SIZE % 32) != 0); + + /* Allocate memory for SW descriptor rings */ + fpga_dev->sw_rings = rte_zmalloc_socket(dev->device->driver->name, + num_queues * ring_size, RTE_CACHE_LINE_SIZE, + socket_id); + if (fpga_dev->sw_rings == NULL) { + rte_bbdev_log(ERR, + "Failed to allocate memory for %s:%u sw_rings", + dev->device->driver->name, dev->data->dev_id); + return -ENOMEM; + } + + fpga_dev->sw_rings_phys = rte_malloc_virt2iova(fpga_dev->sw_rings); + fpga_dev->sw_ring_size = ring_size; + fpga_dev->sw_ring_max_depth = FPGA_RING_MAX_SIZE; + + /* Allocate memory for ring flush status */ + fpga_dev->flush_queue_status = rte_zmalloc_socket(NULL, + sizeof(uint64_t), RTE_CACHE_LINE_SIZE, socket_id); + if (fpga_dev->flush_queue_status == NULL) { + rte_bbdev_log(ERR, + "Failed to allocate memory for %s:%u flush_queue_status", + dev->device->driver->name, dev->data->dev_id); + return -ENOMEM; + } + + /* Set the flush status address registers */ + phys_addr = rte_malloc_virt2iova(fpga_dev->flush_queue_status); + + address = FPGA_LTE_FEC_VFQ_FLUSH_STATUS_LW; + payload = (uint32_t)(phys_addr); + fpga_reg_write_32(fpga_dev->mmio_base, address, payload); + + address = FPGA_LTE_FEC_VFQ_FLUSH_STATUS_HI; + payload = (uint32_t)(phys_addr >> 32); + fpga_reg_write_32(fpga_dev->mmio_base, address, payload); + + return 0; +} + +static int +fpga_dev_close(struct rte_bbdev *dev) +{ + struct fpga_lte_fec_device *fpga_dev = dev->data->dev_private; + + rte_free(fpga_dev->sw_rings); + rte_free(fpga_dev->flush_queue_status); + + return 0; +} + +static void +fpga_dev_info_get(struct rte_bbdev *dev, + struct rte_bbdev_driver_info *dev_info) +{ + struct fpga_lte_fec_device *d = dev->data->dev_private; + uint32_t q_id = 0; + + /* TODO RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN and numbers of buffers are set + * to temporary values as they are required by test application while + * validation phase. + */ + static const struct rte_bbdev_op_cap bbdev_capabilities[] = { + { + .type = RTE_BBDEV_OP_TURBO_DEC, + .cap.turbo_dec = { + .capability_flags = + RTE_BBDEV_TURBO_CRC_TYPE_24B | + RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE | + RTE_BBDEV_TURBO_DEC_INTERRUPTS | + RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN | + RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP, + .max_llr_modulus = INT8_MAX, + .num_buffers_src = + RTE_BBDEV_MAX_CODE_BLOCKS, + .num_buffers_hard_out = + RTE_BBDEV_MAX_CODE_BLOCKS, + .num_buffers_soft_out = 0 + } + }, + { + .type = RTE_BBDEV_OP_TURBO_ENC, + .cap.turbo_enc = { + .capability_flags = + RTE_BBDEV_TURBO_CRC_24B_ATTACH | + RTE_BBDEV_TURBO_RATE_MATCH | + RTE_BBDEV_TURBO_ENC_INTERRUPTS, + .num_buffers_src = + RTE_BBDEV_MAX_CODE_BLOCKS, + .num_buffers_dst = + RTE_BBDEV_MAX_CODE_BLOCKS + } + }, + RTE_BBDEV_END_OF_CAPABILITIES_LIST() + }; + + static struct rte_bbdev_queue_conf default_queue_conf; + default_queue_conf.socket = dev->data->socket_id; + default_queue_conf.queue_size = FPGA_RING_MAX_SIZE; + + + dev_info->driver_name = dev->device->driver->name; + dev_info->queue_size_lim = FPGA_RING_MAX_SIZE; + dev_info->hardware_accelerated = true; + dev_info->min_alignment = 64; + dev_info->default_queue_conf = default_queue_conf; + dev_info->capabilities = bbdev_capabilities; + dev_info->cpu_flag_reqs = NULL; + + /* Calculates number of queues assigned to device */ + dev_info->max_num_queues = 0; + for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { + uint32_t hw_q_id = fpga_reg_read_32(d->mmio_base, + FPGA_LTE_FEC_QUEUE_MAP + (q_id << 2)); + if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) + dev_info->max_num_queues++; + } +} + +/** + * Find index of queue bound to current PF/VF which is unassigned. Return -1 + * when there is no available queue + */ +static int +fpga_find_free_queue_idx(struct rte_bbdev *dev, + const struct rte_bbdev_queue_conf *conf) +{ + struct fpga_lte_fec_device *d = dev->data->dev_private; + uint64_t q_idx; + uint8_t i = 0; + uint8_t range = FPGA_TOTAL_NUM_QUEUES >> 1; + + if (conf->op_type == RTE_BBDEV_OP_TURBO_ENC) { + i = FPGA_NUM_DL_QUEUES; + range = FPGA_TOTAL_NUM_QUEUES; + } + + for (; i < range; ++i) { + q_idx = 1ULL << i; + /* Check if index of queue is bound to current PF/VF */ + if (d->q_bound_bit_map & q_idx) + /* Check if found queue was not already assigned */ + if (!(d->q_assigned_bit_map & q_idx)) { + d->q_assigned_bit_map |= q_idx; + return i; + } + } + + rte_bbdev_log(INFO, "Failed to find free queue on %s", dev->data->name); + + return -1; +} + +static int +fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, + const struct rte_bbdev_queue_conf *conf) +{ + uint32_t address, ring_offset; + struct fpga_lte_fec_device *d = dev->data->dev_private; + struct fpga_queue *q; + int8_t q_idx; + + /* Check if there is a free queue to assign */ + q_idx = fpga_find_free_queue_idx(dev, conf); + if (q_idx == -1) + return -1; + + /* Allocate the queue data structure. */ + q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q), + RTE_CACHE_LINE_SIZE, conf->socket); + if (q == NULL) { + /* Mark queue as un-assigned */ + d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx)); + rte_bbdev_log(ERR, "Failed to allocate queue memory"); + return -ENOMEM; + } + + q->d = d; + q->q_idx = q_idx; + + /* Set ring_base_addr */ + q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id)); + q->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys + + (d->sw_ring_size * queue_id); + + /* Allocate memory for Completion Head variable*/ + q->ring_head_addr = rte_zmalloc_socket(dev->device->driver->name, + sizeof(uint64_t), RTE_CACHE_LINE_SIZE, conf->socket); + if (q->ring_head_addr == NULL) { + /* Mark queue as un-assigned */ + d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx)); + rte_free(q); + rte_bbdev_log(ERR, + "Failed to allocate memory for %s:%u completion_head", + dev->device->driver->name, dev->data->dev_id); + return -ENOMEM; + } + /* Set ring_head_addr */ + q->ring_ctrl_reg.ring_head_addr = + rte_malloc_virt2iova(q->ring_head_addr); + + /* Clear shadow_completion_head */ + q->shadow_completion_head = 0; + + /* Set ring_size */ + if (conf->queue_size > FPGA_RING_MAX_SIZE) { + /* Mark queue as un-assigned */ + d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx)); + rte_free(q->ring_head_addr); + rte_free(q); + rte_bbdev_log(ERR, + "Size of queue is too big %d (MAX: %d ) for %s:%u", + conf->queue_size, FPGA_RING_MAX_SIZE, + dev->device->driver->name, dev->data->dev_id); + return -EINVAL; + } + q->ring_ctrl_reg.ring_size = conf->queue_size; + + /* Set Miscellaneous FPGA register*/ + /* Max iteration number for TTI mitigation - todo */ + q->ring_ctrl_reg.max_ul_dec = 0; + /* Enable max iteration number for TTI - todo */ + q->ring_ctrl_reg.max_ul_dec_en = 0; + + /* Enable the ring */ + q->ring_ctrl_reg.enable = 1; + + /* Set FPGA head_point and tail registers */ + q->ring_ctrl_reg.head_point = q->tail = 0; + + /* Set FPGA shadow_tail register */ + q->ring_ctrl_reg.shadow_tail = q->tail; + + /* Calculates the ring offset for found queue */ + ring_offset = FPGA_LTE_FEC_RING_CTRL_REGS + + (sizeof(struct fpga_ring_ctrl_reg) * q_idx); + + /* Set FPGA Ring Control Registers */ + fpga_ring_reg_write(d->mmio_base, ring_offset, q->ring_ctrl_reg); + + /* Store MMIO register of shadow_tail */ + address = ring_offset + FPGA_LTE_FEC_RING_SHADOW_TAIL; + q->shadow_tail_addr = RTE_PTR_ADD(d->mmio_base, address); + + q->head_free_desc = q->tail; + + /* Set wrap mask */ + q->sw_ring_wrap_mask = conf->queue_size - 1; + + rte_bbdev_log_debug("Setup dev%u q%u: queue_idx=%u", + dev->data->dev_id, queue_id, q->q_idx); + + dev->data->queues[queue_id].queue_private = q; + + rte_bbdev_log_debug("BBDEV queue[%d] set up for FPGA queue[%d]", + queue_id, q_idx); + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + /* Read FPGA Ring Control Registers after configuration*/ + print_ring_reg_debug_info(d->mmio_base, ring_offset); +#endif + return 0; +} + +static int +fpga_queue_release(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct fpga_lte_fec_device *d = dev->data->dev_private; + struct fpga_queue *q = dev->data->queues[queue_id].queue_private; + struct fpga_ring_ctrl_reg ring_reg; + uint32_t offset; + + rte_bbdev_log_debug("FPGA Queue[%d] released", queue_id); + + if (q != NULL) { + memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg)); + offset = FPGA_LTE_FEC_RING_CTRL_REGS + + (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx); + /* Disable queue */ + fpga_reg_write_8(d->mmio_base, + offset + FPGA_LTE_FEC_RING_ENABLE, 0x00); + /* Clear queue registers */ + fpga_ring_reg_write(d->mmio_base, offset, ring_reg); + + /* Mark the Queue as un-assigned */ + d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q->q_idx)); + rte_free(q->ring_head_addr); + rte_free(q); + dev->data->queues[queue_id].queue_private = NULL; + } + + return 0; +} + +/* Function starts a device queue. */ +static int +fpga_queue_start(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct fpga_lte_fec_device *d = dev->data->dev_private; +#ifdef RTE_LIBRTE_BBDEV_DEBUG + if (d == NULL) { + rte_bbdev_log(ERR, "Invalid device pointer"); + return -1; + } +#endif + struct fpga_queue *q = dev->data->queues[queue_id].queue_private; + uint32_t offset = FPGA_LTE_FEC_RING_CTRL_REGS + + (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx); + uint8_t enable = 0x01; + uint16_t zero = 0x0000; + + /* Clear queue head and tail variables */ + q->tail = q->head_free_desc = 0; + + /* Clear FPGA head_point and tail registers */ + fpga_reg_write_16(d->mmio_base, offset + FPGA_LTE_FEC_RING_HEAD_POINT, + zero); + fpga_reg_write_16(d->mmio_base, offset + FPGA_LTE_FEC_RING_SHADOW_TAIL, + zero); + + /* Enable queue */ + fpga_reg_write_8(d->mmio_base, offset + FPGA_LTE_FEC_RING_ENABLE, + enable); + + rte_bbdev_log_debug("FPGA Queue[%d] started", queue_id); + return 0; +} + +/* Function stops a device queue. */ +static int +fpga_queue_stop(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct fpga_lte_fec_device *d = dev->data->dev_private; +#ifdef RTE_LIBRTE_BBDEV_DEBUG + if (d == NULL) { + rte_bbdev_log(ERR, "Invalid device pointer"); + return -1; + } +#endif + struct fpga_queue *q = dev->data->queues[queue_id].queue_private; + uint32_t offset = FPGA_LTE_FEC_RING_CTRL_REGS + + (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx); + uint8_t payload = 0x01; + uint8_t counter = 0; + uint8_t timeout = FPGA_QUEUE_FLUSH_TIMEOUT_US / + FPGA_TIMEOUT_CHECK_INTERVAL; + + /* Set flush_queue_en bit to trigger queue flushing */ + fpga_reg_write_8(d->mmio_base, + offset + FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN, payload); + + /** Check if queue flush is completed. + * FPGA will update the completion flag after queue flushing is + * completed. If completion flag is not updated within 1ms it is + * considered as a failure. + */ + while (!(*((uint8_t *)d->flush_queue_status + q->q_idx) & payload)) { + if (counter > timeout) { + rte_bbdev_log(ERR, "FPGA Queue Flush failed for queue %d", + queue_id); + return -1; + } + usleep(FPGA_TIMEOUT_CHECK_INTERVAL); + counter++; + } + + /* Disable queue */ + payload = 0x00; + fpga_reg_write_8(d->mmio_base, offset + FPGA_LTE_FEC_RING_ENABLE, + payload); + + rte_bbdev_log_debug("FPGA Queue[%d] stopped", queue_id); + return 0; +} + +static inline uint16_t +get_queue_id(struct rte_bbdev_data *data, uint8_t q_idx) +{ + uint16_t queue_id; + + for (queue_id = 0; queue_id < data->num_queues; ++queue_id) { + struct fpga_queue *q = data->queues[queue_id].queue_private; + if (q != NULL && q->q_idx == q_idx) + return queue_id; + } + + return -1; +} + +/* Interrupt handler triggered by FPGA dev for handling specific interrupt */ +static void +fpga_dev_interrupt_handler(void *cb_arg) +{ + struct rte_bbdev *dev = cb_arg; + struct fpga_lte_fec_device *fpga_dev = dev->data->dev_private; + struct fpga_queue *q; + uint64_t ring_head; + uint64_t q_idx; + uint16_t queue_id; + uint8_t i; + + /* Scan queue assigned to this device */ + for (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) { + q_idx = 1ULL << i; + if (fpga_dev->q_bound_bit_map & q_idx) { + queue_id = get_queue_id(dev->data, i); + if (queue_id == (uint16_t) -1) + continue; + + /* Check if completion head was changed */ + q = dev->data->queues[queue_id].queue_private; + ring_head = *q->ring_head_addr; + if (q->shadow_completion_head != ring_head && + q->irq_enable == 1) { + q->shadow_completion_head = ring_head; + rte_bbdev_pmd_callback_process( + dev, + RTE_BBDEV_EVENT_DEQUEUE, + &queue_id); + } + } + } +} + +static int +fpga_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct fpga_queue *q = dev->data->queues[queue_id].queue_private; + + if (!rte_intr_cap_multiple(dev->intr_handle)) + return -ENOTSUP; + + q->irq_enable = 1; + + return 0; +} + +static int +fpga_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct fpga_queue *q = dev->data->queues[queue_id].queue_private; + q->irq_enable = 0; + + return 0; +} + +static int +fpga_intr_enable(struct rte_bbdev *dev) +{ + int ret; + uint8_t i; + + if (!rte_intr_cap_multiple(dev->intr_handle)) { + rte_bbdev_log(ERR, "Multiple intr vector is not supported by FPGA (%s)", + dev->data->name); + return -ENOTSUP; + } + + /* Create event file descriptors for each of 64 queue. Event fds will be + * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where + * the IRQ number is a direct translation to the queue number. + * + * 63 (FPGA_NUM_INTR_VEC) event fds are created as rte_intr_enable() + * mapped the first IRQ to already created interrupt event file + * descriptor (intr_handle->fd). + */ + if (rte_intr_efd_enable(dev->intr_handle, FPGA_NUM_INTR_VEC)) { + rte_bbdev_log(ERR, "Failed to create fds for %u queues", + dev->data->num_queues); + return -1; + } + + /* TODO Each event file descriptor is overwritten by interrupt event + * file descriptor. That descriptor is added to epoll observed list. + * It ensures that callback function assigned to that descriptor will + * invoked when any FPGA queue issues interrupt. + */ + for (i = 0; i < FPGA_NUM_INTR_VEC; ++i) + dev->intr_handle->efds[i] = dev->intr_handle->fd; + + if (!dev->intr_handle->intr_vec) { + dev->intr_handle->intr_vec = rte_zmalloc("intr_vec", + dev->data->num_queues * sizeof(int), 0); + if (!dev->intr_handle->intr_vec) { + rte_bbdev_log(ERR, "Failed to allocate %u vectors", + dev->data->num_queues); + return -ENOMEM; + } + } + + ret = rte_intr_enable(dev->intr_handle); + if (ret < 0) { + rte_bbdev_log(ERR, + "Couldn't enable interrupts for device: %s", + dev->data->name); + return ret; + } + + ret = rte_intr_callback_register(dev->intr_handle, + fpga_dev_interrupt_handler, dev); + if (ret < 0) { + rte_bbdev_log(ERR, + "Couldn't register interrupt callback for device: %s", + dev->data->name); + return ret; + } + + return 0; +} + +static const struct rte_bbdev_ops fpga_ops = { + .setup_queues = fpga_setup_queues, + .intr_enable = fpga_intr_enable, + .close = fpga_dev_close, + .info_get = fpga_dev_info_get, + .queue_setup = fpga_queue_setup, + .queue_stop = fpga_queue_stop, + .queue_start = fpga_queue_start, + .queue_release = fpga_queue_release, + .queue_intr_enable = fpga_queue_intr_enable, + .queue_intr_disable = fpga_queue_intr_disable +}; + +static inline void +fpga_dma_enqueue(struct fpga_queue *q, uint16_t num_desc, + struct rte_bbdev_stats *queue_stats) +{ +#ifdef RTE_BBDEV_OFFLOAD_COST + uint64_t start_time = 0; + queue_stats->acc_offload_cycles = 0; +#else + RTE_SET_USED(queue_stats); +#endif + + /* Update tail and shadow_tail register */ + q->tail = (q->tail + num_desc) & q->sw_ring_wrap_mask; + + rte_wmb(); + +#ifdef RTE_BBDEV_OFFLOAD_COST + /* Start time measurement for enqueue function offload. */ + start_time = rte_rdtsc_precise(); +#endif + mmio_write_16(q->shadow_tail_addr, q->tail); + +#ifdef RTE_BBDEV_OFFLOAD_COST + rte_wmb(); + queue_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time; +#endif +} + +/* Calculates number of CBs in processed encoder TB based on 'r' and input + * length. + */ +static inline uint8_t +get_num_cbs_in_op_enc(struct rte_bbdev_op_turbo_enc *turbo_enc) +{ + uint8_t c, c_neg, r, crc24_bits = 0; + uint16_t k, k_neg, k_pos; + uint8_t cbs_in_op = 0; + int32_t length; + + length = turbo_enc->input.length; + r = turbo_enc->tb_params.r; + c = turbo_enc->tb_params.c; + c_neg = turbo_enc->tb_params.c_neg; + k_neg = turbo_enc->tb_params.k_neg; + k_pos = turbo_enc->tb_params.k_pos; + crc24_bits = 24; + while (length > 0 && r < c) { + k = (r < c_neg) ? k_neg : k_pos; + length -= (k - crc24_bits) >> 3; + r++; + cbs_in_op++; + } + + return cbs_in_op; +} + +/* Calculates number of CBs in processed decoder TB based on 'r' and input + * length. + */ +static inline uint16_t +get_num_cbs_in_op_dec(struct rte_bbdev_op_turbo_dec *turbo_dec) +{ + uint8_t c, c_neg, r = 0; + uint16_t kw, k, k_neg, k_pos, cbs_in_op = 0; + int32_t length; + + length = turbo_dec->input.length; + r = turbo_dec->tb_params.r; + c = turbo_dec->tb_params.c; + c_neg = turbo_dec->tb_params.c_neg; + k_neg = turbo_dec->tb_params.k_neg; + k_pos = turbo_dec->tb_params.k_pos; + while (length > 0 && r < c) { + k = (r < c_neg) ? k_neg : k_pos; + kw = RTE_ALIGN_CEIL(k + 4, 32) * 3; + length -= kw; + r++; + cbs_in_op++; + } + + return cbs_in_op; +} + +/* Read flag value 0/1/ from bitmap */ +static inline bool +check_bit(uint32_t bitmap, uint32_t bitmask) +{ + return bitmap & bitmask; +} + +/* Print an error if a descriptor error has occurred. + * Return 0 on success, 1 on failure + */ +static inline int +check_desc_error(uint32_t error_code) { + switch (error_code) { + case DESC_ERR_NO_ERR: + return 0; + case DESC_ERR_K_OUT_OF_RANGE: + rte_bbdev_log(ERR, "Block_size_k is out of range (k<40 or k>6144)"); + break; + case DESC_ERR_K_NOT_NORMAL: + rte_bbdev_log(ERR, "Block_size_k is not a normal value within normal range"); + break; + case DESC_ERR_KPAI_NOT_NORMAL: + rte_bbdev_log(ERR, "Three_kpai is not a normal value for UL only"); + break; + case DESC_ERR_DESC_OFFSET_ERR: + rte_bbdev_log(ERR, "Queue offset does not meet the expectation in the FPGA"); + break; + case (DESC_ERR_K_OUT_OF_RANGE | DESC_ERR_DESC_OFFSET_ERR): + rte_bbdev_log(ERR, "Block_size_k is out of range (k<40 or k>6144) and queue offset error"); + break; + case (DESC_ERR_K_NOT_NORMAL | DESC_ERR_DESC_OFFSET_ERR): + rte_bbdev_log(ERR, "Block_size_k is not a normal value within normal range and queue offset error"); + break; + case (DESC_ERR_KPAI_NOT_NORMAL | DESC_ERR_DESC_OFFSET_ERR): + rte_bbdev_log(ERR, "Three_kpai is not a normal value for UL only and queue offset error"); + break; + case DESC_ERR_DESC_READ_FAIL: + rte_bbdev_log(ERR, "Unsuccessful completion for descriptor read"); + break; + case DESC_ERR_DESC_READ_TIMEOUT: + rte_bbdev_log(ERR, "Descriptor read time-out"); + break; + case DESC_ERR_DESC_READ_TLP_POISONED: + rte_bbdev_log(ERR, "Descriptor read TLP poisoned"); + break; + case DESC_ERR_CB_READ_FAIL: + rte_bbdev_log(ERR, "Unsuccessful completion for code block"); + break; + case DESC_ERR_CB_READ_TIMEOUT: + rte_bbdev_log(ERR, "Code block read time-out"); + break; + case DESC_ERR_CB_READ_TLP_POISONED: + rte_bbdev_log(ERR, "Code block read TLP poisoned"); + break; + default: + rte_bbdev_log(ERR, "Descriptor error unknown error code %u", + error_code); + break; + } + return 1; +} + +/** + * Set DMA descriptor for encode operation (1 Code Block) + * + * @param op + * Pointer to a single encode operation. + * @param desc + * Pointer to DMA descriptor. + * @param input + * Pointer to pointer to input data which will be decoded. + * @param k + * K value (length of input in bits). + * @param e + * E value (length of output in bits). + * @param ncb + * Ncb value (size of the soft buffer). + * @param out_length + * Length of output buffer + * @param in_offset + * Input offset in rte_mbuf structure. It is used for calculating the point + * where data is starting. + * @param out_offset + * Output offset in rte_mbuf structure. It is used for calculating the point + * where hard output data will be stored. + * @param cbs_in_op + * Number of CBs contained in one operation. + */ +static inline int +fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op, + struct fpga_dma_enc_desc *desc, struct rte_mbuf *input, + struct rte_mbuf *output, uint16_t k, uint16_t e, uint16_t ncb, + uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset, + uint8_t cbs_in_op) + +{ + /* reset */ + desc->done = 0; + desc->crc_en = check_bit(op->turbo_enc.op_flags, + RTE_BBDEV_TURBO_CRC_24B_ATTACH); + desc->bypass_rm = !check_bit(op->turbo_enc.op_flags, + RTE_BBDEV_TURBO_RATE_MATCH); + desc->k = k; + desc->e = e; + desc->ncb = ncb; + desc->rv = op->turbo_enc.rv_index; + desc->offset = desc_offset; + /* Set inbound data buffer address */ + desc->in_addr_hi = (uint32_t)( + rte_pktmbuf_mtophys_offset(input, in_offset) >> 32); + desc->in_addr_lw = (uint32_t)( + rte_pktmbuf_mtophys_offset(input, in_offset)); + + desc->out_addr_hi = (uint32_t)( + rte_pktmbuf_mtophys_offset(output, out_offset) >> 32); + desc->out_addr_lw = (uint32_t)( + rte_pktmbuf_mtophys_offset(output, out_offset)); + + /* Save software context needed for dequeue */ + desc->op_addr = op; + + /* Set total number of CBs in an op */ + desc->cbs_in_op = cbs_in_op; + + return 0; +} + +/** + * Set DMA descriptor for encode operation (1 Code Block) + * + * @param op + * Pointer to a single encode operation. + * @param desc + * Pointer to DMA descriptor. + * @param input + * Pointer to pointer to input data which will be decoded. + * @param in_length + * Length of an input. + * @param k + * K value (length of an output in bits). + * @param in_offset + * Input offset in rte_mbuf structure. It is used for calculating the point + * where data is starting. + * @param out_offset + * Output offset in rte_mbuf structure. It is used for calculating the point + * where hard output data will be stored. + * @param cbs_in_op + * Number of CBs contained in one operation. + */ +static inline int +fpga_dma_desc_td_fill(struct rte_bbdev_dec_op *op, + struct fpga_dma_dec_desc *desc, struct rte_mbuf *input, + struct rte_mbuf *output, uint16_t in_length, uint16_t k, + uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset, + uint8_t cbs_in_op) +{ + /* reset */ + desc->done = 0; + /* Set inbound data buffer address */ + desc->in_addr_hi = (uint32_t)( + rte_pktmbuf_mtophys_offset(input, in_offset) >> 32); + desc->in_addr_lw = (uint32_t)( + rte_pktmbuf_mtophys_offset(input, in_offset)); + desc->in_len = in_length; + desc->k = k; + desc->crc_type = !check_bit(op->turbo_dec.op_flags, + RTE_BBDEV_TURBO_CRC_TYPE_24B); + if ((op->turbo_dec.code_block_mode == 0) + && !check_bit(op->turbo_dec.op_flags, + RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP)) + desc->drop_crc = 1; + desc->max_iter = op->turbo_dec.iter_max * 2; + desc->offset = desc_offset; + desc->out_addr_hi = (uint32_t)( + rte_pktmbuf_mtophys_offset(output, out_offset) >> 32); + desc->out_addr_lw = (uint32_t)( + rte_pktmbuf_mtophys_offset(output, out_offset)); + + /* Save software context needed for dequeue */ + desc->op_addr = op; + + /* Set total number of CBs in an op */ + desc->cbs_in_op = cbs_in_op; + + return 0; +} + +#ifdef RTE_LIBRTE_BBDEV_DEBUG +/* Validates turbo encoder parameters */ +static int +validate_enc_op(struct rte_bbdev_enc_op *op) +{ + struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc; + struct rte_bbdev_op_enc_cb_params *cb = NULL; + struct rte_bbdev_op_enc_tb_params *tb = NULL; + uint16_t kw, kw_neg, kw_pos; + + if (turbo_enc->input.length > + RTE_BBDEV_MAX_TB_SIZE >> 3) { + rte_bbdev_log(ERR, "TB size (%u) is too big, max: %d", + turbo_enc->input.length, RTE_BBDEV_MAX_TB_SIZE); + op->status = 1 << RTE_BBDEV_DATA_ERROR; + return -1; + } + + if (op->mempool == NULL) { + rte_bbdev_log(ERR, "Invalid mempool pointer"); + return -1; + } + if (turbo_enc->input.data == NULL) { + rte_bbdev_log(ERR, "Invalid input pointer"); + return -1; + } + if (turbo_enc->output.data == NULL) { + rte_bbdev_log(ERR, "Invalid output pointer"); + return -1; + } + if (turbo_enc->rv_index > 3) { + rte_bbdev_log(ERR, + "rv_index (%u) is out of range 0 <= value <= 3", + turbo_enc->rv_index); + return -1; + } + if (turbo_enc->code_block_mode != 0 && + turbo_enc->code_block_mode != 1) { + rte_bbdev_log(ERR, + "code_block_mode (%u) is out of range 0 <= value <= 1", + turbo_enc->code_block_mode); + return -1; + } + + if (turbo_enc->code_block_mode == 0) { + tb = &turbo_enc->tb_params; + if ((tb->k_neg < RTE_BBDEV_MIN_CB_SIZE + || tb->k_neg > RTE_BBDEV_MAX_CB_SIZE) + && tb->c_neg > 0) { + rte_bbdev_log(ERR, + "k_neg (%u) is out of range %u <= value <= %u", + tb->k_neg, RTE_BBDEV_MIN_CB_SIZE, + RTE_BBDEV_MAX_CB_SIZE); + return -1; + } + if (tb->k_pos < RTE_BBDEV_MIN_CB_SIZE + || tb->k_pos > RTE_BBDEV_MAX_CB_SIZE) { + rte_bbdev_log(ERR, + "k_pos (%u) is out of range %u <= value <= %u", + tb->k_pos, RTE_BBDEV_MIN_CB_SIZE, + RTE_BBDEV_MAX_CB_SIZE); + return -1; + } + if (tb->c_neg > (RTE_BBDEV_MAX_CODE_BLOCKS - 1)) + rte_bbdev_log(ERR, + "c_neg (%u) is out of range 0 <= value <= %u", + tb->c_neg, + RTE_BBDEV_MAX_CODE_BLOCKS - 1); + if (tb->c < 1 || tb->c > RTE_BBDEV_MAX_CODE_BLOCKS) { + rte_bbdev_log(ERR, + "c (%u) is out of range 1 <= value <= %u", + tb->c, RTE_BBDEV_MAX_CODE_BLOCKS); + return -1; + } + if (tb->cab > tb->c) { + rte_bbdev_log(ERR, + "cab (%u) is greater than c (%u)", + tb->cab, tb->c); + return -1; + } + if ((tb->ea < RTE_BBDEV_MIN_CB_SIZE || (tb->ea % 2)) + && tb->r < tb->cab) { + rte_bbdev_log(ERR, + "ea (%u) is less than %u or it is not even", + tb->ea, RTE_BBDEV_MIN_CB_SIZE); + return -1; + } + if ((tb->eb < RTE_BBDEV_MIN_CB_SIZE || (tb->eb % 2)) + && tb->c > tb->cab) { + rte_bbdev_log(ERR, + "eb (%u) is less than %u or it is not even", + tb->eb, RTE_BBDEV_MIN_CB_SIZE); + return -1; + } + + kw_neg = 3 * RTE_ALIGN_CEIL(tb->k_neg + 4, + RTE_BBDEV_C_SUBBLOCK); + if (tb->ncb_neg < tb->k_neg || tb->ncb_neg > kw_neg) { + rte_bbdev_log(ERR, + "ncb_neg (%u) is out of range (%u) k_neg <= value <= (%u) kw_neg", + tb->ncb_neg, tb->k_neg, kw_neg); + return -1; + } + + kw_pos = 3 * RTE_ALIGN_CEIL(tb->k_pos + 4, + RTE_BBDEV_C_SUBBLOCK); + if (tb->ncb_pos < tb->k_pos || tb->ncb_pos > kw_pos) { + rte_bbdev_log(ERR, + "ncb_pos (%u) is out of range (%u) k_pos <= value <= (%u) kw_pos", + tb->ncb_pos, tb->k_pos, kw_pos); + return -1; + } + if (tb->r > (tb->c - 1)) { + rte_bbdev_log(ERR, + "r (%u) is greater than c - 1 (%u)", + tb->r, tb->c - 1); + return -1; + } + } else { + cb = &turbo_enc->cb_params; + if (cb->k < RTE_BBDEV_MIN_CB_SIZE + || cb->k > RTE_BBDEV_MAX_CB_SIZE) { + rte_bbdev_log(ERR, + "k (%u) is out of range %u <= value <= %u", + cb->k, RTE_BBDEV_MIN_CB_SIZE, + RTE_BBDEV_MAX_CB_SIZE); + return -1; + } + + if (cb->e < RTE_BBDEV_MIN_CB_SIZE || (cb->e % 2)) { + rte_bbdev_log(ERR, + "e (%u) is less than %u or it is not even", + cb->e, RTE_BBDEV_MIN_CB_SIZE); + return -1; + } + + kw = RTE_ALIGN_CEIL(cb->k + 4, RTE_BBDEV_C_SUBBLOCK) * 3; + if (cb->ncb < cb->k || cb->ncb > kw) { + rte_bbdev_log(ERR, + "ncb (%u) is out of range (%u) k <= value <= (%u) kw", + cb->ncb, cb->k, kw); + return -1; + } + } + + return 0; +} +#endif + +static inline char * +mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len) +{ + if (unlikely(len > rte_pktmbuf_tailroom(m))) + return NULL; + + char *tail = (char *)m->buf_addr + m->data_off + m->data_len; + m->data_len = (uint16_t)(m->data_len + len); + m_head->pkt_len = (m_head->pkt_len + len); + return tail; +} + +static inline int +enqueue_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op, + uint16_t desc_offset) +{ + union fpga_dma_desc *desc; + struct rte_mbuf *input; + struct rte_mbuf *output; + int ret; + uint16_t k, e, ncb, ring_offset; + uint32_t total_left, in_length, out_length, in_offset, out_offset; + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + /* Validate op structure */ + if (validate_enc_op(op) == -1) { + rte_bbdev_log(ERR, "Turbo encoder validation failed"); + return -EINVAL; + } +#endif + + input = op->turbo_enc.input.data; + output = op->turbo_enc.output.data; + in_offset = op->turbo_enc.input.offset; + out_offset = op->turbo_enc.output.offset; + total_left = op->turbo_enc.input.length; + k = op->turbo_enc.cb_params.k; + e = op->turbo_enc.cb_params.e; + ncb = op->turbo_enc.cb_params.ncb; + + if (check_bit(op->turbo_enc.op_flags, RTE_BBDEV_TURBO_CRC_24B_ATTACH)) + in_length = ((k - 24) >> 3); + else + in_length = k >> 3; + + if (check_bit(op->turbo_enc.op_flags, RTE_BBDEV_TURBO_RATE_MATCH)) + out_length = (e + 7) >> 3; + else + out_length = (k >> 3) * 3 + 2; + + mbuf_append(output, output, out_length); + + /* Offset into the ring */ + ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask); + /* Setup DMA Descriptor */ + desc = q->ring_addr + ring_offset; + + ret = fpga_dma_desc_te_fill(op, &desc->enc_req, input, output, k, e, + ncb, in_offset, out_offset, ring_offset, 1); + if (unlikely(ret < 0)) + return ret; + + /* Update lengths */ + total_left -= in_length; + op->turbo_enc.output.length += out_length; + + if (total_left > 0) { + rte_bbdev_log(ERR, + "Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u", + total_left, in_length); + return -1; + } + + return 1; +} + +static inline int +enqueue_enc_one_op_tb(struct fpga_queue *q, struct rte_bbdev_enc_op *op, + uint16_t desc_offset, uint8_t cbs_in_op) +{ + union fpga_dma_desc *desc; + struct rte_mbuf *input, *output_head, *output; + int ret; + uint8_t r, c, crc24_bits = 0; + uint16_t k, e, ncb, ring_offset; + uint32_t mbuf_total_left, in_length, out_length, in_offset, out_offset; + uint32_t seg_total_left; + uint16_t current_enqueued_cbs = 0; + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + /* Validate op structure */ + if (validate_enc_op(op) == -1) { + rte_bbdev_log(ERR, "Turbo encoder validation failed"); + return -EINVAL; + } +#endif + + input = op->turbo_enc.input.data; + output_head = output = op->turbo_enc.output.data; + in_offset = op->turbo_enc.input.offset; + out_offset = op->turbo_enc.output.offset; + mbuf_total_left = op->turbo_enc.input.length; + + c = op->turbo_enc.tb_params.c; + r = op->turbo_enc.tb_params.r; + + if (check_bit(op->turbo_enc.op_flags, RTE_BBDEV_TURBO_CRC_24B_ATTACH)) + crc24_bits = 24; + + while (mbuf_total_left > 0 && r < c && input != NULL) { + seg_total_left = rte_pktmbuf_data_len(input) - in_offset; + + e = (r < op->turbo_enc.tb_params.cab) ? + op->turbo_enc.tb_params.ea : + op->turbo_enc.tb_params.eb; + k = (r < op->turbo_enc.tb_params.c_neg) ? + op->turbo_enc.tb_params.k_neg : + op->turbo_enc.tb_params.k_pos; + ncb = (r < op->turbo_enc.tb_params.c_neg) ? + op->turbo_enc.tb_params.ncb_neg : + op->turbo_enc.tb_params.ncb_pos; + + in_length = ((k - crc24_bits) >> 3); + + if (check_bit(op->turbo_enc.op_flags, + RTE_BBDEV_TURBO_RATE_MATCH)) + out_length = (e + 7) >> 3; + else + out_length = (k >> 3) * 3 + 2; + + mbuf_append(output_head, output, out_length); + + /* Setup DMA Descriptor */ + ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask); + desc = q->ring_addr + ring_offset; + ret = fpga_dma_desc_te_fill(op, &desc->enc_req, input, output, + k, e, ncb, in_offset, out_offset, ring_offset, + cbs_in_op); + if (unlikely(ret < 0)) + return ret; + + rte_bbdev_log_debug("DMA request desc %p", desc); + + /* Update lengths */ + op->turbo_enc.output.length += out_length; + mbuf_total_left -= in_length; + + /* Update offsets */ + if (seg_total_left == in_length) { + /* Go to the next mbuf */ + input = input->next; + output = output->next; + in_offset = 0; + out_offset = 0; + } else { + in_offset += in_length; + out_offset += out_length; + } + + r++; + desc_offset++; + current_enqueued_cbs++; + } + + if (mbuf_total_left > 0) { + rte_bbdev_log(ERR, + "Some date still left for processing: mbuf_total_left = %u", + mbuf_total_left); + return -1; + } + + return current_enqueued_cbs; +} + +#ifdef RTE_LIBRTE_BBDEV_DEBUG +/* Validates turbo decoder parameters */ +static int +validate_dec_op(struct rte_bbdev_dec_op *op) +{ + struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec; + struct rte_bbdev_op_dec_cb_params *cb = NULL; + struct rte_bbdev_op_dec_tb_params *tb = NULL; + + if (op->mempool == NULL) { + rte_bbdev_log(ERR, "Invalid mempool pointer"); + return -1; + } + if (turbo_dec->input.data == NULL) { + rte_bbdev_log(ERR, "Invalid input pointer"); + return -1; + } + if (turbo_dec->hard_output.data == NULL) { + rte_bbdev_log(ERR, "Invalid hard_output pointer"); + return -1; + } + if (turbo_dec->rv_index > 3) { + rte_bbdev_log(ERR, + "rv_index (%u) is out of range 0 <= value <= 3", + turbo_dec->rv_index); + return -1; + } + if (turbo_dec->iter_min < 1) { + rte_bbdev_log(ERR, + "iter_min (%u) is less than 1", + turbo_dec->iter_min); + return -1; + } + if (turbo_dec->iter_max <= 2) { + rte_bbdev_log(ERR, + "iter_max (%u) is less than or equal to 2", + turbo_dec->iter_max); + return -1; + } + if (turbo_dec->iter_min > turbo_dec->iter_max) { + rte_bbdev_log(ERR, + "iter_min (%u) is greater than iter_max (%u)", + turbo_dec->iter_min, turbo_dec->iter_max); + return -1; + } + if (turbo_dec->code_block_mode != 0 && + turbo_dec->code_block_mode != 1) { + rte_bbdev_log(ERR, + "code_block_mode (%u) is out of range 0 <= value <= 1", + turbo_dec->code_block_mode); + return -1; + } + + if (turbo_dec->code_block_mode == 0) { + + if ((turbo_dec->op_flags & + RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP) && + !(turbo_dec->op_flags & RTE_BBDEV_TURBO_CRC_TYPE_24B)) { + rte_bbdev_log(ERR, + "RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP should accompany RTE_BBDEV_TURBO_CRC_TYPE_24B"); + return -1; + } + + tb = &turbo_dec->tb_params; + if ((tb->k_neg < RTE_BBDEV_MIN_CB_SIZE + || tb->k_neg > RTE_BBDEV_MAX_CB_SIZE) + && tb->c_neg > 0) { + rte_bbdev_log(ERR, + "k_neg (%u) is out of range %u <= value <= %u", + tb->k_neg, RTE_BBDEV_MIN_CB_SIZE, + RTE_BBDEV_MAX_CB_SIZE); + return -1; + } + if ((tb->k_pos < RTE_BBDEV_MIN_CB_SIZE + || tb->k_pos > RTE_BBDEV_MAX_CB_SIZE) + && tb->c > tb->c_neg) { + rte_bbdev_log(ERR, + "k_pos (%u) is out of range %u <= value <= %u", + tb->k_pos, RTE_BBDEV_MIN_CB_SIZE, + RTE_BBDEV_MAX_CB_SIZE); + return -1; + } + if (tb->c_neg > (RTE_BBDEV_MAX_CODE_BLOCKS - 1)) + rte_bbdev_log(ERR, + "c_neg (%u) is out of range 0 <= value <= %u", + tb->c_neg, + RTE_BBDEV_MAX_CODE_BLOCKS - 1); + if (tb->c < 1 || tb->c > RTE_BBDEV_MAX_CODE_BLOCKS) { + rte_bbdev_log(ERR, + "c (%u) is out of range 1 <= value <= %u", + tb->c, RTE_BBDEV_MAX_CODE_BLOCKS); + return -1; + } + if (tb->cab > tb->c) { + rte_bbdev_log(ERR, + "cab (%u) is greater than c (%u)", + tb->cab, tb->c); + return -1; + } + } else { + + if (turbo_dec->op_flags & RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP) { + rte_bbdev_log(ERR, + "RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP is invalid in CB-mode"); + return -1; + } + + cb = &turbo_dec->cb_params; + if (cb->k < RTE_BBDEV_MIN_CB_SIZE + || cb->k > RTE_BBDEV_MAX_CB_SIZE) { + rte_bbdev_log(ERR, + "k (%u) is out of range %u <= value <= %u", + cb->k, RTE_BBDEV_MIN_CB_SIZE, + RTE_BBDEV_MAX_CB_SIZE); + return -1; + } + } + + return 0; +} +#endif + +static inline int +enqueue_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op, + uint16_t desc_offset) +{ + union fpga_dma_desc *desc; + struct rte_mbuf *input; + struct rte_mbuf *output; + int ret; + uint16_t k, kw, ring_offset; + uint32_t total_left, in_length, out_length, in_offset, out_offset; + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + /* Validate op structure */ + if (validate_dec_op(op) == -1) { + rte_bbdev_log(ERR, "Turbo decoder validation failed"); + return -EINVAL; + } +#endif + + input = op->turbo_dec.input.data; + output = op->turbo_dec.hard_output.data; + total_left = op->turbo_dec.input.length; + in_offset = op->turbo_dec.input.offset; + out_offset = op->turbo_dec.hard_output.offset; + + k = op->turbo_dec.cb_params.k; + kw = RTE_ALIGN_CEIL(k + 4, 32) * 3; + in_length = kw; + out_length = k >> 3; + + mbuf_append(output, output, out_length); + + /* Setup DMA Descriptor */ + ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask); + desc = q->ring_addr + ring_offset; + ret = fpga_dma_desc_td_fill(op, &desc->dec_req, input, output, + in_length, k, in_offset, out_offset, ring_offset, 1); + if (unlikely(ret < 0)) + return ret; + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + print_dma_dec_desc_debug_info(desc); +#endif + + /* Update lengths */ + total_left -= in_length; + op->turbo_dec.hard_output.length += out_length; + + if (total_left > 0) { + rte_bbdev_log(ERR, + "Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u", + total_left, in_length); + return -1; + } + + return 1; +} + + +static inline int +enqueue_dec_one_op_tb(struct fpga_queue *q, struct rte_bbdev_dec_op *op, + uint16_t desc_offset, uint8_t cbs_in_op) +{ + union fpga_dma_desc *desc; + struct rte_mbuf *input, *output_head, *output; + int ret; + uint8_t r, c; + uint16_t k, kw, in_length, out_length, ring_offset; + uint32_t mbuf_total_left, seg_total_left, in_offset, out_offset; + uint16_t current_enqueued_cbs = 0; + uint16_t crc24_overlap = 0; + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + /* Validate op structure */ + if (validate_dec_op(op) == -1) { + rte_bbdev_log(ERR, "Turbo decoder validation failed"); + return -EINVAL; + } +#endif + + input = op->turbo_dec.input.data; + output_head = output = op->turbo_dec.hard_output.data; + mbuf_total_left = op->turbo_dec.input.length; + in_offset = op->turbo_dec.input.offset; + out_offset = op->turbo_dec.hard_output.offset; + + if (!check_bit(op->turbo_dec.op_flags, + RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP)) + crc24_overlap = 24; + + c = op->turbo_dec.tb_params.c; + r = op->turbo_dec.tb_params.r; + + while (mbuf_total_left > 0 && r < c && input != NULL) { + seg_total_left = rte_pktmbuf_data_len(input) - in_offset; + k = (r < op->turbo_dec.tb_params.c_neg) ? + op->turbo_dec.tb_params.k_neg : + op->turbo_dec.tb_params.k_pos; + kw = RTE_ALIGN_CEIL(k + 4, 32) * 3; + + in_length = kw; + out_length = (k - crc24_overlap) >> 3; + + mbuf_append(output_head, output, out_length); + + if (seg_total_left < in_length) { + rte_bbdev_log(ERR, + "Partial CB found in a TB. FPGA Driver doesn't support scatter-gather operations!"); + return -1; + } + + /* Setup DMA Descriptor */ + ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask); + desc = q->ring_addr + ring_offset; + ret = fpga_dma_desc_td_fill(op, &desc->dec_req, input, output, + in_length, k, in_offset, out_offset, + ring_offset, cbs_in_op); + if (unlikely(ret < 0)) + return ret; + + /* Update lengths */ + ret = rte_pktmbuf_trim(op->turbo_dec.hard_output.data, + (crc24_overlap >> 3)); +#ifdef RTE_LIBRTE_BBDEV_DEBUG + if (ret < 0) { + rte_bbdev_log(ERR, + "The length to remove is greater than the length of the last segment"); + return -EINVAL; + } +#endif + op->turbo_dec.hard_output.length += out_length; + mbuf_total_left -= in_length; + + /* Update offsets */ + if (seg_total_left == in_length) { + /* Go to the next mbuf */ + input = input->next; + output = output->next; + in_offset = 0; + out_offset = 0; + } else { + in_offset += in_length; + out_offset += out_length; + } + + r++; + desc_offset++; + current_enqueued_cbs++; + } + + if (mbuf_total_left > 0) { + rte_bbdev_log(ERR, + "Some date still left for processing: mbuf_total_left = %u", + mbuf_total_left); + return -1; + } + + return current_enqueued_cbs; +} + +static uint16_t +fpga_enqueue_enc(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_enc_op **ops, uint16_t num) +{ + uint8_t cbs_in_op; + uint16_t i, total_enqueued_cbs = 0; + int32_t avail; + int enqueued_cbs; + struct fpga_queue *q = q_data->queue_private; + union fpga_dma_desc *desc; + + /* Check if queue is not full */ + if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == + q->head_free_desc)) + return 0; + + /* Calculates available space */ + avail = (q->head_free_desc > q->tail) ? + q->head_free_desc - q->tail - 1 : + q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1; + + for (i = 0; i < num; ++i) { + if (ops[i]->turbo_enc.code_block_mode == 0) { + cbs_in_op = get_num_cbs_in_op_enc(&ops[i]->turbo_enc); + /* Check if there is available space for further + * processing + */ + if (unlikely(avail - cbs_in_op < 0)) + break; + avail -= cbs_in_op; + enqueued_cbs = enqueue_enc_one_op_tb(q, ops[i], + total_enqueued_cbs, cbs_in_op); + } else { + /* Check if there is available space for further + * processing + */ + if (unlikely(avail - 1 < 0)) + break; + avail -= 1; + enqueued_cbs = enqueue_enc_one_op_cb(q, ops[i], + total_enqueued_cbs); + } + + if (enqueued_cbs < 0) + break; + + total_enqueued_cbs += enqueued_cbs; + + rte_bbdev_log_debug("enqueuing enc ops [%d/%d] | head %d | tail %d", + total_enqueued_cbs, num, + q->head_free_desc, q->tail); + } + + /* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt + * only when all previous CBs were already processed. + */ + desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1) + & q->sw_ring_wrap_mask); + desc->enc_req.irq_en = q->irq_enable; + + fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats); + + /* Update stats */ + q_data->queue_stats.enqueued_count += i; + q_data->queue_stats.enqueue_err_count += num - i; + + return i; +} + +static uint16_t +fpga_enqueue_dec(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_dec_op **ops, uint16_t num) +{ + uint8_t cbs_in_op; + uint16_t i, total_enqueued_cbs = 0; + int32_t avail; + int enqueued_cbs; + struct fpga_queue *q = q_data->queue_private; + union fpga_dma_desc *desc; + + /* Check if queue is not full */ + if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == + q->head_free_desc)) + return 0; + + /* Calculates available space */ + avail = (q->head_free_desc > q->tail) ? + q->head_free_desc - q->tail - 1 : + q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1; + + for (i = 0; i < num; ++i) { + if (ops[i]->turbo_dec.code_block_mode == 0) { + cbs_in_op = get_num_cbs_in_op_dec(&ops[i]->turbo_dec); + /* Check if there is available space for further + * processing + */ + if (unlikely(avail - cbs_in_op < 0)) + break; + avail -= cbs_in_op; + enqueued_cbs = enqueue_dec_one_op_tb(q, ops[i], + total_enqueued_cbs, cbs_in_op); + } else { + /* Check if there is available space for further + * processing + */ + if (unlikely(avail - 1 < 0)) + break; + avail -= 1; + enqueued_cbs = enqueue_dec_one_op_cb(q, ops[i], + total_enqueued_cbs); + } + + if (enqueued_cbs < 0) + break; + + total_enqueued_cbs += enqueued_cbs; + + rte_bbdev_log_debug("enqueuing dec ops [%d/%d] | head %d | tail %d", + total_enqueued_cbs, num, + q->head_free_desc, q->tail); + } + + /* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt + * only when all previous CBs were already processed. + */ + desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1) + & q->sw_ring_wrap_mask); + desc->dec_req.irq_en = q->irq_enable; + + fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats); + + /* Update stats */ + q_data->queue_stats.enqueued_count += i; + q_data->queue_stats.enqueue_err_count += num - i; + + return i; +} + +static inline int +dequeue_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op **op, + uint16_t desc_offset) +{ + union fpga_dma_desc *desc; + int desc_error = 0; + + /* Set current desc */ + desc = q->ring_addr + ((q->head_free_desc + desc_offset) + & q->sw_ring_wrap_mask); + + /*check if done */ + if (desc->enc_req.done == 0) + return -1; + + /* make sure the response is read atomically */ + rte_smp_rmb(); + + rte_bbdev_log_debug("DMA response desc %p", desc); + + *op = desc->enc_req.op_addr; + /* Check the decriptor error field, return 1 on error */ + desc_error = check_desc_error(desc->enc_req.error); + (*op)->status = desc_error << RTE_BBDEV_DATA_ERROR; + + return 1; +} + +static inline int +dequeue_enc_one_op_tb(struct fpga_queue *q, struct rte_bbdev_enc_op **op, + uint16_t desc_offset) +{ + union fpga_dma_desc *desc; + uint8_t cbs_in_op, cb_idx; + int desc_error = 0; + int status = 0; + + /* Set descriptor */ + desc = q->ring_addr + ((q->head_free_desc + desc_offset) + & q->sw_ring_wrap_mask); + + /* Verify if done bit is set */ + if (desc->enc_req.done == 0) + return -1; + + /* Make sure the response is read atomically */ + rte_smp_rmb(); + + /* Verify if done bit in all CBs is set */ + cbs_in_op = desc->enc_req.cbs_in_op; + for (cb_idx = 1; cb_idx < cbs_in_op; ++cb_idx) { + desc = q->ring_addr + ((q->head_free_desc + desc_offset + + cb_idx) & q->sw_ring_wrap_mask); + if (desc->enc_req.done == 0) + return -1; + } + + /* Make sure the response is read atomically */ + rte_smp_rmb(); + + for (cb_idx = 0; cb_idx < cbs_in_op; ++cb_idx) { + desc = q->ring_addr + ((q->head_free_desc + desc_offset + + cb_idx) & q->sw_ring_wrap_mask); + /* Check the decriptor error field, return 1 on error */ + desc_error = check_desc_error(desc->enc_req.error); + status |= desc_error << RTE_BBDEV_DATA_ERROR; + rte_bbdev_log_debug("DMA response desc %p", desc); + } + + *op = desc->enc_req.op_addr; + (*op)->status = status; + return cbs_in_op; +} + +static inline int +dequeue_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op, + uint16_t desc_offset) +{ + union fpga_dma_desc *desc; + int desc_error = 0; + /* Set descriptor */ + desc = q->ring_addr + ((q->head_free_desc + desc_offset) + & q->sw_ring_wrap_mask); + + /* Verify done bit is set */ + if (desc->dec_req.done == 0) + return -1; + + /* make sure the response is read atomically */ + rte_smp_rmb(); + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + print_dma_dec_desc_debug_info(desc); + +#endif + + *op = desc->dec_req.op_addr; + /* FPGA reports in half-iterations, from 0 to 31. get ceiling */ + (*op)->turbo_dec.iter_count = (desc->dec_req.iter + 2) >> 1; + /* crc_pass = 0 when decoder fails */ + (*op)->status = !(desc->dec_req.crc_pass) << RTE_BBDEV_CRC_ERROR; + /* Check the decriptor error field, return 1 on error */ + desc_error = check_desc_error(desc->enc_req.error); + (*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR; + return 1; +} + +static inline int +dequeue_dec_one_op_tb(struct fpga_queue *q, struct rte_bbdev_dec_op **op, + uint16_t desc_offset) +{ + union fpga_dma_desc *desc; + uint8_t cbs_in_op, cb_idx, iter_count = 0; + int status = 0; + int desc_error = 0; + /* Set descriptor */ + desc = q->ring_addr + ((q->head_free_desc + desc_offset) + & q->sw_ring_wrap_mask); + + /* Verify if done bit is set */ + if (desc->dec_req.done == 0) + return -1; + + /* Make sure the response is read atomically */ + rte_smp_rmb(); + + /* Verify if done bit in all CBs is set */ + cbs_in_op = desc->dec_req.cbs_in_op; + for (cb_idx = 1; cb_idx < cbs_in_op; ++cb_idx) { + desc = q->ring_addr + ((q->head_free_desc + desc_offset + + cb_idx) & q->sw_ring_wrap_mask); + if (desc->dec_req.done == 0) + return -1; + } + + /* Make sure the response is read atomically */ + rte_smp_rmb(); + + for (cb_idx = 0; cb_idx < cbs_in_op; ++cb_idx) { + desc = q->ring_addr + ((q->head_free_desc + desc_offset + + cb_idx) & q->sw_ring_wrap_mask); + /* get max iter_count for all CBs in op */ + iter_count = RTE_MAX(iter_count, (uint8_t) desc->dec_req.iter); + /* crc_pass = 0 when decoder fails, one fails all */ + status |= !(desc->dec_req.crc_pass) << RTE_BBDEV_CRC_ERROR; + /* Check the decriptor error field, return 1 on error */ + desc_error = check_desc_error(desc->enc_req.error); + status |= desc_error << RTE_BBDEV_DATA_ERROR; + rte_bbdev_log_debug("DMA response desc %p", desc); + } + + *op = desc->dec_req.op_addr; + + /* FPGA reports in half-iterations, get ceiling */ + (*op)->turbo_dec.iter_count = (iter_count + 2) >> 1; + (*op)->status = status; + return cbs_in_op; +} + +static uint16_t +fpga_dequeue_enc(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_enc_op **ops, uint16_t num) +{ + struct fpga_queue *q = q_data->queue_private; + uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask; + uint16_t i; + uint16_t dequeued_cbs = 0; + struct rte_bbdev_enc_op *op; + int ret; + + for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) { + op = (q->ring_addr + ((q->head_free_desc + dequeued_cbs) + & q->sw_ring_wrap_mask))->enc_req.op_addr; + if (op->turbo_enc.code_block_mode == 0) + ret = dequeue_enc_one_op_tb(q, &ops[i], dequeued_cbs); + else + ret = dequeue_enc_one_op_cb(q, &ops[i], dequeued_cbs); + + if (ret < 0) + break; + + dequeued_cbs += ret; + + rte_bbdev_log_debug("dequeuing enc ops [%d/%d] | head %d | tail %d", + dequeued_cbs, num, q->head_free_desc, q->tail); + } + + /* Update head */ + q->head_free_desc = (q->head_free_desc + dequeued_cbs) & + q->sw_ring_wrap_mask; + + /* Update stats */ + q_data->queue_stats.dequeued_count += i; + + return i; +} + +static uint16_t +fpga_dequeue_dec(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_dec_op **ops, uint16_t num) +{ + struct fpga_queue *q = q_data->queue_private; + uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask; + uint16_t i; + uint16_t dequeued_cbs = 0; + struct rte_bbdev_dec_op *op; + int ret; + + for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) { + op = (q->ring_addr + ((q->head_free_desc + dequeued_cbs) + & q->sw_ring_wrap_mask))->dec_req.op_addr; + if (op->turbo_dec.code_block_mode == 0) + ret = dequeue_dec_one_op_tb(q, &ops[i], dequeued_cbs); + else + ret = dequeue_dec_one_op_cb(q, &ops[i], dequeued_cbs); + + if (ret < 0) + break; + + dequeued_cbs += ret; + + rte_bbdev_log_debug("dequeuing dec ops [%d/%d] | head %d | tail %d", + dequeued_cbs, num, q->head_free_desc, q->tail); + } + + /* Update head */ + q->head_free_desc = (q->head_free_desc + dequeued_cbs) & + q->sw_ring_wrap_mask; + + /* Update stats */ + q_data->queue_stats.dequeued_count += i; + + return i; +} + +/* Initialization Function */ +static void +fpga_lte_fec_init(struct rte_bbdev *dev) +{ + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); + + dev->dev_ops = &fpga_ops; + dev->enqueue_enc_ops = fpga_enqueue_enc; + dev->enqueue_dec_ops = fpga_enqueue_dec; + dev->dequeue_enc_ops = fpga_dequeue_enc; + dev->dequeue_dec_ops = fpga_dequeue_dec; + + ((struct fpga_lte_fec_device *) dev->data->dev_private)->pf_device = + !strcmp(dev->device->driver->name, + RTE_STR(FPGA_LTE_FEC_PF_DRIVER_NAME)); + ((struct fpga_lte_fec_device *) dev->data->dev_private)->mmio_base = + pci_dev->mem_resource[0].addr; + + rte_bbdev_log_debug( + "Init device %s [%s] @ virtaddr %p phyaddr %#"PRIx64, + dev->device->driver->name, dev->data->name, + (void *)pci_dev->mem_resource[0].addr, + pci_dev->mem_resource[0].phys_addr); +} + +static int +fpga_lte_fec_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + struct rte_bbdev *bbdev = NULL; + char dev_name[RTE_BBDEV_NAME_MAX_LEN]; + + if (pci_dev == NULL) { + rte_bbdev_log(ERR, "NULL PCI device"); + return -EINVAL; + } + + rte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name)); + + /* Allocate memory to be used privately by drivers */ + bbdev = rte_bbdev_allocate(pci_dev->device.name); + if (bbdev == NULL) + return -ENODEV; + + /* allocate device private memory */ + bbdev->data->dev_private = rte_zmalloc_socket(dev_name, + sizeof(struct fpga_lte_fec_device), RTE_CACHE_LINE_SIZE, + pci_dev->device.numa_node); + + if (bbdev->data->dev_private == NULL) { + rte_bbdev_log(CRIT, + "Allocate of %zu bytes for device \"%s\" failed", + sizeof(struct fpga_lte_fec_device), dev_name); + rte_bbdev_release(bbdev); + return -ENOMEM; + } + + /* Fill HW specific part of device structure */ + bbdev->device = &pci_dev->device; + bbdev->intr_handle = &pci_dev->intr_handle; + bbdev->data->socket_id = pci_dev->device.numa_node; + + /* Invoke FEC FPGA device initialization function */ + fpga_lte_fec_init(bbdev); + + rte_bbdev_log_debug("bbdev id = %u [%s]", + bbdev->data->dev_id, dev_name); + + struct fpga_lte_fec_device *d = bbdev->data->dev_private; + uint32_t version_id = fpga_reg_read_32(d->mmio_base, + FPGA_LTE_FEC_VERSION_ID); + rte_bbdev_log(INFO, "FEC FPGA RTL v%u.%u", + ((uint16_t)(version_id >> 16)), ((uint16_t)version_id)); + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + if (!strcmp(bbdev->device->driver->name, + RTE_STR(FPGA_LTE_FEC_PF_DRIVER_NAME))) + print_static_reg_debug_info(d->mmio_base); +#endif + return 0; +} + +static int +fpga_lte_fec_remove(struct rte_pci_device *pci_dev) +{ + struct rte_bbdev *bbdev; + int ret; + uint8_t dev_id; + + if (pci_dev == NULL) + return -EINVAL; + + /* Find device */ + bbdev = rte_bbdev_get_named_dev(pci_dev->device.name); + if (bbdev == NULL) { + rte_bbdev_log(CRIT, + "Couldn't find HW dev \"%s\" to uninitialise it", + pci_dev->device.name); + return -ENODEV; + } + dev_id = bbdev->data->dev_id; + + /* free device private memory before close */ + rte_free(bbdev->data->dev_private); + + /* Close device */ + ret = rte_bbdev_close(dev_id); + if (ret < 0) + rte_bbdev_log(ERR, + "Device %i failed to close during uninit: %i", + dev_id, ret); + + /* release bbdev from library */ + ret = rte_bbdev_release(bbdev); + if (ret) + rte_bbdev_log(ERR, "Device %i failed to uninit: %i", dev_id, + ret); + + rte_bbdev_log_debug("Destroyed bbdev = %u", dev_id); + + return 0; +} + +static inline void +set_default_fpga_conf(struct fpga_lte_fec_conf *def_conf) +{ + /* clear default configuration before initialization */ + memset(def_conf, 0, sizeof(struct fpga_lte_fec_conf)); + /* Set pf mode to true */ + def_conf->pf_mode_en = true; + + /* Set ratio between UL and DL to 1:1 (unit of weight is 3 CBs) */ + def_conf->ul_bandwidth = 3; + def_conf->dl_bandwidth = 3; + + /* Set Load Balance Factor to 64 */ + def_conf->dl_load_balance = 64; + def_conf->ul_load_balance = 64; +} + +/* Initial configuration of FPGA LTE FEC device */ +int +fpga_lte_fec_configure(const char *dev_name, + const struct fpga_lte_fec_conf *conf) +{ + uint32_t payload_32, address; + uint16_t payload_16; + uint8_t payload_8; + uint16_t q_id, vf_id, total_q_id, total_ul_q_id, total_dl_q_id; + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name); + struct fpga_lte_fec_conf def_conf; + + if (bbdev == NULL) { + rte_bbdev_log(ERR, + "Invalid dev_name (%s), or device is not yet initialised", + dev_name); + return -ENODEV; + } + + struct fpga_lte_fec_device *d = bbdev->data->dev_private; + + if (conf == NULL) { + rte_bbdev_log(ERR, + "FPGA Configuration was not provided. Default configuration will be loaded."); + set_default_fpga_conf(&def_conf); + conf = &def_conf; + } + + /* + * Configure UL:DL ratio. + * [7:0]: UL weight + * [15:8]: DL weight + */ + payload_16 = (conf->dl_bandwidth << 8) | conf->ul_bandwidth; + address = FPGA_LTE_FEC_CONFIGURATION; + fpga_reg_write_16(d->mmio_base, address, payload_16); + + /* Clear all queues registers */ + payload_32 = FPGA_INVALID_HW_QUEUE_ID; + for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { + address = (q_id << 2) + FPGA_LTE_FEC_QUEUE_MAP; + fpga_reg_write_32(d->mmio_base, address, payload_32); + } + + /* + * If PF mode is enabled allocate all queues for PF only. + * + * For VF mode each VF can have different number of UL and DL queues. + * Total number of queues to configure cannot exceed FPGA + * capabilities - 64 queues - 32 queues for UL and 32 queues for DL. + * Queues mapping is done according to configuration: + * + * UL queues: + * | Q_ID | VF_ID | + * | 0 | 0 | + * | ... | 0 | + * | conf->vf_dl_queues_number[0] - 1 | 0 | + * | conf->vf_dl_queues_number[0] | 1 | + * | ... | 1 | + * | conf->vf_dl_queues_number[1] - 1 | 1 | + * | ... | ... | + * | conf->vf_dl_queues_number[7] - 1 | 7 | + * + * DL queues: + * | Q_ID | VF_ID | + * | 32 | 0 | + * | ... | 0 | + * | conf->vf_ul_queues_number[0] - 1 | 0 | + * | conf->vf_ul_queues_number[0] | 1 | + * | ... | 1 | + * | conf->vf_ul_queues_number[1] - 1 | 1 | + * | ... | ... | + * | conf->vf_ul_queues_number[7] - 1 | 7 | + * + * Example of configuration: + * conf->vf_ul_queues_number[0] = 4; -> 4 UL queues for VF0 + * conf->vf_dl_queues_number[0] = 4; -> 4 DL queues for VF0 + * conf->vf_ul_queues_number[1] = 2; -> 2 UL queues for VF1 + * conf->vf_dl_queues_number[1] = 2; -> 2 DL queues for VF1 + * + * UL: + * | Q_ID | VF_ID | + * | 0 | 0 | + * | 1 | 0 | + * | 2 | 0 | + * | 3 | 0 | + * | 4 | 1 | + * | 5 | 1 | + * + * DL: + * | Q_ID | VF_ID | + * | 32 | 0 | + * | 33 | 0 | + * | 34 | 0 | + * | 35 | 0 | + * | 36 | 1 | + * | 37 | 1 | + */ + if (conf->pf_mode_en) { + payload_32 = 0x1; + for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { + address = (q_id << 2) + FPGA_LTE_FEC_QUEUE_MAP; + fpga_reg_write_32(d->mmio_base, address, payload_32); + } + } else { + /* Calculate total number of UL and DL queues to configure */ + total_ul_q_id = total_dl_q_id = 0; + for (vf_id = 0; vf_id < FPGA_LTE_FEC_NUM_VFS; ++vf_id) { + total_ul_q_id += conf->vf_ul_queues_number[vf_id]; + total_dl_q_id += conf->vf_dl_queues_number[vf_id]; + } + total_q_id = total_dl_q_id + total_ul_q_id; + /* + * Check if total number of queues to configure does not exceed + * FPGA capabilities (64 queues - 32 UL and 32 DL queues) + */ + if ((total_ul_q_id > FPGA_NUM_UL_QUEUES) || + (total_dl_q_id > FPGA_NUM_DL_QUEUES) || + (total_q_id > FPGA_TOTAL_NUM_QUEUES)) { + rte_bbdev_log(ERR, + "FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u", + total_ul_q_id, total_dl_q_id, + FPGA_TOTAL_NUM_QUEUES); + return -EINVAL; + } + total_ul_q_id = 0; + for (vf_id = 0; vf_id < FPGA_LTE_FEC_NUM_VFS; ++vf_id) { + for (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id]; + ++q_id, ++total_ul_q_id) { + address = (total_ul_q_id << 2) + + FPGA_LTE_FEC_QUEUE_MAP; + payload_32 = ((0x80 + vf_id) << 16) | 0x1; + fpga_reg_write_32(d->mmio_base, address, + payload_32); + } + } + total_dl_q_id = 0; + for (vf_id = 0; vf_id < FPGA_LTE_FEC_NUM_VFS; ++vf_id) { + for (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id]; + ++q_id, ++total_dl_q_id) { + address = ((total_dl_q_id + FPGA_NUM_UL_QUEUES) + << 2) + FPGA_LTE_FEC_QUEUE_MAP; + payload_32 = ((0x80 + vf_id) << 16) | 0x1; + fpga_reg_write_32(d->mmio_base, address, + payload_32); + } + } + } + + /* Setting Load Balance Factor */ + payload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance); + address = FPGA_LTE_FEC_LOAD_BALANCE_FACTOR; + fpga_reg_write_16(d->mmio_base, address, payload_16); + + /* Setting length of ring descriptor entry */ + payload_16 = FPGA_RING_DESC_ENTRY_LENGTH; + address = FPGA_LTE_FEC_RING_DESC_LEN; + fpga_reg_write_16(d->mmio_base, address, payload_16); + + /* Setting FLR timeout value */ + payload_16 = conf->flr_time_out; + address = FPGA_LTE_FEC_FLR_TIME_OUT; + fpga_reg_write_16(d->mmio_base, address, payload_16); + + /* Queue PF/VF mapping table is ready */ + payload_8 = 0x1; + address = FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE; + fpga_reg_write_8(d->mmio_base, address, payload_8); + + rte_bbdev_log_debug("PF FPGA LTE FEC configuration complete for %s", + dev_name); + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + print_static_reg_debug_info(d->mmio_base); +#endif + return 0; +} + +/* FPGA LTE FEC PCI PF address map */ +static struct rte_pci_id pci_id_fpga_lte_fec_pf_map[] = { + { + RTE_PCI_DEVICE(FPGA_LTE_FEC_VENDOR_ID, + FPGA_LTE_FEC_PF_DEVICE_ID) + }, + {.device_id = 0}, +}; + +static struct rte_pci_driver fpga_lte_fec_pci_pf_driver = { + .probe = fpga_lte_fec_probe, + .remove = fpga_lte_fec_remove, + .id_table = pci_id_fpga_lte_fec_pf_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING +}; + +/* FPGA LTE FEC PCI VF address map */ +static struct rte_pci_id pci_id_fpga_lte_fec_vf_map[] = { + { + RTE_PCI_DEVICE(FPGA_LTE_FEC_VENDOR_ID, + FPGA_LTE_FEC_VF_DEVICE_ID) + }, + {.device_id = 0}, +}; + +static struct rte_pci_driver fpga_lte_fec_pci_vf_driver = { + .probe = fpga_lte_fec_probe, + .remove = fpga_lte_fec_remove, + .id_table = pci_id_fpga_lte_fec_vf_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING +}; + + +RTE_PMD_REGISTER_PCI(FPGA_LTE_FEC_PF_DRIVER_NAME, fpga_lte_fec_pci_pf_driver); +RTE_PMD_REGISTER_PCI_TABLE(FPGA_LTE_FEC_PF_DRIVER_NAME, + pci_id_fpga_lte_fec_pf_map); +RTE_PMD_REGISTER_PCI(FPGA_LTE_FEC_VF_DRIVER_NAME, fpga_lte_fec_pci_vf_driver); +RTE_PMD_REGISTER_PCI_TABLE(FPGA_LTE_FEC_VF_DRIVER_NAME, + pci_id_fpga_lte_fec_vf_map); + +RTE_INIT(fpga_lte_fec_init_log) +{ + fpga_lte_fec_logtype = rte_log_register("pmd.bb.fpga_lte_fec"); + if (fpga_lte_fec_logtype >= 0) +#ifdef RTE_LIBRTE_BBDEV_DEBUG + rte_log_set_level(fpga_lte_fec_logtype, RTE_LOG_DEBUG); +#else + rte_log_set_level(fpga_lte_fec_logtype, RTE_LOG_NOTICE); +#endif +} diff --git a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.h b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.h new file mode 100644 index 0000000..9ae8b12 --- /dev/null +++ b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Intel Corporation + */ + +#ifndef _FPGA_LTE_FEC_H_ +#define _FPGA_LTE_FEC_H_ + +#include +#include + +/** + * @file fpga_lte_fec.h + * + * Interface for Intel(R) FGPA LTE FEC device configuration at the host level, + * directly accessible by the application. + * Configuration related to LTE Turbo coding functionality is done through + * librte_bbdev library. + * + * @warning + * @b EXPERIMENTAL: this API may change without prior notice + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/**< Number of Virtual Functions FGPA 4G FEC supports */ +#define FPGA_LTE_FEC_NUM_VFS 8 + +/** + * Structure to pass FPGA 4G FEC configuration. + */ +struct fpga_lte_fec_conf { + /**< 1 if PF is used for dataplane, 0 for VFs */ + bool pf_mode_en; + /**< Number of UL queues per VF */ + uint8_t vf_ul_queues_number[FPGA_LTE_FEC_NUM_VFS]; + /**< Number of DL queues per VF */ + uint8_t vf_dl_queues_number[FPGA_LTE_FEC_NUM_VFS]; + /**< UL bandwidth. Needed for schedule algorithm */ + uint8_t ul_bandwidth; + /**< DL bandwidth. Needed for schedule algorithm */ + uint8_t dl_bandwidth; + /**< UL Load Balance */ + uint8_t ul_load_balance; + /**< DL Load Balance */ + uint8_t dl_load_balance; + /**< FLR timeout value */ + uint16_t flr_time_out; +}; + +/** + * Configure Intel(R) FPGA LTE FEC device + * + * @param dev_name + * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0. + * It can also be retrieved for a bbdev device from the dev_name field in the + * rte_bbdev_info structure returned by rte_bbdev_info_get(). + * @param conf + * Configuration to apply to FPGA 4G FEC. + * + * @return + * Zero on success, negative value on failure. + */ +int +fpga_lte_fec_configure(const char *dev_name, + const struct fpga_lte_fec_conf *conf); + +#ifdef __cplusplus +} +#endif + +#endif /* _FPGA_LTE_FEC_H_ */ diff --git a/drivers/baseband/fpga_lte_fec/meson.build b/drivers/baseband/fpga_lte_fec/meson.build new file mode 100644 index 0000000..bf44e6b --- /dev/null +++ b/drivers/baseband/fpga_lte_fec/meson.build @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2019 Intel Corporation + +deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci'] +name = 'bbdev_fpga_lte_fec' +allow_experimental_apis = true +sources = files('fpga_lte_fec.c') diff --git a/drivers/baseband/fpga_lte_fec/rte_pmd_bbdev_fpga_lte_fec_version.map b/drivers/baseband/fpga_lte_fec/rte_pmd_bbdev_fpga_lte_fec_version.map new file mode 100644 index 0000000..e923270 --- /dev/null +++ b/drivers/baseband/fpga_lte_fec/rte_pmd_bbdev_fpga_lte_fec_version.map @@ -0,0 +1,3 @@ +DPDK_19.08 { + local: *; +}; diff --git a/drivers/baseband/meson.build b/drivers/baseband/meson.build index 40a87d2..391bd51 100644 --- a/drivers/baseband/meson.build +++ b/drivers/baseband/meson.build @@ -1,7 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Luca Boccassi -drivers = ['null', 'turbo_sw'] +drivers = ['null', 'turbo_sw', 'fpga_lte_fec'] config_flag_fmt = 'RTE_LIBRTE_@0@_PMD' driver_name_fmt = 'rte_pmd_@0@' diff --git a/mk/rte.app.mk b/mk/rte.app.mk index 2c3d07a..cdd6073 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -216,6 +216,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_NETVSC_PMD) += -lrte_pmd_netvsc ifeq ($(CONFIG_RTE_LIBRTE_BBDEV),y) _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_NULL) += -lrte_pmd_bbdev_null +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_FPGA_LTE_FEC) += -lrte_pmd_fpga_lte_fec # TURBO SOFTWARE PMD is dependent on the FLEXRAN library _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -lrte_pmd_bbdev_turbo_sw From patchwork Mon Jun 24 02:52:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 55226 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 299D41BF75; Mon, 24 Jun 2019 04:53:14 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 6FC231BEAD for ; Mon, 24 Jun 2019 04:53:02 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jun 2019 19:52:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,410,1557212400"; d="scan'208";a="183991190" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga004.fm.intel.com with ESMTP; 23 Jun 2019 19:52:59 -0700 From: Nicolas Chautru To: akhil.goyal@nxp.com, dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@intel.com, amr.mokhtar@intel.com, Nicolas Chautru Date: Sun, 23 Jun 2019 19:52:49 -0700 Message-Id: <1561344776-43990-4-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> References: <1561136352-32198-2-git-send-email-nicolas.chautru@intel.com> <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v4 03/10] bbdev: renaming non-generic LTE specific structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Renaming of the enums and structure which were LTE specific to allow for extension and support for 5GNR operations. Signed-off-by: Nicolas Chautru Acked-by: Amr Mokhtar --- app/test-bbdev/test_bbdev_vector.c | 4 +- app/test-bbdev/test_bbdev_vector.h | 2 +- drivers/baseband/fpga_lte_fec/fpga_lte_fec.c | 103 ++++++++++++----------- drivers/baseband/turbo_sw/bbdev_turbo_software.c | 36 ++++---- lib/librte_bbdev/rte_bbdev_op.h | 26 +++--- 5 files changed, 86 insertions(+), 85 deletions(-) diff --git a/app/test-bbdev/test_bbdev_vector.c b/app/test-bbdev/test_bbdev_vector.c index e4f68e2..e149ced 100644 --- a/app/test-bbdev/test_bbdev_vector.c +++ b/app/test-bbdev/test_bbdev_vector.c @@ -298,9 +298,9 @@ op_data = vector->entries[type].segments; nb_ops = &vector->entries[type].nb_segments; - if (*nb_ops >= RTE_BBDEV_MAX_CODE_BLOCKS) { + if (*nb_ops >= RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) { printf("Too many segments (code blocks defined): %u, max %d!\n", - *nb_ops, RTE_BBDEV_MAX_CODE_BLOCKS); + *nb_ops, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS); return -1; } diff --git a/app/test-bbdev/test_bbdev_vector.h b/app/test-bbdev/test_bbdev_vector.h index 476aae1..c85e94d 100644 --- a/app/test-bbdev/test_bbdev_vector.h +++ b/app/test-bbdev/test_bbdev_vector.h @@ -46,7 +46,7 @@ struct op_data_buf { }; struct op_data_entries { - struct op_data_buf segments[RTE_BBDEV_MAX_CODE_BLOCKS]; + struct op_data_buf segments[RTE_BBDEV_TURBO_MAX_CODE_BLOCKS]; unsigned int nb_segments; }; diff --git a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c index 19e7689..7e05b94 100644 --- a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c +++ b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c @@ -607,9 +607,9 @@ struct __rte_cache_aligned fpga_queue { RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP, .max_llr_modulus = INT8_MAX, .num_buffers_src = - RTE_BBDEV_MAX_CODE_BLOCKS, + RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, .num_buffers_hard_out = - RTE_BBDEV_MAX_CODE_BLOCKS, + RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, .num_buffers_soft_out = 0 } }, @@ -621,9 +621,9 @@ struct __rte_cache_aligned fpga_queue { RTE_BBDEV_TURBO_RATE_MATCH | RTE_BBDEV_TURBO_ENC_INTERRUPTS, .num_buffers_src = - RTE_BBDEV_MAX_CODE_BLOCKS, + RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, .num_buffers_dst = - RTE_BBDEV_MAX_CODE_BLOCKS + RTE_BBDEV_TURBO_MAX_CODE_BLOCKS } }, RTE_BBDEV_END_OF_CAPABILITIES_LIST() @@ -1332,14 +1332,15 @@ struct __rte_cache_aligned fpga_queue { validate_enc_op(struct rte_bbdev_enc_op *op) { struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc; - struct rte_bbdev_op_enc_cb_params *cb = NULL; - struct rte_bbdev_op_enc_tb_params *tb = NULL; + struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL; + struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL; uint16_t kw, kw_neg, kw_pos; if (turbo_enc->input.length > - RTE_BBDEV_MAX_TB_SIZE >> 3) { + RTE_BBDEV_TURBO_MAX_TB_SIZE >> 3) { rte_bbdev_log(ERR, "TB size (%u) is too big, max: %d", - turbo_enc->input.length, RTE_BBDEV_MAX_TB_SIZE); + turbo_enc->input.length, + RTE_BBDEV_TURBO_MAX_TB_SIZE); op->status = 1 << RTE_BBDEV_DATA_ERROR; return -1; } @@ -1372,32 +1373,32 @@ struct __rte_cache_aligned fpga_queue { if (turbo_enc->code_block_mode == 0) { tb = &turbo_enc->tb_params; - if ((tb->k_neg < RTE_BBDEV_MIN_CB_SIZE - || tb->k_neg > RTE_BBDEV_MAX_CB_SIZE) + if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE + || tb->k_neg > RTE_BBDEV_TURBO_MAX_CB_SIZE) && tb->c_neg > 0) { rte_bbdev_log(ERR, "k_neg (%u) is out of range %u <= value <= %u", - tb->k_neg, RTE_BBDEV_MIN_CB_SIZE, - RTE_BBDEV_MAX_CB_SIZE); + tb->k_neg, RTE_BBDEV_TURBO_MIN_CB_SIZE, + RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } - if (tb->k_pos < RTE_BBDEV_MIN_CB_SIZE - || tb->k_pos > RTE_BBDEV_MAX_CB_SIZE) { + if (tb->k_pos < RTE_BBDEV_TURBO_MIN_CB_SIZE + || tb->k_pos > RTE_BBDEV_TURBO_MAX_CB_SIZE) { rte_bbdev_log(ERR, "k_pos (%u) is out of range %u <= value <= %u", - tb->k_pos, RTE_BBDEV_MIN_CB_SIZE, - RTE_BBDEV_MAX_CB_SIZE); + tb->k_pos, RTE_BBDEV_TURBO_MIN_CB_SIZE, + RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } - if (tb->c_neg > (RTE_BBDEV_MAX_CODE_BLOCKS - 1)) + if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1)) rte_bbdev_log(ERR, "c_neg (%u) is out of range 0 <= value <= %u", tb->c_neg, - RTE_BBDEV_MAX_CODE_BLOCKS - 1); - if (tb->c < 1 || tb->c > RTE_BBDEV_MAX_CODE_BLOCKS) { + RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1); + if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) { rte_bbdev_log(ERR, "c (%u) is out of range 1 <= value <= %u", - tb->c, RTE_BBDEV_MAX_CODE_BLOCKS); + tb->c, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS); return -1; } if (tb->cab > tb->c) { @@ -1406,23 +1407,23 @@ struct __rte_cache_aligned fpga_queue { tb->cab, tb->c); return -1; } - if ((tb->ea < RTE_BBDEV_MIN_CB_SIZE || (tb->ea % 2)) + if ((tb->ea < RTE_BBDEV_TURBO_MIN_CB_SIZE || (tb->ea % 2)) && tb->r < tb->cab) { rte_bbdev_log(ERR, "ea (%u) is less than %u or it is not even", - tb->ea, RTE_BBDEV_MIN_CB_SIZE); + tb->ea, RTE_BBDEV_TURBO_MIN_CB_SIZE); return -1; } - if ((tb->eb < RTE_BBDEV_MIN_CB_SIZE || (tb->eb % 2)) + if ((tb->eb < RTE_BBDEV_TURBO_MIN_CB_SIZE || (tb->eb % 2)) && tb->c > tb->cab) { rte_bbdev_log(ERR, "eb (%u) is less than %u or it is not even", - tb->eb, RTE_BBDEV_MIN_CB_SIZE); + tb->eb, RTE_BBDEV_TURBO_MIN_CB_SIZE); return -1; } kw_neg = 3 * RTE_ALIGN_CEIL(tb->k_neg + 4, - RTE_BBDEV_C_SUBBLOCK); + RTE_BBDEV_TURBO_C_SUBBLOCK); if (tb->ncb_neg < tb->k_neg || tb->ncb_neg > kw_neg) { rte_bbdev_log(ERR, "ncb_neg (%u) is out of range (%u) k_neg <= value <= (%u) kw_neg", @@ -1431,7 +1432,7 @@ struct __rte_cache_aligned fpga_queue { } kw_pos = 3 * RTE_ALIGN_CEIL(tb->k_pos + 4, - RTE_BBDEV_C_SUBBLOCK); + RTE_BBDEV_TURBO_C_SUBBLOCK); if (tb->ncb_pos < tb->k_pos || tb->ncb_pos > kw_pos) { rte_bbdev_log(ERR, "ncb_pos (%u) is out of range (%u) k_pos <= value <= (%u) kw_pos", @@ -1446,23 +1447,23 @@ struct __rte_cache_aligned fpga_queue { } } else { cb = &turbo_enc->cb_params; - if (cb->k < RTE_BBDEV_MIN_CB_SIZE - || cb->k > RTE_BBDEV_MAX_CB_SIZE) { + if (cb->k < RTE_BBDEV_TURBO_MIN_CB_SIZE + || cb->k > RTE_BBDEV_TURBO_MAX_CB_SIZE) { rte_bbdev_log(ERR, "k (%u) is out of range %u <= value <= %u", - cb->k, RTE_BBDEV_MIN_CB_SIZE, - RTE_BBDEV_MAX_CB_SIZE); + cb->k, RTE_BBDEV_TURBO_MIN_CB_SIZE, + RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } - if (cb->e < RTE_BBDEV_MIN_CB_SIZE || (cb->e % 2)) { + if (cb->e < RTE_BBDEV_TURBO_MIN_CB_SIZE || (cb->e % 2)) { rte_bbdev_log(ERR, "e (%u) is less than %u or it is not even", - cb->e, RTE_BBDEV_MIN_CB_SIZE); + cb->e, RTE_BBDEV_TURBO_MIN_CB_SIZE); return -1; } - kw = RTE_ALIGN_CEIL(cb->k + 4, RTE_BBDEV_C_SUBBLOCK) * 3; + kw = RTE_ALIGN_CEIL(cb->k + 4, RTE_BBDEV_TURBO_C_SUBBLOCK) * 3; if (cb->ncb < cb->k || cb->ncb > kw) { rte_bbdev_log(ERR, "ncb (%u) is out of range (%u) k <= value <= (%u) kw", @@ -1655,8 +1656,8 @@ struct __rte_cache_aligned fpga_queue { validate_dec_op(struct rte_bbdev_dec_op *op) { struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec; - struct rte_bbdev_op_dec_cb_params *cb = NULL; - struct rte_bbdev_op_dec_tb_params *tb = NULL; + struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL; + struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL; if (op->mempool == NULL) { rte_bbdev_log(ERR, "Invalid mempool pointer"); @@ -1713,33 +1714,33 @@ struct __rte_cache_aligned fpga_queue { } tb = &turbo_dec->tb_params; - if ((tb->k_neg < RTE_BBDEV_MIN_CB_SIZE - || tb->k_neg > RTE_BBDEV_MAX_CB_SIZE) + if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE + || tb->k_neg > RTE_BBDEV_TURBO_MAX_CB_SIZE) && tb->c_neg > 0) { rte_bbdev_log(ERR, "k_neg (%u) is out of range %u <= value <= %u", - tb->k_neg, RTE_BBDEV_MIN_CB_SIZE, - RTE_BBDEV_MAX_CB_SIZE); + tb->k_neg, RTE_BBDEV_TURBO_MIN_CB_SIZE, + RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } - if ((tb->k_pos < RTE_BBDEV_MIN_CB_SIZE - || tb->k_pos > RTE_BBDEV_MAX_CB_SIZE) + if ((tb->k_pos < RTE_BBDEV_TURBO_MIN_CB_SIZE + || tb->k_pos > RTE_BBDEV_TURBO_MAX_CB_SIZE) && tb->c > tb->c_neg) { rte_bbdev_log(ERR, "k_pos (%u) is out of range %u <= value <= %u", - tb->k_pos, RTE_BBDEV_MIN_CB_SIZE, - RTE_BBDEV_MAX_CB_SIZE); + tb->k_pos, RTE_BBDEV_TURBO_MIN_CB_SIZE, + RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } - if (tb->c_neg > (RTE_BBDEV_MAX_CODE_BLOCKS - 1)) + if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1)) rte_bbdev_log(ERR, "c_neg (%u) is out of range 0 <= value <= %u", tb->c_neg, - RTE_BBDEV_MAX_CODE_BLOCKS - 1); - if (tb->c < 1 || tb->c > RTE_BBDEV_MAX_CODE_BLOCKS) { + RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1); + if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) { rte_bbdev_log(ERR, "c (%u) is out of range 1 <= value <= %u", - tb->c, RTE_BBDEV_MAX_CODE_BLOCKS); + tb->c, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS); return -1; } if (tb->cab > tb->c) { @@ -1757,12 +1758,12 @@ struct __rte_cache_aligned fpga_queue { } cb = &turbo_dec->cb_params; - if (cb->k < RTE_BBDEV_MIN_CB_SIZE - || cb->k > RTE_BBDEV_MAX_CB_SIZE) { + if (cb->k < RTE_BBDEV_TURBO_MIN_CB_SIZE + || cb->k > RTE_BBDEV_TURBO_MAX_CB_SIZE) { rte_bbdev_log(ERR, "k (%u) is out of range %u <= value <= %u", - cb->k, RTE_BBDEV_MIN_CB_SIZE, - RTE_BBDEV_MAX_CB_SIZE); + cb->k, RTE_BBDEV_TURBO_MIN_CB_SIZE, + RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } } diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c index 94aa536..374d177 100644 --- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c +++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c @@ -34,9 +34,9 @@ rte_bbdev_log(DEBUG, RTE_STR(__LINE__) ":%s() " fmt, __func__, \ ##__VA_ARGS__) -#define DEINT_INPUT_BUF_SIZE (((RTE_BBDEV_MAX_CB_SIZE >> 3) + 1) * 48) +#define DEINT_INPUT_BUF_SIZE (((RTE_BBDEV_TURBO_MAX_CB_SIZE >> 3) + 1) * 48) #define DEINT_OUTPUT_BUF_SIZE (DEINT_INPUT_BUF_SIZE * 6) -#define ADAPTER_OUTPUT_BUF_SIZE ((RTE_BBDEV_MAX_CB_SIZE + 4) * 48) +#define ADAPTER_OUTPUT_BUF_SIZE ((RTE_BBDEV_TURBO_MAX_CB_SIZE + 4) * 48) /* private data structure */ struct bbdev_private { @@ -103,7 +103,7 @@ struct turbo_sw_queue { { int32_t result = 0; - if (k < RTE_BBDEV_MIN_CB_SIZE || k > RTE_BBDEV_MAX_CB_SIZE) + if (k < RTE_BBDEV_TURBO_MIN_CB_SIZE || k > RTE_BBDEV_TURBO_MAX_CB_SIZE) return -1; if (k > 2048) { @@ -158,9 +158,9 @@ struct turbo_sw_queue { RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP | RTE_BBDEV_TURBO_EARLY_TERMINATION, .max_llr_modulus = 16, - .num_buffers_src = RTE_BBDEV_MAX_CODE_BLOCKS, + .num_buffers_src = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, .num_buffers_hard_out = - RTE_BBDEV_MAX_CODE_BLOCKS, + RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, .num_buffers_soft_out = 0, } }, @@ -172,8 +172,8 @@ struct turbo_sw_queue { RTE_BBDEV_TURBO_CRC_24A_ATTACH | RTE_BBDEV_TURBO_RATE_MATCH | RTE_BBDEV_TURBO_RV_INDEX_BYPASS, - .num_buffers_src = RTE_BBDEV_MAX_CODE_BLOCKS, - .num_buffers_dst = RTE_BBDEV_MAX_CODE_BLOCKS, + .num_buffers_src = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, + .num_buffers_dst = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, } }, #endif @@ -257,7 +257,7 @@ struct turbo_sw_queue { return -ENAMETOOLONG; } q->enc_out = rte_zmalloc_socket(name, - ((RTE_BBDEV_MAX_TB_SIZE >> 3) + 3) * + ((RTE_BBDEV_TURBO_MAX_TB_SIZE >> 3) + 3) * sizeof(*q->enc_out) * 3, RTE_CACHE_LINE_SIZE, queue_conf->socket); if (q->enc_out == NULL) { @@ -277,7 +277,7 @@ struct turbo_sw_queue { return -ENAMETOOLONG; } q->enc_in = rte_zmalloc_socket(name, - (RTE_BBDEV_MAX_CB_SIZE >> 3) * sizeof(*q->enc_in), + (RTE_BBDEV_TURBO_MAX_CB_SIZE >> 3) * sizeof(*q->enc_in), RTE_CACHE_LINE_SIZE, queue_conf->socket); if (q->enc_in == NULL) { rte_bbdev_log(ERR, @@ -295,7 +295,7 @@ struct turbo_sw_queue { return -ENAMETOOLONG; } q->ag = rte_zmalloc_socket(name, - RTE_BBDEV_MAX_CB_SIZE * 10 * sizeof(*q->ag), + RTE_BBDEV_TURBO_MAX_CB_SIZE * 10 * sizeof(*q->ag), RTE_CACHE_LINE_SIZE, queue_conf->socket); if (q->ag == NULL) { rte_bbdev_log(ERR, @@ -313,7 +313,7 @@ struct turbo_sw_queue { return -ENAMETOOLONG; } q->code_block = rte_zmalloc_socket(name, - RTE_BBDEV_MAX_CB_SIZE * sizeof(*q->code_block), + RTE_BBDEV_TURBO_MAX_CB_SIZE * sizeof(*q->code_block), RTE_CACHE_LINE_SIZE, queue_conf->socket); if (q->code_block == NULL) { rte_bbdev_log(ERR, @@ -439,9 +439,9 @@ struct turbo_sw_queue { return -1; } - if (k > RTE_BBDEV_MAX_CB_SIZE) { + if (k > RTE_BBDEV_TURBO_MAX_CB_SIZE) { rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d", - k, RTE_BBDEV_MAX_CB_SIZE); + k, RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } @@ -466,9 +466,9 @@ struct turbo_sw_queue { return -1; } - if (kw > RTE_BBDEV_MAX_KW) { + if (kw > RTE_BBDEV_TURBO_MAX_KW) { rte_bbdev_log(ERR, "Input length (%u) is too big, max: %d", - kw, RTE_BBDEV_MAX_KW); + kw, RTE_BBDEV_TURBO_MAX_KW); return -1; } @@ -773,9 +773,9 @@ struct turbo_sw_queue { /* Clear op status */ op->status = 0; - if (mbuf_total_left > RTE_BBDEV_MAX_TB_SIZE >> 3) { + if (mbuf_total_left > RTE_BBDEV_TURBO_MAX_TB_SIZE >> 3) { rte_bbdev_log(ERR, "TB size (%u) is too big, max: %d", - mbuf_total_left, RTE_BBDEV_MAX_TB_SIZE); + mbuf_total_left, RTE_BBDEV_TURBO_MAX_TB_SIZE); op->status = 1 << RTE_BBDEV_DATA_ERROR; return; } @@ -1074,7 +1074,7 @@ struct turbo_sw_queue { * where D is the size of each output from turbo encoder block * (k + 4). */ - kw = RTE_ALIGN_CEIL(k + 4, RTE_BBDEV_C_SUBBLOCK) * 3; + kw = RTE_ALIGN_CEIL(k + 4, RTE_BBDEV_TURBO_C_SUBBLOCK) * 3; process_dec_cb(q, op, c, k, kw, m_in, m_out_head, m_out, in_offset, out_offset, check_bit(dec->op_flags, diff --git a/lib/librte_bbdev/rte_bbdev_op.h b/lib/librte_bbdev/rte_bbdev_op.h index 6be53f5..f61c115 100644 --- a/lib/librte_bbdev/rte_bbdev_op.h +++ b/lib/librte_bbdev/rte_bbdev_op.h @@ -26,22 +26,22 @@ #include /* Number of columns in sub-block interleaver (36.212, section 5.1.4.1.1) */ -#define RTE_BBDEV_C_SUBBLOCK (32) +#define RTE_BBDEV_TURBO_C_SUBBLOCK (32) /* Maximum size of Transport Block (36.213, Table, Table 7.1.7.2.5-1) */ -#define RTE_BBDEV_MAX_TB_SIZE (391656) +#define RTE_BBDEV_TURBO_MAX_TB_SIZE (391656) /* Maximum size of Code Block (36.212, Table 5.1.3-3) */ -#define RTE_BBDEV_MAX_CB_SIZE (6144) +#define RTE_BBDEV_TURBO_MAX_CB_SIZE (6144) /* Minimum size of Code Block (36.212, Table 5.1.3-3) */ -#define RTE_BBDEV_MIN_CB_SIZE (40) +#define RTE_BBDEV_TURBO_MIN_CB_SIZE (40) /* Maximum size of circular buffer */ -#define RTE_BBDEV_MAX_KW (18528) +#define RTE_BBDEV_TURBO_MAX_KW (18528) /* * Maximum number of Code Blocks in Transport Block. It is calculated based on * maximum size of one Code Block and one Transport Block (considering CRC24A * and CRC24B): * (391656 + 24) / (6144 - 24) = 64 */ -#define RTE_BBDEV_MAX_CODE_BLOCKS (64) +#define RTE_BBDEV_TURBO_MAX_CODE_BLOCKS (64) /** Flags for turbo decoder operation and capability structure */ enum rte_bbdev_op_td_flag_bitmasks { @@ -133,7 +133,7 @@ struct rte_bbdev_op_data { * multiple CBs contiguously located next to each other. * A Transport Block (TB) represents a whole piece of data that is * divided into one or more CBs. Maximum number of CBs can be contained - * in one TB is defined by RTE_BBDEV_MAX_CODE_BLOCKS. + * in one TB is defined by RTE_BBDEV_TURBO_MAX_CODE_BLOCKS. * * An mbuf data structure cannot represent more than one TB. The * smallest piece of data that can be contained in one mbuf is one CB. @@ -204,7 +204,7 @@ struct rte_bbdev_op_dec_tb_params { uint16_t k_pos; /**< The number of CBs that have K- size, [0:63] */ uint8_t c_neg; - /**< The total number of CBs in the TB, [1:RTE_BBDEV_MAX_CODE_BLOCKS] */ + /**< The total number of CBs in the TB, [1:RTE_BBDEV_TURBO_MAX_CODE_BLOCKS] */ uint8_t c; /**< The number of CBs that uses Ea before switching to Eb, [0:63] */ uint8_t cab; @@ -288,7 +288,7 @@ struct rte_bbdev_op_turbo_dec { }; }; -struct rte_bbdev_op_enc_cb_params { +struct rte_bbdev_op_enc_turbo_cb_params { /**< The K size of the input CB, in bits [40:6144], as specified in * 3GPP TS 36.212. * This size is inclusive of CRC24A, regardless whether it was @@ -305,7 +305,7 @@ struct rte_bbdev_op_enc_cb_params { uint16_t ncb; }; -struct rte_bbdev_op_enc_tb_params { +struct rte_bbdev_op_enc_turbo_tb_params { /**< The K- size of the input CB, in bits [40:6144], that is in the * Turbo operation when r < C-, as in 3GPP TS 36.212. * This size is inclusive of CRC24B, regardless whether it was @@ -320,7 +320,7 @@ struct rte_bbdev_op_enc_tb_params { uint16_t k_pos; /**< The number of CBs that have K- size, [0:63] */ uint8_t c_neg; - /**< The total number of CBs in the TB, [1:RTE_BBDEV_MAX_CODE_BLOCKS] */ + /**< The total number of CBs in the TB, [1:RTE_BBDEV_TURBO_MAX_CODE_BLOCKS] */ uint8_t c; /**< The number of CBs that uses Ea before switching to Eb, [0:63] */ uint8_t cab; @@ -375,9 +375,9 @@ struct rte_bbdev_op_turbo_enc { uint8_t code_block_mode; /**< [0 - TB : 1 - CB] */ union { /**< Struct which stores Code Block specific parameters */ - struct rte_bbdev_op_enc_cb_params cb_params; + struct rte_bbdev_op_enc_turbo_cb_params cb_params; /**< Struct which stores Transport Block specific parameters */ - struct rte_bbdev_op_enc_tb_params tb_params; + struct rte_bbdev_op_enc_turbo_tb_params tb_params; }; }; From patchwork Mon Jun 24 02:52:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 55227 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F3CC31BF7C; Mon, 24 Jun 2019 04:53:16 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id EA7FF1BF6B for ; Mon, 24 Jun 2019 04:53:02 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jun 2019 19:52:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,410,1557212400"; d="scan'208";a="183991194" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga004.fm.intel.com with ESMTP; 23 Jun 2019 19:52:59 -0700 From: Nicolas Chautru To: akhil.goyal@nxp.com, dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@intel.com, amr.mokhtar@intel.com, Nicolas Chautru Date: Sun, 23 Jun 2019 19:52:50 -0700 Message-Id: <1561344776-43990-5-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> References: <1561136352-32198-2-git-send-email-nicolas.chautru@intel.com> <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 04/10] bbdev: extension of BBDEV API for 5G FEC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Extension to BBDEV operations to support 5G on top of existing 4G operations. Signed-off-by: Nicolas Chautru Acked-by: Amr Mokhtar --- lib/librte_bbdev/rte_bbdev.c | 22 +- lib/librte_bbdev/rte_bbdev.h | 135 +++++++++- lib/librte_bbdev/rte_bbdev_op.h | 567 ++++++++++++++++++++++++++++++++-------- 3 files changed, 602 insertions(+), 122 deletions(-) diff --git a/lib/librte_bbdev/rte_bbdev.c b/lib/librte_bbdev/rte_bbdev.c index a3ab5d9..7e4acfc 100644 --- a/lib/librte_bbdev/rte_bbdev.c +++ b/lib/librte_bbdev/rte_bbdev.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include @@ -215,7 +214,7 @@ struct rte_bbdev * __rte_experimental bbdev->data->dev_id = dev_id; bbdev->state = RTE_BBDEV_INITIALIZED; - ret = strlcpy(bbdev->data->name, name, RTE_BBDEV_NAME_MAX_LEN); + ret = snprintf(bbdev->data->name, RTE_BBDEV_NAME_MAX_LEN, "%s", name); if ((ret < 0) || (ret >= RTE_BBDEV_NAME_MAX_LEN)) { rte_bbdev_log(ERR, "Copying device name \"%s\" failed", name); return NULL; @@ -499,7 +498,7 @@ struct rte_bbdev * __rte_experimental if (conf->op_type == RTE_BBDEV_OP_TURBO_DEC && conf->priority > dev_info.max_ul_queue_priority) { rte_bbdev_log(ERR, - "Priority (%u) of queue %u of bdev %u must be <= %u", + "Priority (%u) of queue %u of bbdev %u must be <= %u", conf->priority, queue_id, dev_id, dev_info.max_ul_queue_priority); return -EINVAL; @@ -507,7 +506,7 @@ struct rte_bbdev * __rte_experimental if (conf->op_type == RTE_BBDEV_OP_TURBO_ENC && conf->priority > dev_info.max_dl_queue_priority) { rte_bbdev_log(ERR, - "Priority (%u) of queue %u of bdev %u must be <= %u", + "Priority (%u) of queue %u of bbdev %u must be <= %u", conf->priority, queue_id, dev_id, dev_info.max_dl_queue_priority); return -EINVAL; @@ -796,7 +795,7 @@ struct rte_bbdev * __rte_experimental memset(dev_info, 0, sizeof(*dev_info)); dev_info->dev_name = dev->data->name; dev_info->num_queues = dev->data->num_queues; - dev_info->bus = rte_bus_find_by_device(dev->device); + dev_info->device = dev->device; dev_info->socket_id = dev->data->socket_id; dev_info->started = dev->data->started; @@ -847,6 +846,12 @@ struct rte_bbdev * __rte_experimental case RTE_BBDEV_OP_TURBO_ENC: result = sizeof(struct rte_bbdev_enc_op); break; + case RTE_BBDEV_OP_LDPC_DEC: + result = sizeof(struct rte_bbdev_dec_op); + break; + case RTE_BBDEV_OP_LDPC_ENC: + result = sizeof(struct rte_bbdev_enc_op); + break; default: break; } @@ -861,11 +866,12 @@ struct rte_bbdev * __rte_experimental { enum rte_bbdev_op_type type = *(enum rte_bbdev_op_type *)arg; - if (type == RTE_BBDEV_OP_TURBO_DEC) { + if (type == RTE_BBDEV_OP_TURBO_DEC || type == RTE_BBDEV_OP_LDPC_DEC) { struct rte_bbdev_dec_op *op = element; memset(op, 0, mempool->elt_size); op->mempool = mempool; - } else if (type == RTE_BBDEV_OP_TURBO_ENC) { + } else if (type == RTE_BBDEV_OP_TURBO_ENC || + type == RTE_BBDEV_OP_LDPC_ENC) { struct rte_bbdev_enc_op *op = element; memset(op, 0, mempool->elt_size); op->mempool = mempool; @@ -1117,6 +1123,8 @@ struct rte_mempool * __rte_experimental "RTE_BBDEV_OP_NONE", "RTE_BBDEV_OP_TURBO_DEC", "RTE_BBDEV_OP_TURBO_ENC", + "RTE_BBDEV_OP_LDPC_DEC", + "RTE_BBDEV_OP_LDPC_ENC", }; if (op_type < RTE_BBDEV_OP_TYPE_COUNT) diff --git a/lib/librte_bbdev/rte_bbdev.h b/lib/librte_bbdev/rte_bbdev.h index d131692..a0e9b1a 100644 --- a/lib/librte_bbdev/rte_bbdev.h +++ b/lib/librte_bbdev/rte_bbdev.h @@ -161,7 +161,7 @@ struct rte_bbdev_queue_conf { /** * Start a device. - * This is the last step needed before enqueuing operations is possible. + * This is the last step needed before enqueueing operations is possible. * * @param dev_id * The identifier of the device. @@ -313,7 +313,7 @@ struct rte_bbdev_driver_info { struct rte_bbdev_info { int socket_id; /**< NUMA socket that device is on */ const char *dev_name; /**< Unique device name */ - const struct rte_bus *bus; /**< Bus information */ + const struct rte_device *device; /**< Device Information */ uint16_t num_queues; /**< Number of queues currently configured */ bool started; /**< Set if device is currently started */ struct rte_bbdev_driver_info drv; /**< Info from device driver */ @@ -433,6 +433,14 @@ struct __rte_cache_aligned rte_bbdev { rte_bbdev_dequeue_enc_ops_t dequeue_enc_ops; /**< Dequeue decode function */ rte_bbdev_dequeue_dec_ops_t dequeue_dec_ops; + /**< Enqueue encode function */ + rte_bbdev_enqueue_enc_ops_t enqueue_ldpc_enc_ops; + /**< Enqueue decode function */ + rte_bbdev_enqueue_dec_ops_t enqueue_ldpc_dec_ops; + /**< Dequeue encode function */ + rte_bbdev_dequeue_enc_ops_t dequeue_ldpc_enc_ops; + /**< Dequeue decode function */ + rte_bbdev_dequeue_dec_ops_t dequeue_ldpc_dec_ops; const struct rte_bbdev_ops *dev_ops; /**< Functions exported by PMD */ struct rte_bbdev_data *data; /**< Pointer to device data */ enum rte_bbdev_state state; /**< If device is currently used or not */ @@ -506,6 +514,67 @@ struct __rte_cache_aligned rte_bbdev { } /** + * Enqueue a burst of processed encode operations to a queue of the device. + * This functions only enqueues as many operations as currently possible and + * does not block until @p num_ops entries in the queue are available. + * This function does not provide any error notification to avoid the + * corresponding overhead. + * + * @param dev_id + * The identifier of the device. + * @param queue_id + * The index of the queue. + * @param ops + * Pointer array containing operations to be enqueued Must have at least + * @p num_ops entries + * @param num_ops + * The maximum number of operations to enqueue. + * + * @return + * The number of operations actually enqueued (this is the number of processed + * entries in the @p ops array). + */ +static inline uint16_t __rte_experimental +rte_bbdev_enqueue_ldpc_enc_ops(uint16_t dev_id, uint16_t queue_id, + struct rte_bbdev_enc_op **ops, uint16_t num_ops) +{ + struct rte_bbdev *dev = &rte_bbdev_devices[dev_id]; + struct rte_bbdev_queue_data *q_data = &dev->data->queues[queue_id]; + return dev->enqueue_ldpc_enc_ops(q_data, ops, num_ops); +} + +/** + * Enqueue a burst of processed decode operations to a queue of the device. + * This functions only enqueues as many operations as currently possible and + * does not block until @p num_ops entries in the queue are available. + * This function does not provide any error notification to avoid the + * corresponding overhead. + * + * @param dev_id + * The identifier of the device. + * @param queue_id + * The index of the queue. + * @param ops + * Pointer array containing operations to be enqueued Must have at least + * @p num_ops entries + * @param num_ops + * The maximum number of operations to enqueue. + * + * @return + * The number of operations actually enqueued (this is the number of processed + * entries in the @p ops array). + */ +static inline uint16_t __rte_experimental +rte_bbdev_enqueue_ldpc_dec_ops(uint16_t dev_id, uint16_t queue_id, + struct rte_bbdev_dec_op **ops, uint16_t num_ops) +{ + struct rte_bbdev *dev = &rte_bbdev_devices[dev_id]; + struct rte_bbdev_queue_data *q_data = &dev->data->queues[queue_id]; + return dev->enqueue_ldpc_dec_ops(q_data, ops, num_ops); +} + + +/** * Dequeue a burst of processed encode operations from a queue of the device. * This functions returns only the current contents of the queue, and does not * block until @ num_ops is available. @@ -566,6 +635,68 @@ struct __rte_cache_aligned rte_bbdev { return dev->dequeue_dec_ops(q_data, ops, num_ops); } + +/** + * Dequeue a burst of processed encode operations from a queue of the device. + * This functions returns only the current contents of the queue, and does not + * block until @ num_ops is available. + * This function does not provide any error notification to avoid the + * corresponding overhead. + * + * @param dev_id + * The identifier of the device. + * @param queue_id + * The index of the queue. + * @param ops + * Pointer array where operations will be dequeued to. Must have at least + * @p num_ops entries + * @param num_ops + * The maximum number of operations to dequeue. + * + * @return + * The number of operations actually dequeued (this is the number of entries + * copied into the @p ops array). + */ +static inline uint16_t __rte_experimental +rte_bbdev_dequeue_ldpc_enc_ops(uint16_t dev_id, uint16_t queue_id, + struct rte_bbdev_enc_op **ops, uint16_t num_ops) +{ + struct rte_bbdev *dev = &rte_bbdev_devices[dev_id]; + struct rte_bbdev_queue_data *q_data = &dev->data->queues[queue_id]; + return dev->dequeue_ldpc_enc_ops(q_data, ops, num_ops); +} + +/** + * Dequeue a burst of processed decode operations from a queue of the device. + * This functions returns only the current contents of the queue, and does not + * block until @ num_ops is available. + * This function does not provide any error notification to avoid the + * corresponding overhead. + * + * @param dev_id + * The identifier of the device. + * @param queue_id + * The index of the queue. + * @param ops + * Pointer array where operations will be dequeued to. Must have at least + * @p num_ops entries + * @param num_ops + * The maximum number of operations to dequeue. + * + * @return + * The number of operations actually dequeued (this is the number of entries + * copied into the @p ops array). + */ + +static inline uint16_t __rte_experimental +rte_bbdev_dequeue_ldpc_dec_ops(uint16_t dev_id, uint16_t queue_id, + struct rte_bbdev_dec_op **ops, uint16_t num_ops) +{ + struct rte_bbdev *dev = &rte_bbdev_devices[dev_id]; + struct rte_bbdev_queue_data *q_data = &dev->data->queues[queue_id]; + return dev->dequeue_ldpc_dec_ops(q_data, ops, num_ops); +} + /** Definitions of device event types */ enum rte_bbdev_event_type { RTE_BBDEV_EVENT_UNKNOWN, /**< unknown event type */ diff --git a/lib/librte_bbdev/rte_bbdev_op.h b/lib/librte_bbdev/rte_bbdev_op.h index f61c115..e80d2ce 100644 --- a/lib/librte_bbdev/rte_bbdev_op.h +++ b/lib/librte_bbdev/rte_bbdev_op.h @@ -31,57 +31,61 @@ #define RTE_BBDEV_TURBO_MAX_TB_SIZE (391656) /* Maximum size of Code Block (36.212, Table 5.1.3-3) */ #define RTE_BBDEV_TURBO_MAX_CB_SIZE (6144) +/* Maximum size of Code Block */ +#define RTE_BBDEV_LDPC_MAX_CB_SIZE (8448) /* Minimum size of Code Block (36.212, Table 5.1.3-3) */ #define RTE_BBDEV_TURBO_MIN_CB_SIZE (40) /* Maximum size of circular buffer */ #define RTE_BBDEV_TURBO_MAX_KW (18528) /* - * Maximum number of Code Blocks in Transport Block. It is calculated based on - * maximum size of one Code Block and one Transport Block (considering CRC24A - * and CRC24B): + * Turbo: Maximum number of Code Blocks in Transport Block. It is calculated + * based on maximum size of one Code Block and one Transport Block + * (considering CRC24A and CRC24B): * (391656 + 24) / (6144 - 24) = 64 */ #define RTE_BBDEV_TURBO_MAX_CODE_BLOCKS (64) +/* LDPC: Maximum number of Code Blocks in Transport Block.*/ +#define RTE_BBDEV_LDPC_MAX_CODE_BLOCKS (256) /** Flags for turbo decoder operation and capability structure */ enum rte_bbdev_op_td_flag_bitmasks { - /**< If sub block de-interleaving is to be performed. */ + /** If sub block de-interleaving is to be performed. */ RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE = (1ULL << 0), - /**< To use CRC Type 24B (otherwise use CRC Type 24A). */ + /** To use CRC Type 24B (otherwise use CRC Type 24A). */ RTE_BBDEV_TURBO_CRC_TYPE_24B = (1ULL << 1), - /**< If turbo equalization is to be performed. */ + /** If turbo equalization is to be performed. */ RTE_BBDEV_TURBO_EQUALIZER = (1ULL << 2), - /**< If set, saturate soft output to +/-127 */ + /** If set, saturate soft output to +/-127 */ RTE_BBDEV_TURBO_SOFT_OUT_SATURATE = (1ULL << 3), - /**< Set to 1 to start iteration from even, else odd; one iteration = + /** Set to 1 to start iteration from even, else odd; one iteration = * max_iteration + 0.5 */ RTE_BBDEV_TURBO_HALF_ITERATION_EVEN = (1ULL << 4), - /**< If 0, TD stops after CRC matches; else if 1, runs to end of next + /** If 0, TD stops after CRC matches; else if 1, runs to end of next * odd iteration after CRC matches */ RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH = (1ULL << 5), - /**< Set if soft output is required to be output */ + /** Set if soft output is required to be output */ RTE_BBDEV_TURBO_SOFT_OUTPUT = (1ULL << 6), - /**< Set to enable early termination mode */ + /** Set to enable early termination mode */ RTE_BBDEV_TURBO_EARLY_TERMINATION = (1ULL << 7), - /**< Set if a device supports decoder dequeue interrupts */ + /** Set if a device supports decoder dequeue interrupts */ RTE_BBDEV_TURBO_DEC_INTERRUPTS = (1ULL << 9), - /**< Set if positive LLR encoded input is supported. Positive LLR value + /** Set if positive LLR encoded input is supported. Positive LLR value * represents the level of confidence for bit '1', and vice versa for * bit '0'. * This is mutually exclusive with RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN * when used to formalize the input data format. */ RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN = (1ULL << 10), - /**< Set if negative LLR encoded input is supported. Negative LLR value + /** Set if negative LLR encoded input is supported. Negative LLR value * represents the level of confidence for bit '1', and vice versa for * bit '0'. * This is mutually exclusive with RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN * when used to formalize the input data format. */ RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN = (1ULL << 11), - /**< Set if positive LLR soft output is supported. Positive LLR value + /** Set if positive LLR soft output is supported. Positive LLR value * represents the level of confidence for bit '1', and vice versa for * bit '0'. * This is mutually exclusive with @@ -89,7 +93,7 @@ enum rte_bbdev_op_td_flag_bitmasks { * the input data format. */ RTE_BBDEV_TURBO_POS_LLR_1_BIT_SOFT_OUT = (1ULL << 12), - /**< Set if negative LLR soft output is supported. Negative LLR value + /** Set if negative LLR soft output is supported. Negative LLR value * represents the level of confidence for bit '1', and vice versa for * bit '0'. * This is mutually exclusive with @@ -97,43 +101,114 @@ enum rte_bbdev_op_td_flag_bitmasks { * input data format. */ RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT = (1ULL << 13), - /**< Set if driver supports flexible parallel MAP engine decoding. If + /** Set if driver supports flexible parallel MAP engine decoding. If * not supported, num_maps (number of MAP engines) argument is unusable. */ RTE_BBDEV_TURBO_MAP_DEC = (1ULL << 14), - /**< Set if a device supports scatter-gather functionality */ + /** Set if a device supports scatter-gather functionality */ RTE_BBDEV_TURBO_DEC_SCATTER_GATHER = (1ULL << 15), - /**< Set to keep CRC24B bits appended while decoding. Only usable when + /** Set to keep CRC24B bits appended while decoding. Only usable when * decoding Transport Blocks (code_block_mode = 0). */ RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP = (1ULL << 16) }; + /** Flags for turbo encoder operation and capability structure */ enum rte_bbdev_op_te_flag_bitmasks { - /**< Ignore rv_index and set K0 = 0 */ + /** Ignore rv_index and set K0 = 0 */ RTE_BBDEV_TURBO_RV_INDEX_BYPASS = (1ULL << 0), - /**< If rate matching is to be performed */ + /** If rate matching is to be performed */ RTE_BBDEV_TURBO_RATE_MATCH = (1ULL << 1), - /**< This bit must be set to enable CRC-24B generation */ + /** This bit must be set to enable CRC-24B generation */ RTE_BBDEV_TURBO_CRC_24B_ATTACH = (1ULL << 2), - /**< This bit must be set to enable CRC-24A generation */ + /** This bit must be set to enable CRC-24A generation */ RTE_BBDEV_TURBO_CRC_24A_ATTACH = (1ULL << 3), - /**< Set if a device supports encoder dequeue interrupts */ + /** Set if a device supports encoder dequeue interrupts */ RTE_BBDEV_TURBO_ENC_INTERRUPTS = (1ULL << 4), - /**< Set if a device supports scatter-gather functionality */ + /** Set if a device supports scatter-gather functionality */ RTE_BBDEV_TURBO_ENC_SCATTER_GATHER = (1ULL << 5) }; -/**< Data input and output buffer for BBDEV operations */ +/** Flags for LDPC decoder operation and capability structure */ +enum rte_bbdev_op_ldpcdec_flag_bitmasks { + /** Set for transport block CRC-24A checking */ + RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK = (1ULL << 0), + /** Set for code block CRC-24B checking */ + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK = (1ULL << 1), + /** Set to drop the last CRC bits decoding output */ + RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP = (1ULL << 2), + /** Set for bit-level de-interleaver bypass on Rx stream. */ + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS = (1ULL << 3), + /** Set for HARQ combined input stream enable. */ + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE = (1ULL << 4), + /** Set for HARQ combined output stream enable. */ + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE = (1ULL << 5), + /** Set for LDPC decoder bypass. + * RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE must be set. + */ + RTE_BBDEV_LDPC_DECODE_BYPASS = (1ULL << 6), + /** Set for soft-output stream enable */ + RTE_BBDEV_LDPC_SOFT_OUT_ENABLE = (1ULL << 7), + /** Set for Rate-Matching bypass on soft-out stream. */ + RTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS = (1ULL << 8), + /** Set for bit-level de-interleaver bypass on soft-output stream. */ + RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS = (1ULL << 9), + /** Set for iteration stopping on successful decode condition + * i.e. a successful syndrome check. + */ + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE = (1ULL << 10), + /** Set if a device supports decoder dequeue interrupts. */ + RTE_BBDEV_LDPC_DEC_INTERRUPTS = (1ULL << 11), + /** Set if a device supports scatter-gather functionality. */ + RTE_BBDEV_LDPC_DEC_SCATTER_GATHER = (1ULL << 12), + /** Set if a device supports input/output HARQ compression. */ + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION = (1ULL << 13), + /** Set if a device supports input LLR compression. */ + RTE_BBDEV_LDPC_LLR_COMPRESSION = (1ULL << 14), + /** Set if a device supports HARQ input from + * device's internal memory. + */ + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE = (1ULL << 15), + /** Set if a device supports HARQ output to + * device's internal memory. + */ + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE = (1ULL << 16), + /** Set if a device supports loop-back access to + * HARQ internal memory. Intended for troubleshooting. + */ + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK = (1ULL << 17) +}; + +/** Flags for LDPC encoder operation and capability structure */ +enum rte_bbdev_op_ldpcenc_flag_bitmasks { + /** Set for bit-level interleaver bypass on output stream. */ + RTE_BBDEV_LDPC_INTERLEAVER_BYPASS = (1ULL << 0), + /** If rate matching is to be performed */ + RTE_BBDEV_LDPC_RATE_MATCH = (1ULL << 1), + /** Set for transport block CRC-24A attach */ + RTE_BBDEV_LDPC_CRC_24A_ATTACH = (1ULL << 2), + /** Set for code block CRC-24B attach */ + RTE_BBDEV_LDPC_CRC_24B_ATTACH = (1ULL << 3), + /** Set for code block CRC-16 attach */ + RTE_BBDEV_LDPC_CRC_16_ATTACH = (1ULL << 4), + /** Set if a device supports encoder dequeue interrupts. */ + RTE_BBDEV_LDPC_ENC_INTERRUPTS = (1ULL << 5), + /** Set if a device supports scatter-gather functionality. */ + RTE_BBDEV_LDPC_ENC_SCATTER_GATHER = (1ULL << 6), + /** Set if a device supports concatenation of non byte aligned output */ + RTE_BBDEV_LDPC_ENC_CONCATENATION = (1ULL << 7) +}; + +/** Data input and output buffer for BBDEV operations */ struct rte_bbdev_op_data { - /**< The mbuf data structure representing the data for BBDEV operation. + /** The mbuf data structure representing the data for BBDEV operation. * * This mbuf pointer can point to one Code Block (CB) data buffer or * multiple CBs contiguously located next to each other. * A Transport Block (TB) represents a whole piece of data that is * divided into one or more CBs. Maximum number of CBs can be contained - * in one TB is defined by RTE_BBDEV_TURBO_MAX_CODE_BLOCKS. + * in one TB is defined by RTE_BBDEV_(TURBO/LDPC)_MAX_CODE_BLOCKS. * * An mbuf data structure cannot represent more than one TB. The * smallest piece of data that can be contained in one mbuf is one CB. @@ -145,8 +220,8 @@ struct rte_bbdev_op_data { * then it is capable of collecting (gathering) non-contiguous * (scattered) data from multiple locations in the memory. * This capability is reported by the capability flags: - * - RTE_BBDEV_TURBO_ENC_SCATTER_GATHER and - * - RTE_BBDEV_TURBO_DEC_SCATTER_GATHER. + * - RTE_BBDEV_(TURBO/LDPC)_ENC_SCATTER_GATHER and + * - RTE_BBDEV_(TURBO/LDPC)_DEC_SCATTER_GATHER. * Only if a BBDEV PMD supports this feature, chained mbuf data * structures are accepted. A chained mbuf can represent one * non-contiguous CB or multiple non-contiguous CBs. @@ -157,7 +232,7 @@ struct rte_bbdev_op_data { * was a chained mbuf. */ struct rte_mbuf *data; - /**< The starting point of the BBDEV (encode/decode) operation, + /** The starting point of the BBDEV (encode/decode) operation, * in bytes. * * BBDEV starts to read data past this offset. @@ -165,13 +240,13 @@ struct rte_bbdev_op_data { * segment. */ uint32_t offset; - /**< The total data length to be processed in one operation, in bytes. + /** The total data length to be processed in one operation, in bytes. * * In case the mbuf data is representing one CB, this is the length of * the CB undergoing the operation. * If it's for multiple CBs, this is the total length of those CBs * undergoing the operation. - * If it's for one TB, this is the total length of the TB under + * If it is for one TB, this is the total length of the TB under * operation. * * In case of chained mbuf, this data length includes the lengths of the @@ -180,51 +255,83 @@ struct rte_bbdev_op_data { uint32_t length; }; -struct rte_bbdev_op_dec_cb_params { - /**< The K size of the input CB, in bits [40:6144], as specified in +/** Turbo decode code block parameters */ +struct rte_bbdev_op_dec_turbo_cb_params { + /** The K size of the input CB, in bits [40:6144], as specified in * 3GPP TS 36.212. * This size is inclusive of CRC bits, regardless whether it was * pre-calculated by the application or not. */ uint16_t k; - /**< The E length of the CB rate matched LLR output, in bytes, as in + /** The E length of the CB rate matched LLR output, in bytes, as in * 3GPP TS 36.212. */ uint32_t e; }; -struct rte_bbdev_op_dec_tb_params { - /**< The K- size of the input CB, in bits [40:6144], that is in the +/** LDPC decode code block parameters */ +struct rte_bbdev_op_dec_ldpc_cb_params { + /** Rate matching output sequence length in bits or LLRs. + * [3GPP TS38.212, section 5.4.2.1] + */ + uint32_t e; +}; + +/** Turbo decode transport block parameters */ +struct rte_bbdev_op_dec_turbo_tb_params { + /** The K- size of the input CB, in bits [40:6144], that is in the * Turbo operation when r < C-, as in 3GPP TS 36.212. */ uint16_t k_neg; - /**< The K+ size of the input CB, in bits [40:6144], that is in the + /** The K+ size of the input CB, in bits [40:6144], that is in the * Turbo operation when r >= C-, as in 3GPP TS 36.212. */ uint16_t k_pos; - /**< The number of CBs that have K- size, [0:63] */ + /** The number of CBs that have K- size, [0:63] */ uint8_t c_neg; - /**< The total number of CBs in the TB, [1:RTE_BBDEV_TURBO_MAX_CODE_BLOCKS] */ + /** The total number of CBs in the TB, + * [1:RTE_BBDEV_TURBO_MAX_CODE_BLOCKS] + */ uint8_t c; - /**< The number of CBs that uses Ea before switching to Eb, [0:63] */ + /** The number of CBs that uses Ea before switching to Eb, [0:63] */ uint8_t cab; - /**< The E size of the CB rate matched output to use in the Turbo + /** The E size of the CB rate matched output to use in the Turbo * operation when r < cab */ uint32_t ea; - /**< The E size of the CB rate matched output to use in the Turbo + /** The E size of the CB rate matched output to use in the Turbo * operation when r >= cab */ uint32_t eb; - /**< The index of the first CB in the inbound mbuf data, default is 0 */ + /** The index of the first CB in the inbound mbuf data, default is 0 */ uint8_t r; }; -/**< Operation structure for Turbo decode. - * An operation can perform on one CB at a time "CB-mode". - * An operation can perform on one or multiple CBs that are logically belonging - * to one TB "TB-mode". - * The provided K size parameter of the CB is its size out coming from the +/** LDPC decode transport block parameters */ +struct rte_bbdev_op_dec_ldpc_tb_params { + /** Ea, length after rate matching in bits, r < cab. + * [3GPP TS38.212, section 5.4.2.1] + */ + uint32_t ea; + /** Eb, length after rate matching in bits, r >= cab. + * [3GPP TS38.212, section 5.4.2.1] + */ + uint32_t eb; + /** The total number of CBs in the TB or partial TB + * [1:RTE_BBDEV_LDPC_MAX_CODE_BLOCKS] + */ + uint8_t c; + /** The index of the first CB in the inbound mbuf data, default is 0 */ + uint8_t r; + /** The number of CBs that use Ea before switching to Eb, [0:63] */ + uint8_t cab; +}; + +/** Operation structure for Turbo decode. + * An operation can be performed on one CB at a time "CB-mode". + * An operation can be performed on one or multiple CBs that logically + * belong to one TB "TB-mode". + * The provided K size parameter of the CB is its size coming from the * decode operation. * CRC24A/B check is requested by the application by setting the flag * RTE_BBDEV_TURBO_CRC_TYPE_24B for CRC24B check or CRC24A otherwise. @@ -249,94 +356,192 @@ struct rte_bbdev_op_dec_tb_params { * application with enough room for the output data. */ struct rte_bbdev_op_turbo_dec { - /**< The Virtual Circular Buffer, wk, size 3*Kpi for each CB */ + /** The Virtual Circular Buffer, wk, size 3*Kpi for each CB */ struct rte_bbdev_op_data input; - /**< The hard decisions buffer for the decoded output, + /** The hard decisions buffer for the decoded output, * size K for each CB */ struct rte_bbdev_op_data hard_output; - /**< The soft LLR output buffer - optional */ + /** The soft LLR output buffer - optional */ struct rte_bbdev_op_data soft_output; - uint32_t op_flags; /**< Flags from rte_bbdev_op_td_flag_bitmasks */ - uint8_t rv_index; /**< Rv index for rate matching [0:3] */ - /**< The minimum number of iterations to perform in decoding all CBs in + /** Flags from rte_bbdev_op_td_flag_bitmasks */ + uint32_t op_flags; + + /** Rv index for rate matching [0:3] */ + uint8_t rv_index; + /** The minimum number of iterations to perform in decoding all CBs in * this operation - input */ uint8_t iter_min:4; - /**< The maximum number of iterations to perform in decoding all CBs in + /** The maximum number of iterations to perform in decoding all CBs in * this operation - input */ uint8_t iter_max:4; - /**< The maximum number of iterations that were perform in decoding all - * CBs in this decode operation - output + /** The maximum number of iterations that were performed in decoding + * all CBs in this decode operation - output */ uint8_t iter_count; - /**< 5 bit extrinsic scale (scale factor on extrinsic info) */ + /** 5 bit extrinsic scale (scale factor on extrinsic info) */ uint8_t ext_scale; - /**< Number of MAP engines to use in decode, - * must be power of 2 (or 0 to auto-select) + /** Number of MAP engines to use in decode, + * must be power of 2 (or 0 to auto-select) */ uint8_t num_maps; - uint8_t code_block_mode; /**< [0 - TB : 1 - CB] */ + /**< [0 - TB : 1 - CB] */ + uint8_t code_block_mode; union { /**< Struct which stores Code Block specific parameters */ - struct rte_bbdev_op_dec_cb_params cb_params; + struct rte_bbdev_op_dec_turbo_cb_params cb_params; /**< Struct which stores Transport Block specific parameters */ - struct rte_bbdev_op_dec_tb_params tb_params; + struct rte_bbdev_op_dec_turbo_tb_params tb_params; }; }; +/** Operation structure for LDPC decode. + * + * An operation can be performed on one CB at a time "CB-mode". + * An operation can also be performed on one or multiple CBs that logically + * belong to a TB "TB-mode" (Currently not supported). + * + * The input encoded CB data is the Virtual Circular Buffer data stream. + * + * Each byte in the input circular buffer is the LLR value of each bit of the + * original CB. + * + * Hard output is a mandatory capability that all BBDEV PMDs support. This is + * the decoded CBs (CRC24A/B is the last 24-bit in each decoded CB). + * + * Soft output is an optional capability for BBDEV PMDs. If supported, an LLR + * rate matched output is computed in the soft_output buffer structure. + * These are A Posteriori Probabilities (APP) LLR samples for coded bits. + * + * HARQ combined output is an optional capability for BBDEV PMDs. + * If supported, a LLR output is streamed to the harq_combined_output + * buffer. + * + * HARQ combined input is an optional capability for BBDEV PMDs. + * If supported, a LLR input is streamed from the harq_combined_input + * buffer. + * + * The output mbuf data structure is expected to be allocated by the + * application with enough room for the output data. + */ +struct rte_bbdev_op_ldpc_dec { + /** The Virtual Circular Buffer for this code block, one LLR + * per bit of the original CB. + */ + struct rte_bbdev_op_data input; + /** The hard decisions buffer for the decoded output, + * size K for each CB + */ + struct rte_bbdev_op_data hard_output; + /** The soft LLR output LLR stream buffer - optional */ + struct rte_bbdev_op_data soft_output; + /** The HARQ combined LLR stream input buffer - optional */ + struct rte_bbdev_op_data harq_combined_input; + /** The HARQ combined LLR stream output buffer - optional */ + struct rte_bbdev_op_data harq_combined_output; + + /** Flags from rte_bbdev_op_ldpcdec_flag_bitmasks */ + uint32_t op_flags; + + /** Rate matching redundancy version + * [3GPP TS38.212, section 5.4.2.1] + */ + uint8_t rv_index; + /** The maximum number of iterations to perform in decoding CB in + * this operation - input + */ + uint8_t iter_max; + /** The number of iterations that were performed in decoding + * CB in this decode operation - output + */ + uint8_t iter_count; + /** 1: LDPC Base graph 1, 2: LDPC Base graph 2. + * [3GPP TS38.212, section 5.2.2] + */ + uint8_t basegraph; + /** Zc, LDPC lifting size. + * [3GPP TS38.212, section 5.2.2] + */ + uint16_t z_c; + /** Ncb, length of the circular buffer in bits. + * [3GPP TS38.212, section 5.4.2.1] + */ + uint16_t n_cb; + /** Qm, modulation order {1,2,4,6,8}. + * [3GPP TS38.212, section 5.4.2.2] + */ + uint8_t q_m; + /** Number of Filler bits, n_filler = K – K’ + * [3GPP TS38.212 section 5.2.2] + */ + uint16_t n_filler; + /** [0 - TB : 1 - CB] */ + uint8_t code_block_mode; + union { + /** Struct which stores Code Block specific parameters */ + struct rte_bbdev_op_dec_ldpc_cb_params cb_params; + /** Struct which stores Transport Block specific parameters */ + struct rte_bbdev_op_dec_ldpc_tb_params tb_params; + }; +}; + +/** Turbo encode code block parameters */ struct rte_bbdev_op_enc_turbo_cb_params { - /**< The K size of the input CB, in bits [40:6144], as specified in + /** The K size of the input CB, in bits [40:6144], as specified in * 3GPP TS 36.212. * This size is inclusive of CRC24A, regardless whether it was * pre-calculated by the application or not. */ uint16_t k; - /**< The E length of the CB rate matched output, in bits, as in + /** The E length of the CB rate matched output, in bits, as in * 3GPP TS 36.212. */ uint32_t e; - /**< The Ncb soft buffer size of the CB rate matched output [K:3*Kpi], + /** The Ncb soft buffer size of the CB rate matched output [K:3*Kpi], * in bits, as specified in 3GPP TS 36.212. */ uint16_t ncb; }; +/** Turbo encode transport block parameters */ struct rte_bbdev_op_enc_turbo_tb_params { - /**< The K- size of the input CB, in bits [40:6144], that is in the + /** The K- size of the input CB, in bits [40:6144], that is in the * Turbo operation when r < C-, as in 3GPP TS 36.212. * This size is inclusive of CRC24B, regardless whether it was * pre-calculated and appended by the application or not. */ uint16_t k_neg; - /**< The K+ size of the input CB, in bits [40:6144], that is in the + /** The K+ size of the input CB, in bits [40:6144], that is in the * Turbo operation when r >= C-, as in 3GPP TS 36.212. * This size is inclusive of CRC24B, regardless whether it was * pre-calculated and appended by the application or not. */ uint16_t k_pos; - /**< The number of CBs that have K- size, [0:63] */ + /** The number of CBs that have K- size, [0:63] */ uint8_t c_neg; - /**< The total number of CBs in the TB, [1:RTE_BBDEV_TURBO_MAX_CODE_BLOCKS] */ + /** The total number of CBs in the TB, + * [1:RTE_BBDEV_TURBO_MAX_CODE_BLOCKS] + */ uint8_t c; - /**< The number of CBs that uses Ea before switching to Eb, [0:63] */ + /** The number of CBs that uses Ea before switching to Eb, [0:63] */ uint8_t cab; - /**< The E size of the CB rate matched output to use in the Turbo + /** The E size of the CB rate matched output to use in the Turbo * operation when r < cab */ uint32_t ea; - /**< The E size of the CB rate matched output to use in the Turbo + /** The E size of the CB rate matched output to use in the Turbo * operation when r >= cab */ uint32_t eb; - /**< The Ncb soft buffer size for the rate matched CB that is used in + /** The Ncb soft buffer size for the rate matched CB that is used in * the Turbo operation when r < C-, [K:3*Kpi] */ uint16_t ncb_neg; - /**< The Ncb soft buffer size for the rate matched CB that is used in + /** The Ncb soft buffer size for the rate matched CB that is used in * the Turbo operation when r >= C-, [K:3*Kpi] */ uint16_t ncb_pos; @@ -344,10 +549,38 @@ struct rte_bbdev_op_enc_turbo_tb_params { uint8_t r; }; -/**< Operation structure for Turbo encode. - * An operation can perform on one CB at a time "CB-mode". - * An operation can perform on one or multiple CBs that are logically - * belonging to one TB "TB-mode". +/** LDPC encode code block parameters */ +struct rte_bbdev_op_enc_ldpc_cb_params { + /** E, length after rate matching in bits. + * [3GPP TS38.212, section 5.4.2.1] + */ + uint32_t e; +}; + +/** LDPC encode transport block parameters */ +struct rte_bbdev_op_enc_ldpc_tb_params { + /** Ea, length after rate matching in bits, r < cab. + * [3GPP TS38.212, section 5.4.2.1] + */ + uint32_t ea; + /** Eb, length after rate matching in bits, r >= cab. + * [3GPP TS38.212, section 5.4.2.1] + */ + uint32_t eb; + /** The total number of CBs in the TB or partial TB + * [1:RTE_BBDEV_LDPC_MAX_CODE_BLOCKS] + */ + uint8_t c; + /** The index of the first CB in the inbound mbuf data, default is 0 */ + uint8_t r; + /** The number of CBs that use Ea before switching to Eb, [0:63] */ + uint8_t cab; +}; + +/** Operation structure for Turbo encode. + * An operation can be performed on one CB at a time "CB-mode". + * An operation can pbe erformd on one or multiple CBs that logically + * belong to one TB "TB-mode". * * In CB-mode, CRC24A/B is an optional operation. K size parameter is not * affected by CRC24A/B inclusion, this only affects the inbound mbuf data @@ -364,44 +597,131 @@ struct rte_bbdev_op_enc_turbo_tb_params { * application with enough room for the output data. */ struct rte_bbdev_op_turbo_enc { - /**< The input CB or TB data */ + /** The input CB or TB data */ struct rte_bbdev_op_data input; - /**< The rate matched CB or TB output buffer */ + /** The rate matched CB or TB output buffer */ struct rte_bbdev_op_data output; + /** Flags from rte_bbdev_op_te_flag_bitmasks */ + uint32_t op_flags; - uint32_t op_flags; /**< Flags from rte_bbdev_op_te_flag_bitmasks */ - uint8_t rv_index; /**< Rv index for rate matching [0:3] */ - - uint8_t code_block_mode; /**< [0 - TB : 1 - CB] */ + /** Rv index for rate matching [0:3] */ + uint8_t rv_index; + /** [0 - TB : 1 - CB] */ + uint8_t code_block_mode; union { - /**< Struct which stores Code Block specific parameters */ + /** Struct which stores Code Block specific parameters */ struct rte_bbdev_op_enc_turbo_cb_params cb_params; - /**< Struct which stores Transport Block specific parameters */ + /** Struct which stores Transport Block specific parameters */ struct rte_bbdev_op_enc_turbo_tb_params tb_params; }; }; -/**< List of the capabilities for the Turbo Decoder */ +/** Operation structure for LDPC encode. + * An operation can be performed on one CB at a time "CB-mode". + * An operation can be performed on one or multiple CBs that logically + * belong to a TB "TB-mode". + * + * The input data is the CB or TB input to the decoder. + * + * The output data is the ratematched CB or TB data, or the output after + * bit-selection if RTE_BBDEV_LDPC_INTERLEAVER_BYPASS is set. + * + * The output mbuf data structure is expected to be allocated by the + * application with enough room for the output data. + */ +struct rte_bbdev_op_ldpc_enc { + /** The input TB or CB data */ + struct rte_bbdev_op_data input; + /** The rate matched TB or CB output buffer */ + struct rte_bbdev_op_data output; + + /** Flags from rte_bbdev_op_ldpcenc_flag_bitmasks */ + uint32_t op_flags; + + /** Rate matching redundancy version */ + uint8_t rv_index; + /** 1: LDPC Base graph 1, 2: LDPC Base graph 2. + * [3GPP TS38.212, section 5.2.2] + */ + uint8_t basegraph; + /** Zc, LDPC lifting size. + * [3GPP TS38.212, section 5.2.2] + */ + uint16_t z_c; + /** Ncb, length of the circular buffer in bits. + * [3GPP TS38.212, section 5.4.2.1] + */ + uint16_t n_cb; + /** Qm, modulation order {2,4,6,8,10}. + * [3GPP TS38.212, section 5.4.2.2] + */ + uint8_t q_m; + /** Number of Filler bits, n_filler = K – K’ + * [3GPP TS38.212 section 5.2.2] + */ + uint16_t n_filler; + /** [0 - TB : 1 - CB] */ + uint8_t code_block_mode; + union { + /** Struct which stores Code Block specific parameters */ + struct rte_bbdev_op_enc_ldpc_cb_params cb_params; + /** Struct which stores Transport Block specific parameters */ + struct rte_bbdev_op_enc_ldpc_tb_params tb_params; + }; +}; + +/** List of the capabilities for the Turbo Decoder */ struct rte_bbdev_op_cap_turbo_dec { - /**< Flags from rte_bbdev_op_td_flag_bitmasks */ + /** Flags from rte_bbdev_op_td_flag_bitmasks */ uint32_t capability_flags; /** Maximal LLR absolute value. Acceptable LLR values lie in range * [-max_llr_modulus, max_llr_modulus]. */ int8_t max_llr_modulus; + /** Num input code block buffers */ uint8_t num_buffers_src; /**< Num input code block buffers */ - /**< Num hard output code block buffers */ + /** Num hard output code block buffers */ uint8_t num_buffers_hard_out; - /**< Num soft output code block buffers if supported by the driver */ + /** Num soft output code block buffers if supported by the driver */ uint8_t num_buffers_soft_out; }; -/**< List of the capabilities for the Turbo Encoder */ +/** List of the capabilities for the Turbo Encoder */ struct rte_bbdev_op_cap_turbo_enc { - /**< Flags from rte_bbdev_op_te_flag_bitmasks */ + /** Flags from rte_bbdev_op_te_flag_bitmasks */ uint32_t capability_flags; - uint8_t num_buffers_src; /**< Num input code block buffers */ - uint8_t num_buffers_dst; /**< Num output code block buffers */ + /** Num input code block buffers */ + uint8_t num_buffers_src; + /** Num output code block buffers */ + uint8_t num_buffers_dst; +}; + +/** List of the capabilities for the LDPC Decoder */ +struct rte_bbdev_op_cap_ldpc_dec { + /** Flags from rte_bbdev_op_ldpcdec_flag_bitmasks */ + uint32_t capability_flags; + /** LLR size in bits. LLR is a two’s complement number. */ + int8_t llr_size; + /** LLR numbers of decimals bit for arithmetic representation */ + int8_t llr_decimals; + /** Amount of memory for HARQ in external DDR in MB */ + uint16_t harq_memory_size; + /** Num input code block buffers */ + uint16_t num_buffers_src; + /** Num hard output code block buffers */ + uint16_t num_buffers_hard_out; + /** Num soft output code block buffers if supported by the driver */ + uint16_t num_buffers_soft_out; +}; + +/** List of the capabilities for the LDPC Encoder */ +struct rte_bbdev_op_cap_ldpc_enc { + /** Flags from rte_bbdev_op_ldpcenc_flag_bitmasks */ + uint32_t capability_flags; + /** Num input code block buffers */ + uint16_t num_buffers_src; + /** Num output code block buffers */ + uint16_t num_buffers_dst; }; /** Different operation types supported by the device */ @@ -409,40 +729,59 @@ enum rte_bbdev_op_type { RTE_BBDEV_OP_NONE, /**< Dummy operation that does nothing */ RTE_BBDEV_OP_TURBO_DEC, /**< Turbo decode */ RTE_BBDEV_OP_TURBO_ENC, /**< Turbo encode */ + RTE_BBDEV_OP_LDPC_DEC, /**< LDPC decode */ + RTE_BBDEV_OP_LDPC_ENC, /**< LDPC encode */ RTE_BBDEV_OP_TYPE_COUNT, /**< Count of different op types */ }; -/**< Bit indexes of possible errors reported through status field */ +/** Bit indexes of possible errors reported through status field */ enum { RTE_BBDEV_DRV_ERROR, RTE_BBDEV_DATA_ERROR, RTE_BBDEV_CRC_ERROR, + RTE_BBDEV_SYNDROME_ERROR }; -/**< Structure specifying a single encode operation */ +/** Structure specifying a single encode operation */ struct rte_bbdev_enc_op { - int status; /**< Status of operation that was performed */ - struct rte_mempool *mempool; /**< Mempool which op instance is in */ - void *opaque_data; /**< Opaque pointer for user data */ - /**< Contains encoder specific parameters */ - struct rte_bbdev_op_turbo_enc turbo_enc; + /**< Status of operation that was performed */ + int status; + /**< Mempool which op instance is in */ + struct rte_mempool *mempool; + /**< Opaque pointer for user data */ + void *opaque_data; + union { + /** Contains turbo decoder specific parameters */ + struct rte_bbdev_op_turbo_enc turbo_enc; + /** Contains LDPC decoder specific parameters */ + struct rte_bbdev_op_ldpc_enc ldpc_enc; + }; }; -/**< Structure specifying a single decode operation */ +/** Structure specifying a single decode operation */ struct rte_bbdev_dec_op { - int status; /**< Status of operation that was performed */ - struct rte_mempool *mempool; /**< Mempool which op instance is in */ - void *opaque_data; /**< Opaque pointer for user data */ - /**< Contains decoder specific parameters */ - struct rte_bbdev_op_turbo_dec turbo_dec; + /** Status of operation that was performed */ + int status; + /** Mempool which op instance is in */ + struct rte_mempool *mempool; + /** Opaque pointer for user data */ + void *opaque_data; + union { + /** Contains turbo decoder specific parameters */ + struct rte_bbdev_op_turbo_dec turbo_dec; + /** Contains LDPC decoder specific parameters */ + struct rte_bbdev_op_ldpc_dec ldpc_dec; + }; }; -/**< Operation capabilities supported by a device */ +/** Operation capabilities supported by a device */ struct rte_bbdev_op_cap { enum rte_bbdev_op_type type; /**< Type of operation */ union { struct rte_bbdev_op_cap_turbo_dec turbo_dec; struct rte_bbdev_op_cap_turbo_enc turbo_enc; + struct rte_bbdev_op_cap_ldpc_dec ldpc_dec; + struct rte_bbdev_op_cap_ldpc_enc ldpc_enc; } cap; /**< Operation-type specific capabilities */ }; @@ -513,7 +852,8 @@ struct rte_mempool * __rte_experimental /* Check type */ priv = (struct rte_bbdev_op_pool_private *) rte_mempool_get_priv(mempool); - if (unlikely(priv->type != RTE_BBDEV_OP_TURBO_ENC)) + if (unlikely((priv->type != RTE_BBDEV_OP_TURBO_ENC) && + (priv->type != RTE_BBDEV_OP_LDPC_ENC))) return -EINVAL; /* Get elements */ @@ -548,7 +888,8 @@ struct rte_mempool * __rte_experimental /* Check type */ priv = (struct rte_bbdev_op_pool_private *) rte_mempool_get_priv(mempool); - if (unlikely(priv->type != RTE_BBDEV_OP_TURBO_DEC)) + if (unlikely((priv->type != RTE_BBDEV_OP_TURBO_DEC) && + (priv->type != RTE_BBDEV_OP_LDPC_DEC))) return -EINVAL; /* Get elements */ From patchwork Mon Jun 24 02:52:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 55228 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 760AB1BF83; Mon, 24 Jun 2019 04:53:19 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 01BE01BF0A for ; Mon, 24 Jun 2019 04:53:02 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jun 2019 19:52:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,410,1557212400"; d="scan'208";a="183991197" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga004.fm.intel.com with ESMTP; 23 Jun 2019 19:52:59 -0700 From: Nicolas Chautru To: akhil.goyal@nxp.com, dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@intel.com, amr.mokhtar@intel.com, Nicolas Chautru Date: Sun, 23 Jun 2019 19:52:51 -0700 Message-Id: <1561344776-43990-6-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> References: <1561136352-32198-2-git-send-email-nicolas.chautru@intel.com> <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v4 05/10] docs/guides: updating bbdev API for 5GNR operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The documentation captures the related change in BBDEV API to support 5GNR encode/decode operations. Signed-off-by: Nicolas Chautru Acked-by: Amr Mokhtar --- doc/guides/prog_guide/bbdev.rst | 505 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 458 insertions(+), 47 deletions(-) diff --git a/doc/guides/prog_guide/bbdev.rst b/doc/guides/prog_guide/bbdev.rst index 038bc6e..3858daf 100644 --- a/doc/guides/prog_guide/bbdev.rst +++ b/doc/guides/prog_guide/bbdev.rst @@ -166,9 +166,9 @@ stopped individually. Logical Cores, Memory and Queues Relationships ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The bbdev device Library as the Poll Mode Driver library support NUMA for when -a processor's logical cores and interfaces utilize its local memory. Therefore -baseband operations, the mbuf being operated on should be allocated from memory +The bbdev poll mode device driver library supports NUMA architecture, in which +a processor's logical cores and interfaces utilize it's local memory. Therefore +with baseband operations, the mbuf being operated on should be allocated from memory pools created in the local memory. The buffers should, if possible, remain on the local processor to obtain the best performance results and buffer descriptors should be populated with mbufs allocated from a mempool allocated @@ -220,9 +220,9 @@ relation to Turbo Encoding and Decoding operations. RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP | RTE_BBDEV_TURBO_EARLY_TERMINATION, .max_llr_modulus = 16, - .num_buffers_src = RTE_BBDEV_MAX_CODE_BLOCKS, + .num_buffers_src = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, .num_buffers_hard_out = - RTE_BBDEV_MAX_CODE_BLOCKS, + RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, .num_buffers_soft_out = 0, } }, @@ -234,8 +234,8 @@ relation to Turbo Encoding and Decoding operations. RTE_BBDEV_TURBO_CRC_24A_ATTACH | RTE_BBDEV_TURBO_RATE_MATCH | RTE_BBDEV_TURBO_RV_INDEX_BYPASS, - .num_buffers_src = RTE_BBDEV_MAX_CODE_BLOCKS, - .num_buffers_dst = RTE_BBDEV_MAX_CODE_BLOCKS, + .num_buffers_src = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, + .num_buffers_dst = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, } }, RTE_BBDEV_END_OF_CAPABILITIES_LIST() @@ -266,12 +266,13 @@ information: struct rte_bbdev_info { int socket_id; const char *dev_name; - const struct rte_bus *bus; + const struct rte_device *device; uint16_t num_queues; bool started; struct rte_bbdev_driver_info drv; }; + Operation Processing -------------------- @@ -335,14 +336,20 @@ processed on a particular bbdev device poll mode driver. int status; struct rte_mempool *mempool; void *opaque_data; - struct rte_bbdev_op_turbo_enc turbo_enc; + union { + struct rte_bbdev_op_turbo_enc turbo_enc; + struct rte_bbdev_op_ldpc_enc ldpc_enc; + } }; struct rte_bbdev_dec_op { int status; struct rte_mempool *mempool; void *opaque_data; - struct rte_bbdev_op_turbo_dec turbo_dec; + union { + struct rte_bbdev_op_turbo_dec turbo_enc; + struct rte_bbdev_op_ldpc_dec ldpc_enc; + } }; The operation structure by itself defines the operation type. It includes an @@ -399,19 +406,31 @@ BBDEV Inbound/Outbound Memory ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The bbdev operation structure contains all the mutable data relating to -performing Turbo coding on a referenced mbuf data buffer. It is used for either +performing Turbo and LDPC coding on a referenced mbuf data buffer. It is used for either encode or decode operations. -Turbo Encode operation accepts one input and one output. -Turbo Decode operation accepts one input and two outputs, called *hard-decision* -and *soft-decision* outputs. *Soft-decision* output is optional. + +.. csv-table:: Operation I/O + :header: "FEC", "In", "Out" + :widths: 20, 30, 30 + + "Turbo Encode", "input", "output" + "Turbo Decode", "input", "hard output" + " ", " ", "soft output (optional)" + "LDPC Encode", "input", "output" + "LDPC Decode", "input", "hard output" + "", "HQ combine (optional)", "HQ combine (optional)" + " ", "", "soft output (optional)" + It is expected that the application provides input and output mbuf pointers -allocated and ready to use. The baseband framework supports turbo coding on -Code Blocks (CB) and Transport Blocks (TB). +allocated and ready to use. + +The baseband framework supports FEC coding on Code Blocks (CB) and +Transport Blocks (TB). For the output buffer(s), the application is required to provide an allocated -and free mbuf, so that bbdev write back the resulting output. +and free mbuf, to which the resulting output will be written. The support of split "scattered" buffers is a driver-specific feature, so it is reported individually by the supporting driver as a capability. @@ -436,26 +455,26 @@ This structure has three elements: This mbuf pointer can point to one Code Block (CB) data buffer or multiple CBs contiguously located next to each other. A Transport Block (TB) represents a whole piece of data that is divided into one or more CBs. Maximum number of - CBs can be contained in one TB is defined by ``RTE_BBDEV_MAX_CODE_BLOCKS``. + CBs can be contained in one TB is defined by + ``RTE_BBDEV_(TURBO/LDPC)MAX_CODE_BLOCKS``. An mbuf data structure cannot represent more than one TB. The smallest piece of data that can be contained in one mbuf is one CB. An mbuf can include one contiguous CB, subset of contiguous CBs that are - belonging to one TB, or all contiguous CBs that are belonging to one TB. + belonging to one TB, or all contiguous CBs that belong to one TB. If a BBDEV PMD supports the extended capability "Scatter-Gather", then it is capable of collecting (gathering) non-contiguous (scattered) data from multiple locations in the memory. This capability is reported by the capability flags: - - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER``, and + - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER``, ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER``, - - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER``. + - ``RTE_BBDEV_LDPC_ENC_SCATTER_GATHER``, ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER``. - Only if a BBDEV PMD supports this feature, chained mbuf data structures are - accepted. A chained mbuf can represent one non-contiguous CB or multiple - non-contiguous CBs. - The first mbuf segment in the given chained mbuf represents the first piece + Chained mbuf data structures are only accepted if a BBDEV PMD supports this + feature. A chained mbuf can represent one non-contiguous CB or multiple non-contiguous + CBs. The first mbuf segment in the given chained mbuf represents the first piece of the CB. Offset is only applicable to the first segment. ``length`` is the total length of the CB. @@ -506,14 +525,22 @@ BBDEV Turbo Encode Operation }; }; -The Turbo encode structure is composed of the ``input`` and ``output`` mbuf -data pointers. The provided mbuf pointer of ``input`` needs to be big enough to -stretch for extra CRC trailers. +The Turbo encode structure includes the ``input`` and ``output`` mbuf +data pointers. The provided mbuf pointer of ``input`` needs to be big +enough to stretch for extra CRC trailers. -``op_flags`` parameter holds all operation related flags, like whether CRC24A is -included by the application or not. +.. csv-table:: **struct rte_bbdev_op_turbo_enc** parameters + :header: "Parameter", "Description" + :widths: 10, 30 + + "input","input CB or TB data" + "output","rate matched CB or TB output buffer" + "op_flags","bitmask of all active operation capabilities" + "rv_index","redundancy version index [0..3]" + "code_block_mode","code block or transport block mode" + "cb_params", "code block specific parameters (code block mode only)" + "tb_params", "transport block specific parameters (transport block mode only)" -``code_block_mode`` flag identifies the mode in which bbdev is operating in. The encode interface works on both the code block (CB) and the transport block (TB). An operation executes in "CB-mode" when the CB is standalone. While @@ -525,21 +552,21 @@ are being enqueued. **NOTE:** It is assumed that all enqueued ops in one ``rte_bbdev_enqueue_enc_ops()`` call belong to one mode, either CB-mode or TB-mode. -In case that the CB is smaller than Z (6144 bits), then effectively the TB = CB. +In case that the TB is smaller than Z (6144 bits), then effectively the TB = CB. CRC24A is appended to the tail of the CB. The application is responsible for calculating and appending CRC24A before calling BBDEV in case that the underlying driver does not support CRC24A generation. In CB-mode, CRC24A/B is an optional operation. -The input ``k`` is the size of the CB (this maps to K as described in 3GPP TS -36.212 section 5.1.2), this size is inclusive of CRC24A/B. +The CB parameter ``k`` is the size of the CB (this maps to K as described +in 3GPP TS 36.212 section 5.1.2), this size is inclusive of CRC24A/B. The ``length`` is inclusive of CRC24A/B and equals to ``k`` in this case. Not all BBDEV PMDs are capable of CRC24A/B calculation. Flags ``RTE_BBDEV_TURBO_CRC_24A_ATTACH`` and ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` informs the application with relevant capability. These flags can be set in the -``op_flags`` parameter to indicate BBDEV to calculate and append CRC24A to CB -before going forward with Turbo encoding. +``op_flags`` parameter to indicate to BBDEV to calculate and append CRC24A/B +to CB before going forward with Turbo encoding. Output format of the CB encode will have the encoded CB in ``e`` size output (this maps to E described in 3GPP TS 36.212 section 5.1.4.1.2). The output mbuf @@ -600,13 +627,26 @@ BBDEV Turbo Decode Operation }; }; -The Turbo decode structure is composed of the ``input`` and ``output`` mbuf -data pointers. - -``op_flags`` parameter holds all operation related flags, like whether CRC24B is -retained or not. - -``code_block_mode`` flag identifies the mode in which bbdev is operating in. +The Turbo decode structure includes the ``input``, ``hard_output`` and +optionally the ``soft_output`` mbuf data pointers. + +.. csv-table:: **struct rte_bbdev_op_turbo_dec** parameters + :header: "Parameter", "Description" + :widths: 10, 30 + + "input","virtual circular buffer, wk, size 3*Kpi for each CB" + "hard output","hard decisions buffer, decoded output, size K for each CB" + "soft output","soft LLR output buffer (optional)" + "op_flags","bitmask of all active operation capabilities" + "rv_index","redundancy version index [0..3]" + "iter_max","maximum number of iterations to perofrm in decode all CBs" + "iter_min","minimum number of iterations to perform in decoding all CBs" + "iter_count","number of iterations to performed in decoding all CBs" + "ext_scale","scale factor on extrinsic info (5 bits)" + "num_maps","number of MAP engines to use in decode" + "code_block_mode","code block or transport block mode" + "cb_params", "code block specific parameters (code block mode only)" + "tb_params", "transport block specific parameters (transport block mode only)" Similarly, the decode interface works on both the code block (CB) and the transport block (TB). An operation executes in "CB-mode" when the CB is @@ -618,7 +658,8 @@ to a bigger TB are being enqueued. **NOTE:** It is assumed that all enqueued ops in one ``rte_bbdev_enqueue_dec_ops()`` call belong to one mode, either CB-mode or TB-mode. -The input ``k`` is the size of the decoded CB (this maps to K as described in + +The CB parameter ``k`` is the size of the decoded CB (this maps to K as described in 3GPP TS 36.212 section 5.1.2), this size is inclusive of CRC24A/B. The ``length`` is inclusive of CRC24A/B and equals to ``k`` in this case. @@ -638,9 +679,9 @@ Soft output is an optional capability for BBDEV PMDs. Setting flag CRC24B at the end of each CB. This might be useful for the application in debug mode. An LLR rate matched output is computed in the ``soft_output`` buffer structure -for the given ``e`` size (this maps to E described in 3GPP TS 36.212 section -5.1.4.1.2). The output mbuf buffer size needs to be big enough to hold the -encoded buffer of size ``e``. +for the given CB parameter ``e`` size (this maps to E described in +3GPP TS 36.212 section 5.1.4.1.2). The output mbuf buffer size needs to be big +enough to hold the encoded buffer of size ``e``. The first CB Virtual Circular Buffer (VCB) index is given by ``r`` but the number of the remaining CB VCBs is calculated automatically by BBDEV before @@ -669,6 +710,376 @@ TB-mode. CB-mode is a reduced version, where only one CB exists: Turbo decoding of Code Blocks in mbuf structure +BBDEV LDPC Encode Operation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The operation flags that can be set for each LDPC encode operation are +given below. + + **NOTE:** The actual operation flags that may be used with a specific + BBDEV PMD are dependent on the driver capabilities as reported via + ``rte_bbdev_info_get()``, and may be a subset of those below. + ++--------------------------------------------------------------------+ +|Description of LDPC encode capability flags | ++====================================================================+ +|RTE_BBDEV_LDPC_INTERLEAVER_BYPASS | +| Set to bypass bit-level interleaver on output stream | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_RATE_MATCH | +| Set to enabling the RATE_MATCHING processing | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_CRC_24A_ATTACH | +| Set to attach transport block CRC-24A | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_CRC_24B_ATTACH | +| Set to attach code block CRC-24B | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_CRC_16_ATTACH | +| Set to attach code block CRC-16 | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_ENC_INTERRUPTS | +| Set if a device supports encoder dequeue interrupts | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_ENC_SCATTER_GATHER | +| Set if a device supports scatter-gather functionality | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_ENC_CONCATENATION | +| Set if a device supports concatenation of non byte aligned output | ++--------------------------------------------------------------------+ + +The structure passed for each LDPC encode operation is given below, +with the operation flags forming a bitmask in the ``op_flags`` field. + +.. code-block:: c + + struct rte_bbdev_op_ldpc_enc { + + struct rte_bbdev_op_data input; + struct rte_bbdev_op_data output; + + uint32_t op_flags; + uint8_t rv_index; + uint8_t basegraph; + uint16_t z_c; + uint16_t n_cb; + uint8_t q_m; + uint16_t n_filler; + uint8_t code_block_mode; + union { + struct rte_bbdev_op_enc_ldpc_cb_params cb_params; + struct rte_bbdev_op_enc_ldpc_tb_params tb_params; + }; + }; + +The LDPC encode parameters are set out in the table below. + ++----------------+--------------------------------------------------------------------+ +|Parameter |Description | ++================+====================================================================+ +|input |input CB or TB data | ++----------------+--------------------------------------------------------------------+ +|output |rate matched CB or TB output buffer | ++----------------+--------------------------------------------------------------------+ +|op_flags |bitmask of all active operation capabilities | ++----------------+--------------------------------------------------------------------+ +|rv_index |redundancy version index [0..3] | ++----------------+--------------------------------------------------------------------+ +|basegraph |Basegraph 1 or 2 | ++----------------+--------------------------------------------------------------------+ +|z_c |Zc, LDPC lifting size | ++----------------+--------------------------------------------------------------------+ +|n_cb |Ncb, length of the circular buffer in bits. | ++----------------+--------------------------------------------------------------------+ +|q_m |Qm, modulation order {2,4,6,8,10} | ++----------------+--------------------------------------------------------------------+ +|n_filler |number of filler bits | ++----------------+--------------------------------------------------------------------+ +|code_block_mode |code block or transport block mode | ++----------------+--------------------------------------------------------------------+ +|op_flags |bitmask of all active operation capabilities | ++----------------+--------------------------------------------------------------------+ +|**cb_params** |code block specific parameters (code block mode only) | ++----------------+------------+-------------------------------------------------------+ +| |e |E, length of the rate matched output sequence in bits | ++----------------+------------+-------------------------------------------------------+ +|**tb_params** | transport block specific parameters (transport block mode only) | ++----------------+------------+-------------------------------------------------------+ +| |c |number of CBs in the TB or partial TB | ++----------------+------------+-------------------------------------------------------+ +| |r |index of the first CB in the inbound mbuf data | ++----------------+------------+-------------------------------------------------------+ ++ +c_ab +number of CBs that use Ea before switching to Eb | ++----------------+------------+-------------------------------------------------------+ +| |ea |Ea, length of the RM output sequence in bits, r < cab | ++----------------+------------+-------------------------------------------------------+ +| |eb |Eb, length of the RM output sequence in bits, r >= cab | ++----------------+------------+-------------------------------------------------------+ + +The mbuf input ``input`` is mandatory for all BBDEV PMDs and is the +incoming code block or transport block data. + +The mbuf output ``output`` is mandatory and is the encoded CB(s). In +CB-mode ut contains the encoded CB of size ``e`` (E in 3GPP TS 38.212 +section 6.2.5). In TB-mode it contains multiple contiguous encoded CBs +of size ``ea`` or ``eb``. +The ``output`` buffer is allocated by the application with enough room +for the output data. + +The encode interface works on both a code block (CB) and a transport +block (TB) basis. + + **NOTE:** All enqueued ops in one ``rte_bbdev_enqueue_enc_ops()`` + call belong to one mode, either CB-mode or TB-mode. + +The valid modes of operation are: + +* CB-mode: one CB (attach CRC24B if required) +* CB-mode: one CB making up one TB (attach CRC24A if required) +* TB-mode: one or more CB of a partial TB (attach CRC24B(s) if required) +* TB-mode: one or more CB of a complete TB (attach CRC24AB(s) if required) + +In CB-mode if ``RTE_BBDEV_LDPC_CRC_24A_ATTACH`` is set then CRC24A +is appended to the CB. If ``RTE_BBDEV_LDPC_CRC_24A_ATTACH`` is not +set the application is responsible for calculating and appending CRC24A +before calling BBDEV. The input data mbuf ``length`` is inclusive of +CRC24A/B where present and is equal to the code block size ``K``. + +In TB-mode, CRC24A is assumed to be pre-calculated and appended to the +inbound TB data buffer, unless the ``RTE_BBDEV_LDPC_CRC_24A_ATTACH`` +flag is set when it is the responsibility of BBDEV. The input data +mbuf ``length`` is total size of the CBs inclusive of any CRC24A and +CRC24B in the case they were appended by the application. + +Not all BBDEV PMDs may be capable of CRC24A/B calculation. Flags +``RTE_BBDEV_LDPC_CRC_24A_ATTACH`` and ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` +inform the application of the relevant capability. These flags can be set +in the ``op_flags`` parameter to indicate BBDEV to calculate and append +CRC24A to CB before going forward with LDPC encoding. + +The difference between the partial and full-size TB is that BBDEV needs +the index of the first CB in this group and the number of CBs in the group. +The first CB index is given by ``r`` but the number of the CBs is +calculated by BBDEV before signalling to the driver. + +The number of CBs in the group should not be confused with ``c``, the +total number of CBs in the full TB (``C`` as per 3GPP TS 38.212 section 5.2.2) + +Figure 13.1 above showing the Turbo encoding of CBs using BBDEV +interface in TB-mode is also valid for LDPC encode. + +BBDEV LDPC Decode Operation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The operation flags that can be set for each LDPC decode operation are +given below. + + **NOTE:** The actual operation flags that may be used with a specific + BBDEV PMD are dependent on the driver capabilities as reported via + ``rte_bbdev_info_get()``, and may be a subset of those below. + ++--------------------------------------------------------------------+ +|Description of LDPC decode capability flags | ++====================================================================+ +|RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK | +| Set for transport block CRC-24A checking | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK | +| Set for code block CRC-24B checking | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP | +| Set to drop the last CRC bits decoding output | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS | +| Set for bit-level de-interleaver bypass on input stream | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE | +| Set for HARQ combined input stream enable | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE | +| Set for HARQ combined output stream enable | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_DECODE_BYPASS | +| Set for LDPC decoder bypass | +| | +| RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE must be set | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_DECODE_SOFT_OUT | +| Set for soft-output stream enable | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS | +| Set for Rate-Matching bypass on soft-out stream | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS | +| Set for bit-level de-interleaver bypass on soft-output stream | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE | +| Set for iteration stopping on successful decode condition enable | +| | +| Where a successful decode is a successful syndrome check | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_DEC_INTERRUPTS | +| Set if a device supports decoder dequeue interrupts | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_DEC_SCATTER_GATHER | +| Set if a device supports scatter-gather functionality | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION | +| Set if a device supports input/output HARQ compression | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_LLR_COMPRESSION | +| Set if a device supports input LLR compression | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE | +| Set if a device supports HARQ input to device's internal memory | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE | +| Set if a device supports HARQ output to device's internal memory | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK | +| Set if a device supports loopback access to HARQ internal memory | ++--------------------------------------------------------------------+ + +The structure passed for each LDPC decode operation is given below, +with the operation flags forming a bitmask in the ``op_flags`` field. + +.. code-block:: c + + + struct rte_bbdev_op_ldpc_dec { + + struct rte_bbdev_op_data input; + struct rte_bbdev_op_data hard_output; + struct rte_bbdev_op_data soft_output; + struct rte_bbdev_op_data harq_combined_input; + struct rte_bbdev_op_data harq_combined_output; + + uint32_t op_flags; + uint8_t rv_index; + uint8_t basegraph; + uint16_t z_c; + uint16_t n_cb; + uint8_t q_m; + uint16_t n_filler; + uint8_t iter_max; + uint8_t iter_count; + uint8_t code_block_mode; + union { + struct rte_bbdev_op_dec_ldpc_cb_params cb_params; + struct rte_bbdev_op_dec_ldpc_tb_params tb_params; + }; + }; + + +The LDPC decode parameters are set out in the table below. + ++----------------+--------------------------------------------------------------------+ +|Parameter |Description | ++================+====================================================================+ +|input |input CB or TB data | ++----------------+--------------------------------------------------------------------+ +|hard_output |hard decisions buffer, decoded output | ++----------------+--------------------------------------------------------------------+ +|soft_output |soft LLR output buffer (optional) | ++----------------+--------------------------------------------------------------------+ +|harq_comb_input |HARQ combined input buffer (optional) | ++----------------+--------------------------------------------------------------------+ +|harq_comb_output|HARQ combined output buffer (optional) | ++----------------+--------------------------------------------------------------------+ +|op_flags |bitmask of all active operation capabilities | ++----------------+--------------------------------------------------------------------+ +|rv_index |redundancy version index [0..3] | ++----------------+--------------------------------------------------------------------+ +|basegraph |Basegraph 1 or 2 | ++----------------+--------------------------------------------------------------------+ +|z_c |Zc, LDPC lifting size | ++----------------+--------------------------------------------------------------------+ +|n_cb |Ncb, length of the circular buffer in bits. | ++----------------+--------------------------------------------------------------------+ +|q_m |Qm, modulation order {1,2,4,6,8} from pi/2-BPSK to 256QAM | ++----------------+--------------------------------------------------------------------+ +|n_filler |number of filler bits | ++----------------+--------------------------------------------------------------------+ +|iter_max |maximum number of iterations to perform in decode all CBs | ++----------------+--------------------------------------------------------------------+ +|iter_count |number of iterations performed in decoding all CBs | ++----------------+--------------------------------------------------------------------+ +|code_block_mode |code block or transport block mode | ++----------------+--------------------------------------------------------------------+ +|op_flags |bitmask of all active operation capabilities | ++----------------+--------------------------------------------------------------------+ +|**cb_params** |code block specific parameters (code block mode only) | ++----------------+------------+-------------------------------------------------------+ +| |e |E, length of the rate matched output sequence in bits | ++----------------+------------+-------------------------------------------------------+ +|**tb_params** | transport block specific parameters (transport block mode only) | ++----------------+------------+-------------------------------------------------------+ +| |c |number of CBs in the TB or partial TB | ++----------------+------------+-------------------------------------------------------+ +| |r |index of the first CB in the inbound mbuf data | ++----------------+------------+-------------------------------------------------------+ +| |c_ab |number of CBs that use Ea before switching to Eb | ++----------------+------------+-------------------------------------------------------+ +| |ea |Ea, length of the RM output sequence in bits, r < cab | ++----------------+------------+-------------------------------------------------------+ +| |eb |Eb, length of the RM output sequence in bits r >= cab | ++----------------+------------+-------------------------------------------------------+ + +The mbuf input ``input`` encoded CB data is mandatory for all BBDEV PMDs +and is the Virtual Circular Buffer data stream with null padding. +Each byte in the input circular buffer is the LLR value of each bit of +the original CB. + +The mbuf output ``hard_output`` is mandatory and is the decoded CBs size +K (CRC24A/B is the last 24-bit in each decoded CB). + +The mbuf output ``soft_output`` is optional and is an LLR rate matched +output of size ``e`` (this is ``E`` as per 3GPP TS 38.212 section 6.2.5). + +The mbuf input ``harq_combine_input`` is optional and is a buffer with +the input to the HARQ combination function of the device. If the +capability RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE is set +then the HARQ is stored in memory internal to the device and not visible +to BBDEV. + +The mbuf output ``harq_combine_output`` is optional and is a buffer for +the output of the HARQ combination function of the device. If the +capability RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE is set +then the HARQ is stored in memory internal to the device and not visible +to BBDEV. + +The output mbuf data structures are expected to be allocated by the +application with enough room for the output data. + +As with the LDPC encode, the decode interface works on both a code block +(CB) and a transport block (TB) basis. + + **NOTE:** All enqueued ops in one ``rte_bbdev_enqueue_dec_ops()`` + call belong to one mode, either CB-mode or TB-mode. + +The valid modes of operation are: + +* CB-mode: one CB (check CRC24B if required) +* CB-mode: one CB making up one TB (check CRC24A if required) +* TB-mode: one or more CB making up a partial TB (check CRC24B(s) if required) +* TB-mode: one or more CB making up a complete TB (check CRC24B(s) if required) + +The mbuf ``length`` is inclusive of CRC24A/B where present and is equal +the code block size ``K``. + +The first CB Virtual Circular Buffer (VCB) index is given by ``r`` but the +the number of the remaining CB VCBs is calculated automatically by BBDEV +and passed down to the driver. + +The number of remaining CB VCBs should not be confused with ``c``, the +total number of CBs in the full TB (``C`` as per 3GPP TS 38.212 section 5.2.2) + +The ``length`` is total size of the CBs inclusive of any CRC24A and CRC24B in +case they were appended by the application. + +Figure 13.2 above showing the Turbo decoding of CBs using BBDEV +interface in TB-mode is also valid for LDPC decode. + Sample code ----------- From patchwork Mon Jun 24 02:52:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 55229 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6AD001BF8B; Mon, 24 Jun 2019 04:53:22 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 7256C1BEAD for ; Mon, 24 Jun 2019 04:53:03 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jun 2019 19:52:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,410,1557212400"; d="scan'208";a="183991199" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga004.fm.intel.com with ESMTP; 23 Jun 2019 19:52:59 -0700 From: Nicolas Chautru To: akhil.goyal@nxp.com, dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@intel.com, amr.mokhtar@intel.com, Nicolas Chautru Date: Sun, 23 Jun 2019 19:52:52 -0700 Message-Id: <1561344776-43990-7-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> References: <1561136352-32198-2-git-send-email-nicolas.chautru@intel.com> <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v4 06/10] baseband/turbo_sw: extension of turbosw PMD for 5G X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Implementation still based on Intel SDK libraries optimized for AVX512 instructions set and 5GNR. This can be also build for AVX2 for 4G capability or without SDK dependency for maintenance. Signed-off-by: Nicolas Chautru Acked-by: Amr Mokhtar --- config/common_base | 1 + drivers/baseband/turbo_sw/Makefile | 15 +- drivers/baseband/turbo_sw/bbdev_turbo_software.c | 686 ++++++++++++++++++++++- drivers/baseband/turbo_sw/meson.build | 10 + mk/rte.app.mk | 8 +- 5 files changed, 707 insertions(+), 13 deletions(-) diff --git a/config/common_base b/config/common_base index cc13025..67e1cc6 100644 --- a/config/common_base +++ b/config/common_base @@ -530,6 +530,7 @@ CONFIG_RTE_LIBRTE_BBDEV_DEBUG=n CONFIG_RTE_BBDEV_MAX_DEVS=128 CONFIG_RTE_BBDEV_OFFLOAD_COST=y CONFIG_RTE_BBDEV_SDK_AVX2=n +CONFIG_RTE_BBDEV_SDK_AVX512=n # # Compile PMD for NULL bbdev device diff --git a/drivers/baseband/turbo_sw/Makefile b/drivers/baseband/turbo_sw/Makefile index 414d0d9..4aa05d2 100644 --- a/drivers/baseband/turbo_sw/Makefile +++ b/drivers/baseband/turbo_sw/Makefile @@ -3,7 +3,6 @@ include $(RTE_SDK)/mk/rte.vars.mk - # library name LIB = librte_pmd_bbdev_turbo_sw.a @@ -34,6 +33,20 @@ LDLIBS += -L$(FLEXRAN_SDK)/lib_common -lcommon LDLIBS += -lstdc++ -lirc -limf -lipps -lsvml endif +ifeq ($(CONFIG_RTE_BBDEV_SDK_AVX512),y) +ifeq ($(CONFIG_RTE_BBDEV_SDK_AVX2),n) +$(error "CONFIG_RTE_BBDEV_SDK_AVX512 requires CONFIG_RTE_BBDEV_SDK_AVX2 set") +endif +CFLAGS += -I$(FLEXRAN_SDK)/lib_ldpc_encoder_5gnr +CFLAGS += -I$(FLEXRAN_SDK)/lib_ldpc_decoder_5gnr +CFLAGS += -I$(FLEXRAN_SDK)/lib_LDPC_ratematch_5gnr +CFLAGS += -I$(FLEXRAN_SDK)/lib_rate_dematching_5gnr +LDLIBS += -L$(FLEXRAN_SDK)/lib_ldpc_encoder_5gnr -lldpc_encoder_5gnr +LDLIBS += -L$(FLEXRAN_SDK)/lib_ldpc_decoder_5gnr -lldpc_decoder_5gnr +LDLIBS += -L$(FLEXRAN_SDK)/lib_LDPC_ratematch_5gnr -lLDPC_ratematch_5gnr +LDLIBS += -L$(FLEXRAN_SDK)/lib_rate_dematching_5gnr -lrate_dematching_5gnr +endif + # library version LIBABIVER := 1 diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c index 374d177..2f06369 100644 --- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c +++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c @@ -14,11 +14,24 @@ #include #include +#include +#include +#include + #ifdef RTE_BBDEV_SDK_AVX2 +#include +#include #include #include #include #endif +#ifdef RTE_BBDEV_SDK_AVX512 +#include +#include +#include +#include +#include +#endif #define DRIVER_NAME baseband_turbo_sw @@ -84,6 +97,7 @@ struct turbo_sw_queue { enum rte_bbdev_op_type type; } __rte_cache_aligned; + #ifdef RTE_BBDEV_SDK_AVX2 static inline char * mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len) @@ -158,7 +172,8 @@ struct turbo_sw_queue { RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP | RTE_BBDEV_TURBO_EARLY_TERMINATION, .max_llr_modulus = 16, - .num_buffers_src = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, + .num_buffers_src = + RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, .num_buffers_hard_out = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, .num_buffers_soft_out = 0, @@ -172,25 +187,60 @@ struct turbo_sw_queue { RTE_BBDEV_TURBO_CRC_24A_ATTACH | RTE_BBDEV_TURBO_RATE_MATCH | RTE_BBDEV_TURBO_RV_INDEX_BYPASS, - .num_buffers_src = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, - .num_buffers_dst = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, + .num_buffers_src = + RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, + .num_buffers_dst = + RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, } }, #endif +#ifdef RTE_BBDEV_SDK_AVX512 + { + .type = RTE_BBDEV_OP_LDPC_ENC, + .cap.ldpc_enc = { + .capability_flags = + RTE_BBDEV_LDPC_RATE_MATCH | + RTE_BBDEV_LDPC_CRC_24A_ATTACH | + RTE_BBDEV_LDPC_CRC_24B_ATTACH, + .num_buffers_src = + RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, + .num_buffers_dst = + RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, + } + }, + { + .type = RTE_BBDEV_OP_LDPC_DEC, + .cap.ldpc_dec = { + .capability_flags = + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK | + RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK | + RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP | + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE | + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE | + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, + .llr_size = 8, + .llr_decimals = 2, + .harq_memory_size = 0, + .num_buffers_src = + RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, + .num_buffers_hard_out = + RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, + .num_buffers_soft_out = 0, + } + }, +#endif RTE_BBDEV_END_OF_CAPABILITIES_LIST() }; static struct rte_bbdev_queue_conf default_queue_conf = { .queue_size = RTE_BBDEV_QUEUE_SIZE_LIMIT, }; - #ifdef RTE_BBDEV_SDK_AVX2 static const enum rte_cpu_flag_t cpu_flag = RTE_CPUFLAG_SSE4_2; dev_info->cpu_flag_reqs = &cpu_flag; #else dev_info->cpu_flag_reqs = NULL; #endif - default_queue_conf.socket = dev->data->socket_id; dev_info->driver_name = RTE_STR(DRIVER_NAME); @@ -277,7 +327,7 @@ struct turbo_sw_queue { return -ENAMETOOLONG; } q->enc_in = rte_zmalloc_socket(name, - (RTE_BBDEV_TURBO_MAX_CB_SIZE >> 3) * sizeof(*q->enc_in), + (RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) * sizeof(*q->enc_in), RTE_CACHE_LINE_SIZE, queue_conf->socket); if (q->enc_in == NULL) { rte_bbdev_log(ERR, @@ -285,7 +335,7 @@ struct turbo_sw_queue { goto free_q; } - /* Allocate memory for Aplha Gamma temp buffer. */ + /* Allocate memory for Alpha Gamma temp buffer. */ ret = snprintf(name, RTE_RING_NAMESIZE, RTE_STR(DRIVER_NAME)"_ag%u:%u", dev->data->dev_id, q_id); if ((ret < 0) || (ret >= (int)RTE_RING_NAMESIZE)) { @@ -420,6 +470,7 @@ struct turbo_sw_queue { }; #ifdef RTE_BBDEV_SDK_AVX2 +#ifdef RTE_LIBRTE_BBDEV_DEBUG /* Checks if the encoder input buffer is correct. * Returns 0 if it's valid, -1 otherwise. */ @@ -475,16 +526,21 @@ struct turbo_sw_queue { return 0; } #endif +#endif static inline void process_enc_cb(struct turbo_sw_queue *q, struct rte_bbdev_enc_op *op, uint8_t r, uint8_t c, uint16_t k, uint16_t ncb, uint32_t e, struct rte_mbuf *m_in, struct rte_mbuf *m_out_head, - struct rte_mbuf *m_out, uint16_t in_offset, uint16_t out_offset, + struct rte_mbuf *m_out, uint16_t in_offset, uint16_t out_offset, uint16_t in_length, struct rte_bbdev_stats *q_stats) { #ifdef RTE_BBDEV_SDK_AVX2 +#ifdef RTE_LIBRTE_BBDEV_DEBUG int ret; +#else + RTE_SET_USED(in_length); +#endif int16_t k_idx; uint16_t m; uint8_t *in, *out0, *out1, *out2, *tmp_out, *rm_out; @@ -508,11 +564,14 @@ struct turbo_sw_queue { /* CRC24A (for TB) */ if ((enc->op_flags & RTE_BBDEV_TURBO_CRC_24A_ATTACH) && (enc->code_block_mode == 1)) { +#ifdef RTE_LIBRTE_BBDEV_DEBUG ret = is_enc_input_valid(k - 24, k_idx, in_length); if (ret != 0) { op->status |= 1 << RTE_BBDEV_DATA_ERROR; return; } +#endif + crc_req.data = in; crc_req.len = k - 24; /* Check if there is a room for CRC bits if not use @@ -541,11 +600,14 @@ struct turbo_sw_queue { #endif } else if (enc->op_flags & RTE_BBDEV_TURBO_CRC_24B_ATTACH) { /* CRC24B */ +#ifdef RTE_LIBRTE_BBDEV_DEBUG ret = is_enc_input_valid(k - 24, k_idx, in_length); if (ret != 0) { op->status |= 1 << RTE_BBDEV_DATA_ERROR; return; } +#endif + crc_req.data = in; crc_req.len = k - 24; /* Check if there is a room for CRC bits if this is the last @@ -572,13 +634,16 @@ struct turbo_sw_queue { #ifdef RTE_BBDEV_OFFLOAD_COST q_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time; #endif - } else { + } +#ifdef RTE_LIBRTE_BBDEV_DEBUG + else { ret = is_enc_input_valid(k, k_idx, in_length); if (ret != 0) { op->status |= 1 << RTE_BBDEV_DATA_ERROR; return; } } +#endif /* Turbo encoder */ @@ -754,6 +819,143 @@ struct turbo_sw_queue { #endif } + +static inline void +process_ldpc_enc_cb(struct turbo_sw_queue *q, struct rte_bbdev_enc_op *op, + uint32_t e, struct rte_mbuf *m_in, struct rte_mbuf *m_out_head, + struct rte_mbuf *m_out, uint16_t in_offset, uint16_t out_offset, + uint16_t seg_total_left, struct rte_bbdev_stats *q_stats) +{ +#ifdef RTE_BBDEV_SDK_AVX512 + RTE_SET_USED(seg_total_left); + uint8_t *in, *rm_out; + struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc; + struct bblib_ldpc_encoder_5gnr_request ldpc_req; + struct bblib_ldpc_encoder_5gnr_response ldpc_resp; + struct bblib_LDPC_ratematch_5gnr_request rm_req; + struct bblib_LDPC_ratematch_5gnr_response rm_resp; + struct bblib_crc_request crc_req; + struct bblib_crc_response crc_resp; + uint16_t msgLen, puntBits, parity_offset, out_len; + uint16_t K = (enc->basegraph == 1 ? 22 : 10) * enc->z_c; + uint16_t in_length_in_bits = K - enc->n_filler; + uint16_t in_length_in_bytes = (in_length_in_bits + 7) >> 3; + +#ifdef RTE_BBDEV_OFFLOAD_COST + uint64_t start_time = rte_rdtsc_precise(); +#else + RTE_SET_USED(q_stats); +#endif + + in = rte_pktmbuf_mtod_offset(m_in, uint8_t *, in_offset); + + /* Masking the Filler bits explicitly */ + memset(q->enc_in + (in_length_in_bytes - 3), 0, + ((K + 7) >> 3) - (in_length_in_bytes - 3)); + /* CRC Generation */ + if (enc->op_flags & RTE_BBDEV_LDPC_CRC_24A_ATTACH) { + rte_memcpy(q->enc_in, in, in_length_in_bytes - 3); + crc_req.data = in; + crc_req.len = in_length_in_bits - 24; + crc_resp.data = q->enc_in; + bblib_lte_crc24a_gen(&crc_req, &crc_resp); + } else if (enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH) { + rte_memcpy(q->enc_in, in, in_length_in_bytes - 3); + crc_req.data = in; + crc_req.len = in_length_in_bits - 24; + crc_resp.data = q->enc_in; + bblib_lte_crc24b_gen(&crc_req, &crc_resp); + } else + rte_memcpy(q->enc_in, in, in_length_in_bytes); + + /* LDPC Encoding */ + ldpc_req.Zc = enc->z_c; + ldpc_req.baseGraph = enc->basegraph; + /* Number of rows set to maximum */ + ldpc_req.nRows = ldpc_req.baseGraph == 1 ? 46 : 42; + ldpc_req.numberCodeblocks = 1; + ldpc_req.input[0] = (int8_t *) q->enc_in; + ldpc_resp.output[0] = (int8_t *) q->enc_out; + + bblib_bit_reverse(ldpc_req.input[0], in_length_in_bytes << 3); + + if (bblib_ldpc_encoder_5gnr(&ldpc_req, &ldpc_resp) != 0) { + op->status |= 1 << RTE_BBDEV_DRV_ERROR; + rte_bbdev_log(ERR, "LDPC Encoder failed"); + return; + } + + /* + * Systematic + Parity : Recreating stream with filler bits, ideally + * the bit select could handle this in the RM SDK + */ + msgLen = (ldpc_req.baseGraph == 1 ? 22 : 10) * ldpc_req.Zc; + puntBits = 2 * ldpc_req.Zc; + parity_offset = msgLen - puntBits; + ippsCopyBE_1u(((uint8_t *) ldpc_req.input[0]) + (puntBits / 8), + puntBits%8, q->adapter_output, 0, parity_offset); + ippsCopyBE_1u(q->enc_out, 0, q->adapter_output + (parity_offset / 8), + parity_offset % 8, ldpc_req.nRows * ldpc_req.Zc); + + out_len = (e + 7) >> 3; + /* get output data starting address */ + rm_out = (uint8_t *)mbuf_append(m_out_head, m_out, out_len); + if (rm_out == NULL) { + op->status |= 1 << RTE_BBDEV_DATA_ERROR; + rte_bbdev_log(ERR, + "Too little space in output mbuf"); + return; + } + /* + * rte_bbdev_op_data.offset can be different than the offset + * of the appended bytes + */ + rm_out = rte_pktmbuf_mtod_offset(m_out, uint8_t *, out_offset); + + /* Rate-Matching */ + rm_req.E = e; + rm_req.Ncb = enc->n_cb; + rm_req.Qm = enc->q_m; + rm_req.Zc = enc->z_c; + rm_req.baseGraph = enc->basegraph; + rm_req.input = q->adapter_output; + rm_req.nLen = enc->n_filler; + rm_req.nullIndex = parity_offset - enc->n_filler; + rm_req.rvidx = enc->rv_index; + rm_resp.output = q->deint_output; + + if (bblib_LDPC_ratematch_5gnr(&rm_req, &rm_resp) != 0) { + op->status |= 1 << RTE_BBDEV_DRV_ERROR; + rte_bbdev_log(ERR, "Rate matching failed"); + return; + } + + /* RM SDK may provide non zero bits on last byte */ + if ((e % 8) != 0) + q->deint_output[out_len-1] &= (1 << (e % 8)) - 1; + + bblib_bit_reverse((int8_t *) q->deint_output, out_len << 3); + + rte_memcpy(rm_out, q->deint_output, out_len); + enc->output.length += out_len; + +#ifdef RTE_BBDEV_OFFLOAD_COST + q_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time; +#endif +#else + RTE_SET_USED(q); + RTE_SET_USED(op); + RTE_SET_USED(e); + RTE_SET_USED(m_in); + RTE_SET_USED(m_out_head); + RTE_SET_USED(m_out); + RTE_SET_USED(in_offset); + RTE_SET_USED(out_offset); + RTE_SET_USED(seg_total_left); + RTE_SET_USED(q_stats); +#endif +} + static inline void enqueue_enc_one_op(struct turbo_sw_queue *q, struct rte_bbdev_enc_op *op, struct rte_bbdev_stats *queue_stats) @@ -847,6 +1049,93 @@ struct turbo_sw_queue { } } + +static inline void +enqueue_ldpc_enc_one_op(struct turbo_sw_queue *q, struct rte_bbdev_enc_op *op, + struct rte_bbdev_stats *queue_stats) +{ + uint8_t c, r, crc24_bits = 0; + uint32_t e; + struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc; + uint16_t in_offset = enc->input.offset; + uint16_t out_offset = enc->output.offset; + struct rte_mbuf *m_in = enc->input.data; + struct rte_mbuf *m_out = enc->output.data; + struct rte_mbuf *m_out_head = enc->output.data; + uint32_t in_length, mbuf_total_left = enc->input.length; + + uint16_t seg_total_left; + + /* Clear op status */ + op->status = 0; + + if (mbuf_total_left > RTE_BBDEV_TURBO_MAX_TB_SIZE >> 3) { + rte_bbdev_log(ERR, "TB size (%u) is too big, max: %d", + mbuf_total_left, RTE_BBDEV_TURBO_MAX_TB_SIZE); + op->status = 1 << RTE_BBDEV_DATA_ERROR; + return; + } + + if (m_in == NULL || m_out == NULL) { + rte_bbdev_log(ERR, "Invalid mbuf pointer"); + op->status = 1 << RTE_BBDEV_DATA_ERROR; + return; + } + + if ((enc->op_flags & RTE_BBDEV_TURBO_CRC_24B_ATTACH) || + (enc->op_flags & RTE_BBDEV_TURBO_CRC_24A_ATTACH)) + crc24_bits = 24; + + if (enc->code_block_mode == 0) { /* For Transport Block mode */ + c = enc->tb_params.c; + r = enc->tb_params.r; + } else { /* For Code Block mode */ + c = 1; + r = 0; + } + + while (mbuf_total_left > 0 && r < c) { + + seg_total_left = rte_pktmbuf_data_len(m_in) - in_offset; + + if (enc->code_block_mode == 0) { + e = (r < enc->tb_params.cab) ? + enc->tb_params.ea : enc->tb_params.eb; + } else { + e = enc->cb_params.e; + } + + process_ldpc_enc_cb(q, op, e, m_in, m_out_head, + m_out, in_offset, out_offset, seg_total_left, + queue_stats); + /* Update total_left */ + in_length = (enc->basegraph == 1 ? 22 : 10) * enc->z_c; + in_length = ((in_length - crc24_bits - enc->n_filler) >> 3); + mbuf_total_left -= in_length; + /* Update offsets for next CBs (if exist) */ + in_offset += in_length; + out_offset += (e + 7) >> 3; + + /* Update offsets */ + if (seg_total_left == in_length) { + /* Go to the next mbuf */ + m_in = m_in->next; + m_out = m_out->next; + in_offset = 0; + out_offset = 0; + } + r++; + } + + /* check if all input data was processed */ + if (mbuf_total_left != 0) { + op->status |= 1 << RTE_BBDEV_DATA_ERROR; + rte_bbdev_log(ERR, + "Mismatch between mbuf length and included CBs sizes %d", + mbuf_total_left); + } +} + static inline uint16_t enqueue_enc_all_ops(struct turbo_sw_queue *q, struct rte_bbdev_enc_op **ops, uint16_t nb_ops, struct rte_bbdev_stats *queue_stats) @@ -863,6 +1152,23 @@ struct turbo_sw_queue { NULL); } +static inline uint16_t +enqueue_ldpc_enc_all_ops(struct turbo_sw_queue *q, + struct rte_bbdev_enc_op **ops, + uint16_t nb_ops, struct rte_bbdev_stats *queue_stats) +{ + uint16_t i; +#ifdef RTE_BBDEV_OFFLOAD_COST + queue_stats->acc_offload_cycles = 0; +#endif + + for (i = 0; i < nb_ops; ++i) + enqueue_ldpc_enc_one_op(q, ops[i], queue_stats); + + return rte_ring_enqueue_burst(q->processed_pkts, (void **)ops, nb_ops, + NULL); +} + #ifdef RTE_BBDEV_SDK_AVX2 static inline void move_padding_bytes(const uint8_t *in, uint8_t *out, uint16_t k, @@ -887,7 +1193,11 @@ struct turbo_sw_queue { struct rte_bbdev_stats *q_stats) { #ifdef RTE_BBDEV_SDK_AVX2 +#ifdef RTE_LIBRTE_BBDEV_DEBUG int ret; +#else + RTE_SET_USED(in_length); +#endif int32_t k_idx; int32_t iter_cnt; uint8_t *in, *out, *adapter_input; @@ -905,11 +1215,13 @@ struct turbo_sw_queue { k_idx = compute_idx(k); +#ifdef RTE_LIBRTE_BBDEV_DEBUG ret = is_dec_input_valid(k_idx, kw, in_length); if (ret != 0) { op->status |= 1 << RTE_BBDEV_DATA_ERROR; return; } +#endif in = rte_pktmbuf_mtod_offset(m_in, uint8_t *, in_offset); ncb = kw; @@ -925,11 +1237,12 @@ struct turbo_sw_queue { deint_resp.pinteleavebuffer = q->deint_output; #ifdef RTE_BBDEV_OFFLOAD_COST - start_time = rte_rdtsc_precise(); + start_time = rte_rdtsc_precise(); #endif + /* Sub-block De-Interleaving */ bblib_deinterleave_ul(&deint_req, &deint_resp); #ifdef RTE_BBDEV_OFFLOAD_COST - q_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time; + q_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time; #endif } else move_padding_bytes(in, q->deint_output, k, ncb); @@ -1022,6 +1335,202 @@ struct turbo_sw_queue { } static inline void +process_ldpc_dec_cb(struct turbo_sw_queue *q, struct rte_bbdev_dec_op *op, + uint8_t c, uint16_t out_length, uint16_t e, + struct rte_mbuf *m_in, + struct rte_mbuf *m_out_head, struct rte_mbuf *m_out, + struct rte_mbuf *m_harq_in, + struct rte_mbuf *m_harq_out_head, struct rte_mbuf *m_harq_out, + uint16_t in_offset, uint16_t out_offset, + uint16_t harq_in_offset, uint16_t harq_out_offset, + bool check_crc_24b, + uint16_t crc24_overlap, uint16_t in_length, + struct rte_bbdev_stats *q_stats) +{ +#ifdef RTE_BBDEV_SDK_AVX512 + RTE_SET_USED(in_length); + RTE_SET_USED(c); + uint8_t *in, *out, *harq_in, *harq_out, *adapter_input; + struct bblib_rate_dematching_5gnr_request derm_req; + struct bblib_rate_dematching_5gnr_response derm_resp; + struct bblib_ldpc_decoder_5gnr_request dec_req; + struct bblib_ldpc_decoder_5gnr_response dec_resp; + struct bblib_crc_request crc_req; + struct bblib_crc_response crc_resp; + struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec; + uint16_t K, parity_offset, sys_cols, outLenWithCrc; + int16_t deRmOutSize, numRows; + + /* Compute some LDPC BG lengths */ + outLenWithCrc = out_length + (crc24_overlap >> 3); + sys_cols = (dec->basegraph == 1) ? 22 : 10; + K = sys_cols * dec->z_c; + parity_offset = K - 2 * dec->z_c; + +#ifdef RTE_BBDEV_OFFLOAD_COST + uint64_t start_time = rte_rdtsc_precise(); +#else + RTE_SET_USED(q_stats); +#endif + + in = rte_pktmbuf_mtod_offset(m_in, uint8_t *, in_offset); + + if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) { + /** + * Single contiguous block from the first LLR of the + * circular buffer. + */ + harq_in = NULL; + if (m_harq_in != NULL) + harq_in = rte_pktmbuf_mtod_offset(m_harq_in, + uint8_t *, harq_in_offset); + if (harq_in == NULL) { + op->status |= 1 << RTE_BBDEV_DATA_ERROR; + rte_bbdev_log(ERR, "No space in harq input mbuf"); + return; + } + uint16_t harq_in_length = RTE_MIN( + dec->harq_combined_input.length, + (uint32_t) dec->n_cb); + memset(q->ag + harq_in_length, 0, + dec->n_cb - harq_in_length); + rte_memcpy(q->ag, harq_in, harq_in_length); + } + + derm_req.p_in = (int8_t *) in; + derm_req.p_harq = q->ag; /* This doesn't include the filler bits */ + derm_req.base_graph = dec->basegraph; + derm_req.zc = dec->z_c; + derm_req.ncb = dec->n_cb; + derm_req.e = e; + derm_req.k0 = 0; /* Actual output from SDK */ + derm_req.isretx = check_bit(dec->op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); + derm_req.rvid = dec->rv_index; + derm_req.modulation_order = dec->q_m; + derm_req.start_null_index = parity_offset - dec->n_filler; + derm_req.num_of_null = dec->n_filler; + + bblib_rate_dematching_5gnr(&derm_req, &derm_resp); + + /* Compute RM out size and number of rows */ + deRmOutSize = RTE_MIN( + derm_req.k0 + derm_req.e - + ((derm_req.k0 < derm_req.start_null_index) ? + 0 : dec->n_filler), + dec->n_cb - dec->n_filler); + if (m_harq_in != NULL) + deRmOutSize = RTE_MAX(deRmOutSize, + RTE_MIN(dec->n_cb - dec->n_filler, + m_harq_in->data_len)); + numRows = ((deRmOutSize + dec->n_filler + dec->z_c - 1) / dec->z_c) + - sys_cols + 2; + numRows = RTE_MAX(4, numRows); + + /* get output data starting address */ + out = (uint8_t *)mbuf_append(m_out_head, m_out, out_length); + if (out == NULL) { + op->status |= 1 << RTE_BBDEV_DATA_ERROR; + rte_bbdev_log(ERR, + "Too little space in LDPC decoder output mbuf"); + return; + } + + /* rte_bbdev_op_data.offset can be different than the offset + * of the appended bytes + */ + out = rte_pktmbuf_mtod_offset(m_out, uint8_t *, out_offset); + adapter_input = q->enc_out; + + dec_req.Zc = dec->z_c; + dec_req.baseGraph = dec->basegraph; + dec_req.nRows = numRows; + dec_req.numChannelLlrs = deRmOutSize; + dec_req.varNodes = derm_req.p_harq; + dec_req.numFillerBits = dec->n_filler; + dec_req.maxIterations = dec->iter_max; + dec_req.enableEarlyTermination = check_bit(dec->op_flags, + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE); + dec_resp.varNodes = (int16_t *) q->adapter_output; + dec_resp.compactedMessageBytes = q->enc_out; + + bblib_ldpc_decoder_5gnr(&dec_req, &dec_resp); + + dec->iter_count = RTE_MAX(dec_resp.iterationAtTermination, + dec->iter_count); + if (!dec_resp.parityPassedAtTermination) + op->status |= 1 << RTE_BBDEV_SYNDROME_ERROR; + + bblib_bit_reverse((int8_t *) q->enc_out, outLenWithCrc << 3); + + if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK) || + check_bit(dec->op_flags, + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK)) { + crc_req.data = adapter_input; + crc_req.len = K - dec->n_filler - 24; + crc_resp.check_passed = false; + crc_resp.data = adapter_input; + if (check_crc_24b) + bblib_lte_crc24b_check(&crc_req, &crc_resp); + else + bblib_lte_crc24a_check(&crc_req, &crc_resp); + if (!crc_resp.check_passed) + op->status |= 1 << RTE_BBDEV_CRC_ERROR; + } + +#ifdef RTE_BBDEV_OFFLOAD_COST + q_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time; +#endif + if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { + harq_out = NULL; + if (m_harq_out != NULL) { + /* Initialize HARQ data length since we overwrite */ + m_harq_out->data_len = 0; + /* Check there is enough space + * in the HARQ outbound buffer + */ + harq_out = (uint8_t *)mbuf_append(m_harq_out_head, + m_harq_out, deRmOutSize); + } + if (harq_out == NULL) { + op->status |= 1 << RTE_BBDEV_DATA_ERROR; + rte_bbdev_log(ERR, "No space in HARQ output mbuf"); + return; + } + /* get output data starting address and overwrite the data */ + harq_out = rte_pktmbuf_mtod_offset(m_harq_out, uint8_t *, + harq_out_offset); + rte_memcpy(harq_out, derm_req.p_harq, deRmOutSize); + dec->harq_combined_output.length += deRmOutSize; + } + + rte_memcpy(out, adapter_input, out_length); + dec->hard_output.length += out_length; +#else + RTE_SET_USED(q); + RTE_SET_USED(op); + RTE_SET_USED(c); + RTE_SET_USED(out_length); + RTE_SET_USED(e); + RTE_SET_USED(m_in); + RTE_SET_USED(m_out_head); + RTE_SET_USED(m_out); + RTE_SET_USED(m_harq_in); + RTE_SET_USED(m_harq_out_head); + RTE_SET_USED(m_harq_out); + RTE_SET_USED(harq_in_offset); + RTE_SET_USED(harq_out_offset); + RTE_SET_USED(in_offset); + RTE_SET_USED(out_offset); + RTE_SET_USED(check_crc_24b); + RTE_SET_USED(crc24_overlap); + RTE_SET_USED(in_length); + RTE_SET_USED(q_stats); +#endif +} + + +static inline void enqueue_dec_one_op(struct turbo_sw_queue *q, struct rte_bbdev_dec_op *op, struct rte_bbdev_stats *queue_stats) { @@ -1080,6 +1589,7 @@ struct turbo_sw_queue { in_offset, out_offset, check_bit(dec->op_flags, RTE_BBDEV_TURBO_CRC_TYPE_24B), crc24_overlap, seg_total_left, queue_stats); + /* To keep CRC24 attached to end of Code block, use * RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP flag as it * removed by default once verified. @@ -1101,6 +1611,103 @@ struct turbo_sw_queue { } r++; } + + if (mbuf_total_left != 0) { + op->status |= 1 << RTE_BBDEV_DATA_ERROR; + rte_bbdev_log(ERR, + "Mismatch between mbuf length and included Circular buffer sizes"); + } +} + +static inline void +enqueue_ldpc_dec_one_op(struct turbo_sw_queue *q, struct rte_bbdev_dec_op *op, + struct rte_bbdev_stats *queue_stats) +{ + uint8_t c, r = 0; + uint16_t e, out_length; + uint16_t crc24_overlap = 0; + struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec; + struct rte_mbuf *m_in = dec->input.data; + struct rte_mbuf *m_harq_in = dec->harq_combined_input.data; + struct rte_mbuf *m_harq_out = dec->harq_combined_output.data; + struct rte_mbuf *m_harq_out_head = dec->harq_combined_output.data; + struct rte_mbuf *m_out = dec->hard_output.data; + struct rte_mbuf *m_out_head = dec->hard_output.data; + uint16_t in_offset = dec->input.offset; + uint16_t harq_in_offset = dec->harq_combined_input.offset; + uint16_t harq_out_offset = dec->harq_combined_output.offset; + uint16_t out_offset = dec->hard_output.offset; + uint32_t mbuf_total_left = dec->input.length; + uint16_t seg_total_left; + + /* Clear op status */ + op->status = 0; + + if (m_in == NULL || m_out == NULL) { + rte_bbdev_log(ERR, "Invalid mbuf pointer"); + op->status = 1 << RTE_BBDEV_DATA_ERROR; + return; + } + + if (dec->code_block_mode == 0) { /* For Transport Block mode */ + c = dec->tb_params.c; + e = dec->tb_params.ea; + } else { /* For Code Block mode */ + c = 1; + e = dec->cb_params.e; + } + + if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP)) + crc24_overlap = 24; + + out_length = (dec->basegraph == 1 ? 22 : 10) * dec->z_c; /* K */ + out_length = ((out_length - crc24_overlap - dec->n_filler) >> 3); + + while (mbuf_total_left > 0) { + if (dec->code_block_mode == 0) + e = (r < dec->tb_params.cab) ? + dec->tb_params.ea : dec->tb_params.eb; + + seg_total_left = rte_pktmbuf_data_len(m_in) - in_offset; + + process_ldpc_dec_cb(q, op, c, out_length, e, + m_in, m_out_head, m_out, + m_harq_in, m_harq_out_head, m_harq_out, + in_offset, out_offset, harq_in_offset, + harq_out_offset, + check_bit(dec->op_flags, + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK), + crc24_overlap, + seg_total_left, queue_stats); + + /* To keep CRC24 attached to end of Code block, use + * RTE_BBDEV_LDPC_DEC_TB_CRC_24B_KEEP flag as it + * removed by default once verified. + */ + + mbuf_total_left -= e; + + /* Update offsets */ + if (seg_total_left == e) { + /* Go to the next mbuf */ + m_in = m_in->next; + m_out = m_out->next; + if (m_harq_in != NULL) + m_harq_in = m_harq_in->next; + if (m_harq_out != NULL) + m_harq_out = m_harq_out->next; + in_offset = 0; + out_offset = 0; + harq_in_offset = 0; + harq_out_offset = 0; + } else { + /* Update offsets for next CBs (if exist) */ + in_offset += e; + out_offset += out_length; + } + r++; + } + if (mbuf_total_left != 0) { op->status |= 1 << RTE_BBDEV_DATA_ERROR; rte_bbdev_log(ERR, @@ -1124,6 +1731,23 @@ struct turbo_sw_queue { NULL); } +static inline uint16_t +enqueue_ldpc_dec_all_ops(struct turbo_sw_queue *q, + struct rte_bbdev_dec_op **ops, + uint16_t nb_ops, struct rte_bbdev_stats *queue_stats) +{ + uint16_t i; +#ifdef RTE_BBDEV_OFFLOAD_COST + queue_stats->acc_offload_cycles = 0; +#endif + + for (i = 0; i < nb_ops; ++i) + enqueue_ldpc_dec_one_op(q, ops[i], queue_stats); + + return rte_ring_enqueue_burst(q->processed_pkts, (void **)ops, nb_ops, + NULL); +} + /* Enqueue burst */ static uint16_t enqueue_enc_ops(struct rte_bbdev_queue_data *q_data, @@ -1143,6 +1767,24 @@ struct turbo_sw_queue { /* Enqueue burst */ static uint16_t +enqueue_ldpc_enc_ops(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_enc_op **ops, uint16_t nb_ops) +{ + void *queue = q_data->queue_private; + struct turbo_sw_queue *q = queue; + uint16_t nb_enqueued = 0; + + nb_enqueued = enqueue_ldpc_enc_all_ops( + q, ops, nb_ops, &q_data->queue_stats); + + q_data->queue_stats.enqueue_err_count += nb_ops - nb_enqueued; + q_data->queue_stats.enqueued_count += nb_enqueued; + + return nb_enqueued; +} + +/* Enqueue burst */ +static uint16_t enqueue_dec_ops(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t nb_ops) { @@ -1158,6 +1800,24 @@ struct turbo_sw_queue { return nb_enqueued; } +/* Enqueue burst */ +static uint16_t +enqueue_ldpc_dec_ops(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_dec_op **ops, uint16_t nb_ops) +{ + void *queue = q_data->queue_private; + struct turbo_sw_queue *q = queue; + uint16_t nb_enqueued = 0; + + nb_enqueued = enqueue_ldpc_dec_all_ops(q, ops, nb_ops, + &q_data->queue_stats); + + q_data->queue_stats.enqueue_err_count += nb_ops - nb_enqueued; + q_data->queue_stats.enqueued_count += nb_enqueued; + + return nb_enqueued; +} + /* Dequeue decode burst */ static uint16_t dequeue_dec_ops(struct rte_bbdev_queue_data *q_data, @@ -1270,6 +1930,10 @@ struct turbo_sw_queue { bbdev->dequeue_dec_ops = dequeue_dec_ops; bbdev->enqueue_enc_ops = enqueue_enc_ops; bbdev->enqueue_dec_ops = enqueue_dec_ops; + bbdev->dequeue_ldpc_enc_ops = dequeue_enc_ops; + bbdev->dequeue_ldpc_dec_ops = dequeue_dec_ops; + bbdev->enqueue_ldpc_enc_ops = enqueue_ldpc_enc_ops; + bbdev->enqueue_ldpc_dec_ops = enqueue_ldpc_dec_ops; ((struct bbdev_private *) bbdev->data->dev_private)->max_nb_queues = init_params->queues_num; diff --git a/drivers/baseband/turbo_sw/meson.build b/drivers/baseband/turbo_sw/meson.build index 438b5a7..33345aa 100644 --- a/drivers/baseband/turbo_sw/meson.build +++ b/drivers/baseband/turbo_sw/meson.build @@ -23,6 +23,16 @@ if dpdk_conf.has('RTE_BBDEV_SDK_AVX2') includes += include_directories(path + '/lib_common') endif endif +if dpdk_conf.has('RTE_BBDEV_SDK_AVX512') + ext_deps += cc.find_library('libldpc_encoder_5gnr', dirs: [path + '/lib_ldpc_encoder_5gnr'], required: true) + ext_deps += cc.find_library('libldpc_decoder_5gnr', dirs: [path + '/lib_ldpc_decoder_5gnr'], required: true) + ext_deps += cc.find_library('libLDPC_ratematch_5gnr', dirs: [path + '/lib_LDPC_ratematch_5gnr'], required: true) + ext_deps += cc.find_library('librate_dematching_5gnr', dirs: [path + '/lib_rate_dematching_5gnr'], required: true) + includes += include_directories(path + '/lib_ldpc_encoder_5gnr') + includes += include_directories(path + '/lib_ldpc_decoder_5gnr') + includes += include_directories(path + '/lib_LDPC_ratematch_5gnr') + includes += include_directories(path + '/lib_rate_dematching_5gnr') +endif deps += ['bbdev', 'bus_vdev', 'ring'] name = 'bbdev_turbo_sw' diff --git a/mk/rte.app.mk b/mk/rte.app.mk index cdd6073..a586388 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -226,7 +226,13 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_crc -lcr _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_turbo -lturbo _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_rate_matching -lrate_matching _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_common -lcommon -_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -lirc -limf -lstdc++ -lipps +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -lirc -limf -lstdc++ -lipps -lsvml +ifeq ($(CONFIG_RTE_BBDEV_SDK_AVX512),y) +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_LDPC_ratematch_5gnr -lLDPC_ratematch_5gnr +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_ldpc_encoder_5gnr -lldpc_encoder_5gnr +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_ldpc_decoder_5gnr -lldpc_decoder_5gnr +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_rate_dematching_5gnr -lrate_dematching_5gnr +endif # CONFIG_RTE_BBDEV_SDK_AVX512 endif # CONFIG_RTE_BBDEV_SDK_AVX2 endif # CONFIG_RTE_LIBRTE_BBDEV From patchwork Mon Jun 24 02:52:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 55230 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 80CC51BF8F; Mon, 24 Jun 2019 04:53:25 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 1572E1BF6C for ; Mon, 24 Jun 2019 04:53:03 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jun 2019 19:52:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,410,1557212400"; d="scan'208";a="183991203" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga004.fm.intel.com with ESMTP; 23 Jun 2019 19:52:59 -0700 From: Nicolas Chautru To: akhil.goyal@nxp.com, dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@intel.com, amr.mokhtar@intel.com, Nicolas Chautru Date: Sun, 23 Jun 2019 19:52:53 -0700 Message-Id: <1561344776-43990-8-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> References: <1561136352-32198-2-git-send-email-nicolas.chautru@intel.com> <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v4 07/10] docs/guides: updating building steps for BBDEV PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This now includes steps to build with either libraries for AVX2, or AVX512 or no dependency. Signed-off-by: Nicolas Chautru Acked-by: Amr Mokhtar --- doc/guides/bbdevs/turbo_sw.rst | 42 +++++++++++++++++++++++++++++------------- 1 file changed, 29 insertions(+), 13 deletions(-) diff --git a/doc/guides/bbdevs/turbo_sw.rst b/doc/guides/bbdevs/turbo_sw.rst index 455fa1d..2785a50 100644 --- a/doc/guides/bbdevs/turbo_sw.rst +++ b/doc/guides/bbdevs/turbo_sw.rst @@ -5,20 +5,21 @@ SW Turbo Poll Mode Driver ========================= The SW Turbo PMD (**baseband_turbo_sw**) provides a software only poll mode bbdev -driver that can optionally utilize Intel optimized libraries for LTE Layer 1 -workloads acceleration. +driver that can optionally utilize Intel optimized libraries for LTE and 5GNR +Layer 1 workloads acceleration. Note that the driver can also be built without any dependency with reduced functionality for maintenance purpose. To enable linking to the SDK libraries see detailed installation section below. -One flag can be enabled depending on whether the target machine can support -AVX2 instructions sets and the related SDK libraries for vectorized +Two flags can be enabled depending on whether the target machine can support +AVX2 and AVX512 instructions sets and the related SDK libraries for vectorized signal processing functions are installed : - CONFIG_RTE_BBDEV_SDK_AVX2 - -By default this flag is disabled. For AVX2 machine and SDK -library installed then this flag can be enabled. +- CONFIG_RTE_BBDEV_SDK_AVX512 +By default these 2 flags are disabled by default. For AVX2 machine and SDK +library installed then the first flag can be enabled. For AVX512 machine and +SDK library installed then both flags can be enabled for full real time capability. This PMD supports the functions: FEC, Rate Matching and CRC functions detailed in the Features section. @@ -45,11 +46,25 @@ For the LTE decode operation: * ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` * ``RTE_BBDEV_TURBO_EARLY_TERMINATION`` +For the 5G NR LDPC encode operation: + +* ``RTE_BBDEV_LDPC_RATE_MATCH`` +* ``RTE_BBDEV_LDPC_CRC_24A_ATTACH`` +* ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` + +For the 5G NR LDPC decode operation: + +* ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` +* ``RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK`` +* ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` +* ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` +* ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` +* ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` Limitations ----------- -* In-place operations for Turbo encode and decode are not supported +* In-place operations for encode and decode are not supported Installation ------------ @@ -60,7 +75,7 @@ FlexRAN SDK Download As an option it is possible to link this driver with FleXRAN SDK libraries which can enable real time signal processing using AVX instructions. -These libraries are available through this link `link `_. +These libraries are available through this `link `_. After download is complete, the user needs to unpack and compile on their system before building DPDK. @@ -115,14 +130,13 @@ The following instructions should be followed in this exact order: .. code-block:: console - cd build-avx2-icc/ + cd build-avx512-icc/ make && make install - Initialization -------------- -In order to enable this virtual bbdev PMD, the user must: +In order to enable this virtual bbdev PMD, the user may: * Build the ``FLEXRAN SDK`` libraries (explained in Installation section). @@ -137,9 +151,11 @@ Example: export FLEXRAN_SDK=/FlexRAN-FEC-SDK-19-04/sdk/build-avx2-icc/install export DIR_WIRELESS_SDK=/FlexRAN-FEC-SDK-19-04/sdk/build-avx2-icc/ -* Set ``CONFIG_RTE_BBDEV_SDK_AVX2=y`` +* Set ``CONFIG_RTE_BBDEV_SDK_AVX2=y`` and ``CONFIG_RTE_BBDEV_SDK_AVX512=y`` in DPDK common configuration file ``config/common_base`` to be able to use the SDK libraries as mentioned above. + For AVX2 machine it is possible to only enable CONFIG_RTE_BBDEV_SDK_AVX2 + for limited 4G functionality. If no flag are set the PMD driver will still build but its capabilities will be limited accordingly. From patchwork Mon Jun 24 02:52:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 55232 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3B9861BF9C; Mon, 24 Jun 2019 04:53:29 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 228701BF6D for ; Mon, 24 Jun 2019 04:53:03 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jun 2019 19:52:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,410,1557212400"; d="scan'208";a="183991206" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga004.fm.intel.com with ESMTP; 23 Jun 2019 19:52:59 -0700 From: Nicolas Chautru To: akhil.goyal@nxp.com, dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@intel.com, amr.mokhtar@intel.com, Nicolas Chautru Date: Sun, 23 Jun 2019 19:52:54 -0700 Message-Id: <1561344776-43990-9-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> References: <1561136352-32198-2-git-send-email-nicolas.chautru@intel.com> <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v4 08/10] test-bbdev: update of bbdev test-app for 5GNR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Extending test framework for FEC 5GNR operations for UT verification and profiling. Signed-off-by: Nicolas Chautru Acked-by: Amr Mokhtar --- app/test-bbdev/main.c | 48 +- app/test-bbdev/main.h | 6 +- app/test-bbdev/meson.build | 3 + app/test-bbdev/test-bbdev.py | 7 + app/test-bbdev/test_bbdev.c | 12 +- app/test-bbdev/test_bbdev_perf.c | 1233 ++++++++++++++++++++++++++++++--- app/test-bbdev/test_bbdev_vector.c | 517 +++++++++++++- app/test-bbdev/test_bbdev_vector.h | 14 +- app/test-bbdev/turbo_enc_default.data | 2 +- 9 files changed, 1715 insertions(+), 127 deletions(-) diff --git a/app/test-bbdev/main.c b/app/test-bbdev/main.c index a2f8722..8a42115 100644 --- a/app/test-bbdev/main.c +++ b/app/test-bbdev/main.c @@ -16,11 +16,13 @@ #include "main.h" + /* Defines how many testcases can be specified as cmdline args */ #define MAX_CMDLINE_TESTCASES 8 static const char tc_sep = ','; +/* Declare structure for command line test parameters and options */ static struct test_params { struct test_command *test_to_run[MAX_CMDLINE_TESTCASES]; unsigned int num_tests; @@ -28,6 +30,7 @@ unsigned int burst_sz; unsigned int num_lcores; char test_vector_filename[PATH_MAX]; + bool init_device; } test_params; static struct test_commands_list commands_list = @@ -46,9 +49,8 @@ unsigned int total = 0, skipped = 0, succeeded = 0, failed = 0; uint64_t start, end; - printf( - "\n + ------------------------------------------------------- +\n"); - printf(" + Starting Test Suite : %s\n", suite->suite_name); + printf("\n===========================================================\n"); + printf("Starting Test Suite : %s\n", suite->suite_name); start = rte_rdtsc_precise(); @@ -57,15 +59,13 @@ if (test_result == TEST_FAILED) { printf(" + Test suite setup %s failed!\n", suite->suite_name); - printf( - " + ------------------------------------------------------- +\n"); + printf(" + ------------------------------------------------------- +\n"); return 1; } if (test_result == TEST_SKIPPED) { printf(" + Test suite setup %s skipped!\n", suite->suite_name); - printf( - " + ------------------------------------------------------- +\n"); + printf(" + ------------------------------------------------------- +\n"); return 0; } } @@ -82,15 +82,15 @@ if (test_result == TEST_SUCCESS) { succeeded++; - printf(" + TestCase [%2d] : %s passed\n", total, + printf("TestCase [%2d] : %s passed\n", total, suite->unit_test_cases[total].name); } else if (test_result == TEST_SKIPPED) { skipped++; - printf(" + TestCase [%2d] : %s skipped\n", total, + printf("TestCase [%2d] : %s skipped\n", total, suite->unit_test_cases[total].name); } else { failed++; - printf(" + TestCase [%2d] : %s failed\n", total, + printf("TestCase [%2d] : %s failed\n", total, suite->unit_test_cases[total].name); } @@ -103,7 +103,7 @@ end = rte_rdtsc_precise(); - printf(" + ------------------------------------------------------- +\n"); + printf(" + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +\n"); printf(" + Test Suite Summary : %s\n", suite->suite_name); printf(" + Tests Total : %2d\n", total); printf(" + Tests Skipped : %2d\n", skipped); @@ -111,7 +111,7 @@ printf(" + Tests Failed : %2d\n", failed); printf(" + Tests Lasted : %lg ms\n", ((end - start) * 1000) / (double)rte_get_tsc_hz()); - printf(" + ------------------------------------------------------- +\n"); + printf(" + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +\n"); return (failed > 0) ? 1 : 0; } @@ -140,12 +140,18 @@ return test_params.num_lcores; } +bool +get_init_device(void) +{ + return test_params.init_device; +} + static void print_usage(const char *prog_name) { struct test_command *t; - printf("Usage: %s [EAL params] [-- [-n/--num-ops NUM_OPS]\n" + printf("***Usage: %s [EAL params] [-- [-n/--num-ops NUM_OPS]\n" "\t[-b/--burst-size BURST_SIZE]\n" "\t[-v/--test-vector VECTOR_FILE]\n" "\t[-c/--test-cases TEST_CASE[,TEST_CASE,...]]]\n", @@ -174,11 +180,12 @@ { "test-cases", 1, 0, 'c' }, { "test-vector", 1, 0, 'v' }, { "lcores", 1, 0, 'l' }, + { "init-device", 0, 0, 'i'}, { "help", 0, 0, 'h' }, { NULL, 0, 0, 0 } }; - while ((opt = getopt_long(argc, argv, "hn:b:c:v:l:", lgopts, + while ((opt = getopt_long(argc, argv, "hin:b:c:v:l:", lgopts, &option_index)) != EOF) switch (opt) { case 'n': @@ -226,8 +233,9 @@ TEST_ASSERT(strlen(optarg) > 0, "Config file name is null"); - strlcpy(tp->test_vector_filename, optarg, - sizeof(tp->test_vector_filename)); + snprintf(tp->test_vector_filename, + sizeof(tp->test_vector_filename), + "%s", optarg); break; case 'l': TEST_ASSERT(strlen(optarg) > 0, @@ -237,6 +245,10 @@ "Num of lcores mustn't be greater than %u", RTE_MAX_LCORE); break; + case 'i': + /* indicate fpga fec config required */ + tp->init_device = true; + break; case 'h': print_usage(argv[0]); return 0; @@ -279,7 +291,7 @@ struct test_command *t; TAILQ_FOREACH(t, &commands_list, next) - ret |= t->callback(); + ret |= (int) t->callback(); return ret; } @@ -291,7 +303,7 @@ unsigned int i; for (i = 0; i < tp->num_tests; ++i) - ret |= tp->test_to_run[i]->callback(); + ret |= (int) tp->test_to_run[i]->callback(); return ret; } diff --git a/app/test-bbdev/main.h b/app/test-bbdev/main.h index 2bbe1b8..23b4d58 100644 --- a/app/test-bbdev/main.h +++ b/app/test-bbdev/main.h @@ -20,6 +20,7 @@ #define DEFAULT_BURST 32U #define DEFAULT_OPS 64U + #define TEST_ASSERT(cond, msg, ...) do { \ if (!(cond)) { \ printf("TestCase %s() line %d failed: " \ @@ -103,7 +104,8 @@ struct test_command { .command = RTE_STR(name), \ .callback = test_func_##name, \ }; \ - RTE_INIT(test_register_##name) \ + static void __attribute__((constructor, used)) \ + test_register_##name(void) \ { \ add_test_command(&test_struct_##name); \ } @@ -116,4 +118,6 @@ struct test_command { unsigned int get_num_lcores(void); +bool get_init_device(void); + #endif diff --git a/app/test-bbdev/meson.build b/app/test-bbdev/meson.build index eb8cc04..d3f2b77 100644 --- a/app/test-bbdev/meson.build +++ b/app/test-bbdev/meson.build @@ -7,3 +7,6 @@ sources = files('main.c', 'test_bbdev_vector.c') allow_experimental_apis = true deps += ['bbdev', 'bus_vdev'] +if dpdk_conf.has('RTE_LIBRTE_PMD_FPGA_LTE_FEC') + deps += ['bbdev_fpga_lte_fec'] +endif \ No newline at end of file diff --git a/app/test-bbdev/test-bbdev.py b/app/test-bbdev/test-bbdev.py index 25340ec..0194be0 100755 --- a/app/test-bbdev/test-bbdev.py +++ b/app/test-bbdev/test-bbdev.py @@ -59,6 +59,9 @@ def kill(process): type=int, help="Number of lcores to run.", default=16) +parser.add_argument("-i", "--init-device", + action='store_true', + help="Initialise PF device with default values.") args = parser.parse_args() @@ -82,6 +85,10 @@ def kill(process): params.extend(["-c"]) params.extend([",".join(args.test_cases)]) +if args.init_device: + params.extend(["-i"]) + + exit_status = 0 for vector in args.test_vector: for burst_size in args.burst_size: diff --git a/app/test-bbdev/test_bbdev.c b/app/test-bbdev/test_bbdev.c index 137c74c..ac06d73 100644 --- a/app/test-bbdev/test_bbdev.c +++ b/app/test-bbdev/test_bbdev.c @@ -14,8 +14,6 @@ #include #include #include -#include -#include #include "main.h" @@ -770,7 +768,7 @@ struct bbdev_testsuite_params { { struct rte_bbdev *dev1, *dev2; const char *name = "dev_name"; - char name_tmp[16]; + char name_tmp[32]; int num_devs, num_devs_tmp; dev1 = rte_bbdev_allocate(NULL); @@ -790,14 +788,14 @@ struct bbdev_testsuite_params { /* Initialize the maximum amount of devices */ do { - snprintf(name_tmp, sizeof(name_tmp), "%s%i", "name_", num_devs); + sprintf(name_tmp, "%s%i", "name_", num_devs); dev2 = rte_bbdev_allocate(name_tmp); TEST_ASSERT(dev2 != NULL, "Failed to initialize bbdev driver"); ++num_devs; } while (num_devs < (RTE_BBDEV_MAX_DEVS - 1)); - snprintf(name_tmp, sizeof(name_tmp), "%s%i", "name_", num_devs); + sprintf(name_tmp, "%s%i", "name_", num_devs); dev2 = rte_bbdev_allocate(name_tmp); TEST_ASSERT(dev2 == NULL, "Failed to initialize bbdev driver number %d " "more drivers than RTE_BBDEV_MAX_DEVS: %d ", num_devs, @@ -806,7 +804,7 @@ struct bbdev_testsuite_params { num_devs--; while (num_devs >= num_devs_tmp) { - snprintf(name_tmp, sizeof(name_tmp), "%s%i", "name_", num_devs); + sprintf(name_tmp, "%s%i", "name_", num_devs); dev2 = rte_bbdev_get_named_dev(name_tmp); TEST_ASSERT_SUCCESS(rte_bbdev_release(dev2), "Failed to uninitialize bbdev driver %s ", @@ -827,7 +825,7 @@ struct bbdev_testsuite_params { TEST_ASSERT_FAIL(rte_bbdev_release(NULL), "Failed to uninitialize bbdev driver with NULL bbdev"); - strlcpy(name_tmp, "invalid_name", sizeof(name_tmp)); + sprintf(name_tmp, "%s", "invalid_name"); dev2 = rte_bbdev_get_named_dev(name_tmp); TEST_ASSERT_FAIL(rte_bbdev_release(dev2), "Failed to uninitialize bbdev driver with invalid name"); diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c index d18ddae..a166eaf 100644 --- a/app/test-bbdev/test_bbdev_perf.c +++ b/app/test-bbdev/test_bbdev_perf.c @@ -16,6 +16,11 @@ #include #include #include +#include + +#ifdef RTE_LIBRTE_PMD_FPGA_LTE_FEC +#include +#endif #include "main.h" #include "test_bbdev_vector.h" @@ -25,6 +30,18 @@ #define MAX_QUEUES RTE_MAX_LCORE #define TEST_REPETITIONS 1000 +#ifdef RTE_LIBRTE_PMD_FPGA_LTE_FEC +#define FPGA_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf") +#define FPGA_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf") +#define VF_UL_QUEUE_VALUE 4 +#define VF_DL_QUEUE_VALUE 4 +#define UL_BANDWIDTH 3 +#define DL_BANDWIDTH 3 +#define UL_LOAD_BALANCE 128 +#define DL_LOAD_BALANCE 128 +#define FLR_TIMEOUT 610 +#endif + #define OPS_CACHE_SIZE 256U #define OPS_POOL_SIZE_MIN 511U /* 0.5K per queue */ @@ -49,6 +66,8 @@ struct rte_mempool *in_mbuf_pool; struct rte_mempool *hard_out_mbuf_pool; struct rte_mempool *soft_out_mbuf_pool; + struct rte_mempool *harq_in_mbuf_pool; + struct rte_mempool *harq_out_mbuf_pool; } active_devs[RTE_BBDEV_MAX_DEVS]; static uint8_t nb_active_devs; @@ -58,6 +77,8 @@ struct test_buffers { struct rte_bbdev_op_data *inputs; struct rte_bbdev_op_data *hard_outputs; struct rte_bbdev_op_data *soft_outputs; + struct rte_bbdev_op_data *harq_inputs; + struct rte_bbdev_op_data *harq_outputs; }; /* Operation parameters specific for given test case */ @@ -128,6 +149,13 @@ typedef int (test_case_function)(struct active_device *ad, } while (m != NULL); } +/* Read flag value 0/1 from bitmap */ +static inline bool +check_bit(uint32_t bitmap, uint32_t bitmask) +{ + return bitmap & bitmask; +} + static inline void set_avail_op(struct active_device *ad, enum rte_bbdev_op_type op_type) { @@ -158,12 +186,15 @@ typedef int (test_case_function)(struct active_device *ad, check_dev_cap(const struct rte_bbdev_info *dev_info) { unsigned int i; - unsigned int nb_inputs, nb_soft_outputs, nb_hard_outputs; + unsigned int nb_inputs, nb_soft_outputs, nb_hard_outputs, + nb_harq_inputs, nb_harq_outputs; const struct rte_bbdev_op_cap *op_cap = dev_info->drv.capabilities; nb_inputs = test_vector.entries[DATA_INPUT].nb_segments; nb_soft_outputs = test_vector.entries[DATA_SOFT_OUTPUT].nb_segments; nb_hard_outputs = test_vector.entries[DATA_HARD_OUTPUT].nb_segments; + nb_harq_inputs = test_vector.entries[DATA_HARQ_INPUT].nb_segments; + nb_harq_outputs = test_vector.entries[DATA_HARQ_OUTPUT].nb_segments; for (i = 0; op_cap->type != RTE_BBDEV_OP_NONE; ++i, ++op_cap) { if (op_cap->type != test_vector.op_type) @@ -180,7 +211,7 @@ typedef int (test_case_function)(struct active_device *ad, !(cap->capability_flags & RTE_BBDEV_TURBO_SOFT_OUTPUT)) { printf( - "WARNING: Device \"%s\" does not support soft output - soft output flags will be ignored.\n", + "INFO: Device \"%s\" does not support soft output - soft output flags will be ignored.\n", dev_info->dev_name); clear_soft_out_cap( &test_vector.turbo_dec.op_flags); @@ -233,7 +264,35 @@ typedef int (test_case_function)(struct active_device *ad, if (nb_hard_outputs > cap->num_buffers_dst) { printf( "Too many hard outputs defined: %u, max: %u\n", - nb_hard_outputs, cap->num_buffers_src); + nb_hard_outputs, cap->num_buffers_dst); + return TEST_FAILED; + } + if (intr_enabled && !(cap->capability_flags & + RTE_BBDEV_TURBO_ENC_INTERRUPTS)) { + printf( + "Dequeue interrupts are not supported!\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; + } else if (op_cap->type == RTE_BBDEV_OP_LDPC_ENC) { + const struct rte_bbdev_op_cap_ldpc_enc *cap = + &op_cap->cap.ldpc_enc; + + if (!flags_match(test_vector.ldpc_enc.op_flags, + cap->capability_flags)){ + printf("Flag Mismatch\n"); + return TEST_FAILED; + } + if (nb_inputs > cap->num_buffers_src) { + printf("Too many inputs defined: %u, max: %u\n", + nb_inputs, cap->num_buffers_src); + return TEST_FAILED; + } + if (nb_hard_outputs > cap->num_buffers_dst) { + printf( + "Too many hard outputs defined: %u, max: %u\n", + nb_hard_outputs, cap->num_buffers_dst); return TEST_FAILED; } if (intr_enabled && !(cap->capability_flags & @@ -244,6 +303,49 @@ typedef int (test_case_function)(struct active_device *ad, } return TEST_SUCCESS; + } else if (op_cap->type == RTE_BBDEV_OP_LDPC_DEC) { + const struct rte_bbdev_op_cap_ldpc_dec *cap = + &op_cap->cap.ldpc_dec; + + if (!flags_match(test_vector.ldpc_dec.op_flags, + cap->capability_flags)){ + printf("Flag Mismatch\n"); + return TEST_FAILED; + } + if (nb_inputs > cap->num_buffers_src) { + printf("Too many inputs defined: %u, max: %u\n", + nb_inputs, cap->num_buffers_src); + return TEST_FAILED; + } + if (nb_hard_outputs > cap->num_buffers_hard_out) { + printf( + "Too many hard outputs defined: %u, max: %u\n", + nb_hard_outputs, + cap->num_buffers_hard_out); + return TEST_FAILED; + } + if (nb_harq_inputs > cap->num_buffers_hard_out) { + printf( + "Too many HARQ inputs defined: %u, max: %u\n", + nb_hard_outputs, + cap->num_buffers_hard_out); + return TEST_FAILED; + } + if (nb_harq_outputs > cap->num_buffers_hard_out) { + printf( + "Too many HARQ outputs defined: %u, max: %u\n", + nb_hard_outputs, + cap->num_buffers_hard_out); + return TEST_FAILED; + } + if (intr_enabled && !(cap->capability_flags & + RTE_BBDEV_TURBO_DEC_INTERRUPTS)) { + printf( + "Dequeue interrupts are not supported!\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; } } @@ -297,6 +399,10 @@ typedef int (test_case_function)(struct active_device *ad, &test_vector.entries[DATA_HARD_OUTPUT]; struct op_data_entries *soft_out = &test_vector.entries[DATA_SOFT_OUTPUT]; + struct op_data_entries *harq_in = + &test_vector.entries[DATA_HARQ_INPUT]; + struct op_data_entries *harq_out = + &test_vector.entries[DATA_HARQ_OUTPUT]; /* allocate ops mempool */ ops_pool_size = optimal_mempool_size(RTE_MAX( @@ -350,22 +456,53 @@ typedef int (test_case_function)(struct active_device *ad, socket_id); ad->hard_out_mbuf_pool = mp; - if (soft_out->nb_segments == 0) - return TEST_SUCCESS; /* Soft outputs */ - mbuf_pool_size = optimal_mempool_size(ops_pool_size * - soft_out->nb_segments); - mp = create_mbuf_pool(soft_out, ad->dev_id, socket_id, mbuf_pool_size, - "soft_out"); - TEST_ASSERT_NOT_NULL(mp, - "ERROR Failed to create %uB soft output pktmbuf pool for dev %u on socket %u.", - mbuf_pool_size, - ad->dev_id, - socket_id); - ad->soft_out_mbuf_pool = mp; + if (soft_out->nb_segments > 0) { + mbuf_pool_size = optimal_mempool_size(ops_pool_size * + soft_out->nb_segments); + mp = create_mbuf_pool(soft_out, ad->dev_id, socket_id, + mbuf_pool_size, + "soft_out"); + TEST_ASSERT_NOT_NULL(mp, + "ERROR Failed to create %uB soft output pktmbuf pool for dev %u on socket %u.", + mbuf_pool_size, + ad->dev_id, + socket_id); + ad->soft_out_mbuf_pool = mp; + } - return 0; + /* HARQ inputs */ + if (harq_in->nb_segments > 0) { + mbuf_pool_size = optimal_mempool_size(ops_pool_size * + harq_in->nb_segments); + mp = create_mbuf_pool(harq_in, ad->dev_id, socket_id, + mbuf_pool_size, + "harq_in"); + TEST_ASSERT_NOT_NULL(mp, + "ERROR Failed to create %uB harq input pktmbuf pool for dev %u on socket %u.", + mbuf_pool_size, + ad->dev_id, + socket_id); + ad->harq_in_mbuf_pool = mp; + } + + /* HARQ outputs */ + if (harq_out->nb_segments > 0) { + mbuf_pool_size = optimal_mempool_size(ops_pool_size * + harq_out->nb_segments); + mp = create_mbuf_pool(harq_out, ad->dev_id, socket_id, + mbuf_pool_size, + "harq_out"); + TEST_ASSERT_NOT_NULL(mp, + "ERROR Failed to create %uB harq output pktmbuf pool for dev %u on socket %u.", + mbuf_pool_size, + ad->dev_id, + socket_id); + ad->harq_out_mbuf_pool = mp; + } + + return TEST_SUCCESS; } static int @@ -379,7 +516,58 @@ typedef int (test_case_function)(struct active_device *ad, unsigned int nb_queues; enum rte_bbdev_op_type op_type = vector->op_type; +/* Configure fpga lte fec with PF & VF values + * if '-i' flag is set and using fpga device + */ +#ifndef RTE_BUILD_SHARED_LIB +#ifdef RTE_LIBRTE_PMD_FPGA_LTE_FEC + if ((get_init_device() == true) && + (!strcmp(info->drv.driver_name, FPGA_PF_DRIVER_NAME))) { + struct fpga_lte_fec_conf conf; + unsigned int i; + + printf("Configure FPGA FEC Driver %s with default values\n", + info->drv.driver_name); + + /* clear default configuration before initialization */ + memset(&conf, 0, sizeof(struct fpga_lte_fec_conf)); + + /* Set PF mode : + * true if PF is used for data plane + * false for VFs + */ + conf.pf_mode_en = true; + + for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) { + /* Number of UL queues per VF (fpga supports 8 VFs) */ + conf.vf_ul_queues_number[i] = VF_UL_QUEUE_VALUE; + /* Number of DL queues per VF (fpga supports 8 VFs) */ + conf.vf_dl_queues_number[i] = VF_DL_QUEUE_VALUE; + } + + /* UL bandwidth. Needed for schedule algorithm */ + conf.ul_bandwidth = UL_BANDWIDTH; + /* DL bandwidth */ + conf.dl_bandwidth = DL_BANDWIDTH; + + /* UL & DL load Balance Factor to 64 */ + conf.ul_load_balance = UL_LOAD_BALANCE; + conf.dl_load_balance = DL_LOAD_BALANCE; + + /**< FLR timeout value */ + conf.flr_time_out = FLR_TIMEOUT; + + /* setup FPGA PF with configuration information */ + ret = fpga_lte_fec_configure(info->dev_name, &conf); + TEST_ASSERT_SUCCESS(ret, + "Failed to configure 4G FPGA PF for bbdev %s", + info->dev_name); + } +#endif +#endif nb_queues = RTE_MIN(rte_lcore_count(), info->drv.max_num_queues); + nb_queues = RTE_MIN(nb_queues, (unsigned int) MAX_QUEUES); + /* setup device */ ret = rte_bbdev_setup_queues(dev_id, nb_queues, info->socket_id); if (ret < 0) { @@ -596,7 +784,7 @@ typedef int (test_case_function)(struct active_device *ad, bufs[i].offset = 0; bufs[i].length = 0; - if (op_type == DATA_INPUT) { + if ((op_type == DATA_INPUT) || (op_type == DATA_HARQ_INPUT)) { data = rte_pktmbuf_append(m_head, seg->length); TEST_ASSERT_NOT_NULL(data, "Couldn't append %u bytes to mbuf from %d data type mbuf pool", @@ -635,7 +823,6 @@ typedef int (test_case_function)(struct active_device *ad, "Couldn't chain mbufs from %d data type mbuf pool", op_type); } - } else { /* allocate chained-mbuf for output buffer */ @@ -682,7 +869,7 @@ typedef int (test_case_function)(struct active_device *ad, static void limit_input_llr_val_range(struct rte_bbdev_op_data *input_ops, - uint16_t n, int8_t max_llr_modulus) + const uint16_t n, const int8_t max_llr_modulus) { uint16_t i, byte_idx; @@ -701,10 +888,50 @@ typedef int (test_case_function)(struct active_device *ad, } } +static void +ldpc_input_llr_scaling(struct rte_bbdev_op_data *input_ops, + const uint16_t n, const int8_t llr_size, + const int8_t llr_decimals) +{ + if (input_ops == NULL) + return; + + uint16_t i, byte_idx; + + int16_t llr_max, llr_min, llr_tmp; + llr_max = (1 << (llr_size - 1)) - 1; + llr_min = -llr_max; + for (i = 0; i < n; ++i) { + struct rte_mbuf *m = input_ops[i].data; + while (m != NULL) { + int8_t *llr = rte_pktmbuf_mtod_offset(m, int8_t *, + input_ops[i].offset); + for (byte_idx = 0; byte_idx < rte_pktmbuf_data_len(m); + ++byte_idx) { + + llr_tmp = llr[byte_idx]; + if (llr_decimals == 2) + llr_tmp *= 2; + else if (llr_decimals == 0) + llr_tmp /= 2; + llr_tmp = RTE_MIN(llr_max, + RTE_MAX(llr_min, llr_tmp)); + llr[byte_idx] = (int8_t) llr_tmp; + } + + m = m->next; + } + } +} + + + static int fill_queue_buffers(struct test_op_params *op_params, struct rte_mempool *in_mp, struct rte_mempool *hard_out_mp, - struct rte_mempool *soft_out_mp, uint16_t queue_id, + struct rte_mempool *soft_out_mp, + struct rte_mempool *harq_in_mp, struct rte_mempool *harq_out_mp, + uint16_t queue_id, const struct rte_bbdev_op_cap *capabilities, uint16_t min_alignment, const int socket_id) { @@ -716,12 +943,16 @@ typedef int (test_case_function)(struct active_device *ad, in_mp, soft_out_mp, hard_out_mp, + harq_in_mp, + harq_out_mp, }; struct rte_bbdev_op_data **queue_ops[DATA_NUM_TYPES] = { &op_params->q_bufs[socket_id][queue_id].inputs, &op_params->q_bufs[socket_id][queue_id].soft_outputs, &op_params->q_bufs[socket_id][queue_id].hard_outputs, + &op_params->q_bufs[socket_id][queue_id].harq_inputs, + &op_params->q_bufs[socket_id][queue_id].harq_outputs, }; for (type = DATA_INPUT; type < DATA_NUM_TYPES; ++type) { @@ -746,6 +977,15 @@ typedef int (test_case_function)(struct active_device *ad, limit_input_llr_val_range(*queue_ops[DATA_INPUT], n, capabilities->cap.turbo_dec.max_llr_modulus); + if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) { + ldpc_input_llr_scaling(*queue_ops[DATA_INPUT], n, + capabilities->cap.ldpc_dec.llr_size, + capabilities->cap.ldpc_dec.llr_decimals); + ldpc_input_llr_scaling(*queue_ops[DATA_HARQ_INPUT], n, + capabilities->cap.ldpc_dec.llr_size, + capabilities->cap.ldpc_dec.llr_decimals); + } + return 0; } @@ -758,12 +998,16 @@ typedef int (test_case_function)(struct active_device *ad, rte_mempool_free(ad->in_mbuf_pool); rte_mempool_free(ad->hard_out_mbuf_pool); rte_mempool_free(ad->soft_out_mbuf_pool); + rte_mempool_free(ad->harq_in_mbuf_pool); + rte_mempool_free(ad->harq_out_mbuf_pool); for (i = 0; i < rte_lcore_count(); ++i) { for (j = 0; j < RTE_MAX_NUMA_NODES; ++j) { rte_free(op_params->q_bufs[j][i].inputs); rte_free(op_params->q_bufs[j][i].hard_outputs); rte_free(op_params->q_bufs[j][i].soft_outputs); + rte_free(op_params->q_bufs[j][i].harq_inputs); + rte_free(op_params->q_bufs[j][i].harq_outputs); } } } @@ -863,6 +1107,93 @@ typedef int (test_case_function)(struct active_device *ad, } } +static void +copy_reference_ldpc_dec_op(struct rte_bbdev_dec_op **ops, unsigned int n, + unsigned int start_idx, + struct rte_bbdev_op_data *inputs, + struct rte_bbdev_op_data *hard_outputs, + struct rte_bbdev_op_data *soft_outputs, + struct rte_bbdev_op_data *harq_inputs, + struct rte_bbdev_op_data *harq_outputs, + struct rte_bbdev_dec_op *ref_op) +{ + unsigned int i; + struct rte_bbdev_op_ldpc_dec *ldpc_dec = &ref_op->ldpc_dec; + + for (i = 0; i < n; ++i) { + if (ldpc_dec->code_block_mode == 0) { + ops[i]->ldpc_dec.tb_params.ea = + ldpc_dec->tb_params.ea; + ops[i]->ldpc_dec.tb_params.eb = + ldpc_dec->tb_params.eb; + ops[i]->ldpc_dec.tb_params.c = + ldpc_dec->tb_params.c; + ops[i]->ldpc_dec.tb_params.cab = + ldpc_dec->tb_params.cab; + ops[i]->ldpc_dec.tb_params.r = + ldpc_dec->tb_params.r; + } else { + ops[i]->ldpc_dec.cb_params.e = ldpc_dec->cb_params.e; + } + + ops[i]->ldpc_dec.basegraph = ldpc_dec->basegraph; + ops[i]->ldpc_dec.z_c = ldpc_dec->z_c; + ops[i]->ldpc_dec.q_m = ldpc_dec->q_m; + ops[i]->ldpc_dec.n_filler = ldpc_dec->n_filler; + ops[i]->ldpc_dec.n_cb = ldpc_dec->n_cb; + ops[i]->ldpc_dec.iter_max = ldpc_dec->iter_max; + ops[i]->ldpc_dec.rv_index = ldpc_dec->rv_index; + ops[i]->ldpc_dec.op_flags = ldpc_dec->op_flags; + ops[i]->ldpc_dec.code_block_mode = ldpc_dec->code_block_mode; + + ops[i]->ldpc_dec.hard_output = hard_outputs[start_idx + i]; + ops[i]->ldpc_dec.input = inputs[start_idx + i]; + if (soft_outputs != NULL) + ops[i]->ldpc_dec.soft_output = + soft_outputs[start_idx + i]; + if (harq_inputs != NULL) + ops[i]->ldpc_dec.harq_combined_input = + harq_inputs[start_idx + i]; + if (harq_outputs != NULL) + ops[i]->ldpc_dec.harq_combined_output = + harq_outputs[start_idx + i]; + } +} + + +static void +copy_reference_ldpc_enc_op(struct rte_bbdev_enc_op **ops, unsigned int n, + unsigned int start_idx, + struct rte_bbdev_op_data *inputs, + struct rte_bbdev_op_data *outputs, + struct rte_bbdev_enc_op *ref_op) +{ + unsigned int i; + struct rte_bbdev_op_ldpc_enc *ldpc_enc = &ref_op->ldpc_enc; + for (i = 0; i < n; ++i) { + if (ldpc_enc->code_block_mode == 0) { + ops[i]->ldpc_enc.tb_params.ea = ldpc_enc->tb_params.ea; + ops[i]->ldpc_enc.tb_params.eb = ldpc_enc->tb_params.eb; + ops[i]->ldpc_enc.tb_params.cab = + ldpc_enc->tb_params.cab; + ops[i]->ldpc_enc.tb_params.c = ldpc_enc->tb_params.c; + ops[i]->ldpc_enc.tb_params.r = ldpc_enc->tb_params.r; + } else { + ops[i]->ldpc_enc.cb_params.e = ldpc_enc->cb_params.e; + } + ops[i]->ldpc_enc.basegraph = ldpc_enc->basegraph; + ops[i]->ldpc_enc.z_c = ldpc_enc->z_c; + ops[i]->ldpc_enc.q_m = ldpc_enc->q_m; + ops[i]->ldpc_enc.n_filler = ldpc_enc->n_filler; + ops[i]->ldpc_enc.n_cb = ldpc_enc->n_cb; + ops[i]->ldpc_enc.rv_index = ldpc_enc->rv_index; + ops[i]->ldpc_enc.op_flags = ldpc_enc->op_flags; + ops[i]->ldpc_enc.code_block_mode = ldpc_enc->code_block_mode; + ops[i]->ldpc_enc.output = outputs[start_idx + i]; + ops[i]->ldpc_enc.input = inputs[start_idx + i]; + } +} + static int check_dec_status_and_ordering(struct rte_bbdev_dec_op *op, unsigned int order_idx, const int expected_status) @@ -975,6 +1306,64 @@ typedef int (test_case_function)(struct active_device *ad, return TEST_SUCCESS; } + +static int +validate_ldpc_dec_op(struct rte_bbdev_dec_op **ops, const uint16_t n, + struct rte_bbdev_dec_op *ref_op, const int vector_mask) +{ + unsigned int i; + int ret; + struct op_data_entries *hard_data_orig = + &test_vector.entries[DATA_HARD_OUTPUT]; + struct op_data_entries *soft_data_orig = + &test_vector.entries[DATA_SOFT_OUTPUT]; + struct op_data_entries *harq_data_orig = + &test_vector.entries[DATA_HARQ_OUTPUT]; + struct rte_bbdev_op_ldpc_dec *ops_td; + struct rte_bbdev_op_data *hard_output; + struct rte_bbdev_op_data *harq_output; + struct rte_bbdev_op_data *soft_output; + struct rte_bbdev_op_ldpc_dec *ref_td = &ref_op->ldpc_dec; + + for (i = 0; i < n; ++i) { + ops_td = &ops[i]->ldpc_dec; + hard_output = &ops_td->hard_output; + harq_output = &ops_td->harq_combined_output; + soft_output = &ops_td->soft_output; + + ret = check_dec_status_and_ordering(ops[i], i, ref_op->status); + TEST_ASSERT_SUCCESS(ret, + "Checking status and ordering for decoder failed"); + if (vector_mask & TEST_BBDEV_VF_EXPECTED_ITER_COUNT) + TEST_ASSERT(ops_td->iter_count <= ref_td->iter_count, + "Returned iter_count (%d) > expected iter_count (%d)", + ops_td->iter_count, ref_td->iter_count); + /* We can ignore data when the decoding failed to converge */ + if ((ops[i]->status & (1 << RTE_BBDEV_SYNDROME_ERROR)) == 0) + TEST_ASSERT_SUCCESS(validate_op_chain(hard_output, + hard_data_orig), + "Hard output buffers (CB=%u) are not equal", + i); + + if (ref_op->ldpc_dec.op_flags & RTE_BBDEV_LDPC_SOFT_OUT_ENABLE) + TEST_ASSERT_SUCCESS(validate_op_chain(soft_output, + soft_data_orig), + "Soft output buffers (CB=%u) are not equal", + i); + if (ref_op->ldpc_dec.op_flags & + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE) { + ldpc_input_llr_scaling(harq_output, 1, 8, 0); + TEST_ASSERT_SUCCESS(validate_op_chain(harq_output, + harq_data_orig), + "HARQ output buffers (CB=%u) are not equal", + i); + } + } + + return TEST_SUCCESS; +} + + static int validate_enc_op(struct rte_bbdev_enc_op **ops, const uint16_t n, struct rte_bbdev_enc_op *ref_op) @@ -998,6 +1387,29 @@ typedef int (test_case_function)(struct active_device *ad, return TEST_SUCCESS; } +static int +validate_ldpc_enc_op(struct rte_bbdev_enc_op **ops, const uint16_t n, + struct rte_bbdev_enc_op *ref_op) +{ + unsigned int i; + int ret; + struct op_data_entries *hard_data_orig = + &test_vector.entries[DATA_HARD_OUTPUT]; + + for (i = 0; i < n; ++i) { + ret = check_enc_status_and_ordering(ops[i], i, ref_op->status); + TEST_ASSERT_SUCCESS(ret, + "Checking status and ordering for encoder failed"); + TEST_ASSERT_SUCCESS(validate_op_chain( + &ops[i]->ldpc_enc.output, + hard_data_orig), + "Output buffers (CB=%u) are not equal", + i); + } + + return TEST_SUCCESS; +} + static void create_reference_dec_op(struct rte_bbdev_dec_op *op) { @@ -1012,6 +1424,27 @@ typedef int (test_case_function)(struct active_device *ad, } static void +create_reference_ldpc_dec_op(struct rte_bbdev_dec_op *op) +{ + unsigned int i; + struct op_data_entries *entry; + + op->ldpc_dec = test_vector.ldpc_dec; + entry = &test_vector.entries[DATA_INPUT]; + for (i = 0; i < entry->nb_segments; ++i) + op->ldpc_dec.input.length += + entry->segments[i].length; + if (test_vector.ldpc_dec.op_flags & + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) { + entry = &test_vector.entries[DATA_HARQ_INPUT]; + for (i = 0; i < entry->nb_segments; ++i) + op->ldpc_dec.harq_combined_input.length += + entry->segments[i].length; + } +} + + +static void create_reference_enc_op(struct rte_bbdev_enc_op *op) { unsigned int i; @@ -1024,6 +1457,19 @@ typedef int (test_case_function)(struct active_device *ad, entry->segments[i].length; } +static void +create_reference_ldpc_enc_op(struct rte_bbdev_enc_op *op) +{ + unsigned int i; + struct op_data_entries *entry; + + op->ldpc_enc = test_vector.ldpc_enc; + entry = &test_vector.entries[DATA_INPUT]; + for (i = 0; i < entry->nb_segments; ++i) + op->ldpc_enc.input.length += + entry->segments[i].length; +} + static uint32_t calc_dec_TB_size(struct rte_bbdev_dec_op *op) { @@ -1044,6 +1490,25 @@ typedef int (test_case_function)(struct active_device *ad, } static uint32_t +calc_ldpc_dec_TB_size(struct rte_bbdev_dec_op *op) +{ + uint8_t i; + uint32_t c, r, tb_size = 0; + uint16_t sys_cols = (op->ldpc_dec.basegraph == 1) ? 22 : 10; + + if (op->ldpc_dec.code_block_mode) { + tb_size = sys_cols * op->ldpc_dec.z_c - op->ldpc_dec.n_filler; + } else { + c = op->ldpc_dec.tb_params.c; + r = op->ldpc_dec.tb_params.r; + for (i = 0; i < c-r; i++) + tb_size += sys_cols * op->ldpc_dec.z_c + - op->ldpc_dec.n_filler; + } + return tb_size; +} + +static uint32_t calc_enc_TB_size(struct rte_bbdev_enc_op *op) { uint8_t i; @@ -1062,6 +1527,26 @@ typedef int (test_case_function)(struct active_device *ad, return tb_size; } +static uint32_t +calc_ldpc_enc_TB_size(struct rte_bbdev_enc_op *op) +{ + uint8_t i; + uint32_t c, r, tb_size = 0; + uint16_t sys_cols = (op->ldpc_enc.basegraph == 1) ? 22 : 10; + + if (op->turbo_enc.code_block_mode) { + tb_size = sys_cols * op->ldpc_enc.z_c - op->ldpc_enc.n_filler; + } else { + c = op->turbo_enc.tb_params.c; + r = op->turbo_enc.tb_params.r; + for (i = 0; i < c-r; i++) + tb_size += sys_cols * op->ldpc_enc.z_c + - op->ldpc_enc.n_filler; + } + return tb_size; +} + + static int init_test_op_params(struct test_op_params *op_params, enum rte_bbdev_op_type op_type, const int expected_status, @@ -1069,7 +1554,8 @@ typedef int (test_case_function)(struct active_device *ad, uint16_t burst_sz, uint16_t num_to_process, uint16_t num_lcores) { int ret = 0; - if (op_type == RTE_BBDEV_OP_TURBO_DEC) + if (op_type == RTE_BBDEV_OP_TURBO_DEC || + op_type == RTE_BBDEV_OP_LDPC_DEC) ret = rte_bbdev_dec_op_alloc_bulk(ops_mp, &op_params->ref_dec_op, 1); else @@ -1083,11 +1569,12 @@ typedef int (test_case_function)(struct active_device *ad, op_params->num_to_process = num_to_process; op_params->num_lcores = num_lcores; op_params->vector_mask = vector_mask; - if (op_type == RTE_BBDEV_OP_TURBO_DEC) + if (op_type == RTE_BBDEV_OP_TURBO_DEC || + op_type == RTE_BBDEV_OP_LDPC_DEC) op_params->ref_dec_op->status = expected_status; - else if (op_type == RTE_BBDEV_OP_TURBO_ENC) + else if (op_type == RTE_BBDEV_OP_TURBO_ENC + || op_type == RTE_BBDEV_OP_LDPC_ENC) op_params->ref_enc_op->status = expected_status; - return 0; } @@ -1133,27 +1620,35 @@ typedef int (test_case_function)(struct active_device *ad, goto fail; } - if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC) { - /* Find Decoder capabilities */ - const struct rte_bbdev_op_cap *cap = info.drv.capabilities; - while (cap->type != RTE_BBDEV_OP_NONE) { - if (cap->type == RTE_BBDEV_OP_TURBO_DEC) { - capabilities = cap; - break; - } - } - TEST_ASSERT_NOT_NULL(capabilities, - "Couldn't find Decoder capabilities"); - create_reference_dec_op(op_params->ref_dec_op); + /* Find capabilities */ + const struct rte_bbdev_op_cap *cap = info.drv.capabilities; + for (i = 0; i < RTE_BBDEV_OP_TYPE_COUNT; i++) { + if (cap->type == test_vector.op_type) { + capabilities = cap; + break; + } + cap++; + } + TEST_ASSERT_NOT_NULL(capabilities, + "Couldn't find capabilities"); + + if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC) { + create_reference_dec_op(op_params->ref_dec_op); } else if (test_vector.op_type == RTE_BBDEV_OP_TURBO_ENC) create_reference_enc_op(op_params->ref_enc_op); + else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_ENC) + create_reference_ldpc_enc_op(op_params->ref_enc_op); + else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) + create_reference_ldpc_dec_op(op_params->ref_dec_op); for (i = 0; i < ad->nb_queues; ++i) { f_ret = fill_queue_buffers(op_params, ad->in_mbuf_pool, ad->hard_out_mbuf_pool, ad->soft_out_mbuf_pool, + ad->harq_in_mbuf_pool, + ad->harq_out_mbuf_pool, ad->queue_ids[i], capabilities, info.drv.min_alignment, @@ -1212,9 +1707,7 @@ typedef int (test_case_function)(struct active_device *ad, uint16_t deq, burst_sz, num_ops; uint16_t queue_id = *(uint16_t *) ret_param; struct rte_bbdev_info info; - double tb_len_bits; - struct thread_params *tp = cb_arg; /* Find matching thread params using queue_id */ @@ -1238,7 +1731,8 @@ typedef int (test_case_function)(struct active_device *ad, burst_sz = rte_atomic16_read(&tp->burst_sz); num_ops = tp->op_params->num_to_process; - if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC) + if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC || + test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) deq = rte_bbdev_dequeue_dec_ops(dev_id, queue_id, &tp->dec_ops[ rte_atomic16_read(&tp->nb_dequeued)], @@ -1282,6 +1776,15 @@ typedef int (test_case_function)(struct active_device *ad, struct rte_bbdev_enc_op *ref_op = tp->op_params->ref_enc_op; ret = validate_enc_op(tp->enc_ops, num_ops, ref_op); rte_bbdev_enc_op_free_bulk(tp->enc_ops, deq); + } else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_ENC) { + struct rte_bbdev_enc_op *ref_op = tp->op_params->ref_enc_op; + ret = validate_ldpc_enc_op(tp->enc_ops, num_ops, ref_op); + rte_bbdev_enc_op_free_bulk(tp->enc_ops, deq); + } else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) { + struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op; + ret = validate_ldpc_dec_op(tp->dec_ops, num_ops, ref_op, + tp->op_params->vector_mask); + rte_bbdev_dec_op_free_bulk(tp->dec_ops, deq); } if (ret) { @@ -1296,6 +1799,12 @@ typedef int (test_case_function)(struct active_device *ad, case RTE_BBDEV_OP_TURBO_ENC: tb_len_bits = calc_enc_TB_size(tp->op_params->ref_enc_op); break; + case RTE_BBDEV_OP_LDPC_DEC: + tb_len_bits = calc_ldpc_dec_TB_size(tp->op_params->ref_dec_op); + break; + case RTE_BBDEV_OP_LDPC_ENC: + tb_len_bits = calc_ldpc_enc_TB_size(tp->op_params->ref_enc_op); + break; case RTE_BBDEV_OP_NONE: tb_len_bits = 0.0; break; @@ -1375,8 +1884,8 @@ typedef int (test_case_function)(struct active_device *ad, enq = 0; do { enq += rte_bbdev_enqueue_dec_ops(tp->dev_id, - queue_id, &ops[enqueued], - num_to_enq); + queue_id, &ops[enqueued], + num_to_enq); } while (unlikely(num_to_enq != enq)); enqueued += enq; @@ -1390,7 +1899,7 @@ typedef int (test_case_function)(struct active_device *ad, rte_atomic16_set(&tp->burst_sz, num_to_enq); /* Wait until processing of previous batch is - * completed. + * completed */ while (rte_atomic16_read(&tp->nb_dequeued) != (int16_t) enqueued) @@ -1479,7 +1988,7 @@ typedef int (test_case_function)(struct active_device *ad, rte_atomic16_set(&tp->burst_sz, num_to_enq); /* Wait until processing of previous batch is - * completed. + * completed */ while (rte_atomic16_read(&tp->nb_dequeued) != (int16_t) enqueued) @@ -1590,6 +2099,116 @@ typedef int (test_case_function)(struct active_device *ad, } static int +throughput_pmd_lcore_ldpc_dec(void *arg) +{ + struct thread_params *tp = arg; + uint16_t enq, deq; + uint64_t total_time = 0, start_time; + const uint16_t queue_id = tp->queue_id; + const uint16_t burst_sz = tp->op_params->burst_sz; + const uint16_t num_ops = tp->op_params->num_to_process; + struct rte_bbdev_dec_op *ops_enq[num_ops]; + struct rte_bbdev_dec_op *ops_deq[num_ops]; + struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op; + struct test_buffers *bufs = NULL; + int i, j, ret; + struct rte_bbdev_info info; + uint16_t num_to_enq; + + TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST), + "BURST_SIZE should be <= %u", MAX_BURST); + + rte_bbdev_info_get(tp->dev_id, &info); + + TEST_ASSERT_SUCCESS((num_ops > info.drv.queue_size_lim), + "NUM_OPS cannot exceed %u for this device", + info.drv.queue_size_lim); + + bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id]; + + while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT) + rte_pause(); + + ret = rte_bbdev_dec_op_alloc_bulk(tp->op_params->mp, ops_enq, num_ops); + TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", num_ops); + + /* For throughput tests we need to disable early termination */ + if (check_bit(ref_op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE)) + ref_op->ldpc_dec.op_flags -= + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE; + ref_op->ldpc_dec.iter_max = 6; + ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max; + + if (test_vector.op_type != RTE_BBDEV_OP_NONE) + copy_reference_ldpc_dec_op(ops_enq, num_ops, 0, bufs->inputs, + bufs->hard_outputs, bufs->soft_outputs, + bufs->harq_inputs, bufs->harq_outputs, ref_op); + + /* Set counter to validate the ordering */ + for (j = 0; j < num_ops; ++j) + ops_enq[j]->opaque_data = (void *)(uintptr_t)j; + + for (i = 0; i < TEST_REPETITIONS; ++i) { + for (j = 0; j < num_ops; ++j) { + mbuf_reset(ops_enq[j]->ldpc_dec.hard_output.data); + if (check_bit(ref_op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) + mbuf_reset( + ops_enq[j]->ldpc_dec.harq_combined_output.data); + } + + start_time = rte_rdtsc_precise(); + + for (enq = 0, deq = 0; enq < num_ops;) { + num_to_enq = burst_sz; + + if (unlikely(num_ops - enq < num_to_enq)) + num_to_enq = num_ops - enq; + + enq += rte_bbdev_enqueue_ldpc_dec_ops(tp->dev_id, + queue_id, &ops_enq[enq], num_to_enq); + + deq += rte_bbdev_dequeue_ldpc_dec_ops(tp->dev_id, + queue_id, &ops_deq[deq], enq - deq); + } + + /* dequeue the remaining */ + while (deq < enq) { + deq += rte_bbdev_dequeue_ldpc_dec_ops(tp->dev_id, + queue_id, &ops_deq[deq], enq - deq); + } + + total_time += rte_rdtsc_precise() - start_time; + } + + tp->iter_count = 0; + /* get the max of iter_count for all dequeued ops */ + for (i = 0; i < num_ops; ++i) { + tp->iter_count = RTE_MAX(ops_enq[i]->ldpc_dec.iter_count, + tp->iter_count); + } + + if (test_vector.op_type != RTE_BBDEV_OP_NONE) { + ret = validate_ldpc_dec_op(ops_deq, num_ops, ref_op, + tp->op_params->vector_mask); + TEST_ASSERT_SUCCESS(ret, "Validation failed!"); + } + + rte_bbdev_dec_op_free_bulk(ops_enq, num_ops); + + double tb_len_bits = calc_ldpc_dec_TB_size(ref_op); + + tp->ops_per_sec = ((double)num_ops * TEST_REPETITIONS) / + ((double)total_time / (double)rte_get_tsc_hz()); + tp->mbps = (((double)(num_ops * TEST_REPETITIONS * tb_len_bits)) / + 1000000.0) / ((double)total_time / + (double)rte_get_tsc_hz()); + + return TEST_SUCCESS; +} + +static int throughput_pmd_lcore_enc(void *arg) { struct thread_params *tp = arg; @@ -1667,6 +2286,8 @@ typedef int (test_case_function)(struct active_device *ad, TEST_ASSERT_SUCCESS(ret, "Validation failed!"); } + rte_bbdev_enc_op_free_bulk(ops_enq, num_ops); + double tb_len_bits = calc_enc_TB_size(ref_op); tp->ops_per_sec = ((double)num_ops * TEST_REPETITIONS) / @@ -1678,6 +2299,97 @@ typedef int (test_case_function)(struct active_device *ad, return TEST_SUCCESS; } +static int +throughput_pmd_lcore_ldpc_enc(void *arg) +{ + struct thread_params *tp = arg; + uint16_t enq, deq; + uint64_t total_time = 0, start_time; + const uint16_t queue_id = tp->queue_id; + const uint16_t burst_sz = tp->op_params->burst_sz; + const uint16_t num_ops = tp->op_params->num_to_process; + struct rte_bbdev_enc_op *ops_enq[num_ops]; + struct rte_bbdev_enc_op *ops_deq[num_ops]; + struct rte_bbdev_enc_op *ref_op = tp->op_params->ref_enc_op; + struct test_buffers *bufs = NULL; + int i, j, ret; + struct rte_bbdev_info info; + uint16_t num_to_enq; + + TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST), + "BURST_SIZE should be <= %u", MAX_BURST); + + rte_bbdev_info_get(tp->dev_id, &info); + + TEST_ASSERT_SUCCESS((num_ops > info.drv.queue_size_lim), + "NUM_OPS cannot exceed %u for this device", + info.drv.queue_size_lim); + + bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id]; + + while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT) + rte_pause(); + + ret = rte_bbdev_enc_op_alloc_bulk(tp->op_params->mp, ops_enq, + num_ops); + TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", + num_ops); + if (test_vector.op_type != RTE_BBDEV_OP_NONE) + copy_reference_ldpc_enc_op(ops_enq, num_ops, 0, bufs->inputs, + bufs->hard_outputs, ref_op); + + /* Set counter to validate the ordering */ + for (j = 0; j < num_ops; ++j) + ops_enq[j]->opaque_data = (void *)(uintptr_t)j; + + for (i = 0; i < TEST_REPETITIONS; ++i) { + + if (test_vector.op_type != RTE_BBDEV_OP_NONE) + for (j = 0; j < num_ops; ++j) + mbuf_reset(ops_enq[j]->turbo_enc.output.data); + + start_time = rte_rdtsc_precise(); + + for (enq = 0, deq = 0; enq < num_ops;) { + num_to_enq = burst_sz; + + if (unlikely(num_ops - enq < num_to_enq)) + num_to_enq = num_ops - enq; + + enq += rte_bbdev_enqueue_ldpc_enc_ops(tp->dev_id, + queue_id, &ops_enq[enq], num_to_enq); + + deq += rte_bbdev_dequeue_ldpc_enc_ops(tp->dev_id, + queue_id, &ops_deq[deq], enq - deq); + } + + /* dequeue the remaining */ + while (deq < enq) { + deq += rte_bbdev_dequeue_ldpc_enc_ops(tp->dev_id, + queue_id, &ops_deq[deq], enq - deq); + } + + total_time += rte_rdtsc_precise() - start_time; + } + + if (test_vector.op_type != RTE_BBDEV_OP_NONE) { + ret = validate_ldpc_enc_op(ops_deq, num_ops, ref_op); + TEST_ASSERT_SUCCESS(ret, "Validation failed!"); + } + + rte_bbdev_enc_op_free_bulk(ops_enq, num_ops); + + double tb_len_bits = calc_ldpc_enc_TB_size(ref_op); + + tp->ops_per_sec = ((double)num_ops * TEST_REPETITIONS) / + ((double)total_time / (double)rte_get_tsc_hz()); + tp->mbps = (((double)(num_ops * TEST_REPETITIONS * tb_len_bits)) + / 1000000.0) / ((double)total_time / + (double)rte_get_tsc_hz()); + + return TEST_SUCCESS; +} + static void print_enc_throughput(struct thread_params *t_params, unsigned int used_cores) { @@ -1740,8 +2452,8 @@ typedef int (test_case_function)(struct active_device *ad, TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u", test_vector.op_type); - printf( - "Throughput test: dev: %s, nb_queues: %u, burst size: %u, num ops: %u, num_lcores: %u, op type: %s, int mode: %s, GHz: %lg\n", + printf("+ ------------------------------------------------------- +\n"); + printf("== test: throughput\ndev: %s, nb_queues: %u, burst size: %u, num ops: %u, num_lcores: %u, op type: %s, itr mode: %s, GHz: %lg\n", info.dev_name, ad->nb_queues, op_params->burst_sz, op_params->num_to_process, op_params->num_lcores, op_type_str, @@ -1763,6 +2475,12 @@ typedef int (test_case_function)(struct active_device *ad, if (intr_enabled) { if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC) throughput_function = throughput_intr_lcore_dec; + else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) + throughput_function = throughput_intr_lcore_dec; + else if (test_vector.op_type == RTE_BBDEV_OP_TURBO_ENC) + throughput_function = throughput_intr_lcore_enc; + else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_ENC) + throughput_function = throughput_intr_lcore_enc; else throughput_function = throughput_intr_lcore_enc; @@ -1777,6 +2495,12 @@ typedef int (test_case_function)(struct active_device *ad, } else { if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC) throughput_function = throughput_pmd_lcore_dec; + else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) + throughput_function = throughput_pmd_lcore_ldpc_dec; + else if (test_vector.op_type == RTE_BBDEV_OP_TURBO_ENC) + throughput_function = throughput_pmd_lcore_enc; + else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_ENC) + throughput_function = throughput_pmd_lcore_ldpc_enc; else throughput_function = throughput_pmd_lcore_enc; } @@ -1819,7 +2543,8 @@ typedef int (test_case_function)(struct active_device *ad, /* Print throughput if interrupts are disabled and test passed */ if (!intr_enabled) { - if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC) + if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC || + test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) print_dec_throughput(t_params, num_lcores); else print_enc_throughput(t_params, num_lcores); @@ -1841,7 +2566,7 @@ typedef int (test_case_function)(struct active_device *ad, tp->ops_per_sec /= TEST_REPETITIONS; tp->mbps /= TEST_REPETITIONS; - ret |= rte_atomic16_read(&tp->processing_status); + ret |= (int)rte_atomic16_read(&tp->processing_status); /* Wait for slave lcores operations */ for (used_cores = 1; used_cores < num_lcores; used_cores++) { @@ -1855,14 +2580,16 @@ typedef int (test_case_function)(struct active_device *ad, tp->ops_per_sec /= TEST_REPETITIONS; tp->mbps /= TEST_REPETITIONS; - ret |= rte_atomic16_read(&tp->processing_status); + ret |= (int)rte_atomic16_read(&tp->processing_status); } /* Print throughput if test passed */ if (!ret) { - if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC) + if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC || + test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) print_dec_throughput(t_params, num_lcores); - else if (test_vector.op_type == RTE_BBDEV_OP_TURBO_ENC) + else if (test_vector.op_type == RTE_BBDEV_OP_TURBO_ENC || + test_vector.op_type == RTE_BBDEV_OP_LDPC_ENC) print_enc_throughput(t_params, num_lcores); } @@ -1940,6 +2667,77 @@ typedef int (test_case_function)(struct active_device *ad, } static int +latency_test_ldpc_dec(struct rte_mempool *mempool, + struct test_buffers *bufs, struct rte_bbdev_dec_op *ref_op, + int vector_mask, uint16_t dev_id, uint16_t queue_id, + const uint16_t num_to_process, uint16_t burst_sz, + uint64_t *total_time, uint64_t *min_time, uint64_t *max_time) +{ + int ret = TEST_SUCCESS; + uint16_t i, j, dequeued; + struct rte_bbdev_dec_op *ops_enq[MAX_BURST], *ops_deq[MAX_BURST]; + uint64_t start_time = 0, last_time = 0; + + for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) { + uint16_t enq = 0, deq = 0; + bool first_time = true; + last_time = 0; + + if (unlikely(num_to_process - dequeued < burst_sz)) + burst_sz = num_to_process - dequeued; + + ret = rte_bbdev_dec_op_alloc_bulk(mempool, ops_enq, burst_sz); + TEST_ASSERT_SUCCESS(ret, + "rte_bbdev_dec_op_alloc_bulk() failed"); + if (test_vector.op_type != RTE_BBDEV_OP_NONE) + copy_reference_ldpc_dec_op(ops_enq, burst_sz, dequeued, + bufs->inputs, + bufs->hard_outputs, + bufs->soft_outputs, + bufs->harq_inputs, + bufs->harq_outputs, + ref_op); + + /* Set counter to validate the ordering */ + for (j = 0; j < burst_sz; ++j) + ops_enq[j]->opaque_data = (void *)(uintptr_t)j; + + start_time = rte_rdtsc_precise(); + + enq = rte_bbdev_enqueue_ldpc_dec_ops(dev_id, queue_id, + &ops_enq[enq], burst_sz); + TEST_ASSERT(enq == burst_sz, + "Error enqueueing burst, expected %u, got %u", + burst_sz, enq); + + /* Dequeue */ + do { + deq += rte_bbdev_dequeue_ldpc_dec_ops(dev_id, queue_id, + &ops_deq[deq], burst_sz - deq); + if (likely(first_time && (deq > 0))) { + last_time = rte_rdtsc_precise() - start_time; + first_time = false; + } + } while (unlikely(burst_sz != deq)); + + *max_time = RTE_MAX(*max_time, last_time); + *min_time = RTE_MIN(*min_time, last_time); + *total_time += last_time; + + if (test_vector.op_type != RTE_BBDEV_OP_NONE) { + ret = validate_ldpc_dec_op(ops_deq, burst_sz, ref_op, + vector_mask); + TEST_ASSERT_SUCCESS(ret, "Validation failed!"); + } + + rte_bbdev_dec_op_free_bulk(ops_enq, deq); + dequeued += deq; + } + + return i; +} + +static int latency_test_enc(struct rte_mempool *mempool, struct test_buffers *bufs, struct rte_bbdev_enc_op *ref_op, uint16_t dev_id, uint16_t queue_id, @@ -2007,6 +2805,84 @@ typedef int (test_case_function)(struct active_device *ad, } static int +latency_test_ldpc_enc(struct rte_mempool *mempool, + struct test_buffers *bufs, struct rte_bbdev_enc_op *ref_op, + uint16_t dev_id, uint16_t queue_id, + const uint16_t num_to_process, uint16_t burst_sz, + uint64_t *total_time, uint64_t *min_time, uint64_t *max_time) +{ + int ret = TEST_SUCCESS; + uint16_t i, j, dequeued; + struct rte_bbdev_enc_op *ops_enq[MAX_BURST], *ops_deq[MAX_BURST]; + uint64_t start_time = 0, last_time = 0; + + for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) { + uint16_t enq = 0, deq = 0; + bool first_time = true; + last_time = 0; + + if (unlikely(num_to_process - dequeued < burst_sz)) + burst_sz = num_to_process - dequeued; + + ret = rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz); + + TEST_ASSERT_SUCCESS(ret, + "rte_bbdev_enc_op_alloc_bulk() failed"); + if (test_vector.op_type != RTE_BBDEV_OP_NONE) + copy_reference_ldpc_enc_op(ops_enq, burst_sz, dequeued, + bufs->inputs, + bufs->hard_outputs, + ref_op); + + /* Set counter to validate the ordering */ + for (j = 0; j < burst_sz; ++j) + ops_enq[j]->opaque_data = (void *)(uintptr_t)j; + + start_time = rte_rdtsc_precise(); + + /* + * printf("Latency Debug %d\n", + * ops_enq[0]->ldpc_enc.cb_params.z_c); REMOVEME + */ + + enq = rte_bbdev_enqueue_ldpc_enc_ops(dev_id, queue_id, + &ops_enq[enq], burst_sz); + TEST_ASSERT(enq == burst_sz, + "Error enqueueing burst, expected %u, got %u", + burst_sz, enq); + + /* Dequeue */ + do { + deq += rte_bbdev_dequeue_ldpc_enc_ops(dev_id, queue_id, + &ops_deq[deq], burst_sz - deq); + if (likely(first_time && (deq > 0))) { + last_time += rte_rdtsc_precise() - start_time; + first_time = false; + } + } while (unlikely(burst_sz != deq)); + + *max_time = RTE_MAX(*max_time, last_time); + *min_time = RTE_MIN(*min_time, last_time); + *total_time += last_time; + + if (test_vector.op_type != RTE_BBDEV_OP_NONE) { + ret = validate_enc_op(ops_deq, burst_sz, ref_op); + TEST_ASSERT_SUCCESS(ret, "Validation failed!"); + } + + /* + * printf("Ready to free - deq %d num_to_process %d\n", FIXME + * deq, num_to_process); + * printf("cache %d\n", ops_enq[0]->mempool->cache_size); + */ + rte_bbdev_enc_op_free_bulk(ops_enq, deq); + dequeued += deq; + } + + return i; +} + +static int latency_test(struct active_device *ad, struct test_op_params *op_params) { @@ -2032,8 +2908,8 @@ typedef int (test_case_function)(struct active_device *ad, op_type_str = rte_bbdev_op_type_str(op_type); TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u", op_type); - printf( - "\nValidation/Latency test: dev: %s, burst size: %u, num ops: %u, op type: %s\n", + printf("+ ------------------------------------------------------- +\n"); + printf("== test: validation/latency\ndev: %s, burst size: %u, num ops: %u, op type: %s\n", info.dev_name, burst_sz, num_to_process, op_type_str); if (op_type == RTE_BBDEV_OP_TURBO_DEC) @@ -2041,19 +2917,35 @@ typedef int (test_case_function)(struct active_device *ad, op_params->ref_dec_op, op_params->vector_mask, ad->dev_id, queue_id, num_to_process, burst_sz, &total_time, &min_time, &max_time); - else + else if (op_type == RTE_BBDEV_OP_TURBO_ENC) iter = latency_test_enc(op_params->mp, bufs, op_params->ref_enc_op, ad->dev_id, queue_id, num_to_process, burst_sz, &total_time, &min_time, &max_time); + else if (op_type == RTE_BBDEV_OP_LDPC_ENC) + iter = latency_test_ldpc_enc(op_params->mp, bufs, + op_params->ref_enc_op, ad->dev_id, queue_id, + num_to_process, burst_sz, &total_time, + &min_time, &max_time); + else if (op_type == RTE_BBDEV_OP_LDPC_DEC) + iter = latency_test_ldpc_dec(op_params->mp, bufs, + op_params->ref_dec_op, op_params->vector_mask, + ad->dev_id, queue_id, num_to_process, + burst_sz, &total_time, &min_time, &max_time); + else + iter = latency_test_enc(op_params->mp, bufs, + op_params->ref_enc_op, + ad->dev_id, queue_id, + num_to_process, burst_sz, &total_time, + &min_time, &max_time); if (iter <= 0) return TEST_FAILED; printf("Operation latency:\n" - "\tavg latency: %lg cycles, %lg us\n" - "\tmin latency: %lg cycles, %lg us\n" - "\tmax latency: %lg cycles, %lg us\n", + "\tavg: %lg cycles, %lg us\n" + "\tmin: %lg cycles, %lg us\n" + "\tmax: %lg cycles, %lg us\n", (double)total_time / (double)iter, (double)(total_time * 1000000) / (double)iter / (double)rte_get_tsc_hz(), (double)min_time, @@ -2104,10 +2996,7 @@ typedef int (test_case_function)(struct active_device *ad, if (unlikely(num_to_process - dequeued < burst_sz)) burst_sz = num_to_process - dequeued; - ret = rte_bbdev_dec_op_alloc_bulk(mempool, ops_enq, burst_sz); - TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", - burst_sz); - + rte_bbdev_dec_op_alloc_bulk(mempool, ops_enq, burst_sz); if (test_vector.op_type != RTE_BBDEV_OP_NONE) copy_reference_dec_op(ops_enq, burst_sz, dequeued, bufs->inputs, @@ -2141,7 +3030,7 @@ typedef int (test_case_function)(struct active_device *ad, stats.acc_offload_cycles); time_st->enq_acc_total_time += stats.acc_offload_cycles; - /* ensure enqueue has been completed */ + /* give time for device to process ops */ rte_delay_us(200); /* Start time meas for dequeue function offload latency */ @@ -2172,6 +3061,91 @@ typedef int (test_case_function)(struct active_device *ad, } static int +offload_latency_test_ldpc_dec(struct rte_mempool *mempool, + struct test_buffers *bufs, + struct rte_bbdev_dec_op *ref_op, uint16_t dev_id, + uint16_t queue_id, const uint16_t num_to_process, + uint16_t burst_sz, struct test_time_stats *time_st) +{ + int i, dequeued, ret; + struct rte_bbdev_dec_op *ops_enq[MAX_BURST], *ops_deq[MAX_BURST]; + uint64_t enq_start_time, deq_start_time; + uint64_t enq_sw_last_time, deq_last_time; + struct rte_bbdev_stats stats; + + for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) { + uint16_t enq = 0, deq = 0; + + if (unlikely(num_to_process - dequeued < burst_sz)) + burst_sz = num_to_process - dequeued; + + rte_bbdev_dec_op_alloc_bulk(mempool, ops_enq, burst_sz); + if (test_vector.op_type != RTE_BBDEV_OP_NONE) + copy_reference_ldpc_dec_op(ops_enq, burst_sz, dequeued, + bufs->inputs, + bufs->hard_outputs, + bufs->soft_outputs, + bufs->harq_inputs, + bufs->harq_outputs, + ref_op); + + /* Start time meas for enqueue function offload latency */ + enq_start_time = rte_rdtsc_precise(); + do { + enq += rte_bbdev_enqueue_ldpc_dec_ops(dev_id, queue_id, + &ops_enq[enq], burst_sz - enq); + } while (unlikely(burst_sz != enq)); + + ret = get_bbdev_queue_stats(dev_id, queue_id, &stats); + TEST_ASSERT_SUCCESS(ret, + "Failed to get stats for queue (%u) of device (%u)", + queue_id, dev_id); + + enq_sw_last_time = rte_rdtsc_precise() - enq_start_time - + stats.acc_offload_cycles; + time_st->enq_sw_max_time = RTE_MAX(time_st->enq_sw_max_time, + enq_sw_last_time); + time_st->enq_sw_min_time = RTE_MIN(time_st->enq_sw_min_time, + enq_sw_last_time); + time_st->enq_sw_total_time += enq_sw_last_time; + + time_st->enq_acc_max_time = RTE_MAX(time_st->enq_acc_max_time, + stats.acc_offload_cycles); + time_st->enq_acc_min_time = RTE_MIN(time_st->enq_acc_min_time, + stats.acc_offload_cycles); + time_st->enq_acc_total_time += stats.acc_offload_cycles; + + /* give time for device to process ops */ + rte_delay_us(200); + + /* Start time meas for dequeue function offload latency */ + deq_start_time = rte_rdtsc_precise(); + /* Dequeue one operation */ + do { + deq += rte_bbdev_dequeue_ldpc_dec_ops(dev_id, queue_id, + &ops_deq[deq], 1); + } while (unlikely(deq != 1)); + + deq_last_time = rte_rdtsc_precise() - deq_start_time; + time_st->deq_max_time = RTE_MAX(time_st->deq_max_time, + deq_last_time); + time_st->deq_min_time = RTE_MIN(time_st->deq_min_time, + deq_last_time); + time_st->deq_total_time += deq_last_time; + + /* Dequeue remaining operations if needed*/ + while (burst_sz != deq) + deq += rte_bbdev_dequeue_dec_ops(dev_id, queue_id, + &ops_deq[deq], burst_sz - deq); + + rte_bbdev_dec_op_free_bulk(ops_enq, deq); + dequeued += deq; + } + + return i; +} + +static int offload_latency_test_enc(struct rte_mempool *mempool, struct test_buffers *bufs, struct rte_bbdev_enc_op *ref_op, uint16_t dev_id, uint16_t queue_id, const uint16_t num_to_process, @@ -2189,10 +3163,7 @@ typedef int (test_case_function)(struct active_device *ad, if (unlikely(num_to_process - dequeued < burst_sz)) burst_sz = num_to_process - dequeued; - ret = rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz); - TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", - burst_sz); - + rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz); if (test_vector.op_type != RTE_BBDEV_OP_NONE) copy_reference_enc_op(ops_enq, burst_sz, dequeued, bufs->inputs, @@ -2225,7 +3196,7 @@ typedef int (test_case_function)(struct active_device *ad, stats.acc_offload_cycles); time_st->enq_acc_total_time += stats.acc_offload_cycles; - /* ensure enqueue has been completed */ + /* give time for device to process ops */ rte_delay_us(200); /* Start time meas for dequeue function offload latency */ @@ -2253,6 +3224,87 @@ typedef int (test_case_function)(struct active_device *ad, return i; } + +static int +offload_latency_test_ldpc_enc(struct rte_mempool *mempool, + struct test_buffers *bufs, + struct rte_bbdev_enc_op *ref_op, uint16_t dev_id, + uint16_t queue_id, const uint16_t num_to_process, + uint16_t burst_sz, struct test_time_stats *time_st) +{ + int i, dequeued, ret; + struct rte_bbdev_enc_op *ops_enq[MAX_BURST], *ops_deq[MAX_BURST]; + uint64_t enq_start_time, deq_start_time; + uint64_t enq_sw_last_time, deq_last_time; + struct rte_bbdev_stats stats; + + for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) { + uint16_t enq = 0, deq = 0; + + if (unlikely(num_to_process - dequeued < burst_sz)) + burst_sz = num_to_process - dequeued; + + rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz); + if (test_vector.op_type != RTE_BBDEV_OP_NONE) + copy_reference_ldpc_enc_op(ops_enq, burst_sz, dequeued, + bufs->inputs, + bufs->hard_outputs, + ref_op); + + /* Start time meas for enqueue function offload latency */ + enq_start_time = rte_rdtsc_precise(); + do { + enq += rte_bbdev_enqueue_ldpc_enc_ops(dev_id, queue_id, + &ops_enq[enq], burst_sz - enq); + } while (unlikely(burst_sz != enq)); + + ret = get_bbdev_queue_stats(dev_id, queue_id, &stats); + TEST_ASSERT_SUCCESS(ret, + "Failed to get stats for queue (%u) of device (%u)", + queue_id, dev_id); + + enq_sw_last_time = rte_rdtsc_precise() - enq_start_time - + stats.acc_offload_cycles; + time_st->enq_sw_max_time = RTE_MAX(time_st->enq_sw_max_time, + enq_sw_last_time); + time_st->enq_sw_min_time = RTE_MIN(time_st->enq_sw_min_time, + enq_sw_last_time); + time_st->enq_sw_total_time += enq_sw_last_time; + + time_st->enq_acc_max_time = RTE_MAX(time_st->enq_acc_max_time, + stats.acc_offload_cycles); + time_st->enq_acc_min_time = RTE_MIN(time_st->enq_acc_min_time, + stats.acc_offload_cycles); + time_st->enq_acc_total_time += stats.acc_offload_cycles; + + /* give time for device to process ops */ + rte_delay_us(200); + + /* Start time meas for dequeue function offload latency */ + deq_start_time = rte_rdtsc_precise(); + /* Dequeue one operation */ + do { + deq += rte_bbdev_dequeue_ldpc_enc_ops(dev_id, queue_id, + &ops_deq[deq], 1); + } while (unlikely(deq != 1)); + + deq_last_time = rte_rdtsc_precise() - deq_start_time; + time_st->deq_max_time = RTE_MAX(time_st->deq_max_time, + deq_last_time); + time_st->deq_min_time = RTE_MIN(time_st->deq_min_time, + deq_last_time); + time_st->deq_total_time += deq_last_time; + + while (burst_sz != deq) + deq += rte_bbdev_dequeue_ldpc_enc_ops(dev_id, queue_id, + &ops_deq[deq], burst_sz - deq); + + rte_bbdev_enc_op_free_bulk(ops_enq, deq); + dequeued += deq; + } + + return i; +} #endif static int @@ -2290,14 +3342,26 @@ typedef int (test_case_function)(struct active_device *ad, op_type_str = rte_bbdev_op_type_str(op_type); TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u", op_type); - printf( - "\nOffload latency test: dev: %s, burst size: %u, num ops: %u, op type: %s\n", + printf("+ ------------------------------------------------------- +\n"); + printf("== test: offload latency test\ndev: %s, burst size: %u, num ops: %u, op type: %s\n", info.dev_name, burst_sz, num_to_process, op_type_str); if (op_type == RTE_BBDEV_OP_TURBO_DEC) iter = offload_latency_test_dec(op_params->mp, bufs, op_params->ref_dec_op, ad->dev_id, queue_id, num_to_process, burst_sz, &time_st); + else if (op_type == RTE_BBDEV_OP_TURBO_ENC) + iter = offload_latency_test_enc(op_params->mp, bufs, + op_params->ref_enc_op, ad->dev_id, queue_id, + num_to_process, burst_sz, &time_st); + else if (op_type == RTE_BBDEV_OP_LDPC_ENC) + iter = offload_latency_test_ldpc_enc(op_params->mp, bufs, + op_params->ref_enc_op, ad->dev_id, queue_id, + num_to_process, burst_sz, &time_st); + else if (op_type == RTE_BBDEV_OP_LDPC_DEC) + iter = offload_latency_test_ldpc_dec(op_params->mp, bufs, + op_params->ref_dec_op, ad->dev_id, queue_id, + num_to_process, burst_sz, &time_st); else iter = offload_latency_test_enc(op_params->mp, bufs, op_params->ref_enc_op, ad->dev_id, queue_id, @@ -2306,13 +3370,14 @@ typedef int (test_case_function)(struct active_device *ad, if (iter <= 0) return TEST_FAILED; - printf("Enqueue offload cost latency:\n" - "\tDriver offload avg %lg cycles, %lg us\n" - "\tDriver offload min %lg cycles, %lg us\n" - "\tDriver offload max %lg cycles, %lg us\n" - "\tAccelerator offload avg %lg cycles, %lg us\n" - "\tAccelerator offload min %lg cycles, %lg us\n" - "\tAccelerator offload max %lg cycles, %lg us\n", + printf("Enqueue driver offload cost latency:\n" + "\tavg: %lg cycles, %lg us\n" + "\tmin: %lg cycles, %lg us\n" + "\tmax: %lg cycles, %lg us\n" + "Enqueue accelerator offload cost latency:\n" + "\tavg: %lg cycles, %lg us\n" + "\tmin: %lg cycles, %lg us\n" + "\tmax: %lg cycles, %lg us\n", (double)time_st.enq_sw_total_time / (double)iter, (double)(time_st.enq_sw_total_time * 1000000) / (double)iter / (double)rte_get_tsc_hz(), @@ -2331,9 +3396,9 @@ typedef int (test_case_function)(struct active_device *ad, rte_get_tsc_hz()); printf("Dequeue offload cost latency - one op:\n" - "\tavg %lg cycles, %lg us\n" - "\tmin %lg cycles, %lg us\n" - "\tmax %lg cycles, %lg us\n", + "\tavg: %lg cycles, %lg us\n" + "\tmin: %lg cycles, %lg us\n" + "\tmax: %lg cycles, %lg us\n", (double)time_st.deq_total_time / (double)iter, (double)(time_st.deq_total_time * 1000000) / (double)iter / (double)rte_get_tsc_hz(), @@ -2437,8 +3502,8 @@ typedef int (test_case_function)(struct active_device *ad, op_type_str = rte_bbdev_op_type_str(op_type); TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u", op_type); - printf( - "\nOffload latency empty dequeue test: dev: %s, burst size: %u, num ops: %u, op type: %s\n", + printf("+ ------------------------------------------------------- +\n"); + printf("== test: offload latency empty dequeue\ndev: %s, burst size: %u, num ops: %u, op type: %s\n", info.dev_name, burst_sz, num_to_process, op_type_str); if (op_type == RTE_BBDEV_OP_TURBO_DEC) @@ -2453,10 +3518,10 @@ typedef int (test_case_function)(struct active_device *ad, if (iter <= 0) return TEST_FAILED; - printf("Empty dequeue offload\n" - "\tavg. latency: %lg cycles, %lg us\n" - "\tmin. latency: %lg cycles, %lg us\n" - "\tmax. latency: %lg cycles, %lg us\n", + printf("Empty dequeue offload:\n" + "\tavg: %lg cycles, %lg us\n" + "\tmin: %lg cycles, %lg us\n" + "\tmax: %lg cycles, %lg us\n", (double)deq_total_time / (double)iter, (double)(deq_total_time * 1000000) / (double)iter / (double)rte_get_tsc_hz(), (double)deq_min_time, diff --git a/app/test-bbdev/test_bbdev_vector.c b/app/test-bbdev/test_bbdev_vector.c index e149ced..d478d76 100644 --- a/app/test-bbdev/test_bbdev_vector.c +++ b/app/test-bbdev/test_bbdev_vector.c @@ -2,7 +2,7 @@ * Copyright(c) 2017 Intel Corporation */ -#ifdef RTE_EXEC_ENV_FREEBSD +#ifdef RTE_EXEC_ENV_BSDAPP #define _WITH_GETLINE #endif #include @@ -18,6 +18,8 @@ "input", "soft_output", "hard_output", + "harq_input", + "harq_output", }; /* trim leading and trailing spaces */ @@ -84,6 +86,7 @@ } values[n_tokens] = (uint32_t) strtoul(tok, &error, 0); + if ((error == NULL) || (*error != '\0')) { printf("Failed with convert '%s'\n", tok); rte_free(values); @@ -154,6 +157,54 @@ return 0; } +/* convert LDPC flag from string to unsigned long int*/ +static int +op_ldpc_decoder_flag_strtoul(char *token, uint32_t *op_flag_value) +{ + if (!strcmp(token, "RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK")) + *op_flag_value = RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK; + else if (!strcmp(token, "RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK")) + *op_flag_value = RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK; + else if (!strcmp(token, "RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP")) + *op_flag_value = RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP; + else if (!strcmp(token, "RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS")) + *op_flag_value = RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS; + else if (!strcmp(token, "RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE")) + *op_flag_value = RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + else if (!strcmp(token, "RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE")) + *op_flag_value = RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE; + else if (!strcmp(token, "RTE_BBDEV_LDPC_DECODE_BYPASS")) + *op_flag_value = RTE_BBDEV_LDPC_DECODE_BYPASS; + else if (!strcmp(token, "RTE_BBDEV_LDPC_SOFT_OUT_ENABLE")) + *op_flag_value = RTE_BBDEV_LDPC_SOFT_OUT_ENABLE; + else if (!strcmp(token, "RTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS")) + *op_flag_value = RTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS; + else if (!strcmp(token, "RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS")) + *op_flag_value = RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS; + else if (!strcmp(token, "RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE")) + *op_flag_value = RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE; + else if (!strcmp(token, "RTE_BBDEV_LDPC_DEC_INTERRUPTS")) + *op_flag_value = RTE_BBDEV_LDPC_DEC_INTERRUPTS; + else if (!strcmp(token, "RTE_BBDEV_LDPC_DEC_SCATTER_GATHER")) + *op_flag_value = RTE_BBDEV_LDPC_DEC_SCATTER_GATHER; + else if (!strcmp(token, "RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION")) + *op_flag_value = RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION; + else if (!strcmp(token, "RTE_BBDEV_LDPC_LLR_COMPRESSION")) + *op_flag_value = RTE_BBDEV_LDPC_LLR_COMPRESSION; + else if (!strcmp(token, + "RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE")) + *op_flag_value = RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE; + else if (!strcmp(token, + "RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE")) + *op_flag_value = RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE; + else { + printf("The given value is not a LDPC decoder flag\n"); + return -1; + } + + return 0; +} + /* convert turbo encoder flag from string to unsigned long int*/ static int op_encoder_flag_strtoul(char *token, uint32_t *op_flag_value) @@ -176,6 +227,32 @@ return 0; } +/* convert LDPC encoder flag from string to unsigned long int*/ +static int +op_ldpc_encoder_flag_strtoul(char *token, uint32_t *op_flag_value) +{ + if (!strcmp(token, "RTE_BBDEV_LDPC_INTERLEAVER_BYPASS")) + *op_flag_value = RTE_BBDEV_LDPC_INTERLEAVER_BYPASS; + else if (!strcmp(token, "RTE_BBDEV_LDPC_RATE_MATCH")) + *op_flag_value = RTE_BBDEV_LDPC_RATE_MATCH; + else if (!strcmp(token, "RTE_BBDEV_LDPC_CRC_24A_ATTACH")) + *op_flag_value = RTE_BBDEV_LDPC_CRC_24A_ATTACH; + else if (!strcmp(token, "RTE_BBDEV_LDPC_CRC_24B_ATTACH")) + *op_flag_value = RTE_BBDEV_LDPC_CRC_24B_ATTACH; + else if (!strcmp(token, "RTE_BBDEV_LDPC_CRC_16_ATTACH")) + *op_flag_value = RTE_BBDEV_LDPC_CRC_16_ATTACH; + else if (!strcmp(token, "RTE_BBDEV_LDPC_ENC_INTERRUPTS")) + *op_flag_value = RTE_BBDEV_LDPC_ENC_INTERRUPTS; + else if (!strcmp(token, "RTE_BBDEV_LDPC_ENC_SCATTER_GATHER")) + *op_flag_value = RTE_BBDEV_LDPC_ENC_SCATTER_GATHER; + else { + printf("The given value is not a turbo encoder flag\n"); + return -1; + } + + return 0; +} + /* tokenization turbo decoder/encoder flags values separated by a comma */ static int parse_turbo_flags(char *tokens, uint32_t *op_flags, @@ -196,6 +273,14 @@ } else if (op_type == RTE_BBDEV_OP_TURBO_ENC) { if (op_encoder_flag_strtoul(tok, &op_flag_value) == -1) return -1; + } else if (op_type == RTE_BBDEV_OP_LDPC_ENC) { + if (op_ldpc_encoder_flag_strtoul(tok, &op_flag_value) + == -1) + return -1; + } else if (op_type == RTE_BBDEV_OP_LDPC_DEC) { + if (op_ldpc_decoder_flag_strtoul(tok, &op_flag_value) + == -1) + return -1; } else { return -1; } @@ -219,6 +304,10 @@ *op_type = RTE_BBDEV_OP_TURBO_DEC; else if (!strcmp(token, "RTE_BBDEV_OP_TURBO_ENC")) *op_type = RTE_BBDEV_OP_TURBO_ENC; + else if (!strcmp(token, "RTE_BBDEV_OP_LDPC_ENC")) + *op_type = RTE_BBDEV_OP_LDPC_ENC; + else if (!strcmp(token, "RTE_BBDEV_OP_LDPC_DEC")) + *op_type = RTE_BBDEV_OP_LDPC_DEC; else if (!strcmp(token, "RTE_BBDEV_OP_NONE")) *op_type = RTE_BBDEV_OP_NONE; else { @@ -248,12 +337,18 @@ *status = *status | (1 << RTE_BBDEV_DRV_ERROR); else if (!strcmp(tok, "FCW")) *status = *status | (1 << RTE_BBDEV_DATA_ERROR); + else if (!strcmp(tok, "SYNCRC")) { + *status = *status | (1 << RTE_BBDEV_SYNDROME_ERROR); + *status = *status | (1 << RTE_BBDEV_CRC_ERROR); + } else if (!strcmp(tok, "SYN")) + *status = *status | (1 << RTE_BBDEV_SYNDROME_ERROR); else if (!strcmp(tok, "CRC")) { - if (op_type == RTE_BBDEV_OP_TURBO_DEC) + if ((op_type == RTE_BBDEV_OP_TURBO_DEC) || + (op_type == RTE_BBDEV_OP_LDPC_DEC)) *status = *status | (1 << RTE_BBDEV_CRC_ERROR); else { printf( - "CRC is only a valid value for turbo decoder\n"); + "CRC is only a valid value for decoder\n"); return -1; } } else { @@ -414,7 +509,7 @@ ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; } else if (!strcmp(key_token, "r")) { vector->mask |= TEST_BBDEV_VF_R; - turbo_dec->tb_params.r = (uint8_t) strtoul(token, &err, 0); + turbo_dec->tb_params.r = (uint8_t)strtoul(token, &err, 0); ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; } else if (!strcmp(key_token, "code_block_mode")) { vector->mask |= TEST_BBDEV_VF_CODE_BLOCK_MODE; @@ -548,6 +643,211 @@ return 0; } + +/* parses LDPC encoder parameters and assigns to global variable */ +static int +parse_ldpc_encoder_params(const char *key_token, char *token, + struct test_bbdev_vector *vector) +{ + int ret = 0, status = 0; + uint32_t op_flags = 0; + char *err = NULL; + + struct rte_bbdev_op_ldpc_enc *ldpc_enc = &vector->ldpc_enc; + + if (starts_with(key_token, op_data_prefixes[DATA_INPUT])) + ret = parse_data_entry(key_token, token, vector, + DATA_INPUT, + op_data_prefixes[DATA_INPUT]); + else if (starts_with(key_token, "output")) + ret = parse_data_entry(key_token, token, vector, + DATA_HARD_OUTPUT, + "output"); + else if (!strcmp(key_token, "e")) { + vector->mask |= TEST_BBDEV_VF_E; + ldpc_enc->cb_params.e = (uint32_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "ea")) { + vector->mask |= TEST_BBDEV_VF_EA; + ldpc_enc->tb_params.ea = (uint32_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "eb")) { + vector->mask |= TEST_BBDEV_VF_EB; + ldpc_enc->tb_params.eb = (uint32_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "c")) { + vector->mask |= TEST_BBDEV_VF_C; + ldpc_enc->tb_params.c = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "cab")) { + vector->mask |= TEST_BBDEV_VF_CAB; + ldpc_enc->tb_params.cab = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "rv_index")) { + vector->mask |= TEST_BBDEV_VF_RV_INDEX; + ldpc_enc->rv_index = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "n_cb")) { + vector->mask |= TEST_BBDEV_VF_NCB; + ldpc_enc->n_cb = (uint16_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "r")) { + vector->mask |= TEST_BBDEV_VF_R; + ldpc_enc->tb_params.r = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "q_m")) { + vector->mask |= TEST_BBDEV_VF_QM; + ldpc_enc->q_m = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "basegraph")) { + vector->mask |= TEST_BBDEV_VF_BG; + ldpc_enc->basegraph = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "z_c")) { + vector->mask |= TEST_BBDEV_VF_ZC; + ldpc_enc->z_c = (uint16_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "n_filler")) { + vector->mask |= TEST_BBDEV_VF_F; + ldpc_enc->n_filler = (uint16_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "code_block_mode")) { + vector->mask |= TEST_BBDEV_VF_CODE_BLOCK_MODE; + ldpc_enc->code_block_mode = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "op_flags")) { + vector->mask |= TEST_BBDEV_VF_OP_FLAGS; + ret = parse_turbo_flags(token, &op_flags, vector->op_type); + if (!ret) + ldpc_enc->op_flags = op_flags; + } else if (!strcmp(key_token, "expected_status")) { + vector->mask |= TEST_BBDEV_VF_EXPECTED_STATUS; + ret = parse_expected_status(token, &status, vector->op_type); + if (!ret) + vector->expected_status = status; + } else { + printf("Not valid ldpc enc key: '%s'\n", key_token); + return -1; + } + + if (ret != 0) { + printf("Failed with convert '%s\t%s'\n", key_token, token); + return -1; + } + + return 0; +} + +/* parses LDPC decoder parameters and assigns to global variable */ +static int +parse_ldpc_decoder_params(const char *key_token, char *token, + struct test_bbdev_vector *vector) +{ + int ret = 0, status = 0; + uint32_t op_flags = 0; + char *err = NULL; + + struct rte_bbdev_op_ldpc_dec *ldpc_dec = &vector->ldpc_dec; + + if (starts_with(key_token, op_data_prefixes[DATA_INPUT])) + ret = parse_data_entry(key_token, token, vector, + DATA_INPUT, + op_data_prefixes[DATA_INPUT]); + else if (starts_with(key_token, "output")) + ret = parse_data_entry(key_token, token, vector, + DATA_HARD_OUTPUT, + "output"); + else if (starts_with(key_token, op_data_prefixes[DATA_HARQ_INPUT])) + ret = parse_data_entry(key_token, token, vector, + DATA_HARQ_INPUT, + op_data_prefixes[DATA_HARQ_INPUT]); + else if (starts_with(key_token, op_data_prefixes[DATA_HARQ_OUTPUT])) + ret = parse_data_entry(key_token, token, vector, + DATA_HARQ_OUTPUT, + op_data_prefixes[DATA_HARQ_OUTPUT]); + else if (!strcmp(key_token, "e")) { + vector->mask |= TEST_BBDEV_VF_E; + ldpc_dec->cb_params.e = (uint32_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "ea")) { + vector->mask |= TEST_BBDEV_VF_EA; + ldpc_dec->tb_params.ea = (uint32_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "eb")) { + vector->mask |= TEST_BBDEV_VF_EB; + ldpc_dec->tb_params.eb = (uint32_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "c")) { + vector->mask |= TEST_BBDEV_VF_C; + ldpc_dec->tb_params.c = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "cab")) { + vector->mask |= TEST_BBDEV_VF_CAB; + ldpc_dec->tb_params.cab = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "rv_index")) { + vector->mask |= TEST_BBDEV_VF_RV_INDEX; + ldpc_dec->rv_index = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "n_cb")) { + vector->mask |= TEST_BBDEV_VF_NCB; + ldpc_dec->n_cb = (uint16_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "r")) { + vector->mask |= TEST_BBDEV_VF_R; + ldpc_dec->tb_params.r = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "q_m")) { + vector->mask |= TEST_BBDEV_VF_QM; + ldpc_dec->q_m = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "basegraph")) { + vector->mask |= TEST_BBDEV_VF_BG; + ldpc_dec->basegraph = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "z_c")) { + vector->mask |= TEST_BBDEV_VF_ZC; + ldpc_dec->z_c = (uint16_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "n_filler")) { + vector->mask |= TEST_BBDEV_VF_F; + ldpc_dec->n_filler = (uint16_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "expected_iter_count")) { + vector->mask |= TEST_BBDEV_VF_EXPECTED_ITER_COUNT; + ldpc_dec->iter_count = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "iter_max")) { + vector->mask |= TEST_BBDEV_VF_ITER_MAX; + ldpc_dec->iter_max = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "code_block_mode")) { + vector->mask |= TEST_BBDEV_VF_CODE_BLOCK_MODE; + ldpc_dec->code_block_mode = (uint8_t) strtoul(token, &err, 0); + ret = ((err == NULL) || (*err != '\0')) ? -1 : 0; + } else if (!strcmp(key_token, "op_flags")) { + vector->mask |= TEST_BBDEV_VF_OP_FLAGS; + ret = parse_turbo_flags(token, &op_flags, vector->op_type); + if (!ret) + ldpc_dec->op_flags = op_flags; + } else if (!strcmp(key_token, "expected_status")) { + vector->mask |= TEST_BBDEV_VF_EXPECTED_STATUS; + ret = parse_expected_status(token, &status, vector->op_type); + if (!ret) + vector->expected_status = status; + } else { + printf("Not valid ldpc dec key: '%s'\n", key_token); + return -1; + } + + if (ret != 0) { + printf("Failed with convert '%s\t%s'\n", key_token, token); + return -1; + } + + return 0; +} + /* checks the type of key and assigns data */ static int parse_entry(char *entry, struct test_bbdev_vector *vector) @@ -593,6 +893,12 @@ } else if (vector->op_type == RTE_BBDEV_OP_TURBO_ENC) { if (parse_encoder_params(key_token, token, vector) == -1) return -1; + } else if (vector->op_type == RTE_BBDEV_OP_LDPC_ENC) { + if (parse_ldpc_encoder_params(key_token, token, vector) == -1) + return -1; + } else if (vector->op_type == RTE_BBDEV_OP_LDPC_DEC) { + if (parse_ldpc_decoder_params(key_token, token, vector) == -1) + return -1; } return 0; @@ -632,6 +938,45 @@ } static int +check_ldpc_decoder_segments(struct test_bbdev_vector *vector) +{ + unsigned char i; + struct rte_bbdev_op_ldpc_dec *ldpc_dec = &vector->ldpc_dec; + + if (vector->entries[DATA_INPUT].nb_segments == 0) + return -1; + + for (i = 0; i < vector->entries[DATA_INPUT].nb_segments; i++) + if (vector->entries[DATA_INPUT].segments[i].addr == NULL) + return -1; + + if (vector->entries[DATA_HARD_OUTPUT].nb_segments == 0) + return -1; + + for (i = 0; i < vector->entries[DATA_HARD_OUTPUT].nb_segments; i++) + if (vector->entries[DATA_HARD_OUTPUT].segments[i].addr == NULL) + return -1; + + if ((ldpc_dec->op_flags & RTE_BBDEV_LDPC_SOFT_OUT_ENABLE) && + (vector->entries[DATA_SOFT_OUTPUT].nb_segments == 0)) + return -1; + + for (i = 0; i < vector->entries[DATA_SOFT_OUTPUT].nb_segments; i++) + if (vector->entries[DATA_SOFT_OUTPUT].segments[i].addr == NULL) + return -1; + + if ((ldpc_dec->op_flags & RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE) && + (vector->entries[DATA_HARQ_OUTPUT].nb_segments == 0)) + return -1; + + for (i = 0; i < vector->entries[DATA_HARQ_OUTPUT].nb_segments; i++) + if (vector->entries[DATA_HARQ_OUTPUT].segments[i].addr == NULL) + return -1; + + return 0; +} + +static int check_decoder_llr_spec(struct test_bbdev_vector *vector) { struct rte_bbdev_op_turbo_dec *turbo_dec = &vector->turbo_dec; @@ -648,7 +993,7 @@ !(turbo_dec->op_flags & RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN)) { printf( - "WARNING: input LLR sign formalism was not specified and will be set to negative LLR for '1' bit\n"); + "INFO: input LLR sign formalism was not specified and will be set to negative LLR for '1' bit\n"); turbo_dec->op_flags |= RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN; } @@ -667,7 +1012,7 @@ !(turbo_dec->op_flags & RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT)) { printf( - "WARNING: soft output LLR sign formalism was not specified and will be set to negative LLR for '1' bit\n"); + "INFO: soft output LLR sign formalism was not specified and will be set to negative LLR for '1' bit\n"); turbo_dec->op_flags |= RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT; } @@ -675,6 +1020,21 @@ return 0; } +static int +check_decoder_op_flags(struct test_bbdev_vector *vector) +{ + struct rte_bbdev_op_turbo_dec *turbo_dec = &vector->turbo_dec; + + if ((turbo_dec->op_flags & RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP) && + !(turbo_dec->op_flags & RTE_BBDEV_TURBO_CRC_TYPE_24B)) { + printf( + "WARNING: RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP flag is missing RTE_BBDEV_TURBO_CRC_TYPE_24B\n"); + return -1; + } + + return 0; +} + /* checks decoder parameters */ static int check_decoder(struct test_bbdev_vector *vector) @@ -688,6 +1048,9 @@ if (check_decoder_llr_spec(vector) < 0) return -1; + if (check_decoder_op_flags(vector) < 0) + return -1; + /* Check which params were set */ if (!(mask & TEST_BBDEV_VF_CODE_BLOCK_MODE)) { printf( @@ -731,7 +1094,7 @@ } if (!(mask & TEST_BBDEV_VF_RV_INDEX)) printf( - "WARNING: rv_index was not specified in vector file and will be set to 0\n"); + "INFO: rv_index was not specified in vector file and will be set to 0\n"); if (!(mask & TEST_BBDEV_VF_ITER_MIN)) printf( "WARNING: iter_min was not specified in vector file and will be set to 0\n"); @@ -751,7 +1114,7 @@ } else if (!(turbo_dec->op_flags & RTE_BBDEV_TURBO_MAP_DEC) && mask & TEST_BBDEV_VF_NUM_MAPS) { printf( - "WARNING: RTE_BBDEV_TURBO_MAP_DEC was not set in vector file and num_maps will be set to 0\n"); + "INFO: RTE_BBDEV_TURBO_MAP_DEC was not set in vector file and num_maps will be set to 0\n"); turbo_dec->num_maps = 0; } if (!(mask & TEST_BBDEV_VF_EXPECTED_STATUS)) @@ -760,6 +1123,72 @@ return 0; } +/* checks LDPC decoder parameters */ +static int +check_ldpc_decoder(struct test_bbdev_vector *vector) +{ + struct rte_bbdev_op_ldpc_dec *ldpc_dec = &vector->ldpc_dec; + const int mask = vector->mask; + + if (check_ldpc_decoder_segments(vector) < 0) + return -1; + + /* + * if (check_ldpc_decoder_llr_spec(vector) < 0) + * return -1; + * + * if (check_ldpc_decoder_op_flags(vector) < 0) + * return -1; + */ + + /* Check which params were set */ + if (!(mask & TEST_BBDEV_VF_CODE_BLOCK_MODE)) { + printf( + "WARNING: code_block_mode was not specified in vector file and will be set to 1 (0 - TB Mode, 1 - CB mode)\n"); + ldpc_dec->code_block_mode = 1; + } + if (ldpc_dec->code_block_mode == 0) { + if (!(mask & TEST_BBDEV_VF_EA)) + printf( + "WARNING: ea was not specified in vector file and will be set to 0\n"); + if (!(mask & TEST_BBDEV_VF_EB)) + printf( + "WARNING: eb was not specified in vector file and will be set to 0\n"); + if (!(mask & TEST_BBDEV_VF_C)) { + printf( + "WARNING: c was not specified in vector file and will be set to 1\n"); + ldpc_dec->tb_params.c = 1; + } + if (!(mask & TEST_BBDEV_VF_CAB)) + printf( + "WARNING: cab was not specified in vector file and will be set to 0\n"); + if (!(mask & TEST_BBDEV_VF_R)) + printf( + "WARNING: r was not specified in vector file and will be set to 0\n"); + } else { + if (!(mask & TEST_BBDEV_VF_E)) + printf( + "WARNING: e was not specified in vector file and will be set to 0\n"); + } + if (!(mask & TEST_BBDEV_VF_RV_INDEX)) + printf( + "INFO: rv_index was not specified in vector file and will be set to 0\n"); + if (!(mask & TEST_BBDEV_VF_ITER_MAX)) + printf( + "WARNING: iter_max was not specified in vector file and will be set to 0\n"); + if (!(mask & TEST_BBDEV_VF_EXPECTED_ITER_COUNT)) + printf( + "WARNING: expected_iter_count was not specified in vector file and iter_count will not be validated\n"); + if (!(mask & TEST_BBDEV_VF_OP_FLAGS)) { + printf( + "WARNING: op_flags was not specified in vector file and capabilities will not be validated\n"); + } + if (!(mask & TEST_BBDEV_VF_EXPECTED_STATUS)) + printf( + "WARNING: expected_status was not specified in vector file and will be set to 0\n"); + return 0; +} + /* checks encoder parameters */ static int check_encoder(struct test_bbdev_vector *vector) @@ -836,10 +1265,66 @@ } if (!(mask & TEST_BBDEV_VF_RV_INDEX)) printf( - "WARNING: rv_index was not specified in vector file and will be set to 0\n"); + "INFO: rv_index was not specified in vector file and will be set to 0\n"); if (!(mask & TEST_BBDEV_VF_OP_FLAGS)) printf( - "WARNING: op_flags was not specified in vector file and capabilities will not be validated\n"); + "INFO: op_flags was not specified in vector file and capabilities will not be validated\n"); + if (!(mask & TEST_BBDEV_VF_EXPECTED_STATUS)) + printf( + "WARNING: expected_status was not specified in vector file and will be set to 0\n"); + + return 0; +} + + +/* checks encoder parameters */ +static int +check_ldpc_encoder(struct test_bbdev_vector *vector) +{ + unsigned char i; + const int mask = vector->mask; + + if (vector->entries[DATA_INPUT].nb_segments == 0) + return -1; + + for (i = 0; i < vector->entries[DATA_INPUT].nb_segments; i++) + if (vector->entries[DATA_INPUT].segments[i].addr == NULL) + return -1; + + if (vector->entries[DATA_HARD_OUTPUT].nb_segments == 0) + return -1; + + for (i = 0; i < vector->entries[DATA_HARD_OUTPUT].nb_segments; i++) + if (vector->entries[DATA_HARD_OUTPUT].segments[i].addr == NULL) + return -1; + + if (!(mask & TEST_BBDEV_VF_CODE_BLOCK_MODE)) { + printf( + "WARNING: code_block_mode was not specified in vector file and will be set to 1\n"); + vector->turbo_enc.code_block_mode = 1; + } + if (vector->turbo_enc.code_block_mode == 0) { + } else { + if (!(mask & TEST_BBDEV_VF_E) && (vector->turbo_enc.op_flags & + RTE_BBDEV_TURBO_RATE_MATCH)) + printf( + "WARNING: e was not specified in vector file and will be set to 0\n"); + if (!(mask & TEST_BBDEV_VF_NCB)) + printf( + "WARNING: ncb was not specified in vector file and will be set to 0\n"); + } + if (!(mask & TEST_BBDEV_VF_BG)) + printf( + "WARNING: BG was not specified in vector file and will be set to 0\n"); + if (!(mask & TEST_BBDEV_VF_ZC)) + printf( + "WARNING: Zc was not specified in vector file and will be set to 0\n"); + if (!(mask & TEST_BBDEV_VF_RV_INDEX)) + printf( + "INFO: rv_index was not specified in vector file and will be set to 0\n"); + if (!(mask & TEST_BBDEV_VF_OP_FLAGS)) + printf( + "INFO: op_flags was not specified in vector file and capabilities will not be validated\n"); if (!(mask & TEST_BBDEV_VF_EXPECTED_STATUS)) printf( "WARNING: expected_status was not specified in vector file and will be set to 0\n"); @@ -856,6 +1341,12 @@ } else if (vector->op_type == RTE_BBDEV_OP_TURBO_ENC) { if (check_encoder(vector) == -1) return -1; + } else if (vector->op_type == RTE_BBDEV_OP_LDPC_ENC) { + if (check_ldpc_encoder(vector) == -1) + return -1; + } else if (vector->op_type == RTE_BBDEV_OP_LDPC_DEC) { + if (check_ldpc_decoder(vector) == -1) + return -1; } else if (vector->op_type != RTE_BBDEV_OP_NONE) { printf("Vector was not filled\n"); return -1; @@ -898,7 +1389,8 @@ goto exit; } - strcpy(entry, line); + memset(entry, 0, strlen(line) + 1); + strncpy(entry, line, strlen(line)); /* check if entry ends with , or = */ if (entry[strlen(entry) - 1] == ',' @@ -920,8 +1412,7 @@ } entry = entry_extended; - /* entry has been allocated accordingly */ - strcpy(&entry[strlen(entry)], line); + strncat(entry, line, strlen(line)); if (entry[strlen(entry) - 1] != ',') break; diff --git a/app/test-bbdev/test_bbdev_vector.h b/app/test-bbdev/test_bbdev_vector.h index c85e94d..4e5dbf5 100644 --- a/app/test-bbdev/test_bbdev_vector.h +++ b/app/test-bbdev/test_bbdev_vector.h @@ -28,15 +28,21 @@ enum { TEST_BBDEV_VF_NCB_NEG = (1ULL << 16), TEST_BBDEV_VF_NCB_POS = (1ULL << 17), TEST_BBDEV_VF_R = (1ULL << 18), - TEST_BBDEV_VF_CODE_BLOCK_MODE = (1ULL << 19), - TEST_BBDEV_VF_OP_FLAGS = (1ULL << 20), - TEST_BBDEV_VF_EXPECTED_STATUS = (1ULL << 21), + TEST_BBDEV_VF_BG = (1ULL << 19), + TEST_BBDEV_VF_ZC = (1ULL << 20), + TEST_BBDEV_VF_F = (1ULL << 21), + TEST_BBDEV_VF_QM = (1ULL << 22), + TEST_BBDEV_VF_CODE_BLOCK_MODE = (1ULL << 23), + TEST_BBDEV_VF_OP_FLAGS = (1ULL << 24), + TEST_BBDEV_VF_EXPECTED_STATUS = (1ULL << 25), }; enum op_data_type { DATA_INPUT = 0, DATA_SOFT_OUTPUT, DATA_HARD_OUTPUT, + DATA_HARQ_INPUT, + DATA_HARQ_OUTPUT, DATA_NUM_TYPES, }; @@ -57,6 +63,8 @@ struct test_bbdev_vector { union { struct rte_bbdev_op_turbo_dec turbo_dec; struct rte_bbdev_op_turbo_enc turbo_enc; + struct rte_bbdev_op_ldpc_dec ldpc_dec; + struct rte_bbdev_op_ldpc_enc ldpc_enc; }; /* Additional storage for op data entries */ struct op_data_entries entries[DATA_NUM_TYPES]; diff --git a/app/test-bbdev/turbo_enc_default.data b/app/test-bbdev/turbo_enc_default.data index 5587f9c..a2bc833 120000 --- a/app/test-bbdev/turbo_enc_default.data +++ b/app/test-bbdev/turbo_enc_default.data @@ -1 +1 @@ -test_vectors/turbo_enc_c1_k6144_r0_e32256_crc24b_rm.data \ No newline at end of file +test_vectors/turbo_enc_c1_k6144_r0_e18444.data \ No newline at end of file From patchwork Mon Jun 24 02:52:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 55298 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7546A1BBB4; Tue, 25 Jun 2019 12:18:28 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id DF2181BEAD for ; Mon, 24 Jun 2019 04:53:04 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jun 2019 19:53:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,410,1557212400"; d="scan'208";a="183991209" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga004.fm.intel.com with ESMTP; 23 Jun 2019 19:52:59 -0700 From: Nicolas Chautru To: akhil.goyal@nxp.com, dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@intel.com, amr.mokhtar@intel.com, Nicolas Chautru Date: Sun, 23 Jun 2019 19:52:55 -0700 Message-Id: <1561344776-43990-10-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> References: <1561136352-32198-2-git-send-email-nicolas.chautru@intel.com> <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> X-Mailman-Approved-At: Tue, 25 Jun 2019 12:18:20 +0200 Subject: [dpdk-dev] [PATCH v4 09/10] test-bbdev: test vectors for 5GNR verification X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Adding LDPC vectors for UT verification, coverage, and profiling for 5GNR encode/decode operations. Signed-off-by: Nicolas Chautru Acked-by: Amr Mokhtar --- app/test-bbdev/ldpc_dec_default.data | 1 + app/test-bbdev/ldpc_enc_default.data | 1 + app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_0.data | 354 ++++++ app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_1.data | 685 +++++++++++ app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_2.data | 903 +++++++++++++++ app/test-bbdev/test_vectors/ldpc_dec_v11835.data | 50 + app/test-bbdev/test_vectors/ldpc_dec_v2342.data | 746 ++++++++++++ .../test_vectors/ldpc_dec_v2342_drop.data | 746 ++++++++++++ app/test-bbdev/test_vectors/ldpc_dec_v7813.data | 49 + app/test-bbdev/test_vectors/ldpc_dec_v8480.data | 75 ++ app/test-bbdev/test_vectors/ldpc_dec_v8568.data | 256 +++++ app/test-bbdev/test_vectors/ldpc_dec_v9503.data | 1216 ++++++++++++++++++++ app/test-bbdev/test_vectors/ldpc_enc_v11835.data | 42 + app/test-bbdev/test_vectors/ldpc_enc_v2342.data | 150 +++ app/test-bbdev/test_vectors/ldpc_enc_v7813.data | 42 + app/test-bbdev/test_vectors/ldpc_enc_v8568.data | 69 ++ app/test-bbdev/test_vectors/ldpc_enc_v9503.data | 196 ++++ 17 files changed, 5581 insertions(+) create mode 120000 app/test-bbdev/ldpc_dec_default.data create mode 120000 app/test-bbdev/ldpc_enc_default.data create mode 100644 app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_0.data create mode 100644 app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_1.data create mode 100644 app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_2.data create mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v11835.data create mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v2342.data create mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v2342_drop.data create mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v7813.data create mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v8480.data create mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v8568.data create mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v9503.data create mode 100644 app/test-bbdev/test_vectors/ldpc_enc_v11835.data create mode 100644 app/test-bbdev/test_vectors/ldpc_enc_v2342.data create mode 100644 app/test-bbdev/test_vectors/ldpc_enc_v7813.data create mode 100644 app/test-bbdev/test_vectors/ldpc_enc_v8568.data create mode 100644 app/test-bbdev/test_vectors/ldpc_enc_v9503.data diff --git a/app/test-bbdev/ldpc_dec_default.data b/app/test-bbdev/ldpc_dec_default.data new file mode 120000 index 0000000..3058cc0 --- /dev/null +++ b/app/test-bbdev/ldpc_dec_default.data @@ -0,0 +1 @@ +test_vectors/ldpc_dec_v2342.data \ No newline at end of file diff --git a/app/test-bbdev/ldpc_enc_default.data b/app/test-bbdev/ldpc_enc_default.data new file mode 120000 index 0000000..371cbc6 --- /dev/null +++ b/app/test-bbdev/ldpc_enc_default.data @@ -0,0 +1 @@ +test_vectors/turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_high_snr.data \ No newline at end of file diff --git a/app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_0.data b/app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_0.data new file mode 100644 index 0000000..c8d38e3 --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_0.data @@ -0,0 +1,354 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2019 Intel Corporation +# Origin : FEC5G_UL_1/xxxx + +op_type = +RTE_BBDEV_OP_LDPC_DEC + +input0 = +0xF301FC03, 0xF50F0EFA, 0xE70BF902, 0x1013060C, 0xF7F6FCE7, 0x04F3F709, 0x0C07FBF1, 0xFCF7070F, +0xEA0FFAF8, 0x0FF71209, 0x070906F2, 0xF705F004, 0x15FA05F7, 0xF4F8010A, 0x0B0E09F5, 0xF70014F6, +0xF106F80D, 0x0A06F9FC, 0x0DFBF803, 0x0308060D, 0x0CF9F8F9, 0xF2F409ED, 0x12FEF3EA, 0xF2FC07F9, +0xEF12EEF8, 0xF90F030C, 0xEC171408, 0x11F902F3, 0xF102F6FF, 0x0AF6090C, 0x0103FA10, 0xF9FFF011, +0x010FFB0F, 0xF80BFEF8, 0x10F2F1EE, 0x140204F6, 0x020AF206, 0x0BED04F2, 0x06FEF5F2, 0x0F070009, +0xECF0F9F0, 0x081405F5, 0xF1000E18, 0xF4F7090C, 0xFD0F01EF, 0x0D12E702, 0x07EF1008, 0xEF06FD02, +0x0302FD00, 0xF2F4040A, 0xF60BF9FC, 0x0BEEF20C, 0xF9ED0901, 0x00060406, 0xFF09F6F3, 0x0FF209F7, +0x0D0EF210, 0xF3150611, 0x06060EF8, 0x0E06EFEC, 0x070C05F8, 0x0CFBF4F1, 0xFBFE0CF6, 0xFD03F714, +0x03FCE40C, 0xF4F5F2F4, 0xF400F6FF, 0x0EF0090C, 0x04F9F9F6, 0xF5F6FEFD, 0xFE08FE01, 0x0607F3F3, +0x11F4020C, 0xFD0FFB04, 0xEEF30D05, 0xFD040406, 0xFCF8F108, 0x0DFAFBF9, 0xE9F10B09, 0xEEF2140D, +0xEE0A09F8, 0xFB010C0A, 0xF1FC0803, 0x0C07130A, 0x0312FD0A, 0xF6F10708, 0xFCF1FAEC, 0x0BF8F4F9, +0xF009FBFF, 0x14EEF2EB, 0xEF0DF701, 0xFA14F90C, 0x08EF0110, 0xF50401E5, 0xEE13F30C, 0xF1F60916, +0x05F414EC, 0xFF030A14, 0x0409FFF2, 0x0C0906FA, 0xF7F70414, 0xFBFA0EFA, 0xFD010BFD, 0xF5FA0EF1, +0xF40FFAF4, 0xFF060503, 0x0BEF0BFA, 0x0717E7F3, 0xF4F1FD09, 0xEF09FEFE, 0x07F9F3FB, 0x0DFD08FE, +0x0D0BF602, 0x05F21008, 0x1A0B0807, 0xEF0CFAF9, 0x090D0A06, 0x02EB0D0F, 0xF709FDFE, 0xFFF7F510, +0xF10A0AF8, 0x15EF1311, 0xF20BEDF9, 0xF10A0BF7, 0x15150B08, 0x0B170F0A, 0x06FAFAF1, 0xF1F803FD, +0x11F3EEEB, 0x0902FB04, 0x0703F215, 0x06EF10FE, 0xFB00140B, 0xF70CF806, 0x040AEE0E, 0xF9F1070C, +0xEAF9F6FC, 0x0AECF80E, 0x09F2F9F3, 0xF708E8F0, 0x0902E9F7, 0x0209F6FD, 0x02F6EE10, 0x090BE811, +0x0BF8E8F7, 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0x08F9F2FD, 0x1107FA03, 0xEC11EDFE, 0x0DF1F810, 0xFC0B11F9, +0xF9FE0AFD, 0x0B0EF4F3, 0xF9F1050C, 0xFC0EF9F8, 0x000F14EA, 0xF00A0107, 0xF903F810, 0x0A040EFA, +0x0C000203, 0xF40C02FE, 0xFA06130D, 0x100CFDF3, 0x0BF505FA, 0xF5FB00FC, 0xF8110808, 0x05ECEA0D, +0x04F7F30A, 0xFE090FEC, 0xF9FBEE08, 0xFD0CEF0E, 0x09F80B0A, 0xF90BF9F4, 0x0EFB0C0C, 0x10EFF2F0, +0x09F8F0FA, 0x060B0909, 0xF4FF0F13, 0x06FA0E16, 0x0515F512, 0x0E0B0708, 0xF6FBF9F7, 0xFBF405F2, +0x050A1207, 0xFA001C0C, 0xFB0FEBEE, 0x0B13100C, 0x0D08F6FB, 0x16FEF2F9, 0x12F9F412, 0x09F600F5, +0x02040B09, 0x0AF11310, 0x0C160A06, 0x0E09FF0E, 0xEF0B0CF3, 0x13F40DF5, 0x0BF704F9, 0x07EE0A00, +0xF0F504F6, 0x0BFAFCFB, 0x0B0BF70A, 0x0207FF08, 0xF20B09E7, 0xF9F1F115, 0xF0090812, 0xFF0DF5F8, +0x0C080709, 0x0512F3EF, 0xEE110708, 0x03EBFCFF, 0xEE0D08FE, 0x110BFCF6, 0x15F61408, 0xF413F30D, +0x06F2F2F1, 0x04120BEF, 0xF90CF30B, 0xE40400FB, 0x0BFC1A09, 0x130109FD, 0xFF08E7F9, 0xF2FAF4F8, +0x060BF901, 0xF112EE02, 0xFF060D0F, 0xFAFC0DED, 0x09FFF6FF, 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0x07F7F70F, 0x00FBF6FC, 0xF9FB0D09, 0xF1ED080D, 0xFCF9EDF4, 0xF3F80C0B, 0xFD0210F4, +0xFBF206F2, 0xF3F5F7FC, 0xF8FDFFF1, 0xF0020908, 0xF804F505, 0xF8F2080B, 0xF0FA09F3, 0xEFF8120A, +0x14EDF8EA, 0x0CF40E15, 0x0EEB0600, 0x02FD01FB, 0xF5F30D0F, 0xFFF400F1, 0xF30F0909, 0xF9ECF107, +0xEE0AF0FF, 0x05FA070D, 0xFD0CFB06, 0xF8F7EFEE, 0x13F0030B, 0x050404F4, 0xEE0FF6F5, 0xFC0813F5 + +output0 = +0xCE63DECD, 0xD5F54E4C, 0xB969BECF, 0x67199350, 0x73BD1B5F, 0xF3FA3DD7, 0xB72F3304, 0xCA6C9E7F, +0xC75EBD3C, 0xE9183BC1, 0xD2EFF1F5, 0xDB98D960, 0x9183FF24, 0x84E53C2E, 0xBC0ACB99, 0x7544F27D, +0x61B01F8C, 0x6F8E7BCA, 0x0F9A1912, 0xA4DE41C3, 0xFB1F18F3, 0x44764A35, 0x9525E193, 0xAD6AFC2C, +0xEAC9CBE7, 0x82E626C3, 0x6764F162, 0xB7180FC5, 0x92F0BF10, 0x6BE2A423, 0x6652CA83, 0x76AB8A79, +0xD2DC0142, 0x3684A5B0, 0x6AF81D1E, 0xCE7B11D8, 0x5C0A7AA6, 0x9B519157, 0xCF71DB9C, 0xE66B5219, +0x0976A858, 0x97CCD7A4, 0xBD21A44D, 0x694DB77D, 0x2046F400, 0x66BF01FF, 0x4FE7F1B2, 0x7D287C99, +0xA6DD65A8, 0xDDAC14DF, 0xB4EA7458, 0x9BF75449, 0xBCCF3BC5, 0x59B3E1D5, 0x04D5FEAA, 0xA91CED07, +0x264A3E33, 0x314BE435, 0x47FB659B, 0xC8C6CBDD, 0xD4BAF083, 0x51A5AE91, 0x39A33C7A, 0xC54DBA59, +0x81FD7FFA, 0xE2A3941C, 0x386750ED, 0x85C6A1CF, 0x52E46581, 0x2DD58578, 0x4F8C20DC, 0xCA6C89B8, +0xD33AF49E, 0xB73D9A1C, 0x8F5992A5, 0x4613FE36, 0x8F724B6A, 0xD2C9A290, 0x5C4791D6, 0x8AA4DE2A, +0xBCA9EEF4, 0x769D6618, 0x71DF1DFC, 0xE9DC6A93, 0x99E831C3, 0x88B8CBD4, 0x4C9E63C5, 0xBEBC2792, +0x9E54A535, 0x55181DEF, 0x0F83F8D2, 0x79A8094D, 0x2DA8AAEB, 0xD64C6C17, 0x4F0AADB5, 0x20CB1D7F, +0x2D6E9F16, 0xB97E8AA9, 0x36167C67, 0x8D84329F, 0x4002AA1C, 0x6326776B, 0xB9B50F8F, 0xF9C52D71, +0x4D1A117F, 0x604A6DEE, 0xBB19DFB2, 0x96121F4E, 0x9E7C8D9E, 0x00F8F1F3, 0x204B8054, 0xA67E9C60, +0xC534F776, 0x94B8C032, 0x38E7CFEC, 0xF1E48A55, 0x821E3625, 0xFAC9EBD0, 0xF3D38EF2, 0xB4DA79FB, +0xF32472 + +harq_output0 = +0x0FFA0103, 0x130C0B02, 0xF309F6E7, 0xF70F07F1, 0xF7090FF8, 0x050409F2, 0xF80AFAF7, 0x00F60EF5, +0x06FC060D, 0x080DFB03, 0xF4EDF9F9, 0xFCF9FEEA, 0x0F0C12F8, 0xF9F31708, 0xF60C02FF, 0xFF110310, +0x0BF80F0F, 0x02F6F2EE, 0xEDF20A06, 0x0709FEF2, 0x14F5F0F0, 0xF70C0018, 0x12020FEF, 0x0602EF08, +0xF40A0200, 0xEE0C0BFC, 0x0606ED01, 0xF2F709F3, 0x15110E10, 0x06EC06F8, 0xFBF10CF8, 0x0314FEF6, +0xF5F4FC0C, 0xF00C00FF, 0xF6FDF9F6, 0x07F30801, 0x0F04F40C, 0x0406F305, 0xFAF9F808, 0xF20DF109, +0x010A0AF8, 0x070AFC03, 0xF108120A, 0xF8F9F1EC, 0xEEEB09FF, 0x140C0D01, 0x04E5EF10, 0xF616130C, +0x0314F4EC, 0x09FA09F2, 0xFAFAF714, 0xFAF101FD, 0x06030FF4, 0x17F3EFFA, 0x09FEF109, 0xFDFEF9FB, +0xF2080B02, 0x0CF90B07, 0xEB0F0D06, 0xF71009FE, 0xEF110AF8, 0x0AF70BF9, 0x170A1508, 0xF8FDFAF1, +0x0204F3EB, 0xEFFE0315, 0x0C06000B, 0xF10C0A0E, 0xEC0EF9FC, 0x08F0F2F3, 0x09FD02F7, 0x0B11F610, +0xF8F1F8F7, 0xF8FB0A09, 0xFB030A13, 0x040804F0, 0xE8080813, 0xF1F4FFF3, 0xEBFCEDF7, 0xF7F00AE8, +0x00F1160E, 0xF007F301, 0x0E13F211, 0x07F815F4, 0xF9EEF70B, 0x0EF7FE15, 0x0706E80C, 0x0611F60E, +0xFB0B0CF5, 0xF4F50E11, 0x14FDF1EB, 0xF403120A, 0x09F80303, 0xFB0AF80B, 0xFA1408F5, 0xF503F717, +0x0FFB1610, 0x1107F3FC, 0xF1F4F7F7, 0x060EF4E8, 0x04F8F5FF, 0x04F30CFA, 0x10F008F8, 0xF514EEF3, +0x0EEDE8FE, 0xE7FEE70B, 0x0404FEF9, 0xF8F509F9, 0x0A0EF6F2, 0xF8080EF8, 0x01F200F3, 0x03FC19F2, +0x0D0FF2F8, 0xF9FD0C13, 0x11FE0703, 0x0BF9F110, 0x0EF3FEFD, 0x0EF8F10C, 0x0A070FEA, 0x04FA0310, +0x0CFE0003, 0x0CF3060D, 0xFBFCF5FA, 0xEC0D1108, 0x09ECF70A, 0x0C0EFB08, 0x0BF4F80A, 0xEFF0FB0C, +0x0B09F8FA, 0xFA16FF13, 0x0B081512, 0xF4F2FBF7, 0x000C0A07, 0x130C0FEE, 0xFEF908FB, 0xF6F5F912, +0xF1100409, 0x090E1606, 0xF4F50BF3, 0xEE00F7F9, 0xFAFBF5F6, 0x07080B0A, 0xF1150BE7, 0x0DF80912, +0x12EF0809, 0xEBFF1108, 0x0BF60DFE, 0x130DF608, 0x12EFF2F1, 0x04FB0C0B, 0x01FDFC09, 0xFAF808F9, +0x12020B01, 0xFCED060F, 0x040DFFFF, 0x04F80AF3, 0xF700F60B, 0x08F40E08, 0x06F7F80F, 0x0DFDEF04, +0xFDEFF916, 0xF21107EF, 0x0A1110F1, 0x03F70DF3, 0x08F50300, 0xF1F711F9, 0xF6FCFF0C, 0x0CFFF704, +0x080CFE09, 0x0FF80D06, 0x05080C08, 0xFE020210, 0xFB11F6E9, 0x060BF2F1, 0xED0BEAF9, 0x02F30C02, +0xF8F40DFB, 0x020D0D01, 0x0CF406F1, 0xF302F812, 0x080C0EF2, 0x06010006, 0xF0FA0908, 0x08F9F905, +0xFB0A0508, 0x0FF0F7F4, 0xFF081210, 0xEE18F6F1, 0xF9F9E8F2, 0x060B09FD, 0x0AFEEE04, 0x09F304F8, +0xEA05F6F8, 0x1C0108F5, 0xF205120F, 0xF40D0A04, 0x0001F30D, 0x00FF0DFA, 0x020BF7F7, 0x02F2F7F0, +0x04F90BF1, 0x01EFEE07, 0xEBE4F807, 0x0AF90FEF, 0x0F040B11, 0x0BF91000, 0x000CF812, 0x0311F3F0, +0xF8070218, 0xEDFFF614, 0xF00C15F1, 0x000D0F16, 0xFA0EF707, 0xEE080901, 0xFF0C09F5, 0xEEF704F1, +0xF10C10F9, 0x060BEBF7, 0xFA0EFDF6, 0xF7F403F2, 0xF5F0F306, 0xEC081A0F, 0x020AEEF5, 0xFBF9F7FB, +0xF60C010A, 0xEC0E0FFF, 0xF014FB10, 0x0EFD0308, 0x04F30015, 0xF4FC0CEE, 0x0CFEF3F7, 0x12F0F702, +0xE803FB07, 0x040D06F5, 0x05FA07F1, 0x140A0BF8, 0xEFEDFF11, 0x01EFEE13, 0x0D0C0B0F, 0xE70105F0, +0x01F70CF4, 0x0603EE12, 0xED08EDF9, 0xF2FCFA02, 0x0E0CFCF3, 0x0E04F8F9, 0xF30D17F9, 0xFEEDFB05, +0x071BF114, 0xF309F7F4, 0x02F503F6, 0x0815F400, 0x0CF0090A, 0xE80D0F02, 0xF9FCFDF8, 0xF00FFEF5, +0xF3F5F70B, 0xFC10F7EF, 0xF2FB0AFE, 0xEEECEC15, 0x0202F60E, 0xF310FEF9, 0x10F8F209, 0xFB0606EE, +0x0D0B0C10, 0x1110080C, 0xFCF2F8F6, 0x030DEE07, 0x0C11F511, 0x0CF6EF08, 0x0900070C, 0x0C160E0F, +0xEEF8FFF9, 0xF7F0EEF5, 0x0A090903, 0xF70A000E, 0xF5FF07F6, 0xF5E5FEFD, 0x08F1F80C, 0x00F2EE0D, +0xFAED07EA, 0x07EA170B, 0xFEFFECFF, 0xED0B0211, 0x0AF4F4E6, 0xF2FAF705, 0x0807F706, 0xFBF2F8F7, +0xF31105F7, 0xF10809FB, 0xF1FEF307, 0x0805FFFA, 0x08FC070D, 0x0A071200, 0xEEEDF107, 0xF908EDFB, +0x09F60FF2, 0x0B0C06F8, 0x07FCF608, 0x000FF30C, 0xFF0EF3FD, 0xE40BFCF4, 0x0CF50BF4, 0x04EDE90D, +0xFD05F3F1, 0xFAECF4FA, 0xF80C080F, 0x0A0BF70A, 0x07F012F4, 0x1109FEF3, 0xF507F9F1, 0xF513F7FD, +0xFE0AF80F, 0x041701F1, 0xF5E7F309, 0x0A0AF70C, 0x0E00FEF1, 0x04E505EF, 0xF4EF0BFD, 0x040CF807, +0x1201EF07, 0xF31508F1, 0xF908F309, 0x0B0EE409, 0xF7EBF9F8, 0xF1F7F406, 0xFB0206F6, 0xECFD11F2, +0x0702EEF6, 0xF409FC04, 0xEEF80010, 0xF3EC0BF0, 0x090600F1, 0xF9F5EBF7, 0xEEFE11F8, 0x070BF0FA, +0xFE16EEF8, 0xF108FD05, 0x15FAF3F7, 0xF60E0D0D, 0xF7FC0AF8, 0x01F40805, 0xF70AFE01, 0xFB0F0BF9, +0x04E701F6, 0x09F517F6, 0xFBE8F5F8, 0x11FE00F6, 0xEF08F2F5, 0xFB0CFB0F, 0x0419080B, 0x0308EE11, +0x07110907, 0xF2F5ED0F, 0x0BFAFEF6, 0xFA12F8F9, 0xE8090606, 0x0E0CEAEC, 0x06FD10F8, 0xF80505FD, +0xF1F70912, 0xF5EF0C0B, 0xF9EF0B0B, 0x0D05F5F2, 0x0A08FF0E, 0x09F50300, 0x08F91314, 0x0AFEF60A, +0xE5FC0504, 0xEF0A000E, 0x06FDFFF1, 0x0D11F103, 0x080CF512, 0xF9F501F2, 0xFAF60708, 0xFE140D05, +0xF90202EF, 0xF0FD0EED, 0x06F2E903, 0xE904F80D, 0xF600F8F8, 0xF4FA09F5, 0x0803FA07, 0xFCF9F90B, +0xF202F4F5, 0x000EFBFE, 0x0409FAFD, 0xF0EA0DF4, 0x0B0D00FF, 0x03F8FB0D, 0x0307FAF2, 0x010C0BFB, +0x140C03FD, 0xF4FE0906, 0xF6F6F8ED, 0x0B11090D, 0xF6F90EF8, 0x09F001E8, 0xEC0600F8, 0x1109F90E, +0xEA010BEF, 0xEF0A0C0A, 0x07F510FD, 0x08F3F500, 0x07ED01F5, 0xF313F60A, 0xF803FA0E, 0xF60B0D08, +0xF1F0F709, 0x0DF609F4, 0xFCED020B, 0x0E0EEDE9, 0x08F907F2, 0xF1FC0C13, 0xFFFB0C06, 0xEB070AF7, +0xF606F80A, 0xF90E1EFF, 0xF6EE0BF5, 0x05FF03F7, 0x0F0DF309, 0xFA0CF4F8, 0x1F0CF6F3, 0xF50DEE0F, +0xF5F7FDF4, 0x0BF501EF, 0xF7FA000F, 0xECFAF0F5, 0xEA02FEF1, 0xF80FFCFC, 0x100B0600, 0xFF050501, +0xFA150716, 0x110FFFF4, 0xEE0B04F8, 0x0E0FF112, 0x12F80BF4, 0xF6F41604, 0x07EDE6EF, 0x17EE0F0B, +0x05F5FEF2, 0xEF0BFEF5, 0xFF07FD15, 0x01090709, 0x02EBEE0D, 0xF6F9FB0D, 0xEFF6070E, 0x090806F6, +0x140FFEF1, 0xF6FCEEEB, 0x07EF14F2, 0xFB03040B, 0x0A05F4FC, 0x0DF6FB0D, 0x060B02F8, 0xFF0FFB0E, +0x090709F7, 0xF7180F02, 0x0BF8F005, 0xFE0CF60D, 0x09F4ECF0, 0x0410F30A, 0xEB05F105, 0x05F90C11, +0xFCF1F30B, 0x120B0BF3, 0x031104FC, 0x030BFC0F, 0xFB09EFFC, 0xF50CFB11, 0x0BF80504, 0xF609FCF7, +0xFE0CFB00, 0x0F08F7FB, 0x0BFD0609, 0x0E120F15, 0x020B07F8, 0x0714FAF0, 0x0615F308, 0xF2FDF8F9, +0xEEF606F8, 0x050906E8, 0x071106F7, 0x000C03F8, 0x04F9F90A, 0x060BF5F7, 0x0D0CF2F7, 0x06FB02F7, +0xF7060AF5, 0x0EF1FCF4, 0xFAFAF5FE, 0x0506F917, 0xFCF40C0A, 0x03FC10E8, 0xF30700FD, 0xFCF40906, +0xFB0B0D0B, 0x1017E4F9, 0xF20408F2, 0x02FA03F7, 0xF0000E07, 0xFB0AEDF1, 0xE6F50FEB, 0xF2FCF80B, +0x04F50DFB, 0xF00BF706, 0xF70507FC, 0x0AF01609, 0xFF0DF20F, 0xEA150EF2, 0x080202F3, 0x00FAF9F5, +0xEFF70E04, 0x0FF6F314, 0xF1FEFAEE, 0x08F1F3F2, 0xF6101102, 0xF8F20206, 0x120DFC03, 0x07F8F613, +0x0CF4F50D, 0x0DFF05FB, 0x040EF409, 0xF8FB06F6, 0xF3FAF20D, 0x0DF90402, 0x05080E00, 0xF5EFEBEC, +0xFE0B0EE7, 0x0B0E0F0E, 0x04F812F4, 0x0EEE0D10, 0x021AF7EF, 0xF70F10EC, 0xF604FDFA, 0x10E90F0B, +0xF60CEFFE, 0x0AEBF407, 0xF60A06F0, 0xF50B1607, 0x1111FF0B, 0xF8F8EF08, 0xF704F410, 0x0B0AEBFE, +0x14000205, 0x03FC0EF2, 0xFD17EBFF, 0x17FAFCF4, 0x0DF90CFA, 0x1004F511, 0x140302FC, 0x14FC0500, +0xFCF6F2FE, 0x0905FA03, 0x08F3F0F4, 0x06FEF5EF, 0x09F801F8, 0xF00913F1, 0xF7F80DED, 0x040AF1FC, +0xFC0F1008, 0x07040EF4, 0x0BF6EC0C, 0x0CF8FA0C, 0xF70F0EFF, 0xFB09FBFC, 0xF9F4ED0D, 0x02F4F80B, +0xF5FCF2F2, 0x0208FDF1, 0xF20B0405, 0xF80AFAF3, 0xF415EDEA, 0xFDFBEB00, 0xF4F1F30F, 0xEC070F09, +0xFA0D0AFF, 0xF7EE0C06, 0x04F4F00B, 0x08F50FF5, 0xF50EF3FC, 0x1006E7F9, 0x04F7F7FC, 0xFC070CFB, +0x0F12EAFA, 0xF7F00706, 0xF4011505, 0xF7140B09, 0x0AF9F1F8, 0x03060DF8, 0xF2090CF8, 0xF20712F3, +0xF903EFEE, 0x1102EC14, 0x0A09F1F6, 0xF9F001FA, 0xF8FE01FB, 0x140410F1, 0x0B0402F2, 0x0F0006F5, +0x0805ECF9, 0xF409F10E, 0x0DE7FD01, 0xEFFD0710, 0xF20403FD, 0x0BF2F6F9, 0x0004F909, 0x0F09FFF6, +0xF3060DF2, 0x0EEF060E, 0x0CF40705, 0xFDF7FB0C, 0xF4F203E4, 0x0E09F4F6, 0xF5FE04F9, 0x06F3FEFE, +0xFDFB1102, 0xFD04EE0D, 0x0DFBFCF1, 0xEE14E90B, 0xFB0CEE09, 0x0C13F108, 0xF60703FD, 0x0BF4FCFA, +0x14F2F0FB, 0xFAF9EFF7, 0xF5010801, 0xF109EEF3, 0xFF0A0514, 0x0C0604FF, 0xFB0EF704, 0xF50EFD0B, +0xFF05F4FA, 0x07E70B0B, 0xEFFEF4FD, 0x0D0807F3, 0x05100DF6, 0xEFFA1A08, 0x020D090A, 0xFFF5F7FD, +0x1513F10A, 0xF10BF2ED, 0x0B0F150B, 0xF10306FA, 0x09FB11EE, 0x061007F2, 0xF7F8FB14, 0xF90704EE, +0x0AF8EAF6, 0xF7E809F9, 0x02F609E9, 0x09E802EE, 0x03F50BE8, 0x040C04F1, 0x0CF41009, 0xFB00EEFA, +0xFC071611, 0xF9F1F203, 0x0BF0F409, 0x0214F801, 0x0A0AF504, 0x0508F5F1, 0xE916E900, 0x07F4F60A, +0xF9F010F2, 0xF906F507, 0x0BFB0AF4, 0xF408F0F1, 0x0EFD0A06, 0x03F80AF6, 0x130CFD0C, 0xF1E9F7F8, +0xF800F502, 0xFEFDFDF4, 0xF90B0713, 0xF506FAFD, 0x0712F9F2, 0xEAF20DF5, 0x10F40D0D, 0x06050B09, +0xF706090E, 0x0F00ED11, 0xF90E02F4, 0xF1FEFCED, 0x0AF5E00D, 0x06F7F3F9, 0x08F81206, 0xF30EF4F5, +0x12FF02EF, 0xF7040DF4, 0x151204F0, 0x04ED07EC, 0xF0F3FB05, 0x08F2FCF4, 0xECED11FA, 0xFC110DF8, +0x0BF4F90A, 0xFCF9F905, 0xF0010014, 0x0A0EF9F8, 0xF4020C02, 0x10FDFA13, 0xF5000B05, 0x05EAF808, +0xFE0F04F3, 0xFDEFF9EE, 0xF9F9090B, 0x10F20E0C, 0x060909F0, 0x060EF40F, 0x0E0705F5, 0xFB05F6F9, +0xFA1C0512, 0x0B10FBEB, 0x16F20DF6, 0x090012F4, 0x0A13020B, 0x0EFF0C0A, 0x130DEF0C, 0x070A0B04, +0x0BFCF004, 0x02FF0BF7, 0xF9F1F209, 0xFFF5F008, 0x05F30C07, 0x03FCEE07, 0x11FCEE08, 0xF4F31514, +0x040B06F2, 0xE400F9F3, 0x13090B1A, 0xF2F4FFE7, 0xF1EE06F9, 0xFA0DFF0D, 0xF3ED09F6, 0xF40305F8, +0xF8FFF507, 0xF8FF1707, 0x0AFC030C, 0xF109F3F4, 0x0406FDF0, 0xEF04F50E, 0xF5FBF3FD, 0xF30704F4, +0xF0ECFC1C, 0xFCECF0F5, 0xF911160F, 0x020B0C0D, 0xF90C060B, 0x03FA08E7, 0x0311FF0D, 0xF405F4FA, +0x0DEBF7F2, 0x0EF6FAF2, 0x09F3ED0E, 0xFE08EFF2, 0x0F170008, 0x0DFF0FFC, 0x0BF0ED0E, 0x0D140E07, +0xF2F611F3, 0x11E9020B, 0xEE03F3F7, 0xFCFD00EF, 0xF518090B, 0xF11510EE, 0xF5FB07FF, 0xFEFC11F0, +0x100DF006, 0x0AF4F300, 0xED0A1200, 0xFEF7EDF5, 0xF7040101, 0x0FF2040E, 0xF01207F7, 0x0AF3FF10, +0xF60B0D00, 0x07F8EFED, 0x060D03FB, 0xFA08FCF6, 0xEEF6FA04, 0x0806FFF9, 0xFF0B0FF0, 0x08F3F1F8, +0xF0F5EFF3, 0xF1EE0D01, 0xFBFEF3F6, 0xF20D060B, 0xEFFE00EB, 0x080803EE, 0x0617120A, 0x1210050C, +0xF010FA07, 0x0908EF0D, 0x030908F2, 0x01160610, 0x120BF415, 0xF9F40FF1, 0x0FF00C02, 0x0B110D0B, +0x0CF9F10A, 0x0C06030D, 0xF20208F5, 0x0F07FAF1, 0xF0FAF50C, 0x08F8F7F0, 0x01EF0EEC, 0x0AEFE90C, +0xEFFCF714, 0x05F2FF13, 0xECF6F9E7, 0xFEEFFD07, 0xF6ED0F0D, 0x060FF407, 0x0803F600, 0x0105EE06, +0xF5F70D0B, 0x02EA110F, 0x070FF8F8, 0x0B040902, 0xF6F30AF0, 0x110C1AF9, 0xF61709F7, 0x0D0FF00E, +0x09F5EFF7, 0x0F13FAFD, 0x0C02F1F3, 0xFBF0F8F7, 0x0DF8F5EB, 0xF1FEF904, 0xFAF1030D, 0x161211F6, +0xFA0AF50B, 0xF316F60E, 0x100708EE, 0x0AF00A00, 0xFFF4F4EE, 0x0C0BFD18, 0xFCEDF7FE, 0xFB11080F, +0x0DF70B08, 0xF90AF309, 0xF9FD0F08, 0x10FEFA0E, 0xEE161508, 0x04FCFFFB, 0x0B1009FE, 0x0CF40D0D, +0xF800F1FC, 0x07080602, 0x1000F8F8, 0xF8F205FD, 0x0809F9F2, 0xF80C09FF, 0xF9F5F6F8, 0x05FE0EFE, +0xFCF6F8F1, 0x09000A0B, 0x07080DFC, 0x09FBEDF0, 0xEF0CF4FA, 0xF8F6100A, 0xF5F4F1F9, 0xFFFC0E0B, +0xEEF6F3EC, 0xF4EA09FE, 0xF7EFF70D, 0xEF0810FC, 0xF311FAFD, 0x0DF201EC, 0xFFF40EF3, 0x1304ED12, +0xF4FCF304, 0x09EC1005, 0x09F80C09, 0x0C10FC0C, 0xF7F7FBFC, 0xF7F60808, 0x05F90308, 0xEC0A13F4, +0xF20BF707, 0x04FE03F5, 0x10020FFE, 0x02F413ED, 0x050AF5FA, 0xF90E00E4, 0xFAFBF3F5, 0x0908140B, +0xF00A0107, 0x13EFED0E, 0x04F5F8F5, 0xF104FF0F, 0xF7F0F6F5, 0x0DF7F704, 0xFF0CEB12, 0xFAF50C07, +0x05EFF5F6, 0x12FA07F6, 0x0AFDF8F9, 0xEE050803, 0x0A04FBED, 0xF61312F2, 0xF10FF7E9, 0xFBFD0307, +0x0AFEF5F7, 0x12FB12F3, 0xFA14F206, 0xFAF80EFB, 0xFAFDFAFC, 0xFAFC0DF6, 0xFD08F1EF, 0x0B0D0D14, +0xF80EF90F, 0x0F0D0903, 0xF609ECF6, 0xF9EFF5F9, 0x0FFBFC06, 0x050A0A08, 0x01F30C03, 0xF9F8EE0A, +0x0B02100A, 0xFDF3F607, 0x0EFF0D01, 0xF8EFF0FF, 0x11F511F7, 0x08F7F809, 0xEB00FE09, 0xF1FA08FF, +0xFA0114F6, 0xF0090F10, 0xF3FBF6EF, 0x1209FE0E, 0xF7FCF309, 0x04F5F8FD, 0xF00203F2, 0xF510FB05, +0x12F7080E, 0x08F10AFC, 0xEFF6F5FE, 0xFFFA0F08, 0x0714F612, 0xF30107F5, 0x06FD08F0, 0xFA0C08EE, +0x05FA02F9, 0xF40108FF, 0xF90DF1F5, 0x17FC0300, 0x09F2080A, 0x10100BF0, 0x12020B10, 0xF5F80AF7, +0xF902EBF0, 0x16E00312, 0xFEEA0600, 0xFFFAFA13, 0xF20206F9, 0x060BEF10, 0x15FAF005, 0xF603010A, +0xF50AF110, 0xF1F903F9, 0xE508F40A, 0x0F0FF704, 0xF00B0AFC, 0xF30DFA02, 0x0202F3F9, 0xF60DEDF1, +0x05FFFC04, 0xF402FFF8, 0xF1F9F807, 0xEF0E0508, 0xF8F6F80D, 0xF4F2FAF5, 0x031209EF, 0xF9FBF6F2, +0x000AF6F5, 0xF6000D12, 0xF5FD0C08, 0x04FAEF00, 0x1103110B, 0xF1F50BF1, 0x08FD1104, 0xF80B0AF1, +0x00160DF7, 0xFD05F3F8, 0x0D01F80B, 0x100502F3, 0xFC0309F6, 0xF41207F6, 0xF2100BFD, 0x040E04F7, +0xE9080908, 0x06030EEA, 0xF40DF805, 0x09EE0608, 0x0C03F4FB, 0x080CFBF1, 0x100416F5, 0x0407F402, +0xFDFBFDFD, 0x0BF4F806, 0xFC0B16FF, 0x08EBF3F5, 0xECF9F00B, 0xF8E9F300, 0x08F802F5, 0xF3EF10F4, +0xFEF409F5, 0x15F7FA13, 0x070DF707, 0x0E0617F9, 0x0206F4FA, 0xF2FAFD0B, 0x10EB0F06, 0x1713EBFF, +0x030A0BF3, 0xF7E30003, 0xECF50DEE, 0x14050506, 0x160AFC0A, 0x0EFD01F6, 0x02050BEB, 0x031615F4, +0xF2F3FC09, 0xFA140704, 0x0AF20F07, 0xF7F9FE04, 0xF10EEC06, 0x130D0BFC, 0xF6F3ED0F, 0xF20D100D, +0xF1F6F40C, 0x0E0BF1F2, 0x0C0FF513, 0xEBEE13FB, 0xF80EF409, 0xF608EC0A, 0xF9090DF1, 0xF602EF09, +0x14F7F6EF, 0xF401F9F0, 0x130B10FB, 0x0FF31101, 0xEC0912ED, 0x0D03F9F8, 0xF4FAF103, 0xFEF4F10A, +0xF60BE90A, 0xFFF0F7F1, 0xF801F2F0, 0x00150B1A, 0x09EE130F, 0x130DF7EA, 0x13FB0008, 0xF1F9F00E, +0x0501F5F0, 0x03F60BF8, 0x090BFE05, 0xEBF8FAF3, 0xEA12F90A, 0xF4FCF4F0, 0x0DF81312, 0x01130DF8, +0xF3060CF2, 0x00F10CF4, 0xE8F611F0, 0xF707FEF6, 0xF81013FC, 0xF0040AFD, 0xF60616FC, 0xFE1109ED, +0xED140DED, 0x0303F812, 0xFDF4F4F8, 0x0CF60B14, 0x0DF11811, 0x0BF4FBFA, 0xF2F906F9, 0x09F3F806, +0x030608FA, 0x0A14E20D, 0x0A08F5FA, 0xE7060DFB, 0x02FD050B, 0xF4F6FB07, 0x01F90BF7, 0x0CFA0FF3, +0x0B04FD01, 0x0F090604, 0x060E0F0A, 0xF6F1FF06, 0xFC0C0611, 0x01030C0D, 0xF612F9F6, 0x120FF002, +0xF0F0F9F0, 0x10FE0DFC, 0xEAFCF6E7, 0xF4F0FFFC, 0xEA080D01, 0x09F6020A, 0xF1EDF2F7, 0xF80609F8, +0xF8F7F80F, 0xF8F7FEFB, 0x0AEE03F4, 0xF60F0406, 0x1309EF03, 0x1215F7FC, 0x0EED07ED, 0x08F30DF5, +0x09E90D02, 0xF1FAFDF4, 0xFD0FFEF4, 0x0317F1F2, 0xF3111203, 0xF208FEFC, 0xF5FB0213, 0x15F20702, +0x0FF918ED, 0xF3F8FF0B, 0x0F0A0A0B, 0xEE0C0A13, 0x0A0AF506, 0x1A0401F6, 0xF0F6080F, 0xEC091201, +0xF9F90C02, 0xF10CF003, 0xF217F200, 0x0DF8FA11, 0x04F603F6, 0x03FB10FA, 0x0AF4090D, 0xF1FBF3EF, +0x0DF00505, 0xFA0B0E0E, 0xFD030811, 0xFEEDF80A, 0xF1F1F40B, 0x050D0514, 0x0DFC0A10, 0xFF0D01EB, +0x07F7010D, 0xF90D00F6, 0xFCEDF108, 0xFD10F30C, 0xF3F7FB06, 0xF009F8FF, 0xF808F8F5, 0xEF12F009, +0x0C0E14F8, 0x02010E06, 0xFF00F50D, 0xF9F1F309, 0x0507EEF0, 0xF8EFFDFB, 0x05041303, 0xFC13EEF6 + +basegraph= +1 + +z_c= +176 + +n_cb= +11616 + +q_m= +2 + +n_filler= +8 + +e= +4640 + +rv_index= +0 + +code_block_mode= +1 + +iter_max= +20 + +expected_iter_count= +20 + +op_flags= +RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE + +expected_status= +SYN diff --git a/app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_1.data b/app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_1.data new file mode 100644 index 0000000..19a1537 --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_1.data @@ -0,0 +1,685 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2019 Intel Corporation +# Origin : FEC5G_UL_1/xxxx + +op_type = +RTE_BBDEV_OP_LDPC_DEC + +input0 = +0xF30110EF, 0x09FB0E0E, 0xFB0BF902, 0x10FF060C, 0xF70A10FB, 0xF007F709, 0x0CF30FF1, 0xFC0B07FB, +0xEA0FFA0D, 0xFB0B1209, 0x0709F1F2, 0x0BF1F004, 0x000EF10B, 0x08F8010A, 0xF70E0909, 0xF7EC00F6, +0x05F2F8F9, 0x0A060D10, 0x0DFB0CEF, 0xEFF4F2F9, 0xF80DF8F9, 0xF20809ED, 0xFDFEF3FE, 0xF2FC07F9, +0xEF12EEF8, 0x0D0FEF0C, 0x011714F4, 0xFDF902F3, 0x05020A13, 0x0A0BF5F8, 0x1517FA10, 0x0DFF04FD, +0xED0F0FFB, 0x0C0B12F8, 0x10F205EE, 0x14EEF0F6, 0xEEF50606, 0xF701F006, 0xF2120906, 0x0FF31409, +0x0004F9F0, 0x080005F5, 0x05000E18, 0x080BF50C, 0xE9FA01EF, 0x0DFDE702, 0xF303FC08, 0x0306FDED, +0x0302FD15, 0xF2F404F6, 0xF60B0DFC, 0xF702F2F8, 0x0D0109ED, 0xECF2F006, 0xFFF50AF3, 0xFB0609F7, +0xF9FAF2FC, 0xF3010611, 0xF2F20EF8, 0x0EF203EC, 0xF30C050D, 0x0CFB0905, 0x10EAF80A, 0x1103F714, +0x17FCE4F8, 0xF409F2F4, 0x09000A13, 0x0EF009F8, 0xF00DF90A, 0x0AF612E9, 0x12F4FE15, 0x06F3F307, +0xFDF4EEF8, 0xFDFBFB04, 0x02F30DF1, 0xE9F0F006, 0x10F80508, 0x0DFAFBF9, 0xE9F10B09, 0x020600F9, +0x020AF50C, 0x0FED0C0A, 0x05FCF403, 0xF8F3FFF6, 0x0312FD0A, 0x0A05F308, 0x10F10E00, 0x0B0CF40D, +0x04090FFF, 0x1402F2FF, 0xEF0D0B01, 0x0E00F9F8, 0x08040110, 0x0A04EDE5, 0xEE13080C, 0x05F6F516, +0x05F414EC, 0xFF030A00, 0xF0F5FF06, 0xF809F20E, 0xF70CF014, 0x0FFAFA0E, 0x1201F611, 0xE10E0EF1, +0xF40FFA09, 0x13F2F103, 0x0B030B0E, 0xF303FCF3, 0xF405FD09, 0xEF09FEEA, 0x07F908FB, 0xF9FD08FE, +0xF9F7F602, 0x0506FCF4, 0x060BF4F3, 0x040C0E0D, 0xF5F9F606, 0x02FF0DFB, 0x0BF51112, 0x13F7F5FB, +0xF10AF6F8, 0x15031311, 0x07F7ED0D, 0x050AF7F7, 0x0101F708, 0xF717FBF6, 0x06FAFA05, 0xF1F8EF11, +0x11070200, 0x09EEFB04, 0x07EF0601, 0x0603FCFE, 0x0FEC140B, 0xF7F7F806, 0xF00A02FA, 0x0E06F30C, +0xFEF90A10, 0x0AECF80E, 0xF5F2F907, 0x0B08E804, 0x0902E9F7, 0xEE09F6E9, 0xEEF60210, 0x09F7E8FD, +0x0B0CFC0B, 0x030C0905, 0xF0F6F109, 0xF0F8F8E7, 0x100A0913, 0xF8FB0817, 0x0204FA04, 0x0FF00008, +0x02F4FD13, 0xFCE8F208, 0x06EBEF07, 0x0DF1F1F4, 0x0801F5F7, 0xF7EB04FC, 0x0C0A15E8, 0x020B1404, +0xF502EF0E, 0xF600F6F1, 0x090705EC, 0xF1F008F2, 0xFDF2EC11, 0xE90E02FF, 0xF615F6F4, 0xF3F3F4F8, +0xFC0BF20B, 0xF9F90402, 0xF512F301, 0xF90E06F7, 0x0AFC080C, 0xF707FB06, 0xF0F6F1FA, 0x0806F4FD, +0xF6F8F10A, 0x0EFBFDF7, 0xF60EF6FD, 0x0308F809, 0x11050CFF, 0xFF140CFD, 0xF7FEF80A, 0xF1F4FD03, +0xF5EF0203, 0xF8F514F8, 0x11F808F7, 0x12FBFD0A, 0xF3F41309, 0x0D0FF700, 0xFA0B1103, 0xF50A06EF, +0xF902F210, 0x070FFEFB, 0x0D070910, 0xEA11F207, 0x0D0B0D0B, 0xFCF1F408, 0xF70809E8, 0x06F2F10E, +0x1DF5FAEB, 0xF7F0F20C, 0xED0C110E, 0xFBF000F3, 0x0208080D, 0x0DFCFAF0, 0x11EE0107, 0xF109FE00, +0xF4FCF9FE, 0x0AFAF501, 0xF3E7F90B, 0x06E70B12, 0xFDFE06F9, 0x08F00C04, 0xF409090D, 0xF30C0EF5, +0x02F6EF06, 0x12F6EB0E, 0x0DFA09F8, 0x0BF8EFF4, 0xF015F007, 0x15ED1206, 0x07050006, 0x18EF0111, +0x0FF2050C, 0x05F9070F, 0xFCF80813, 0xF3F90611, 0xFDF30EEF, 0x00FC0112, 0x0DF1F8FC, 0x10F7FDF9, +0xF9EA0AE9, 0xF70E0807, 0x0DF105F8, 0x100E0DF8, 0x140F14EA, 0x04F60107, 0x0D030C10, 0x0AF0F9FA, +0xF814EE17, 0xF4F802FE, 0xFA06FFF9, 0xFCF811F3, 0xF6F5050E, 0xF5FB00FC, 0xF811F4F3, 0xF0ECEA0D, +0x04F7070A, 0x12090F00, 0xF9FBEEF3, 0x11F8030E, 0xF5F8F7F6, 0xF90BF908, 0x0E0FF80C, 0x10EF06F0, +0xF5F804FA, 0x06F70909, 0x08EB0F13, 0xF20E0E16, 0xF11509FE, 0x0E0BF3F4, 0xF60F0E0B, 0xFBF405F2, +0x050AFDF3, 0x0EEC1C0C, 0xFBFBEB02, 0xF71310F8, 0xF9080BFB, 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0x0A000A14, 0x010E0AF2, 0x0603F010, 0xF4EBFBFF, 0xF011F617, 0x12100108, 0x0017F5FA, +0x0CF8020E, 0x0D0DF9F9, 0xF0F5EF11, 0xF1FCF8F0, 0x06EEECFC, 0x06141703, 0x0EF1FD00, 0x0D00F810, +0x03060A12, 0xF011F60A, 0x10FA0EEF, 0x03F5FB05, 0xF5040DF4, 0xF6F408F3, 0x0809EFEF, 0xF1060F12, +0xF115050C, 0xF909F00C, 0xFA130E06, 0x0E04F7F4, 0x080D11ED, 0xFD0B030C, 0x0CF1F610, 0x12F0EDF6, +0x0810F708, 0x05FC050F, 0x050E1408, 0x05F3F9EF, 0x0AEC10F8, 0x0D0B100A, 0x01FAFF0C, 0xEA0CF9F8, +0x010E0DFF, 0x07F70BFB, 0x140F0AFC, 0xF90F0DF5, 0xF1EDF4F8, 0xFC0D02F4, 0xF30CF80B, 0xE902FC08, +0x0FF2F2F2, 0x07F5F710, 0xF8FDFFF1, 0x04020908, 0x0C04F5F1, 0x0C06080B, 0xF0E6F507, 0x03F8FEF6, +0x00ED0CFF, 0xF8F40E15, 0xFAEBF2EC, 0x02E801FB, 0x09F30D0F, 0x13081405, 0x070FF509, 0xF90005F3, +0x02F6F0EB, 0x05FAF30D, 0xFDF8FB06, 0x0C0BEFEE, 0x13F0EF0B, 0xF1041808, 0xEEFBF609, 0x10F4FFF5 + +harq_input0 = +0x0FFA0103, 0x130C0B02, 0xF309F6E7, 0xF70F07F1, 0xF7090FF8, 0x050409F2, 0xF80AFAF7, 0x00F60EF5, +0x06FC060D, 0x080DFB03, 0xF4EDF9F9, 0xFCF9FEEA, 0x0F0C12F8, 0xF9F31708, 0xF60C02FF, 0xFF110310, +0x0BF80F0F, 0x02F6F2EE, 0xEDF20A06, 0x0709FEF2, 0x14F5F0F0, 0xF70C0018, 0x12020FEF, 0x0602EF08, +0xF40A0200, 0xEE0C0BFC, 0x0606ED01, 0xF2F709F3, 0x15110E10, 0x06EC06F8, 0xFBF10CF8, 0x0314FEF6, +0xF5F4FC0C, 0xF00C00FF, 0xF6FDF9F6, 0x07F30801, 0x0F04F40C, 0x0406F305, 0xFAF9F808, 0xF20DF109, +0x010A0AF8, 0x070AFC03, 0xF108120A, 0xF8F9F1EC, 0xEEEB09FF, 0x140C0D01, 0x04E5EF10, 0xF616130C, +0x0314F4EC, 0x09FA09F2, 0xFAFAF714, 0xFAF101FD, 0x06030FF4, 0x17F3EFFA, 0x09FEF109, 0xFDFEF9FB, +0xF2080B02, 0x0CF90B07, 0xEB0F0D06, 0xF71009FE, 0xEF110AF8, 0x0AF70BF9, 0x170A1508, 0xF8FDFAF1, +0x0204F3EB, 0xEFFE0315, 0x0C06000B, 0xF10C0A0E, 0xEC0EF9FC, 0x08F0F2F3, 0x09FD02F7, 0x0B11F610, +0xF8F1F8F7, 0xF8FB0A09, 0xFB030A13, 0x040804F0, 0xE8080813, 0xF1F4FFF3, 0xEBFCEDF7, 0xF7F00AE8, +0x00F1160E, 0xF007F301, 0x0E13F211, 0x07F815F4, 0xF9EEF70B, 0x0EF7FE15, 0x0706E80C, 0x0611F60E, +0xFB0B0CF5, 0xF4F50E11, 0x14FDF1EB, 0xF403120A, 0x09F80303, 0xFB0AF80B, 0xFA1408F5, 0xF503F717, +0x0FFB1610, 0x1107F3FC, 0xF1F4F7F7, 0x060EF4E8, 0x04F8F5FF, 0x04F30CFA, 0x10F008F8, 0xF514EEF3, +0x0EEDE8FE, 0xE7FEE70B, 0x0404FEF9, 0xF8F509F9, 0x0A0EF6F2, 0xF8080EF8, 0x01F200F3, 0x03FC19F2, +0x0D0FF2F8, 0xF9FD0C13, 0x11FE0703, 0x0BF9F110, 0x0EF3FEFD, 0x0EF8F10C, 0x0A070FEA, 0x04FA0310, +0x0CFE0003, 0x0CF3060D, 0xFBFCF5FA, 0xEC0D1108, 0x09ECF70A, 0x0C0EFB08, 0x0BF4F80A, 0xEFF0FB0C, +0x0B09F8FA, 0xFA16FF13, 0x0B081512, 0xF4F2FBF7, 0x000C0A07, 0x130C0FEE, 0xFEF908FB, 0xF6F5F912, +0xF1100409, 0x090E1606, 0xF4F50BF3, 0xEE00F7F9, 0xFAFBF5F6, 0x07080B0A, 0xF1150BE7, 0x0DF80912, +0x12EF0809, 0xEBFF1108, 0x0BF60DFE, 0x130DF608, 0x12EFF2F1, 0x04FB0C0B, 0x01FDFC09, 0xFAF808F9, +0x12020B01, 0xFCED060F, 0x040DFFFF, 0x04F80AF3, 0xF700F60B, 0x08F40E08, 0x06F7F80F, 0x0DFDEF04, +0xFDEFF916, 0xF21107EF, 0x0A1110F1, 0x03F70DF3, 0x08F50300, 0xF1F711F9, 0xF6FCFF0C, 0x0CFFF704, +0x080CFE09, 0x0FF80D06, 0x05080C08, 0xFE020210, 0xFB11F6E9, 0x060BF2F1, 0xED0BEAF9, 0x02F30C02, +0xF8F40DFB, 0x020D0D01, 0x0CF406F1, 0xF302F812, 0x080C0EF2, 0x06010006, 0xF0FA0908, 0x08F9F905, +0xFB0A0508, 0x0FF0F7F4, 0xFF081210, 0xEE18F6F1, 0xF9F9E8F2, 0x060B09FD, 0x0AFEEE04, 0x09F304F8, +0xEA05F6F8, 0x1C0108F5, 0xF205120F, 0xF40D0A04, 0x0001F30D, 0x00FF0DFA, 0x020BF7F7, 0x02F2F7F0, +0x04F90BF1, 0x01EFEE07, 0xEBE4F807, 0x0AF90FEF, 0x0F040B11, 0x0BF91000, 0x000CF812, 0x0311F3F0, +0xF8070218, 0xEDFFF614, 0xF00C15F1, 0x000D0F16, 0xFA0EF707, 0xEE080901, 0xFF0C09F5, 0xEEF704F1, +0xF10C10F9, 0x060BEBF7, 0xFA0EFDF6, 0xF7F403F2, 0xF5F0F306, 0xEC081A0F, 0x020AEEF5, 0xFBF9F7FB, +0xF60C010A, 0xEC0E0FFF, 0xF014FB10, 0x0EFD0308, 0x04F30015, 0xF4FC0CEE, 0x0CFEF3F7, 0x12F0F702, +0xE803FB07, 0x040D06F5, 0x05FA07F1, 0x140A0BF8, 0xEFEDFF11, 0x01EFEE13, 0x0D0C0B0F, 0xE70105F0, +0x01F70CF4, 0x0603EE12, 0xED08EDF9, 0xF2FCFA02, 0x0E0CFCF3, 0x0E04F8F9, 0xF30D17F9, 0xFEEDFB05, +0x071BF114, 0xF309F7F4, 0x02F503F6, 0x0815F400, 0x0CF0090A, 0xE80D0F02, 0xF9FCFDF8, 0xF00FFEF5, +0xF3F5F70B, 0xFC10F7EF, 0xF2FB0AFE, 0xEEECEC15, 0x0202F60E, 0xF310FEF9, 0x10F8F209, 0xFB0606EE, +0x0D0B0C10, 0x1110080C, 0xFCF2F8F6, 0x030DEE07, 0x0C11F511, 0x0CF6EF08, 0x0900070C, 0x0C160E0F, +0xEEF8FFF9, 0xF7F0EEF5, 0x0A090903, 0xF70A000E, 0xF5FF07F6, 0xF5E5FEFD, 0x08F1F80C, 0x00F2EE0D, +0xFAED07EA, 0x07EA170B, 0xFEFFECFF, 0xED0B0211, 0x0AF4F4E6, 0xF2FAF705, 0x0807F706, 0xFBF2F8F7, +0xF31105F7, 0xF10809FB, 0xF1FEF307, 0x0805FFFA, 0x08FC070D, 0x0A071200, 0xEEEDF107, 0xF908EDFB, +0x09F60FF2, 0x0B0C06F8, 0x07FCF608, 0x000FF30C, 0xFF0EF3FD, 0xE40BFCF4, 0x0CF50BF4, 0x04EDE90D, +0xFD05F3F1, 0xFAECF4FA, 0xF80C080F, 0x0A0BF70A, 0x07F012F4, 0x1109FEF3, 0xF507F9F1, 0xF513F7FD, +0xFE0AF80F, 0x041701F1, 0xF5E7F309, 0x0A0AF70C, 0x0E00FEF1, 0x04E505EF, 0xF4EF0BFD, 0x040CF807, +0x1201EF07, 0xF31508F1, 0xF908F309, 0x0B0EE409, 0xF7EBF9F8, 0xF1F7F406, 0xFB0206F6, 0xECFD11F2, +0x0702EEF6, 0xF409FC04, 0xEEF80010, 0xF3EC0BF0, 0x090600F1, 0xF9F5EBF7, 0xEEFE11F8, 0x070BF0FA, +0xFE16EEF8, 0xF108FD05, 0x15FAF3F7, 0xF60E0D0D, 0xF7FC0AF8, 0x01F40805, 0xF70AFE01, 0xFB0F0BF9, +0x04E701F6, 0x09F517F6, 0xFBE8F5F8, 0x11FE00F6, 0xEF08F2F5, 0xFB0CFB0F, 0x0419080B, 0x0308EE11, +0x07110907, 0xF2F5ED0F, 0x0BFAFEF6, 0xFA12F8F9, 0xE8090606, 0x0E0CEAEC, 0x06FD10F8, 0xF80505FD, +0xF1F70912, 0xF5EF0C0B, 0xF9EF0B0B, 0x0D05F5F2, 0x0A08FF0E, 0x09F50300, 0x08F91314, 0x0AFEF60A, +0xE5FC0504, 0xEF0A000E, 0x06FDFFF1, 0x0D11F103, 0x080CF512, 0xF9F501F2, 0xFAF60708, 0xFE140D05, +0xF90202EF, 0xF0FD0EED, 0x06F2E903, 0xE904F80D, 0xF600F8F8, 0xF4FA09F5, 0x0803FA07, 0xFCF9F90B, +0xF202F4F5, 0x000EFBFE, 0x0409FAFD, 0xF0EA0DF4, 0x0B0D00FF, 0x03F8FB0D, 0x0307FAF2, 0x010C0BFB, +0x140C03FD, 0xF4FE0906, 0xF6F6F8ED, 0x0B11090D, 0xF6F90EF8, 0x09F001E8, 0xEC0600F8, 0x1109F90E, +0xEA010BEF, 0xEF0A0C0A, 0x07F510FD, 0x08F3F500, 0x07ED01F5, 0xF313F60A, 0xF803FA0E, 0xF60B0D08, +0xF1F0F709, 0x0DF609F4, 0xFCED020B, 0x0E0EEDE9, 0x08F907F2, 0xF1FC0C13, 0xFFFB0C06, 0xEB070AF7, +0xF606F80A, 0xF90E1EFF, 0xF6EE0BF5, 0x05FF03F7, 0x0F0DF309, 0xFA0CF4F8, 0x1F0CF6F3, 0xF50DEE0F, +0xF5F7FDF4, 0x0BF501EF, 0xF7FA000F, 0xECFAF0F5, 0xEA02FEF1, 0xF80FFCFC, 0x100B0600, 0xFF050501, +0xFA150716, 0x110FFFF4, 0xEE0B04F8, 0x0E0FF112, 0x12F80BF4, 0xF6F41604, 0x07EDE6EF, 0x17EE0F0B, +0x05F5FEF2, 0xEF0BFEF5, 0xFF07FD15, 0x01090709, 0x02EBEE0D, 0xF6F9FB0D, 0xEFF6070E, 0x090806F6, +0x140FFEF1, 0xF6FCEEEB, 0x07EF14F2, 0xFB03040B, 0x0A05F4FC, 0x0DF6FB0D, 0x060B02F8, 0xFF0FFB0E, +0x090709F7, 0xF7180F02, 0x0BF8F005, 0xFE0CF60D, 0x09F4ECF0, 0x0410F30A, 0xEB05F105, 0x05F90C11, +0xFCF1F30B, 0x120B0BF3, 0x031104FC, 0x030BFC0F, 0xFB09EFFC, 0xF50CFB11, 0x0BF80504, 0xF609FCF7, +0xFE0CFB00, 0x0F08F7FB, 0x0BFD0609, 0x0E120F15, 0x020B07F8, 0x0714FAF0, 0x0615F308, 0xF2FDF8F9, +0xEEF606F8, 0x050906E8, 0x071106F7, 0x000C03F8, 0x04F9F90A, 0x060BF5F7, 0x0D0CF2F7, 0x06FB02F7, +0xF7060AF5, 0x0EF1FCF4, 0xFAFAF5FE, 0x0506F917, 0xFCF40C0A, 0x03FC10E8, 0xF30700FD, 0xFCF40906, +0xFB0B0D0B, 0x1017E4F9, 0xF20408F2, 0x02FA03F7, 0xF0000E07, 0xFB0AEDF1, 0xE6F50FEB, 0xF2FCF80B, +0x04F50DFB, 0xF00BF706, 0xF70507FC, 0x0AF01609, 0xFF0DF20F, 0xEA150EF2, 0x080202F3, 0x00FAF9F5, +0xEFF70E04, 0x0FF6F314, 0xF1FEFAEE, 0x08F1F3F2, 0xF6101102, 0xF8F20206, 0x120DFC03, 0x07F8F613, +0x0CF4F50D, 0x0DFF05FB, 0x040EF409, 0xF8FB06F6, 0xF3FAF20D, 0x0DF90402, 0x05080E00, 0xF5EFEBEC, +0xFE0B0EE7, 0x0B0E0F0E, 0x04F812F4, 0x0EEE0D10, 0x021AF7EF, 0xF70F10EC, 0xF604FDFA, 0x10E90F0B, +0xF60CEFFE, 0x0AEBF407, 0xF60A06F0, 0xF50B1607, 0x1111FF0B, 0xF8F8EF08, 0xF704F410, 0x0B0AEBFE, +0x14000205, 0x03FC0EF2, 0xFD17EBFF, 0x17FAFCF4, 0x0DF90CFA, 0x1004F511, 0x140302FC, 0x14FC0500, +0xFCF6F2FE, 0x0905FA03, 0x08F3F0F4, 0x06FEF5EF, 0x09F801F8, 0xF00913F1, 0xF7F80DED, 0x040AF1FC, +0xFC0F1008, 0x07040EF4, 0x0BF6EC0C, 0x0CF8FA0C, 0xF70F0EFF, 0xFB09FBFC, 0xF9F4ED0D, 0x02F4F80B, +0xF5FCF2F2, 0x0208FDF1, 0xF20B0405, 0xF80AFAF3, 0xF415EDEA, 0xFDFBEB00, 0xF4F1F30F, 0xEC070F09, +0xFA0D0AFF, 0xF7EE0C06, 0x04F4F00B, 0x08F50FF5, 0xF50EF3FC, 0x1006E7F9, 0x04F7F7FC, 0xFC070CFB, +0x0F12EAFA, 0xF7F00706, 0xF4011505, 0xF7140B09, 0x0AF9F1F8, 0x03060DF8, 0xF2090CF8, 0xF20712F3, +0xF903EFEE, 0x1102EC14, 0x0A09F1F6, 0xF9F001FA, 0xF8FE01FB, 0x140410F1, 0x0B0402F2, 0x0F0006F5, +0x0805ECF9, 0xF409F10E, 0x0DE7FD01, 0xEFFD0710, 0xF20403FD, 0x0BF2F6F9, 0x0004F909, 0x0F09FFF6, +0xF3060DF2, 0x0EEF060E, 0x0CF40705, 0xFDF7FB0C, 0xF4F203E4, 0x0E09F4F6, 0xF5FE04F9, 0x06F3FEFE, +0xFDFB1102, 0xFD04EE0D, 0x0DFBFCF1, 0xEE14E90B, 0xFB0CEE09, 0x0C13F108, 0xF60703FD, 0x0BF4FCFA, +0x14F2F0FB, 0xFAF9EFF7, 0xF5010801, 0xF109EEF3, 0xFF0A0514, 0x0C0604FF, 0xFB0EF704, 0xF50EFD0B, +0xFF05F4FA, 0x07E70B0B, 0xEFFEF4FD, 0x0D0807F3, 0x05100DF6, 0xEFFA1A08, 0x020D090A, 0xFFF5F7FD, +0x1513F10A, 0xF10BF2ED, 0x0B0F150B, 0xF10306FA, 0x09FB11EE, 0x061007F2, 0xF7F8FB14, 0xF90704EE, +0x0AF8EAF6, 0xF7E809F9, 0x02F609E9, 0x09E802EE, 0x03F50BE8, 0x040C04F1, 0x0CF41009, 0xFB00EEFA, +0xFC071611, 0xF9F1F203, 0x0BF0F409, 0x0214F801, 0x0A0AF504, 0x0508F5F1, 0xE916E900, 0x07F4F60A, +0xF9F010F2, 0xF906F507, 0x0BFB0AF4, 0xF408F0F1, 0x0EFD0A06, 0x03F80AF6, 0x130CFD0C, 0xF1E9F7F8, +0xF800F502, 0xFEFDFDF4, 0xF90B0713, 0xF506FAFD, 0x0712F9F2, 0xEAF20DF5, 0x10F40D0D, 0x06050B09, +0xF706090E, 0x0F00ED11, 0xF90E02F4, 0xF1FEFCED, 0x0AF5E00D, 0x06F7F3F9, 0x08F81206, 0xF30EF4F5, +0x12FF02EF, 0xF7040DF4, 0x151204F0, 0x04ED07EC, 0xF0F3FB05, 0x08F2FCF4, 0xECED11FA, 0xFC110DF8, +0x0BF4F90A, 0xFCF9F905, 0xF0010014, 0x0A0EF9F8, 0xF4020C02, 0x10FDFA13, 0xF5000B05, 0x05EAF808, +0xFE0F04F3, 0xFDEFF9EE, 0xF9F9090B, 0x10F20E0C, 0x060909F0, 0x060EF40F, 0x0E0705F5, 0xFB05F6F9, +0xFA1C0512, 0x0B10FBEB, 0x16F20DF6, 0x090012F4, 0x0A13020B, 0x0EFF0C0A, 0x130DEF0C, 0x070A0B04, +0x0BFCF004, 0x02FF0BF7, 0xF9F1F209, 0xFFF5F008, 0x05F30C07, 0x03FCEE07, 0x11FCEE08, 0xF4F31514, +0x040B06F2, 0xE400F9F3, 0x13090B1A, 0xF2F4FFE7, 0xF1EE06F9, 0xFA0DFF0D, 0xF3ED09F6, 0xF40305F8, +0xF8FFF507, 0xF8FF1707, 0x0AFC030C, 0xF109F3F4, 0x0406FDF0, 0xEF04F50E, 0xF5FBF3FD, 0xF30704F4, +0xF0ECFC1C, 0xFCECF0F5, 0xF911160F, 0x020B0C0D, 0xF90C060B, 0x03FA08E7, 0x0311FF0D, 0xF405F4FA, +0x0DEBF7F2, 0x0EF6FAF2, 0x09F3ED0E, 0xFE08EFF2, 0x0F170008, 0x0DFF0FFC, 0x0BF0ED0E, 0x0D140E07, +0xF2F611F3, 0x11E9020B, 0xEE03F3F7, 0xFCFD00EF, 0xF518090B, 0xF11510EE, 0xF5FB07FF, 0xFEFC11F0, +0x100DF006, 0x0AF4F300, 0xED0A1200, 0xFEF7EDF5, 0xF7040101, 0x0FF2040E, 0xF01207F7, 0x0AF3FF10, +0xF60B0D00, 0x07F8EFED, 0x060D03FB, 0xFA08FCF6, 0xEEF6FA04, 0x0806FFF9, 0xFF0B0FF0, 0x08F3F1F8, +0xF0F5EFF3, 0xF1EE0D01, 0xFBFEF3F6, 0xF20D060B, 0xEFFE00EB, 0x080803EE, 0x0617120A, 0x1210050C, +0xF010FA07, 0x0908EF0D, 0x030908F2, 0x01160610, 0x120BF415, 0xF9F40FF1, 0x0FF00C02, 0x0B110D0B, +0x0CF9F10A, 0x0C06030D, 0xF20208F5, 0x0F07FAF1, 0xF0FAF50C, 0x08F8F7F0, 0x01EF0EEC, 0x0AEFE90C, +0xEFFCF714, 0x05F2FF13, 0xECF6F9E7, 0xFEEFFD07, 0xF6ED0F0D, 0x060FF407, 0x0803F600, 0x0105EE06, +0xF5F70D0B, 0x02EA110F, 0x070FF8F8, 0x0B040902, 0xF6F30AF0, 0x110C1AF9, 0xF61709F7, 0x0D0FF00E, +0x09F5EFF7, 0x0F13FAFD, 0x0C02F1F3, 0xFBF0F8F7, 0x0DF8F5EB, 0xF1FEF904, 0xFAF1030D, 0x161211F6, +0xFA0AF50B, 0xF316F60E, 0x100708EE, 0x0AF00A00, 0xFFF4F4EE, 0x0C0BFD18, 0xFCEDF7FE, 0xFB11080F, +0x0DF70B08, 0xF90AF309, 0xF9FD0F08, 0x10FEFA0E, 0xEE161508, 0x04FCFFFB, 0x0B1009FE, 0x0CF40D0D, +0xF800F1FC, 0x07080602, 0x1000F8F8, 0xF8F205FD, 0x0809F9F2, 0xF80C09FF, 0xF9F5F6F8, 0x05FE0EFE, +0xFCF6F8F1, 0x09000A0B, 0x07080DFC, 0x09FBEDF0, 0xEF0CF4FA, 0xF8F6100A, 0xF5F4F1F9, 0xFFFC0E0B, +0xEEF6F3EC, 0xF4EA09FE, 0xF7EFF70D, 0xEF0810FC, 0xF311FAFD, 0x0DF201EC, 0xFFF40EF3, 0x1304ED12, +0xF4FCF304, 0x09EC1005, 0x09F80C09, 0x0C10FC0C, 0xF7F7FBFC, 0xF7F60808, 0x05F90308, 0xEC0A13F4, +0xF20BF707, 0x04FE03F5, 0x10020FFE, 0x02F413ED, 0x050AF5FA, 0xF90E00E4, 0xFAFBF3F5, 0x0908140B, +0xF00A0107, 0x13EFED0E, 0x04F5F8F5, 0xF104FF0F, 0xF7F0F6F5, 0x0DF7F704, 0xFF0CEB12, 0xFAF50C07, +0x05EFF5F6, 0x12FA07F6, 0x0AFDF8F9, 0xEE050803, 0x0A04FBED, 0xF61312F2, 0xF10FF7E9, 0xFBFD0307, +0x0AFEF5F7, 0x12FB12F3, 0xFA14F206, 0xFAF80EFB, 0xFAFDFAFC, 0xFAFC0DF6, 0xFD08F1EF, 0x0B0D0D14, +0xF80EF90F, 0x0F0D0903, 0xF609ECF6, 0xF9EFF5F9, 0x0FFBFC06, 0x050A0A08, 0x01F30C03, 0xF9F8EE0A, +0x0B02100A, 0xFDF3F607, 0x0EFF0D01, 0xF8EFF0FF, 0x11F511F7, 0x08F7F809, 0xEB00FE09, 0xF1FA08FF, +0xFA0114F6, 0xF0090F10, 0xF3FBF6EF, 0x1209FE0E, 0xF7FCF309, 0x04F5F8FD, 0xF00203F2, 0xF510FB05, +0x12F7080E, 0x08F10AFC, 0xEFF6F5FE, 0xFFFA0F08, 0x0714F612, 0xF30107F5, 0x06FD08F0, 0xFA0C08EE, +0x05FA02F9, 0xF40108FF, 0xF90DF1F5, 0x17FC0300, 0x09F2080A, 0x10100BF0, 0x12020B10, 0xF5F80AF7, +0xF902EBF0, 0x16E00312, 0xFEEA0600, 0xFFFAFA13, 0xF20206F9, 0x060BEF10, 0x15FAF005, 0xF603010A, +0xF50AF110, 0xF1F903F9, 0xE508F40A, 0x0F0FF704, 0xF00B0AFC, 0xF30DFA02, 0x0202F3F9, 0xF60DEDF1, +0x05FFFC04, 0xF402FFF8, 0xF1F9F807, 0xEF0E0508, 0xF8F6F80D, 0xF4F2FAF5, 0x031209EF, 0xF9FBF6F2, +0x000AF6F5, 0xF6000D12, 0xF5FD0C08, 0x04FAEF00, 0x1103110B, 0xF1F50BF1, 0x08FD1104, 0xF80B0AF1, +0x00160DF7, 0xFD05F3F8, 0x0D01F80B, 0x100502F3, 0xFC0309F6, 0xF41207F6, 0xF2100BFD, 0x040E04F7, +0xE9080908, 0x06030EEA, 0xF40DF805, 0x09EE0608, 0x0C03F4FB, 0x080CFBF1, 0x100416F5, 0x0407F402, +0xFDFBFDFD, 0x0BF4F806, 0xFC0B16FF, 0x08EBF3F5, 0xECF9F00B, 0xF8E9F300, 0x08F802F5, 0xF3EF10F4, +0xFEF409F5, 0x15F7FA13, 0x070DF707, 0x0E0617F9, 0x0206F4FA, 0xF2FAFD0B, 0x10EB0F06, 0x1713EBFF, +0x030A0BF3, 0xF7E30003, 0xECF50DEE, 0x14050506, 0x160AFC0A, 0x0EFD01F6, 0x02050BEB, 0x031615F4, +0xF2F3FC09, 0xFA140704, 0x0AF20F07, 0xF7F9FE04, 0xF10EEC06, 0x130D0BFC, 0xF6F3ED0F, 0xF20D100D, +0xF1F6F40C, 0x0E0BF1F2, 0x0C0FF513, 0xEBEE13FB, 0xF80EF409, 0xF608EC0A, 0xF9090DF1, 0xF602EF09, +0x14F7F6EF, 0xF401F9F0, 0x130B10FB, 0x0FF31101, 0xEC0912ED, 0x0D03F9F8, 0xF4FAF103, 0xFEF4F10A, +0xF60BE90A, 0xFFF0F7F1, 0xF801F2F0, 0x00150B1A, 0x09EE130F, 0x130DF7EA, 0x13FB0008, 0xF1F9F00E, +0x0501F5F0, 0x03F60BF8, 0x090BFE05, 0xEBF8FAF3, 0xEA12F90A, 0xF4FCF4F0, 0x0DF81312, 0x01130DF8, +0xF3060CF2, 0x00F10CF4, 0xE8F611F0, 0xF707FEF6, 0xF81013FC, 0xF0040AFD, 0xF60616FC, 0xFE1109ED, +0xED140DED, 0x0303F812, 0xFDF4F4F8, 0x0CF60B14, 0x0DF11811, 0x0BF4FBFA, 0xF2F906F9, 0x09F3F806, +0x030608FA, 0x0A14E20D, 0x0A08F5FA, 0xE7060DFB, 0x02FD050B, 0xF4F6FB07, 0x01F90BF7, 0x0CFA0FF3, +0x0B04FD01, 0x0F090604, 0x060E0F0A, 0xF6F1FF06, 0xFC0C0611, 0x01030C0D, 0xF612F9F6, 0x120FF002, +0xF0F0F9F0, 0x10FE0DFC, 0xEAFCF6E7, 0xF4F0FFFC, 0xEA080D01, 0x09F6020A, 0xF1EDF2F7, 0xF80609F8, +0xF8F7F80F, 0xF8F7FEFB, 0x0AEE03F4, 0xF60F0406, 0x1309EF03, 0x1215F7FC, 0x0EED07ED, 0x08F30DF5, +0x09E90D02, 0xF1FAFDF4, 0xFD0FFEF4, 0x0317F1F2, 0xF3111203, 0xF208FEFC, 0xF5FB0213, 0x15F20702, +0x0FF918ED, 0xF3F8FF0B, 0x0F0A0A0B, 0xEE0C0A13, 0x0A0AF506, 0x1A0401F6, 0xF0F6080F, 0xEC091201, +0xF9F90C02, 0xF10CF003, 0xF217F200, 0x0DF8FA11, 0x04F603F6, 0x03FB10FA, 0x0AF4090D, 0xF1FBF3EF, +0x0DF00505, 0xFA0B0E0E, 0xFD030811, 0xFEEDF80A, 0xF1F1F40B, 0x050D0514, 0x0DFC0A10, 0xFF0D01EB, +0x07F7010D, 0xF90D00F6, 0xFCEDF108, 0xFD10F30C, 0xF3F7FB06, 0xF009F8FF, 0xF808F8F5, 0xEF12F009, +0x0C0E14F8, 0x02010E06, 0xFF00F50D, 0xF9F1F309, 0x0507EEF0, 0xF8EFFDFB, 0x05041303, 0xFC13EEF6, +0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +output0 = +0x8EC35F65, 0xF1011E4E, 0x01283C76, 0x46C59B44, 0x66BD1E7E, 0x71CC3D13, 0xF54F7B59, 0xC2E51E78, +0x878ACD1F, 0x0BB83AD9, 0xD6EB81F6, 0xDA98D960, 0x9583FF24, 0x84E13C2E, 0xB80A4BD9, 0x7546DA7D, +0x61301F84, 0x4E8E7BCA, 0x0F9A1992, 0x84DE01C3, 0xFB1B38F1, 0x44764A25, 0x9525C193, 0xAD6AFC2C, +0xEAC9CBE7, 0x822626C3, 0x6764F1E2, 0xB7080FC1, 0x92F0BF18, 0x2BE2A423, 0x6652CA22, 0x7E2B8B7D, +0xDADC0042, 0x1684A5B0, 0x6AF80D1E, 0xDE4B11F8, 0x4C027AA7, 0x9B499047, 0xDF71DF9C, 0xE66B5211, +0x0976A858, 0x97CCDFA6, 0xF921AC4D, 0x684DB77D, 0x2046F400, 0x66BF05FF, 0xCFE771B2, 0x7D285899, +0xA6DD74A8, 0xD5AC14DF, 0xB4EE744D, 0x9BF75449, 0xBCCF7BE5, 0xD9B3E1C5, 0x04D5FEEA, 0xA91CED17, +0x260A3E33, 0xB14FA433, 0xC7FB659B, 0xD847CBDD, 0xD4BAF083, 0x51A5AEB1, 0x39A13C7A, 0xC54DBA51, +0x81DD7FFE, 0xE2A3941C, 0x386750AD, 0x85C6A1CF, 0x52E46581, 0x2DC58468, 0x4F8C204C, 0xCA6C89B8, +0xD338F49E, 0xB71D9A1C, 0xAE5992A5, 0x461FFEB6, 0x0F724968, 0xD2D9A290, 0x4C0791D6, 0x8AA45E2A, +0xBCE9EEF4, 0x769D6618, 0x71D659F8, 0xE9DC6A13, 0x99E831C3, 0x8AB8CFD6, 0x489E23C5, 0xBEFC2792, +0x9E54E534, 0x54101DEF, 0x1F83D8D2, 0x69A8094D, 0x2DA8AAEB, 0x564C6C07, 0x4F2AADB5, 0x20CB1D7F, +0x2D6E9D54, 0xB97A8BC9, 0x36365C67, 0x8D84329F, 0x4000A81C, 0x6326766B, 0xB9B50B8D, 0xF9D51D73, +0x4D1A117F, 0x70486DEE, 0xBB19FFB6, 0x96929F46, 0x8E7C8D1C, 0x04B8D1F3, 0x204B8156, 0xA67E9C62, +0x4534F672, 0x94B8C832, 0x38E7CFE4, 0x71F48255, 0x82181625, 0xF8C9EB50, 0xF3D38EF0, 0xB4DE79FB, +0xF32452 + +harq_output0 = +0x0FFA0103, 0x130C0B02, 0xF309F6E7, 0xF70F07F1, 0xF7090FF8, 0x050409F2, 0xF80AFAF7, 0x00F60EF5, +0x06FC060D, 0x080DFB03, 0xF4EDF9F9, 0xFCF9FEEA, 0x0F0C12F8, 0xF9F31708, 0xF60C02FF, 0xFF110310, +0x0BF80F0F, 0x02F6F2EE, 0xEDF20A06, 0x0709FEF2, 0x14F5F0F0, 0xF70C0018, 0x12020FEF, 0x0602EF08, +0xF40A0200, 0xEE0C0BFC, 0x0606ED01, 0xF2F709F3, 0x15110E10, 0x06EC06F8, 0xFBF10CF8, 0x0314FEF6, +0xF5F4FC0C, 0xF00C00FF, 0xF6FDF9F6, 0x07F30801, 0x0F04F40C, 0x0406F305, 0xFAF9F808, 0xF20DF109, +0x010A0AF8, 0x070AFC03, 0xF108120A, 0xF8F9F1EC, 0xEEEB09FF, 0x140C0D01, 0x04E5EF10, 0xF616130C, +0x0314F4EC, 0x09FA09F2, 0xFAFAF714, 0xFAF101FD, 0x06030FF4, 0x17F3EFFA, 0x09FEF109, 0xFDFEF9FB, +0xF2080B02, 0x0CF90B07, 0xEB0F0D06, 0xF71009FE, 0xEF110AF8, 0x0AF70BF9, 0x170A1508, 0xF8FDFAF1, +0x0204F3EB, 0xEFFE0315, 0x0C06000B, 0xF10C0A0E, 0xEC0EF9FC, 0x08F0F2F3, 0x09FD02F7, 0x0B11F610, +0xF8F1F8F7, 0xF8FB0A09, 0xFB030A13, 0x040804F0, 0xE8080813, 0xF1F4FFF3, 0xEBFCEDF7, 0xF7F00AE8, +0x00F1160E, 0xF007F301, 0x0E13F211, 0x07F815F4, 0xF9EEF70B, 0x0EF7FE15, 0x0706E80C, 0x0611F60E, +0xFB0B0CF5, 0xF4F50E11, 0x14FDF1EB, 0xF403120A, 0x09F80303, 0xFB0AF80B, 0xFA1408F5, 0xF503F717, +0x0FFB1610, 0x1107F3FC, 0xF1F4F7F7, 0x060EF4E8, 0x04F8F5FF, 0x04F30CFA, 0x10F008F8, 0xF514EEF3, +0x0EEDE8FE, 0xE7FEE70B, 0x0404FEF9, 0xF8F509F9, 0x0A0EF6F2, 0xF8080EF8, 0x01F200F3, 0x03FC19F2, +0x0D0FF2F8, 0xF9FD0C13, 0x11FE0703, 0x0BF9F110, 0x0EF3FEFD, 0x0EF8F10C, 0x0A070FEA, 0x04FA0310, +0x0CFE0003, 0x0CF3060D, 0xFBFCF5FA, 0xEC0D1108, 0x09ECF70A, 0x0C0EFB08, 0x0BF4F80A, 0xEFF0FB0C, +0x0B09F8FA, 0xFA16FF13, 0x0B081512, 0xF4F2FBF7, 0x000C0A07, 0x130C0FEE, 0xFEF908FB, 0xF6F5F912, +0xF1100409, 0x090E1606, 0xF4F50BF3, 0xEE00F7F9, 0xFAFBF5F6, 0x07080B0A, 0xF1150BE7, 0x0DF80912, +0x12EF0809, 0xEBFF1108, 0x0BF60DFE, 0x130DF608, 0x12EFF2F1, 0x04FB0C0B, 0x01FDFC09, 0xFAF808F9, +0x12020B01, 0xFCED060F, 0x040DFFFF, 0x04F80AF3, 0xF700F60B, 0x08F40E08, 0x06F7F80F, 0x0DFDEF04, +0xFDEFF916, 0xF21107EF, 0x0A1110F1, 0x03F70DF3, 0x08F50300, 0xF1F711F9, 0xF6FCFF0C, 0x0CFFF704, +0x080CFE09, 0x0FF80D06, 0x05080C08, 0xFE020210, 0xFB11F6E9, 0x060BF2F1, 0xED0BEAF9, 0x02F30C02, +0xF8F40DFB, 0x020D0D01, 0x0CF406F1, 0xF302F812, 0x080C0EF2, 0x06010006, 0xF0FA0908, 0x08F9F905, +0xFB0A0508, 0x0FF0F7F4, 0xFF081210, 0xEE18F6F1, 0xF9F9E8F2, 0x060B09FD, 0x0AFEEE04, 0x09F304F8, +0xEA05F6F8, 0x1C0108F5, 0xF205120F, 0xF40D0A04, 0x0001F30D, 0x00FF0DFA, 0x020BF7F7, 0x02F2F7F0, +0x04F90BF1, 0x01EFEE07, 0xEBE4F807, 0x0AF90FEF, 0x0F040B11, 0x0BF91000, 0x000CF812, 0x0311F3F0, +0xF8070218, 0xEDFFF614, 0xF00C15F1, 0x000D0F16, 0xFA0EF707, 0xEE080901, 0xFF0C09F5, 0xEEF704F1, +0xF10C10F9, 0x060BEBF7, 0xFA0EFDF6, 0xF7F403F2, 0xF5F0F306, 0xEC081A0F, 0x020AEEF5, 0xFBF9F7FB, +0xF60C010A, 0xEC0E0FFF, 0xF014FB10, 0x0EFD0308, 0x04F30015, 0xF4FC0CEE, 0x0CFEF3F7, 0x12F0F702, +0xE803FB07, 0x040D06F5, 0x05FA07F1, 0x140A0BF8, 0xEFEDFF11, 0x01EFEE13, 0x0D0C0B0F, 0xE70105F0, +0x01F70CF4, 0x0603EE12, 0xED08EDF9, 0xF2FCFA02, 0x0E0CFCF3, 0x0E04F8F9, 0xF30D17F9, 0xFEEDFB05, +0x071BF114, 0xF309F7F4, 0x02F503F6, 0x0815F400, 0x0CF0090A, 0xE80D0F02, 0xF9FCFDF8, 0xF00FFEF5, +0xF3F5F70B, 0xFC10F7EF, 0xF2FB0AFE, 0xEEECEC15, 0x0202F60E, 0xF310FEF9, 0x10F8F209, 0xFB0606EE, +0x0D0B0C10, 0x1110080C, 0xFCF2F8F6, 0x030DEE07, 0x0C11F511, 0x0CF6EF08, 0x0900070C, 0x0C160E0F, +0xEEF8FFF9, 0xF7F0EEF5, 0x0A090903, 0xF70A000E, 0xF5FF07F6, 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0xE10E12F6, 0x13F1F4FA, 0xF3FC0B0B, 0xEFFEF4FD, 0xF9080708, 0x05FCF9F6, 0x040E06F4, +0x020DF5F6, 0x13F50B11, 0x1513F1F6, 0x05F707ED, 0xF7FB01F7, 0xF1EF06FA, 0x09FB1102, 0x06FC0706, +0xF7F80F14, 0x0EF3F002, 0x0AF8FE0A, 0x0BE8F5F9, 0xEEF609E9, 0x09E8EE02, 0x03090BFC, 0xF0F8F0F1, +0xF8081009, 0x0F0002FA, 0xFCF202FD, 0x0DF106EF, 0xF70408F5, 0x02140C15, 0xF6F6F5EF, 0xF1080905, +0xE902FDEC, 0xF3F4F6F6, 0xF904FCF2, 0xF906F5F3, 0xF7FB0A08, 0x08F4F0F1, 0x0EFDF6F1, 0x03F8F6F6, +0xFF0C110C, 0xF1FDF7F8, 0xF814F502, 0x12FD1108, 0x0DF7F313, 0xF506FA11, 0x07FEF9F2, 0xEAF20D09, +0xFCF40D0D, 0x06F1F709, 0xF7F21DFA, 0xFB00ED11, 0x0DFA0208, 0xF1FE1101, 0x0AF5F4F9, 0x060BF3F9, +0x080CFD06, 0xF30EF409, 0x12EB02EF, 0x0BEF0D09, 0x1512F0F0, 0x18010700, 0x05070F05, 0xF306FC08, +0x0001FD0E, 0x10FD0DF8, 0xF708F90A, 0x100D0D05, 0x04011414, 0x0AF90D0C, 0xF402F8EE, 0xFC11FAFF, +0xF500F605, 0xF0EAF8F4, 0x120F0407, 0x1103F9EE, 0xF9F9F5F7, 0x10060EF8, 0x0609F504, 0xF20E080F, +0x0EF3F109, 0xFB05F60E, 0x0E1C05FD, 0xF710FBEB, 0x16F2F90B, 0xF500FEF4, 0x0A13EEF7, 0x0EFF0CF6, +0xFFF903F8, 0xF30A0BF0, 0xF7FCF004, 0x1613F70B, 0xF90506F5, 0xEB09F008, 0x05F30CF3, 0x0310EEF3, +0xFD1002F4, 0x09070114, 0x040B0606, 0xE400F907, 0x13F40B1A, 0x06F4EBE7, 0xF1EE06F9, 0xFAF9130D, +0xF3ED090A, 0x08EF05F8, 0xF814F507, 0xF8131707, 0x1EFCEF0C, 0xF1090708, 0x04F211F0, 0xEFF0090E, +0x09FBF3FD, 0xF3F204F4, 0xF000FC1C, 0xFC00F009, 0xF9FD160F, 0x16F7F80D, 0x0DF8060B, 0x03FAF4FB, +0x03FDFF0D, 0xF4F1F40E, 0xF9EBF7F2, 0x0EF6FA06, 0x09F3EDFA, 0xFEF4EFF2, 0x0F0300F4, 0x0DEBFBFC, +0x1FF0010E, 0xF9140E07, 0xF2F6FD07, 0x11E9020B, 0xEE17070B, 0x10FD0003, 0x0904F5F7, 0x0515FCEE, +0x090F07FF, 0x12FC1104, 0x10F9F0F1, 0x0A080700, 0x010A1200, 0x120B01F5, 0xF7F0ED01, 0xFB06040E, +0xF0FEF30B, 0x0A0713FC, 0xF6F7F9EC, 0x07F803ED, 0xF2F9EF0F, 0xFAF4100A, 0x020AFA04, 0x0806130D, +0xFF0B0F04, 0x080705F8, 0x04F503F3, 0x05EEF9ED, 0xFBFEF30A, 0xF2F9F20B, 0x03FEECEB, 0x08F40302, +0x0617FE0A, 0xFE10050C, 0x0410FAF3, 0xF508EFF9, 0x030908F2, 0x010206FC, 0xFDF7F415, 0xF9080F05, +0xFBF00CEE, 0x0BFD0D0B, 0xF7F9F10A, 0xF80603F9, 0xF202F4F5, 0x0F07FA05, 0x04FA09F8, 0x08F80B04, +0xED030E00, 0x0A04FDF8, 0xEFFC0B14, 0x05F2FFFE, 0xECF60EFB, 0xFE04FD07, 0x0AEDFB0D, 0xF20FF407, +0xF4030A00, 0x15F1EEF2, 0xF50B0D0B, 0x02FE11FB, 0xF3FBF8F8, 0xF7F0F516, 0xF6070A04, 0xFD0C1A0D, +0xF603F50B, 0x0D0F04FA, 0xF5F5EFF7, 0xFB130FE9, 0x0C0205F3, 0xFB050CF7, 0xF9F809FF, 0xF1120DF0, +0x0E0503F8, 0x16FEFDF6, 0xFA0AF5F7, 0xF302F6F9, 0xFC07F4EE, 0x0A040A00, 0xFFF409EE, 0xF8F7FD18, +0xFC01F7EA, 0x0F11F40F, 0x0DF7F708, 0x0DF60809, 0x0DFD0F08, 0x1012FA0E, 0x021615F4, 0x04FCEBFB, +0xF7FC09FE, 0x0C080DF9, 0xF8EB05FC, 0x0708F2EE, 0xFC14F80C, 0x0C06F111, 0x0809F9F2, 0x0CF809FF, +0x0DF50AF8, 0x05EA0E12, 0xFCF6F805, 0xF5EC0A0B, 0xF2080D10, 0x09FBED04, 0xEFF7F40E, 0xF8F610F6, +0x09F4F1F9, 0xFFFC0E0B, 0x020AF3EC, 0xF4EA09FE, 0xF7EFF70D, 0xEFF410FC, 0x07FD0EFD, 0x0D060100, +0x13F4FAF3, 0xFFF001FE, 0x08FC07F0, 0x0900FC05, 0xF5F8F709, 0x0CFC100C, 0xF7F7FBFC, 0xF7F608F4, +0x05F90308, 0xECF6FF08, 0xF2F70B07, 0x04FE03F5, 0xFC02FBFE, 0x02F41301, 0xF1F6F50E, 0xF9FA00E4, +0x0EFB0709, 0xF50800F7, 0x040AEC07, 0x130301FA, 0x0409F809, 0xF104EA0F, 0xF7F00A09, 0xF80BF704, +0x13F800FE, 0xFAF50CF3, 0xF103090A, 0x12FAF30A, 0xF611F8F9, 0x02F1F403, 0x0A040FED, 0x0AFFFEF2, +0x05FBF7FD, 0x0FE903F3, 0xF6EA090B, 0x120FFE07, 0xFA1406F2, 0x0EF80EFB, 0x0EFDFAFC, 0x0EFC0D0A, +0x120805EF, 0xF70DF900, 0x0C0EE5FB, 0x0F0DF503, 0xF609000A, 0x0D03F5F9, 0x0FFB1006, 0x05F60A08, +0xED07F8EF, 0xF90CEE0A, 0x0B16100A, 0xFD07F607, 0x0EFF0D01, 0x0CEF04EB, 0x11F5FD0B, 0x080B0CF5, +0xFF14FEF5, 0xF1FAF413, 0xFA0100F6, 0xF0090FFC, 0xF3FB0AEF, 0xFE09FE0E, 0xF710F3F5, 0x04090C11, +0x04EEEFF2, 0x09FC0FF1, 0xFE0BF4F9, 0x08F10AFC, 0x030AF5FE, 0x13FA0FF4, 0x07000AFE, 0x071507F5, +0x06FD08F0, 0x0F0C08EE, 0x190E020D, 0x08EDF4EB, 0x0D0DF109, 0x0210EF00, 0xF506080A, 0x1010F7F0, +0xFE02F7FB, 0x09F8F6F7, 0xF902FF04, 0x16E003FE, 0x12EA1A00, 0x130E0FFF, 0x0702F2F9, 0xF10BEFFC, +0x010E04F1, 0xF6EF15F6, 0xF50A0510, 0x050DEF0D, 0xF908F4F6, 0x0F0F0BF0, 0x04F7F6FC, 0x07F9FAEE, +0x02EE07F9, 0xF6F90105, 0xF1FFFC04, 0x0802EB0C, 0xF10E0CF3, 0x030E0508, 0x0CF60CF9, 0x08F20EF5, +0xEFFE09EF, 0xF9FB0A06, 0x14F6F6F5, 0xF6140DFE, 0xF511F8F4, 0xF0FAEF00, 0x1103FC0B, 0xF1090B05, +0xF4FD11F0, 0xF80BF6F1, 0x14160D0B, 0x1105070C, 0x0DEDF80B, 0x1005EE07, 0xFCEFF5E2, 0x0812F3F6, +0xF2100BFD, 0x04FAF00B, 0xFD08F508, 0x06030EEA, 0xF4F90C05, 0xF5EE0608, 0x0CEEF40F, 0xF4F8FB06, +0xFCF01609, 0x0407F402, 0xFDFBFDFD, 0x0BF4F806, 0xFCF701EB, 0x08EB0709, 0xECF9040B, 0xF8E9F300, +0x1C0CEEF5, 0x0703FC08, 0xFEF40909, 0x150B0EFF, 0xF30D0B07, 0xFAF203F9, 0x02F209FA, 0x060EFDF7, +0xFCEB0FF2, 0x0313FF13, 0x030A0B07, 0x0BF70003, 0x00090D02, 0x1405F106, 0x020AFCF6, 0xFAFD01F6, +0xEE05F7EB, 0x030201F4, 0x06071009, 0x0E000704, 0x0A060F07, 0x0C0DFE04, 0xF1FA001A, 0xFFF90B10, +0xF607ED0F, 0x06F9100D, 0x05F6F40C, 0x0E0BF106, 0xF8FB09FF, 0xEBEE13FB, 0x0C0EF4F5, 0xF608EC0A, +0xF9F5F905, 0x0AEE03F5, 0x000B0A03, 0x0815F904, 0x13F7100F, 0xFB0711ED, 0xECF5FD01, 0x0D03F90C, +0xF4FA05EF, 0x1209050A, 0xF60BFD0A, 0xFF04F706, 0xF8ED06F0, 0x0001F71A, 0x09EEFFFA, 0xFF0D0BEA, +0x130F00F4, 0xF1F904FA, 0x05EDF504, 0x030AF7F8, 0x09F712F1, 0xFF0C0E07, 0xFE12F9F6, 0x08FC08F0, +0xF9F813FE, 0x01FF0D0C, 0xF3F10C06, 0xEC05F7F4, 0xFCF6FD04, 0x0B07FEF6, 0xF8FC13E8, 0xF004F611, +0xF6060210, 0x12FDF5ED, 0x0100F9ED, 0xEE03F8FE, 0x11F4F40C, 0x0C0BF614, 0x0D050411, 0x0B080FFA, +0xF2F906F9, 0xF5F3F8F2, 0xEF06080E, 0xF614F60D, 0x0A080A0E, 0xFBF2F9FB, 0x1612F1F7, 0xF4F60FF3, +0x010D0B0B, 0x0C0EFB07, 0x0B04FDED, 0xFAF50604, 0xF2FAFB0A, 0x0AF1FFF2, 0x100C0611, 0x01EF0CF9, +0x0B12F90A, 0x12FBF002, 0x04040D05, 0x10FEF910, 0xEAFC0AE7, 0xF404FFFC, 0xEA08F9ED, 0xF5F616F6, +0xF10106F7, 0xF806F5F8, 0xF8F70CFA, 0x0CF7FEFB, 0x0AEEEF08, 0x0AFBF0F2, 0x13F5EFEF, 0xFD010BFC, +0xFA01F3ED, 0x08F30D09, 0x09FEF902, 0x050FFDF4, 0x11FAFE08, 0x1703F1F2, 0xF3FCFE03, 0x06F4EA10, +0x090FEE13, 0x00F20702, 0xFBF90401, 0x070CEBF7, 0x0FF6F50B, 0xEEF8F6FF, 0x0A0AF506, 0x06F0010A, +0xF0F6F4FB, 0x00F51201, 0x0DF90C02, 0xF1F8F0EF, 0x061706EC, 0x0DF80EFD, 0xF0F6030A, 0x03FB100E, +0xF608F50D, 0xF10F08EF, 0xF9F0F105, 0x0EF7FA0E, 0xFD030811, 0x12ED0CF6, 0x050508F7, 0x05F90514, +0x0D100A10, 0xEAF901FF, 0x070B010D, 0xF90D140A, 0xFC02F1F4, 0xE9FCF3F8, 0x07F70FF2, 0x0409F8FF, +0x0C080CF5, 0x03FEF0F5, 0xF80E000C, 0x0201FAF2, 0x1314090D, 0xF90507F5, 0x05F302F0, 0x0CEFFDFB, +0xF11813EF, 0x10FFEEF6 + + +basegraph= +1 + +z_c= +176 + +n_cb= +11616 + +q_m= +2 + +n_filler= +8 + +e= +4640 + +rv_index= +2 + +code_block_mode= +1 + +iter_max= +20 + +expected_iter_count= +4 + +op_flags= +RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE + +expected_status= +OK diff --git a/app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_2.data b/app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_2.data new file mode 100644 index 0000000..d1f8f45 --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_dec_HARQ_1_2.data @@ -0,0 +1,903 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2019 Intel Corporation +# Origin : FEC5G_UL_1/xxxx + +op_type = +RTE_BBDEV_OP_LDPC_DEC + +input0 = +0xF315FCEF, 0xF50FFAFA, 0xFBF70DEE, 0x1013060C, 0x0B0AFCE7, 0xF0F30BF4, 0x0C070F06, 0x10F7F30F, +0xFE0F0E0D, 0x0FF7FE09, 0x07090606, 0xF705F004, 0x150EF10B, 0x080C010A, 0xF7FA0909, 0x0B00140A, +0xF1F2F8F9, 0x0AF2F910, 0x0D0F0CEF, 0x03F4F20D, 0x0CF90CF9, 0x06F4F501, 0x12FEF3EA, 0xF210F3F9, +0x0312020C, 0x0D0FEF0C, 0x011714F4, 0x110E02F3, 0xF102F613, 0x0A0B090C, 0x1503FA10, 0x0D13F011, +0xED0F0F0F, 0xF8F712F8, 0x10060502, 0x14EEF0F6, 0xEEF50606, 0x0BEDF006, 0xF2120906, 0x0F0700F4, +0xECF00D04, 0xF414F1F5, 0xF1ECF918, 0xF40B090C, 0xFD0FEDEF, 0x0DFDFBED, 0x0703FCF3, 0xEFF2FDED, +0x03021100, 0x0608F00A, 0x0BF7F910, 0xF7EEF20C, 0xF9ED0901, 0xECF2F0F2, 0xEB09F6F3, 0x0F06F5F7, +0xF90E0610, 0x07010611, 0x06F20E0D, 0x0E06EF00, 0x070C050D, 0x0C0F09F1, 0x10FE0CF6, 0x11EF0B14, +0x03FCE40C, 0xF4F506F4, 0xF400F613, 0x0E0509F8, 0xF00DF9F6, 0xF5F612E9, 0x1208FE15, 0x0607F307, +0x1108EE0C, 0xFDFBFB04, 0x02F30D05, 0xFDF0041A, 0x100CF1F4, 0x0DFAFBF9, 0xE9F10B09, 0xEEF214F9, +0x02F6F5F8, 0x0F010CF6, 0xF11008EF, 0x0CF3130A, 0x03FE11F5, 0xF6050708, 0xFC050EEC, 0x0BF8F4F9, +0x04F50FFF, 0x000206EB, 0xEFF9F7ED, 0x0E14F90C, 0x080401FC, 0x0A0401E5, 0xEE13F30C, 0xF10A0916, +0xF0F400EC, 0xFF03F614, 0x0409EBF2, 0x0C0906FA, 0xF70C0400, 0x0FFAFAFA, 0x1201F611, 0xF5FAFAF1, +0xF40FFA09, 0xFFF2F1EF, 0x0BEFF7FA, 0x0703FC07, 0x08F11109, 0xEF09FEEA, 0x07F908FB, 0xF9FD0812, +0xF90B0A02, 0x05F210F4, 0x1AF7F407, 0xEFF8FA0D, 0xF5F9F606, 0x02EB0D0F, 0xF7F5FDFE, 0x130BF5FB, +0x05F6F6F8, 0x1503FFFD, 0xF2F701F9, 0xF1F6F70B, 0x01010B08, 0xF717FBF6, 0x06FAFA05, 0x050CEF11, +0x11F30200, 0x09020F04, 0x07030601, 0x0603FC12, 0xFB0014F7, 0xF7F70CF2, 0xF0F6EEFA, 0x0EF107F8, +0xEA0D0A10, 0x0AEC0C0E, 0xF5060D07, 0xF7F4E804, 0x0902E90B, 0xEE090AFD, 0x02F60210, 0x090BFCFD, +0xF7F8FCF7, 0x030C0905, 0x040AF1F5, 0xF0F80CE7, 0x100AF413, 0xF8FB0817, 0x02EFFA04, 0xFB04EC08, +0x16F4FDFE, 0xE8FD07F4, 0xF2FFEF07, 0x0DF105F4, 0xF4EDF50B, 0xF7EB04FC, 0xF8F601E8, 0xEE0B00F0, +0xF516040E, 0xF600F605, 0x090705EC, 0xF10408F2, 0xE9F2EC11, 0xE90E1613, 0xF601F6F4, 0xF307F4F8, +0x100B060B, 0xF90D0402, 0x09FE0715, 0xF90E06F7, 0xF6FC08F7, 0xF7F30FF2, 0x040A05FA, 0x08F1F411, +0xF6F806F5, 0x0EFBFD0B, 0x0A0EF6FD, 0xEFF4F8F5, 0xFD05F8EB, 0x1300F8FD, 0xF7FE0CF6, 0x05F4E903, +0xF50302EF, 0xF8F514F8, 0x11F8F4F7, 0x120F11F6, 0x07F4FF09, 0x0D0FF700, 0x0EF7FD03, 0x090A06EF, +0xF90206FC, 0xF20FFEFB, 0xF90709FC, 0xFEFDF2F3, 0x0DF70DF7, 0x10F10808, 0x0B08F5FC, 0xF20605F9, +0x1DF5FAFF, 0x0B04F20C, 0xEDF811FA, 0x0F04EC07, 0xEEF4F40D, 0xF9100EF0, 0xFCEEEDF3, 0xF109EA00, +0xE0E8F913, 0x0AFA0AED, 0xF3E7F90B, 0x06FB0BFE, 0x12FEF20D, 0xF4040C04, 0xF409090D, 0xF3F8FAF5, +0x02F60306, 0x12F6FFFA, 0xF9FAF4F8, 0xF70D0408, 0x0400F007, 0x1501FDF2, 0xF305ECF2, 0x18EF01FC, +0x0FF2050C, 0x050DF30F, 0xFCF80813, 0xF3F906FD, 0xFDF3FAEF, 0xECFCEDFE, 0x0D05F810, 0xFC0B11F9, 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0x03FAF400, 0x0A05EE08, 0xF0EBF200, 0xF6090F03, +0x030E03E7, 0x13FEF50B, 0x0B0FFC0E, 0x12F701FA, 0xF3FE01F4, 0x0E04010C, 0xF90DF510, 0xF4FAF302, +0xF90B0203, 0xF516E906, 0xFDFCF400, 0xF1F7FA0F, 0x121108FA, 0xFDF60F04, 0xF1FBF20B, 0x03FC17FD, +0xFE03EE12, 0x070A11F8, 0xFEF4FCF3, 0xF20AF4FF, 0x02F213F0, 0x09F6FBF6, 0x070202F3, 0x1509060B, +0x04EB010B, 0xFB110DFD, 0xEB030BF4, 0x070C0CF8, 0x0A09F7FC, 0xFAF70AEF, 0xF6EBFFFE, 0xEEF70C0A, +0xF5EE06F1, 0x0A14F500, 0x01FAF606, 0x1AEFF0FC, 0x08EB0FEB, 0x0411F617, 0xFE10EDF4, 0xEC0309FA, +0xF8F802FA, 0x0D0D0D0D, 0x0409EFFD, 0xF1FC0C04, 0x06EEECFC, 0x061417EF, 0x0E05FD00, 0xF914F8FC, +0xEFF20AFE, 0xF011F60A, 0x100EFA03, 0x03F5FBF1, 0x0904F808, 0xF608F4F3, 0x08F5EF03, 0xF1060FFE, +0xF115050C, 0x0D09F0F8, 0xFAFF0E06, 0xFA04F7F4, 0xF40D11ED, 0xE90B030C, 0xF805F610, 0x120401F6, +0x08FC0BF4, 0xF110F1FB, 0xF10E1408, 0x1907F9EF, 0x0AEC10F8, 0xF9F7FCF6, 0x010EFF0C, 0xFFF8F90C, +0x01FAF913, 0xF30B0BFB, 0x00FBF610, 0xF90FF809, 0x05ED080D, 0xFC0DEDF4, 0x07F80C0B, 0xFDEEFCF4, +0x0FF2F2F2, 0x07090B10, 0xF8FD1305, 0x04EE0908, 0x0C18F505, 0x0C06080B, 0xF0E6F5F3, 0xEFF812F6, +0x14010CFF, 0xF8080E15, 0xFAFFF2EC, 0x16FD010F, 0x0907F9FB, 0x13F400F1, 0x07FBF509, 0x0DEC05F3, +0x020A04FF, 0x05FA070D, 0x110C0FF2, 0x0C0B0302, 0xFF0403F7, 0x05F018F4, 0x02FB0BF5, 0x10F413F5 + +harq_input0 = +0x0FFA0103, 0x130C0B02, 0xF309F6E7, 0xF70F07F1, 0xF7090FF8, 0x050409F2, 0xF80AFAF7, 0x00F60EF5, +0x06FC060D, 0x080DFB03, 0xF4EDF9F9, 0xFCF9FEEA, 0x0F0C12F8, 0xF9F31708, 0xF60C02FF, 0xFF110310, +0x0BF80F0F, 0x02F6F2EE, 0xEDF20A06, 0x0709FEF2, 0x14F5F0F0, 0xF70C0018, 0x12020FEF, 0x0602EF08, +0xF40A0200, 0xEE0C0BFC, 0x0606ED01, 0xF2F709F3, 0x15110E10, 0x06EC06F8, 0xFBF10CF8, 0x0314FEF6, +0xF5F4FC0C, 0xF00C00FF, 0xF6FDF9F6, 0x07F30801, 0x0F04F40C, 0x0406F305, 0xFAF9F808, 0xF20DF109, +0x010A0AF8, 0x070AFC03, 0xF108120A, 0xF8F9F1EC, 0xEEEB09FF, 0x140C0D01, 0x04E5EF10, 0xF616130C, +0x0314F4EC, 0x09FA09F2, 0xFAFAF714, 0xFAF101FD, 0x06030FF4, 0x17F3EFFA, 0x09FEF109, 0xFDFEF9FB, +0xF2080B02, 0x0CF90B07, 0xEB0F0D06, 0xF71009FE, 0xEF110AF8, 0x0AF70BF9, 0x170A1508, 0xF8FDFAF1, +0x0204F3EB, 0xEFFE0315, 0x0C06000B, 0xF10C0A0E, 0xEC0EF9FC, 0x08F0F2F3, 0x09FD02F7, 0x0B11F610, +0xF8F1F8F7, 0xF8FB0A09, 0xFB030A13, 0x040804F0, 0xE8080813, 0xF1F4FFF3, 0xEBFCEDF7, 0xF7F00AE8, +0x00F1160E, 0xF007F301, 0x0E13F211, 0x07F815F4, 0xF9EEF70B, 0x0EF7FE15, 0x0706E80C, 0x0611F60E, +0xFB0B0CF5, 0xF4F50E11, 0x14FDF1EB, 0xF403120A, 0x09F80303, 0xFB0AF80B, 0xFA1408F5, 0xF503F717, +0x0FFB1610, 0x1107F3FC, 0xF1F4F7F7, 0x060EF4E8, 0x04F8F5FF, 0x04F30CFA, 0x10F008F8, 0xF514EEF3, +0x0EEDE8FE, 0xE7FEE70B, 0x0404FEF9, 0xF8F509F9, 0x0A0EF6F2, 0xF8080EF8, 0x01F200F3, 0x03FC19F2, +0x0D0FF2F8, 0xF9FD0C13, 0x11FE0703, 0x0BF9F110, 0x0EF3FEFD, 0x0EF8F10C, 0x0A070FEA, 0x04FA0310, +0x0CFE0003, 0x0CF3060D, 0xFBFCF5FA, 0xEC0D1108, 0x09ECF70A, 0x0C0EFB08, 0x0BF4F80A, 0xEFF0FB0C, +0x0B09F8FA, 0xFA16FF13, 0x0B081512, 0xF4F2FBF7, 0x000C0A07, 0x130C0FEE, 0xFEF908FB, 0xF6F5F912, +0xF1100409, 0x090E1606, 0xF4F50BF3, 0xEE00F7F9, 0xFAFBF5F6, 0x07080B0A, 0xF1150BE7, 0x0DF80912, +0x12EF0809, 0xEBFF1108, 0x0BF60DFE, 0x130DF608, 0x12EFF2F1, 0x04FB0C0B, 0x01FDFC09, 0xFAF808F9, +0x12020B01, 0xFCED060F, 0x040DFFFF, 0x04F80AF3, 0xF700F60B, 0x08F40E08, 0x06F7F80F, 0x0DFDEF04, +0xFDEFF916, 0xF21107EF, 0x0A1110F1, 0x03F70DF3, 0x08F50300, 0xF1F711F9, 0xF6FCFF0C, 0x0CFFF704, +0x080CFE09, 0x0FF80D06, 0x05080C08, 0xFE020210, 0xFB11F6E9, 0x060BF2F1, 0xED0BEAF9, 0x02F30C02, +0xF8F40DFB, 0x020D0D01, 0x0CF406F1, 0xF302F812, 0x080C0EF2, 0x06010006, 0xF0FA0908, 0x08F9F905, +0xFB0A0508, 0x0FF0F7F4, 0xFF081210, 0xEE18F6F1, 0xF9F9E8F2, 0x060B09FD, 0x0AFEEE04, 0x09F304F8, +0xEA05F6F8, 0x1C0108F5, 0xF205120F, 0xF40D0A04, 0x0001F30D, 0x00FF0DFA, 0x020BF7F7, 0x02F2F7F0, +0x04F90BF1, 0x01EFEE07, 0xEBE4F807, 0x0AF90FEF, 0x0F040B11, 0x0BF91000, 0x000CF812, 0x0311F3F0, +0xF8070218, 0xEDFFF614, 0xF00C15F1, 0x000D0F16, 0xFA0EF707, 0xEE080901, 0xFF0C09F5, 0xEEF704F1, +0xF10C10F9, 0x060BEBF7, 0xFA0EFDF6, 0xF7F403F2, 0xF5F0F306, 0xEC081A0F, 0x020AEEF5, 0xFBF9F7FB, +0xF60C010A, 0xEC0E0FFF, 0xF014FB10, 0x0EFD0308, 0x04F30015, 0xF4FC0CEE, 0x0CFEF3F7, 0x12F0F702, +0xE803FB07, 0x040D06F5, 0x05FA07F1, 0x140A0BF8, 0xEFEDFF11, 0x01EFEE13, 0x0D0C0B0F, 0xE70105F0, +0x01F70CF4, 0x0603EE12, 0xED08EDF9, 0xF2FCFA02, 0x0E0CFCF3, 0x0E04F8F9, 0xF30D17F9, 0xFEEDFB05, +0x071BF114, 0xF309F7F4, 0x02F503F6, 0x0815F400, 0x0CF0090A, 0xE80D0F02, 0xF9FCFDF8, 0xF00FFEF5, +0xF3F5F70B, 0xFC10F7EF, 0xF2FB0AFE, 0xEEECEC15, 0x0202F60E, 0xF310FEF9, 0x10F8F209, 0xFB0606EE, +0x0D0B0C10, 0x1110080C, 0xFCF2F8F6, 0x030DEE07, 0x0C11F511, 0x0CF6EF08, 0x0900070C, 0x0C160E0F, +0xEEF8FFF9, 0xF7F0EEF5, 0x0A090903, 0xF70A000E, 0xF5FF07F6, 0xF5E5FEFD, 0x08F1F80C, 0x00F2EE0D, +0xFAED07EA, 0x07EA170B, 0xFEFFECFF, 0xED0B0211, 0x0AF4F4E6, 0xF2FAF705, 0x0807F706, 0xFBF2F8F7, +0xF31105F7, 0xF10809FB, 0xF1FEF307, 0x0805FFFA, 0x08FC070D, 0x0A071200, 0xEEEDF107, 0xF908EDFB, +0x09F60FF2, 0x0B0C06F8, 0x07FCF608, 0x000FF30C, 0xFF0EF3FD, 0xE40BFCF4, 0x0CF50BF4, 0x04EDE90D, +0xFD05F3F1, 0xFAECF4FA, 0xF80C080F, 0x0A0BF70A, 0x07F012F4, 0x1109FEF3, 0xF507F9F1, 0xF513F7FD, +0xFE0AF80F, 0x041701F1, 0xF5E7F309, 0x0A0AF70C, 0x0E00FEF1, 0x04E505EF, 0xF4EF0BFD, 0x040CF807, +0x1201EF07, 0xF31508F1, 0xF908F309, 0x0B0EE409, 0xF7EBF9F8, 0xF1F7F406, 0xFB0206F6, 0xECFD11F2, +0x0702EEF6, 0xF409FC04, 0xEEF80010, 0xF3EC0BF0, 0x090600F1, 0xF9F5EBF7, 0xEEFE11F8, 0x070BF0FA, +0xFE16EEF8, 0xF108FD05, 0x15FAF3F7, 0xF60E0D0D, 0xF7FC0AF8, 0x01F40805, 0xF70AFE01, 0xFB0F0BF9, +0x04E701F6, 0x09F517F6, 0xFBE8F5F8, 0x11FE00F6, 0xEF08F2F5, 0xFB0CFB0F, 0x0419080B, 0x0308EE11, +0x07110907, 0xF2F5ED0F, 0x0BFAFEF6, 0xFA12F8F9, 0xE8090606, 0x0E0CEAEC, 0x06FD10F8, 0xF80505FD, +0xF1F70912, 0xF5EF0C0B, 0xF9EF0B0B, 0x0D05F5F2, 0x0A08FF0E, 0x09F50300, 0x08F91314, 0x0AFEF60A, +0xE5FC0504, 0xEF0A000E, 0x06FDFFF1, 0x0D11F103, 0x080CF512, 0xF9F501F2, 0xFAF60708, 0xFE140D05, +0xF90202EF, 0xF0FD0EED, 0x06F2E903, 0xE904F80D, 0xF600F8F8, 0xF4FA09F5, 0x0803FA07, 0xFCF9F90B, +0xF202F4F5, 0x000EFBFE, 0x0409FAFD, 0xF0EA0DF4, 0x0B0D00FF, 0x03F8FB0D, 0x0307FAF2, 0x010C0BFB, +0x140C03FD, 0xF4FE0906, 0xF6F6F8ED, 0x0B11090D, 0xF6F90EF8, 0x09F001E8, 0xEC0600F8, 0x1109F90E, +0xEA010BEF, 0xEF0A0C0A, 0x07F510FD, 0x08F3F500, 0x07ED01F5, 0xF313F60A, 0xF803FA0E, 0xF60B0D08, +0xF1F0F709, 0x0DF609F4, 0xFCED020B, 0x0E0EEDE9, 0x08F907F2, 0xF1FC0C13, 0xFFFB0C06, 0xEB070AF7, +0xF606F80A, 0xF90E1EFF, 0xF6EE0BF5, 0x05FF03F7, 0x0F0DF309, 0xFA0CF4F8, 0x1F0CF6F3, 0xF50DEE0F, +0xF5F7FDF4, 0x0BF501EF, 0xF7FA000F, 0xECFAF0F5, 0xEA02FEF1, 0xF80FFCFC, 0x100B0600, 0xFF050501, +0xFA150716, 0x110FFFF4, 0xEE0B04F8, 0x0E0FF112, 0x12F80BF4, 0xF6F41604, 0x07EDE6EF, 0x17EE0F0B, +0x05F5FEF2, 0xEF0BFEF5, 0xFF07FD15, 0x01090709, 0x02EBEE0D, 0xF6F9FB0D, 0xEFF6070E, 0x090806F6, +0x140FFEF1, 0xF6FCEEEB, 0x07EF14F2, 0xFB03040B, 0x0A05F4FC, 0x0DF6FB0D, 0x060B02F8, 0xFF0FFB0E, +0x090709F7, 0xF7180F02, 0x0BF8F005, 0xFE0CF60D, 0x09F4ECF0, 0x0410F30A, 0xEB05F105, 0x05F90C11, +0xFCF1F30B, 0x120B0BF3, 0x031104FC, 0x030BFC0F, 0xFB09EFFC, 0xF50CFB11, 0x0BF80504, 0xF609FCF7, +0xFE0CFB00, 0x0F08F7FB, 0x0BFD0609, 0x0E120F15, 0x020B07F8, 0x0714FAF0, 0x0615F308, 0xF2FDF8F9, +0xEEF606F8, 0x050906E8, 0x071106F7, 0x000C03F8, 0x04F9F90A, 0x060BF5F7, 0x0D0CF2F7, 0x06FB02F7, +0xF7060AF5, 0x0EF1FCF4, 0xFAFAF5FE, 0x0506F917, 0xFCF40C0A, 0x03FC10E8, 0xF30700FD, 0xFCF40906, +0xFB0B0D0B, 0x1017E4F9, 0xF20408F2, 0x02FA03F7, 0xF0000E07, 0xFB0AEDF1, 0xE6F50FEB, 0xF2FCF80B, +0x04F50DFB, 0xF00BF706, 0xF70507FC, 0x0AF01609, 0xFF0DF20F, 0xEA150EF2, 0x080202F3, 0x00FAF9F5, +0xEFF70E04, 0x0FF6F314, 0xF1FEFAEE, 0x08F1F3F2, 0xF6101102, 0xF8F20206, 0x120DFC03, 0x07F8F613, +0x0CF4F50D, 0x0DFF05FB, 0x040EF409, 0xF8FB06F6, 0xF3FAF20D, 0x0DF90402, 0x05080E00, 0xF5EFEBEC, +0xFE0B0EE7, 0x0B0E0F0E, 0x04F812F4, 0x0EEE0D10, 0x021AF7EF, 0xF70F10EC, 0xF604FDFA, 0x10E90F0B, +0xF60CEFFE, 0x0AEBF407, 0xF60A06F0, 0xF50B1607, 0x1111FF0B, 0xF8F8EF08, 0xF704F410, 0x0B0AEBFE, +0x14000205, 0x03FC0EF2, 0xFD17EBFF, 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0xEC05F7F4, 0xFCF6FD04, 0x0B07FEF6, 0xF8FC13E8, 0xF004F611, +0xF6060210, 0x12FDF5ED, 0x0100F9ED, 0xEE03F8FE, 0x11F4F40C, 0x0C0BF614, 0x0D050411, 0x0B080FFA, +0xF2F906F9, 0xF5F3F8F2, 0xEF06080E, 0xF614F60D, 0x0A080A0E, 0xFBF2F9FB, 0x1612F1F7, 0xF4F60FF3, +0x010D0B0B, 0x0C0EFB07, 0x0B04FDED, 0xFAF50604, 0xF2FAFB0A, 0x0AF1FFF2, 0x100C0611, 0x01EF0CF9, +0x0B12F90A, 0x12FBF002, 0x04040D05, 0x10FEF910, 0xEAFC0AE7, 0xF404FFFC, 0xEA08F9ED, 0xF5F616F6, +0xF10106F7, 0xF806F5F8, 0xF8F70CFA, 0x0CF7FEFB, 0x0AEEEF08, 0x0AFBF0F2, 0x13F5EFEF, 0xFD010BFC, +0xFA01F3ED, 0x08F30D09, 0x09FEF902, 0x050FFDF4, 0x11FAFE08, 0x1703F1F2, 0xF3FCFE03, 0x06F4EA10, +0x090FEE13, 0x00F20702, 0xFBF90401, 0x070CEBF7, 0x0FF6F50B, 0xEEF8F6FF, 0x0A0AF506, 0x06F0010A, +0xF0F6F4FB, 0x00F51201, 0x0DF90C02, 0xF1F8F0EF, 0x061706EC, 0x0DF80EFD, 0xF0F6030A, 0x03FB100E, +0xF608F50D, 0xF10F08EF, 0xF9F0F105, 0x0EF7FA0E, 0xFD030811, 0x12ED0CF6, 0x050508F7, 0x05F90514, +0x0D100A10, 0xEAF901FF, 0x070B010D, 0xF90D140A, 0xFC02F1F4, 0xE9FCF3F8, 0x07F70FF2, 0x0409F8FF, +0x0C080CF5, 0x03FEF0F5, 0xF80E000C, 0x0201FAF2, 0x1314090D, 0xF90507F5, 0x05F302F0, 0x0CEFFDFB, +0xF11813EF, 0x10FFEEF6, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + + +output0 = +0x8EC35F65, 0xF1011E4E, 0x01283C76, 0x46C59B44, 0x66BD1E7E, 0x71CC3D13, 0xF54F7B59, 0xC2E51E78, +0x878ACD1F, 0x0BB83AD9, 0xD6EB81F6, 0xDA98D960, 0x9583FF24, 0x84E13C2E, 0xB80A4BD9, 0x7546DA7D, +0x61301F84, 0x4E8E7BCA, 0x0F9A1992, 0x84DE01C3, 0xFB1B38F1, 0x44764A25, 0x9525C193, 0xAD6AFC2C, +0xEAC9CBE7, 0x822626C3, 0x6764F1E2, 0xB7080FC1, 0x92F0BF18, 0x2BE2A423, 0x6652CA22, 0x7E2B8B7D, +0xDADC0042, 0x1684A5B0, 0x6AF80D1E, 0xDE4B11F8, 0x4C027AA7, 0x9B499047, 0xDF71DF9C, 0xE66B5211, +0x0976A858, 0x97CCDFA6, 0xF921AC4D, 0x684DB77D, 0x2046F400, 0x66BF05FF, 0xCFE771B2, 0x7D285899, +0xA6DD74A8, 0xD5AC14DF, 0xB4EE744D, 0x9BF75449, 0xBCCF7BE5, 0xD9B3E1C5, 0x04D5FEEA, 0xA91CED17, +0x260A3E33, 0xB14FA433, 0xC7FB659B, 0xD847CBDD, 0xD4BAF083, 0x51A5AEB1, 0x39A13C7A, 0xC54DBA51, +0x81DD7FFE, 0xE2A3941C, 0x386750AD, 0x85C6A1CF, 0x52E46581, 0x2DC58468, 0x4F8C204C, 0xCA6C89B8, +0xD338F49E, 0xB71D9A1C, 0xAE5992A5, 0x461FFEB6, 0x0F724968, 0xD2D9A290, 0x4C0791D6, 0x8AA45E2A, +0xBCE9EEF4, 0x769D6618, 0x71D659F8, 0xE9DC6A13, 0x99E831C3, 0x8AB8CFD6, 0x489E23C5, 0xBEFC2792, +0x9E54E534, 0x54101DEF, 0x1F83D8D2, 0x69A8094D, 0x2DA8AAEB, 0x564C6C07, 0x4F2AADB5, 0x20CB1D7F, +0x2D6E9D54, 0xB97A8BC9, 0x36365C67, 0x8D84329F, 0x4000A81C, 0x6326766B, 0xB9B50B8D, 0xF9D51D73, +0x4D1A117F, 0x70486DEE, 0xBB19FFB6, 0x96929F46, 0x8E7C8D1C, 0x04B8D1F3, 0x204B8156, 0xA67E9C62, +0x4534F672, 0x94B8C832, 0x38E7CFE4, 0x71F48255, 0x82181625, 0xF8C9EB50, 0xF3D38EF0, 0xB4DE79FB, +0xF32452 + +harq_output0 = +0x14EFEB09, 0x16171D0B, 0xF210F3E8, 0xE4180EE6, 0xE40811F1, 0x0F1118EB, 0xE714EDF1, 0x09EA14EB, +0x1AF71812, 0x121DE902, 0xE7DCF9EB, 0xF7E8EEE1, 0x19111BF4, 0xF2E92615, 0xE81704F7, 0xFE20FE1E, +0x14EB181A, 0x0DFAEDDC, 0xE4EA0E0B, 0x1915F4EB, 0x1DE9DCE0, 0xE71C0722, 0x110714E0, 0x0B0FE719, +0xDC0FF5F7, 0xEC1716EF, 0x0917DC11, 0xE1EE19EE, 0x101A1120, 0x0FE415F5, 0xF2E911E8, 0x0D1D0EED, +0xDFECF70C, 0xEB14F7FA, 0xED0EEBEB, 0x15F11702, 0x110FE718, 0x0B06ED09, 0xECFAEB10, 0xE41EE916, +0x031410F0, 0x0C13EDFF, 0xE4191816, 0xF8F1E0E4, 0xDEE41609, 0x1A17160C, 0x11DDE11B, 0xE8251517, +0x0E1AEAE1, 0x17EB19E6, 0xF4F4EC27, 0xEBE30E00, 0x170B1BEA, 0x1ADBEBE2, 0x1005F11A, 0x0DF2EEED, +0xED1318F9, 0x1CFB0314, 0xDD13150C, 0xE51E0CF5, 0xDF1118EB, 0x19ED0CEA, 0x11132407, 0xEAF9F2E8, +0x060DEBE6, 0xDFF50E1B, 0x170B071C, 0xE7102017, 0xEB1BEBF7, 0x06F1ECE5, 0x111304EA, 0x0B1FEF1A, +0xE7E8F2FB, 0xF305121D, 0xEC011815, 0x0C0D0BE2, 0xDE181915, 0xE9E615F9, 0xE9F4E9E6, 0xEAE814E7, +0x0CE51F1B, 0xE906E310, 0x1221E61A, 0x13DF1BEA, 0xECE8E918, 0x1BF0EE17, 0x0C0EE20C, 0x0F14E10E, +0xF9161ADC, 0xEBEF1D1F, 0x1809EFDF, 0xEE051F1A, 0x1FFE0E06, 0xF219F40B, 0xF01819EF, 0xF100F222, +0x19F31922, 0x1B06E7EF, 0xE7EAE9E7, 0x0F19F6DB, 0x15F5E00A, 0x10EB0FEE, 0x07DF11F4, 0xEC1ED9F1, +0x22EDD6EF, 0xD6FAE111, 0x151BE9E4, 0xFBEF19ED, 0x171BEEEC, 0xF40C17F5, 0x15E1EEEF, 0x17F81EF2, +0x1E19E4F6, 0xEEEE1A16, 0x19F10B0B, 0x11F7E613, 0x17EB1309, 0x12ECF012, 0x15131CD7, 0x08F00820, +0x1CF9FCF7, 0x13E21415, 0xF2F2E1F2, 0xE4191F14, 0x14E7F11D, 0x1B17F618, 0x18E8E517, 0xDDE4F317, +0x1419EAEC, 0xE81EFC18, 0x11132D17, 0xECE8E1EA, 0x08210B06, 0x101B0EDA, 0xF2EA0FF6, 0xE2E8F41B, +0xEB1D0E08, 0x141022F8, 0xE4E90FEA, 0xE2F5F2EE, 0xEFF5E8F2, 0x170E0617, 0xE12016E3, 0x1DEB1521, +0x21ED0617, 0xE2EF180E, 0x13F722EF, 0x1E21ED11, 0x1CE8E3E9, 0x07ED1917, 0x07F20815, 0xECEB1AEC, +0x1FF10E03, 0x0DEF0723, 0x0E16F0F5, 0x11E81FED, 0xEF12E31A, 0x1CE41E0D, 0x11E7E615, 0x1CFDE10D, +0xF1E0E523, 0xE61AF8E8, 0x170C0DDE, 0xF2F414EF, 0x0EE50611, 0xE8E91CF2, 0xE2ECF815, 0x1BF4E2FA, +0x0F12F70F, 0x1DE71314, 0x1111130D, 0x0F0D121C, 0xEF17F9CD, 0x1414E6E7, 0xE21DDAF2, 0x08E61E00, +0xF5EF1EE9, 0xFF110F0E, 0x19EF16E2, 0xE116E11D, 0x171810E7, 0x1214F10E, 0xE6010C19, 0x13EDF513, +0xFB100917, 0x1DE9E6EB, 0x09091A11, 0xDF21E4E4, 0xF8EFD8F2, 0x12110DE8, 0x19F8E508, 0xFEED16EE, +0xE9F6EAF2, 0x23FD13EC, 0xE1031A20, 0xED15110C, 0x0511EC17, 0xEFF927EE, 0x0418ECED, 0x15E7EEED, +0x19F810E7, 0xF2E6E008, 0xE2DFF912, 0x0FE815E9, 0x18131C13, 0x11F51706, 0xF718F326, 0x1118E3DE, +0x0213EC22, 0xE4E7EB21, 0xDE161EDA, 0x09091118, 0xFD17EE03, 0xDE140DF2, 0xF71419E9, 0xE9E306EB, +0xD91326F6, 0x1310DDE6, 0xF112F1EB, 0xE5F4FBF3, 0xEBE6E80A, 0xDD102314, 0xEB20D7E1, 0xEEEDEDF1, +0xEF101110, 0xE5141806, 0xE723F118, 0x16F1070D, 0x12F0F61B, 0xE3F416E4, 0x1FF6F0EF, 0x17D9EE0E, +0xE017F009, 0x161E17E9, 0x12F10EF0, 0x1D1019F5, 0xE1EBF817, 0xFFE1E71C, 0x1D14181C, 0xD90610E5, +0x0CE929EE, 0x15EFDB23, 0xE616DBED, 0xE3E6F6EF, 0x1816DCEC, 0x140FEBF2, 0xE71929EB, 0xF1E7EF0E, +0x191AF317, 0xEA0DF0E8, 0x17F207E6, 0x2016E7EC, 0x11E3180F, 0xDB130B0A, 0xE5E9FAF2, 0xEC200BED, +0xEAE9F015, 0xF81DF0E0, 0xE2E81EFE, 0xE4E5E521, 0x0A18EE10, 0xEF21F8F8, 0x19F8E80E, 0x000412E2, +0x1F1A1017, 0x2213150E, 0xF5EBEDED, 0x1313E813, 0x121AEA15, 0x12F0E317, 0x17F30C15, 0x1B1B191D, +0xE800F0F6, 0xEEECE9E0, 0x200F160E, 0xEC0AFE16, 0xEBFE09ED, 0xEFD0F6F3, 0x1BEAE718, 0x07E8E511, +0xF1E90BDA, 0x1DE92216, 0xF7F0DE08, 0xD8140619, 0x0FE7ECD9, 0xE1F6E50C, 0x1917E5FA, 0xEFE5F9F7, +0xE31C0BE9, 0xD50816EE, 0xF007EA21, 0x0E0DFEE1, 0x0DEA0D1A, 0x181425F9, 0xE1DAE611, 0xED0BDEF3, +0x15F518E5, 0x171F1DEB, 0x11E3E514, 0x0518E614, 0x0314F0ED, 0xD30FF1EE, 0x15F012F1, 0x0BDFD916, +0xED05EFF9, 0xF6D8E4EF, 0xF11D1E1E, 0x2016EF17, 0x14E818EB, 0x1417F2DA, 0xE418F8EA, 0xE918EB0B, +0x0B09EF15, 0xFE21FBE3, 0xEADAE017, 0x1C12E612, 0x1D03FEE5, 0x11D000EB, 0xFFDF0CF6, 0x1120F20E, +0x180BEC0E, 0xEF131EE8, 0xE71FE614, 0x1B1FE40C, 0xECEFEEEF, 0xE2F7F008, 0xF0110DF5, 0xEAF922E2, +0x17FBDEE7, 0xEA11EF04, 0xDBEEFE24, 0xF1E30CE5, 0x140AEDF2, 0xF4E7DBF1, 0xDEFC18EF, 0x1112EFF6, +0x0821E7E4, 0xE400EC06, 0x1BF3E2F2, 0xF0161D17, 0xE5F218E8, 0xF5E61B12, 0xE215F9F1, 0xEF1610F1, +0x08DCF0E9, 0x0EE324E3, 0xF6D2E8EE, 0x17F7F2ED, 0xDE1ADEE0, 0xEF14EA11, 0x0A301A15, 0x1518F31D, +0xF721170E, 0xE7FDDC1C, 0x0EEFF2E8, 0xFB28EAF5, 0xE5140E1B, 0x1C14E5DD, 0x15ED1CE6, 0xEF1612F4, +0xE8F00E1C, 0xEDF50F18, 0xEBDD1314, 0x1CF8EFE3, 0x0E16081A, 0x11ED0EF0, 0x09E82114, 0x14EDDF16, +0xD4F81018, 0xE0FCFF21, 0x06F30DD8, 0x0B15EE0A, 0x120DF01F, 0xEBF0F5E5, 0xEEE411F4, 0xFF19100B, +0xEE0D0FE6, 0xDEE71FE8, 0x0DEDE110, 0xE008ED23, 0xECF3EEE8, 0xF1F223EE, 0x121AEFFE, 0xF5F4E919, +0xE70BE3EC, 0xFB21F5E7, 0x100BEBF0, 0xEBDA19EB, 0x1819F5FE, 0xF4F6F411, 0xFD0CE9EA, 0x171E1CF1, +0x22160CF4, 0xE7001314, 0xF2E9ECDB, 0x1515130D, 0xF5ED17E6, 0x15E712EC, 0xE807F7E2, 0x201AED1D, +0xE2F816E3, 0xE8141413, 0x14DE1FF0, 0x18F1EFFA, 0x09EF16E9, 0xE30FE11A, 0xEF13EF20, 0xEE131A15, +0xE9DBE805, 0x14EA0FE2, 0xF8ED0E17, 0x1A14DEE6, 0x10EE14E4, 0xE9081526, 0xF8F01612, 0xDC0518F5, +0xF210F00F, 0xEE0E280A, 0xE8E218F1, 0x0EFA04E7, 0x1219E717, 0xF216F0EE, 0x2814E7EC, 0xF41DE81A, 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+0x06FD08F0, 0x0F0C08EE, 0x190E020D, 0x08EDF4EB, 0x0D0DF109, 0x0210EF00, 0xF506080A, 0x1010F7F0, +0xFE02F7FB, 0x09F8F6F7, 0xF902FF04, 0x16E003FE, 0x12EA1A00, 0x130E0FFF, 0x0702F2F9, 0xF10BEFFC, +0x010E04F1, 0xF6EF15F6, 0xF50A0510, 0x050DEF0D, 0xF908F4F6, 0x0F0F0BF0, 0x04F7F6FC, 0x07F9FAEE, +0x02EE07F9, 0xF6F90105, 0xF1FFFC04, 0x0802EB0C, 0xF10E0CF3, 0x030E0508, 0x0CF60CF9, 0x08F20EF5, +0xEFFE09EF, 0xF9FB0A06, 0x14F6F6F5, 0xF6140DFE, 0xF511F8F4, 0xF0FAEF00, 0x1103FC0B, 0xF1090B05, +0xF4FD11F0, 0xF80BF6F1, 0x14160D0B, 0x1105070C, 0x0DEDF80B, 0x1005EE07, 0xFCEFF5E2, 0x0812F3F6, +0xF2100BFD, 0x04FAF00B, 0xFD08F508, 0x06030EEA, 0xF4F90C05, 0xF5EE0608, 0x0CEEF40F, 0xF4F8FB06, +0xFCF01609, 0x0407F402, 0xFDFBFDFD, 0x0BF4F806, 0xFCF701EB, 0x08EB0709, 0xECF9040B, 0xF8E9F300, +0x1C0CEEF5, 0x0703FC08, 0xFEF40909, 0x150B0EFF, 0xF30D0B07, 0xFAF203F9, 0x11EC1EE9, 0x191AF4E5, +0xEFDF19D9, 0xFA220619, 0xFA131A14, 0x10FB0909, 0x0C131B0D, 0x140FEB0F, 0xF41AEEEF, 0xEE0A10E5, +0xE206F0E4, 0x13FBFFDE, 0x15132215, 0x1CF31EF8, 0x1512111A, 0x1F1E0114, 0xE8F20F29, 0xEDEF1112, +0xE30DE215, 0x0DED2213, 0x19EBE410, 0x1917DD1E, 0xF5E818EE, 0xDDDB16EE, 0x1418F6F5, 0xE414E31A, +0xEBE7E606, 0x10E50CE8, 0x011C1813, 0x0E15EB11, 0x22E81C1C, 0xEA1B0FE3, 0xE1E9F90D, 0x12FBF91F, +0xEAE312E5, 0x19100D1F, 0xF10F0516, 0xEF1EEA0B, 0xF2E612E4, 0xF2FAE823, 0x0AE4F5F2, 0xF2171BD9, +0x1817FEE9, 0xE9F209E6, 0x07D8EA03, 0x1716F0E5, 0x0DDC16ED, 0x09222113, 0x0126EDE2, 0x11F611E2, +0xF3F21FFE, 0xFBF00E1D, 0xE5E01B0F, 0xEF0CE6EE, 0x05E0EE0D, 0x0819F7F1, 0xEAF01EEA, 0xE811ED18, +0xE115FB16, 0x1DF8EAEB, 0x04FDEFE5, 0xE40EEFF7, 0x28EAF514, 0x181CF019, 0x0F09F711, 0x0E1A12FB, +0xE9EB06F0, 0xE6EBEEEC, 0xDB14151E, 0xEA18FC14, 0x13050C19, 0x06EFEF0B, 0x2217E9EE, 0xECDD19E8, +0xFC24151E, 0x1016EA0B, 0x08F8F1EB, 0xEBE9050B, 0xDDF6E815, 0x15E1F5DA, 0x10111C1F, 0x05E113E5, +0x1925EB1B, 0x19F3F1F6, 0x11061810, 0x1EF5F725, 0xDDEE06DE, 0xE51509F6, 0xE513F1E2, 0xE9EB24F3, +0xF1FE0BE2, 0xEC09F3EE, 0xEDEF0FE9, 0x1BEDF6F2, 0x19EEE311, 0x14EAE7F5, 0x22F0F1EB, 0xFAF412F8, +0xEB09EAE4, 0x0EEC1505, 0x0D0AEE01, 0x0916F5EE, 0x21EAF215, 0x2003DFE5, 0xEDE9E616, 0x01F2D11B, +0x0D13EC20, 0xF8E7100F, 0xF1F3FA07, 0x1414E5EF, 0x10E8F512, 0xDDF4FBF1, 0x1719E712, 0xFFEDF91D, +0xECF4E7EA, 0x0BEE1711, 0x1BEC0AEB, 0xEBF0E1E7, 0x101E15D6, 0x11F211F9, 0xE8F41721, 0x0FEE161B, +0xF118EA1B, 0xDD1C19E2, 0xEEDCE80F, 0x1AF1F516, 0x080B141B, 0x15DD1BEE, 0x100E14F1, 0xFFFB0427, +0x18181F22, 0xDEEBFC0A, 0x07170B14, 0xF819230C, 0xFA0FE5EF, 0xDFF1ECF6, 0x0CF313E7, 0x0D17FA05, +0x141117E8, 0x05FEE7EE, 0xF21DF516, 0xF509F1E8, 0x18291408, 0xF21110F3, 0x17E20AE5, 0x0BEEF9EF, +0xE82220ED, 0x23F8E4EA, 0x1203F2F1, 0xF0FB0CF7, 0xED12FC09, 0xFAF808F9, 0xFE16F701, 0xFC01F20F, +0xF00D13FF, 0xF00C0A07, 0x0BEC0AF7, 0x08F4FAF4, 0xF2F70C0F, 0xF912EF04, 0x11EFF902, 0xF2111BEF, +0xF611FCF1, 0x170B0D07, 0x0809EF00, 0x060B110D, 0xF6FCFFF8, 0x0C13F718, 0x080C12F5, 0xFBF8F9F2, +0xF1F40C08, 0xFE02EEFB, 0xFBFD0AFD, 0x060BF205, 0xED0BFEF9, 0x02070C16, 0xF8F4F9FB, 0x020DF801, +0x0CF4F2F1, 0xF3EE0C12, 0x08F80E06, 0xF2ED00F2, 0x04FA09F4, 0x080DF905, 0xFBF6F1F4, 0xFBF00BF4, +0xEBF41210, 0x02180A05, 0x0D0DE806, 0xF2F709FD, 0x0A120204, 0x09F304F8, 0xFE050AF8, 0x1C01080A, +0xF205120F, 0xF40DF604, 0xECEDF3F9, 0x14FF0D0E, 0x020B0B0B, 0xEE06F704, 0xF00DF705, 0x1503EE07, +0xEBE4F8F3, 0x0AF9FB03, 0x0FF0F711, 0x0BF9FC00, 0x000C0C12, 0x031108F0, 0xF8F30204, 0x02FFF600, +0xF0F80105, 0x00F90F16, 0xFA0EF707, 0xEE08F501, 0xFF0C09F5, 0xEEF7F0F1, 0xF1F710F9, 0xF2F7EB0B, +0xFA0E110A, 0xF7F40306, 0x0904F306, 0xEC081AFB, 0x02F6EE09, 0x0FF9F70F, 0xF6F701F6, 0xEC0E0FEB, +0x0414FB10, 0xF9FDEFF4, 0x04070015, 0xF4FC0CEE, 0x0C1208F7, 0xFEF00BEE, 0xE803FB07, 0xEFF9F209, +0x05FA0705, 0x00F6F7F8, 0x03EDFF11, 0x01EFEE13, 0x0DF8F7FB, 0xFB01F1F0, 0xEDF7F808, 0x06030212, +0x0108010D, 0x06FCFA02, 0x0EF8FC07, 0x0EF00CF9, 0x07F9170D, 0x12EDFB05, 0x0707F114, 0xF3090B09, +0xEE09030A, 0x0815F400, 0xF80409F6, 0xFC0DFBEE, 0xF910FDF8, 0xF00FEAF5, 0xF309F7F7, 0x1010F7EF, +0xF2FB0A12, 0x02000001, 0x02020AFA, 0xF310120D, 0xFCF8F209, 0xE7060602, 0x0DF7F810, 0x111008F8, +0x10F2F8F6, 0xEFF9EEF3, 0xF8FDF511, 0x0C0A04F3, 0x091407F8, 0xF8160EFB, 0x02F8FFF9, 0xF704EE09, +0x0AF5F503, 0xF7F6000E, 0xF513F30A, 0xF5E5FE11, 0x08050DF8, 0x0006EEF9, 0xFA02F3EA, 0x07EA030B, +0xFE13ECFF, 0x02F60211, 0xF6F4F4E6, 0xF20E0CF1, 0x0807F706, 0x0FF20C0B, 0xF3FDF00C, 0xF108F50F, +0x05FE07F3, 0x08F1EBFA, 0x08FC070D, 0x0A07FE14, 0x02ED06F3, 0x0D08ED0F, 0x09F60F06, 0xF70CF2F8, +0x1BFC0A08, 0x000F070C, 0x130E0711, 0xF8F710F4, 0x0CF50B08, 0xF0EDFD0D, 0x1105F3F1, 0x0E00080E, +0xF80C080F, 0xF6F7F70A, 0x07041208, 0x11F5FE08, 0xF507F9F1, 0x09FFF7FD, 0xFE0AF80F, 0x041715F1, +0xF5FBF3F5, 0x0AF6F7F8, 0x0E00FE05, 0x04E519EF, 0x0803F711, 0xF00C0CF3, 0xFEEDEF07, 0x071508F1, +0x0DF407F5, 0x0BFAF809, 0xF7EB0D0C, 0xF1F7F406, 0x0FEEF20A, 0x00FDFC06, 0xF302EEF6, 0xF4F51004, +0xEE0D14FB, 0x07EC0B04, 0x090614F1, 0xF909FFF7, 0x02FEFD0C, 0x070B04FA, 0xEA16EEF8, 0xF1081105, +0x01FA07F7, 0xF60E0D0D, 0x0BFCF6F8, 0x01F40805, 0xF70A1201, 0xFBFBF7F9, 0x04E716F6, 0x09F502F6, +0xFBE8090D, 0xFD12000A, 0x03F4F209, 0x100CFB0F, 0x0405F40B, 0x0308EE11, 0x07110907, 0xF20901FB, +0x0BFAFE0A, 0x0EFEF80D, 0xFCF5F2F2, 0xFAF8EAEC, 0xF211FC0C, 0xF8F1F111, 0x05F709FE, 0x0903F80B, +0xF9030B0B, 0xF919F5F2, 0xF608FFFA, 0x09F50300, 0xF4F91314, 0x0A120AF6, 0xE5FCF1F0, 0x041EECFA, +0xF2FDFFF1, 0x0DFD05EF, 0xF40C0912, 0xF9090106, 0x0EF6071D, 0xFE140DF1, 0xF9EE0203, 0x04110EED, +0x06F2E903, 0xFD04F8F9, 0x0A000C0D, 0x08FAF509, 0xF4EF0E1B, 0x10F9F9F7, 0x06EE0809, 0x140E0F12, +0x04F50FFD, 0xF0EA0D08, 0x0B0D00FF, 0x17F80F0D, 0x17070E06, 0x01F8F7FB, 0x14F80312, 0xF4FEF506, +0x0A0AF8ED, 0x0B1109F9, 0x0B0D0EF8, 0x09F0ECE8, 0x00F2140C, 0xFD090D0E, 0xEA16F703, 0x03F6F80A, +0xF30910FD, 0xF4F3F514, 0xF302ECF5, 0xF3FF0A0A, 0x0CEFFAFA, 0xF60B0D08, 0xF104F7F5, 0xF90AF5F4, +0xFC0102F7, 0xFAFA01FE, 0xF40DF3F2, 0x05FC0CFF, 0x13FBF706, 0xEBF30AF7, 0xF6F20CF6, 0xF90E1EEB, +0xF6EE0BF5, 0xF11303F7, 0xFA0D0709, 0xFAF8080C, 0x1FF80A07, 0xF5F9EE0F, 0x09F7FD08, 0x0B0A1503, +0xF7FA000F, 0x01FAF0F5, 0xEAEEFE05, 0xF8FBFC10, 0x100B0600, 0x13050501, 0xFA15F216, 0xFD0F13F4, +0x030B04F8, 0xFA0FF1FD, 0x12F80BF4, 0x0A080204, 0x0701FA03, 0x17EEFAF7 + +basegraph= +1 + +z_c= +176 + +n_cb= +11616 + +q_m= +2 + +n_filler= +8 + +e= +4640 + +rv_index= +3 + +code_block_mode= +1 + +iter_max= +20 + +expected_iter_count= +3 + +op_flags= +RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE + +expected_status= +OK diff --git a/app/test-bbdev/test_vectors/ldpc_dec_v11835.data b/app/test-bbdev/test_vectors/ldpc_dec_v11835.data new file mode 100644 index 0000000..12c05d0 --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_dec_v11835.data @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2019 Intel Corporation +# Origin : FEC5G_UL_1/xxxx + +op_type = +RTE_BBDEV_OP_LDPC_DEC + +input0 = +0x817F7F81, 0x817F817F, 0x7F818181, 0x7F818181, 0x7F817F81, 0x7F7F8181, 0x817F7F7F, 0x81817F81, +0x7F7F6B7F, 0x7F7F817F, 0x7F7F8181, 0x817F8181, 0x81817F7F, 0x7F818192, 0x7F81817F, 0x817F7F7F, +0x8181 + +output0 = +0x44FB08C0, 0x661CCC + +basegraph= +2 + +z_c= +10 + +n_cb= +500 + +q_m= +6 + +n_filler= +44 + +e= +66 + +rv_index= +0 + +code_block_mode= +1 + +iter_max= +20 + +expected_iter_count= +4 + +op_flags= +RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE + +expected_status= +OK diff --git a/app/test-bbdev/test_vectors/ldpc_dec_v2342.data b/app/test-bbdev/test_vectors/ldpc_dec_v2342.data new file mode 100644 index 0000000..3143fa0 --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_dec_v2342.data @@ -0,0 +1,746 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation +# Origin : FEC5G_UL_1/2342 + +op_type = +RTE_BBDEV_OP_LDPC_DEC + +input0 = +0x7F817F81, 0x817F7F81, 0x8181817F, 0x7F817F81, 0x7F818181, 0x7F81817F, 0x7F817F81, 0x817F8181, +0x817F8181, 0x817F8181, 0x7F818181, 0x81817F81, 0x81817F81, 0x7F7F817F, 0x817F7F7F, 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0x817F8181, 0x7F7F7F81, 0x7F817F81, 0x7F817F7F, 0x7F7F817F, 0x7F7F8181, 0x7F818181, +0x8181817F, 0x7F7F817F, 0x7F81817F, 0x8181817F, 0x7F818181, 0x8181817F, 0x7F7F817F, 0x81817F7F, +0x7F7F817F, 0x7F817F81, 0x817F8181, 0x817F7F7F, 0x817F817F, 0x7F818181, 0x7F817F81, 0x7F7F7F81, +0x7F81817F, 0x817F7F81, 0x7F818181, 0x81817F81, 0x81817F81, 0x817F8181, 0x7F7F8181, 0x81818181, +0x81818181, 0x7F81817F, 0x817F7F81, 0x7F817F81, 0x817F817F, 0x817F817F, 0x817F8181, 0x81818181, +0x817F8181, 0x817F7F7F, 0x81817F7F, 0x81817F7F, 0x81817F81, 0x81818181, 0x7F7F8181, 0x81817F7F, +0x7F7F7F81, 0x7F81817F, 0x81817F81, 0x7F7F817F, 0x81817F7F, 0x81817F81, 0x81818181, 0x7F7F7F7F, +0x81817F81, 0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F817F, 0x8181817F, 0x817F8181, 0x817F7F7F, 0x7F7F7F7F, +0x81817F7F, 0x7F817F7F, 0x817F7F81, 0x7F7F817F, 0x817F7F81, 0x7F818181, 0x817F7F81, 0x81817F81, +0x7F7F8181, 0x7F7F817F, 0x81817F7F, 0x7F818181, 0x7F7F7F81, 0x8181817F, 0x7F818181, 0x7F7F817F, +0x7F7F7F81, 0x817F7F81, 0x7F817F7F, 0x7F818181, 0x8181817F, 0x7F7F8181, 0x81818181, 0x817F8181, +0x7F817F7F, 0x7F81817F, 0x81818181, 0x817F8181, 0x7F81817F, 0x817F7F81, 0x81818181, 0x7F817F81, +0x7F817F7F, 0x817F817F, 0x7F7F7F81, 0x7F7F7F81, 0x7F7F817F, 0x81818181, 0x817F8181, 0x7F7F7F7F, +0x817F7F7F, 0x81818181, 0x81818181, 0x81818181, 0x7F7F8181, 0x7F7F817F, 0x81817F81, 0x817F7F81, +0x7F81817F, 0x7F7F8181, 0x7F7F7F81, 0x7F817F7F, 0x81818181, 0x7F7F7F7F, 0x81817F7F, 0x7F7F7F7F, +0x81817F7F, 0x7F7F817F, 0x7F7F7F81, 0x7F817F81, 0x817F817F, 0x7F817F81, 0x7F7F7F81, 0x7F817F7F, +0x817F8181, 0x7F7F8181, 0x7F7F817F, 0x7F817F81, 0x81817F81, 0x81817F81, 0x817F817F, 0x7F818181, +0x81818181, 0x817F817F, 0x817F7F81, 0x81818181, 0x817F7F7F, 0x7F7F8181, 0x7F817F81, 0x8181817F, +0x7F7F7F81, 0x7F817F81, 0x7F7F8181, 0x81818181, 0x7F7F7F7F, 0x7F818181, 0x7F818181, 0x817F7F81, +0x7F7F7F7F, 0x81818181, 0x7F817F7F, 0x8181817F, 0x81818181, 0x81817F7F, 0x81818181, 0x7F818181, +0x81817F81, 0x7F81817F, 0x7F817F7F, 0x7F817F81, 0x7F81817F, 0x817F7F7F, 0x7F817F7F, 0x817F817F, +0x817F7F7F, 0x81818181, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F, 0x7F81817F, 0x81818181, 0x7F7F7F81, +0x7F7F8181, 0x7F818181, 0x817F7F81, 0x7F818181, 0x817F817F, 0x7F817F81, 0x7F81817F, 0x7F817F7F, +0x7F817F7F, 0x81817F7F, 0x81817F81, 0x817F7F7F, 0x81817F81, 0x817F7F81, 0x817F7F7F, 0x7F817F7F, +0x817F817F, 0x7F7F8181, 0x817F8181, 0x817F817F, 0x7F7F7F81, 0x817F7F7F, 0x7F817F81, 0x7F817F7F, +0x7F7F817F, 0x7F817F81, 0x81817F7F, 0x81817F81, 0x7F81817F, 0x81818181, 0x7F817F7F, 0x8181817F, +0x817F8181, 0x7F7F7F81, 0x817F7F81, 0x817F817F, 0x817F8181, 0x7F818181, 0x7F81817F, 0x7F7F8181, +0x7F81817F, 0x7F81817F, 0x81818181, 0x7F7F7F81, 0x7F818181, 0x817F7F81, 0x8181817F, 0x7F818181, +0x7F7F817F, 0x81818181, 0x817F7F81, 0x7F817F81, 0x8181817F, 0x7F81817F, 0x817F8181, 0x7F7F8181, +0x81818181, 0x7F7F817F, 0x7F818181, 0x817F7F7F, 0x817F7F81, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F, +0x817F7F81, 0x7F81817F, 0x817F817F, 0x8181817F, 0x7F7F7F81, 0x7F7F817F, 0x7F818181, 0x7F817F81, +0x817F7F81, 0x7F818181, 0x81818181, 0x817F8181, 0x81817F7F, 0x7F817F81, 0x7F7F7F7F, 0x817F7F7F, +0x7F7F817F, 0x817F8181, 0x817F7F7F, 0x7F817F81, 0x7F7F7F81, 0x7F818181, 0x7F81817F, 0x81818181, +0x7F818181, 0x817F7F7F, 0x817F7F7F, 0x7F7F7F81, 0x817F8181, 0x81818181, 0x81817F81, 0x7F818181, +0x81817F81, 0x817F8181, 0x7F81817F, 0x8181817F, 0x7F7F8181, 0x817F817F, 0x7F817F7F, 0x7F7F8181, +0x817F7F81, 0x817F8181, 0x7F817F81, 0x7F818181, 0x7F7F8181, 0x81817F81, 0x817F817F, 0x7F81817F, +0x7F818181, 0x7F7F7F81, 0x817F7F7F, 0x7F81817F, 0x817F7F7F, 0x8181817F, 0x81818181, 0x7F7F7F81, +0x7F817F81, 0x7F818181, 0x7F7F817F, 0x7F817F81, 0x7F7F7F81, 0x81817F7F, 0x7F7F7F81, 0x7F7F7F81, +0x7F817F81, 0x7F818181, 0x7F817F81, 0x7F7F7F7F, 0x7F81817F, 0x8181817F, 0x817F7F7F, 0x7F7F8181, +0x81817F7F, 0x81817F7F, 0x7F818181, 0x81817F81, 0x81817F81, 0x7F7F817F, 0x817F8181, 0x817F8181, +0x7F818181, 0x7F81817F, 0x8181817F, 0x7F7F817F, 0x81818181, 0x7F7F7F81, 0x81818181, 0x7F7F7F7F, +0x817F817F, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F, 0x7F818181, 0x817F7F81, 0x7F7F817F, 0x817F8181, +0x7F817F81, 0x817F8181, 0x8181817F, 0x81817F7F, 0x7F817F81, 0x7F7F8181, 0x7F7F8181, 0x7F818181, +0x817F8181, 0x7F7F7F81, 0x7F7F7F7F, 0x81818181, 0x7F7F7F81, 0x7F7F7F7F, 0x817F817F, 0x7F7F8181, +0x817F7F7F, 0x7F817F81, 0x81817F81, 0x7F81817F, 0x81817F7F, 0x817F7F7F, 0x7F81817F, 0x7F817F81, +0x7F7F7F7F, 0x817F7F7F, 0x7F817F81, 0x817F817F, 0x81817F81, 0x81817F7F, 0x7F817F81, 0x7F7F7F81, +0x7F7F7F7F, 0x8181817F, 0x817F7F81, 0x7F81817F, 0x7F81817F, 0x81817F7F, 0x8181817F, 0x81817F7F, +0x7F817F81, 0x7F818181, 0x817F817F, 0x81817F81, 0x7F7F8181, 0x817F7F81 + +output0 = +0x02524C20, 0xB9B1FEA2, 0xC1BAB7E5, 0xEF5714CB, 0x7DE6A64D, 0xA05F9DC9, 0x0747D1E3, 0x3B20BC86, +0x6FCBDB0F, 0xF2FB7A23, 0x79D5E062, 0x5BF4E7C3, 0xD4A68A37, 0x07B4A6AD, 0x37E911F9, 0x7FE7B30A, +0xBBC284A2, 0xD38D6136, 0x25FAB76B, 0xBEBBF534, 0x9A88F9DB, 0xE37FD52D, 0x691DD493, 0xED2F738C, +0x89A96EA0, 0xD981246A, 0x17CC820E, 0x07E3B463, 0xC9FC2590, 0x7475A33C, 0xA5151BB4, 0x1F7E759E, +0x9554F964, 0xD0FA01F4, 0xD31774D2, 0xEB73A9F6, 0x8C9FBCB1, 0xF83010FB, 0x1909E09F, 0xC46023EB, +0x02AEDC62, 0xC6352CC7, 0x674BDC6D, 0xE17CD747, 0x4E25B0B3, 0x4BFF6B17, 0x12C9AAA3, 0xC2BC91CD, +0x44BE23A2, 0x8A72A157, 0x6E0DAD1F, 0x6CA69A09, 0xB55B582E, 0x01818B31, 0x5CA5CAB6, 0x1917AB24, +0x38F98BCD, 0x01917487, 0x05906FDD, 0x760AFCBA, 0x19671085, 0x64E3546E, 0xEC10F922, 0x3CF286CA, +0x68E273EA, 0xF1001325, 0x5DCB3B49, 0xE9547370, 0x65D26AE6, 0xF621256C, 0x25D6D99C, 0x7862EBA0, +0x43365DB0, 0x4DBF06C5, 0x92FCAA02, 0xB0FD58FA, 0x910E80A6, 0x93D24A67, 0x6E39B144, 0x3D46D6F6, +0xEDC55081, 0x33CD70C7, 0xC74B6E8E, 0x91AA27B9, 0x55B3542D, 0xEBF8046A, 0xB9ABDB94, 0x97FC38A8, +0xD5837B4D, 0x764B1809, 0xFBE2096A, 0xC23887AC, 0x2A45029B, 0xCBB7DF70, 0x674654E1, 0x0C6A06BD, +0xB3E8853E, 0x03FCC4CE, 0x26806F2E, 0x2CEB35B0, 0x10538B03, 0x94B059B8, 0xA95E7FFA, 0x48AD3D0A, +0xEB9091E1, 0x972E31EF, 0x5EBC6F8F, 0x947FF108, 0xCB3123FA, 0xFEE1D939, 0xF3DC5C49, 0xA92927AE, +0xF49BB8D0, 0xAA59F730, 0x4A66D1CD, 0x030E1ADF, 0x238D5B19, 0x96F861F1, 0x915424E4, 0x9127880C, +0x8E779839, 0x87375FCE, 0x61FB3D79, 0x96B1EE83, 0x47BF6667, 0x19E7D408, 0x7E91137F, 0x0E4AD8E8, +0xDABD2E45, 0x9B60873F, 0xD0294A65, 0x2A38A862, 0x59DD046D, 0x9832BB79, 0xA5870DB6, 0xB3F1CC48, +0x7E9A8132, 0xEEA2E4BC, 0xF23ED87B, 0x550E011F, 0x9620E0C0, 0xE7CF0834, 0xDEE69623, 0x6184D512, +0xD3D55728, 0xFA7711D4, 0x9C77B0F9, 0x8A26462B, 0xB3F5C8D5, 0x1123246D, 0x78F36272, 0x940EE0F9, +0x757BF240, 0x7EE2B6D0, 0xD40FD5A1, 0xAB4205CA, 0x96E6B758, 0xAC5F4294, 0xC9268C66, 0xB48DC535, +0x3CF6ED4C, 0xF187EFED, 0x7A09B08D, 0x8709EFCE, 0x267B2468, 0x0015D770, 0xDF1B90BF, 0xA03DAD85, +0x2633012E, 0xE5437125, 0x58B79AFF, 0xB929C532, 0x6D890DC9, 0x89A59AD2, 0x2BB99316, 0x41B5B0EB, +0x7304B295, 0xB37F6708, 0x2F84A68E, 0x3637D79A, 0xDD36687B, 0x904BF7B6, 0x6A2CF453, 0x733DED54, +0x5DF48BAA, 0xC3FCC99F, 0x8E3BE1DB, 0x61D9CF2D, 0xB7DC202B, 0xA959FF95, 0x860D0F14, 0x4008C478, +0xD9325A51, 0x27A29D4C, 0x308FE6D4, 0x7A1AA889, 0x5BD38393, 0xCBCBFA5D, 0x7C7B + +basegraph= +1 + +z_c= +320 + +n_cb= +21120 + +q_m= +4 + +n_filler= +688 + +e = +21592 + +rv_index = +0 + +code_block_mode = +1 + +iter_max = +20 + +expected_iter_count = +3 + +op_flags = +RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK + +expected_status = +OK diff --git a/app/test-bbdev/test_vectors/ldpc_dec_v2342_drop.data b/app/test-bbdev/test_vectors/ldpc_dec_v2342_drop.data new file mode 100644 index 0000000..2ea2b8d --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_dec_v2342_drop.data @@ -0,0 +1,746 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation +# Origin : FEC5G_UL_1/2342 + +op_type = +RTE_BBDEV_OP_LDPC_DEC + +input0 = +0x7F817F81, 0x817F7F81, 0x8181817F, 0x7F817F81, 0x7F818181, 0x7F81817F, 0x7F817F81, 0x817F8181, +0x817F8181, 0x817F8181, 0x7F818181, 0x81817F81, 0x81817F81, 0x7F7F817F, 0x817F7F7F, 0x7F7F8181, +0x7F7F7F81, 0x7F7F817F, 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0x7F817F7F, 0x7F7F817F, 0x7F7F8181, 0x7F818181, +0x8181817F, 0x7F7F817F, 0x7F81817F, 0x8181817F, 0x7F818181, 0x8181817F, 0x7F7F817F, 0x81817F7F, +0x7F7F817F, 0x7F817F81, 0x817F8181, 0x817F7F7F, 0x817F817F, 0x7F818181, 0x7F817F81, 0x7F7F7F81, +0x7F81817F, 0x817F7F81, 0x7F818181, 0x81817F81, 0x81817F81, 0x817F8181, 0x7F7F8181, 0x81818181, +0x81818181, 0x7F81817F, 0x817F7F81, 0x7F817F81, 0x817F817F, 0x817F817F, 0x817F8181, 0x81818181, +0x817F8181, 0x817F7F7F, 0x81817F7F, 0x81817F7F, 0x81817F81, 0x81818181, 0x7F7F8181, 0x81817F7F, +0x7F7F7F81, 0x7F81817F, 0x81817F81, 0x7F7F817F, 0x81817F7F, 0x81817F81, 0x81818181, 0x7F7F7F7F, +0x81817F81, 0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F817F, 0x8181817F, 0x817F8181, 0x817F7F7F, 0x7F7F7F7F, +0x81817F7F, 0x7F817F7F, 0x817F7F81, 0x7F7F817F, 0x817F7F81, 0x7F818181, 0x817F7F81, 0x81817F81, +0x7F7F8181, 0x7F7F817F, 0x81817F7F, 0x7F818181, 0x7F7F7F81, 0x8181817F, 0x7F818181, 0x7F7F817F, +0x7F7F7F81, 0x817F7F81, 0x7F817F7F, 0x7F818181, 0x8181817F, 0x7F7F8181, 0x81818181, 0x817F8181, +0x7F817F7F, 0x7F81817F, 0x81818181, 0x817F8181, 0x7F81817F, 0x817F7F81, 0x81818181, 0x7F817F81, +0x7F817F7F, 0x817F817F, 0x7F7F7F81, 0x7F7F7F81, 0x7F7F817F, 0x81818181, 0x817F8181, 0x7F7F7F7F, +0x817F7F7F, 0x81818181, 0x81818181, 0x81818181, 0x7F7F8181, 0x7F7F817F, 0x81817F81, 0x817F7F81, +0x7F81817F, 0x7F7F8181, 0x7F7F7F81, 0x7F817F7F, 0x81818181, 0x7F7F7F7F, 0x81817F7F, 0x7F7F7F7F, +0x81817F7F, 0x7F7F817F, 0x7F7F7F81, 0x7F817F81, 0x817F817F, 0x7F817F81, 0x7F7F7F81, 0x7F817F7F, +0x817F8181, 0x7F7F8181, 0x7F7F817F, 0x7F817F81, 0x81817F81, 0x81817F81, 0x817F817F, 0x7F818181, +0x81818181, 0x817F817F, 0x817F7F81, 0x81818181, 0x817F7F7F, 0x7F7F8181, 0x7F817F81, 0x8181817F, +0x7F7F7F81, 0x7F817F81, 0x7F7F8181, 0x81818181, 0x7F7F7F7F, 0x7F818181, 0x7F818181, 0x817F7F81, +0x7F7F7F7F, 0x81818181, 0x7F817F7F, 0x8181817F, 0x81818181, 0x81817F7F, 0x81818181, 0x7F818181, +0x81817F81, 0x7F81817F, 0x7F817F7F, 0x7F817F81, 0x7F81817F, 0x817F7F7F, 0x7F817F7F, 0x817F817F, +0x817F7F7F, 0x81818181, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F, 0x7F81817F, 0x81818181, 0x7F7F7F81, +0x7F7F8181, 0x7F818181, 0x817F7F81, 0x7F818181, 0x817F817F, 0x7F817F81, 0x7F81817F, 0x7F817F7F, +0x7F817F7F, 0x81817F7F, 0x81817F81, 0x817F7F7F, 0x81817F81, 0x817F7F81, 0x817F7F7F, 0x7F817F7F, +0x817F817F, 0x7F7F8181, 0x817F8181, 0x817F817F, 0x7F7F7F81, 0x817F7F7F, 0x7F817F81, 0x7F817F7F, +0x7F7F817F, 0x7F817F81, 0x81817F7F, 0x81817F81, 0x7F81817F, 0x81818181, 0x7F817F7F, 0x8181817F, +0x817F8181, 0x7F7F7F81, 0x817F7F81, 0x817F817F, 0x817F8181, 0x7F818181, 0x7F81817F, 0x7F7F8181, +0x7F81817F, 0x7F81817F, 0x81818181, 0x7F7F7F81, 0x7F818181, 0x817F7F81, 0x8181817F, 0x7F818181, +0x7F7F817F, 0x81818181, 0x817F7F81, 0x7F817F81, 0x8181817F, 0x7F81817F, 0x817F8181, 0x7F7F8181, +0x81818181, 0x7F7F817F, 0x7F818181, 0x817F7F7F, 0x817F7F81, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F, +0x817F7F81, 0x7F81817F, 0x817F817F, 0x8181817F, 0x7F7F7F81, 0x7F7F817F, 0x7F818181, 0x7F817F81, +0x817F7F81, 0x7F818181, 0x81818181, 0x817F8181, 0x81817F7F, 0x7F817F81, 0x7F7F7F7F, 0x817F7F7F, +0x7F7F817F, 0x817F8181, 0x817F7F7F, 0x7F817F81, 0x7F7F7F81, 0x7F818181, 0x7F81817F, 0x81818181, +0x7F818181, 0x817F7F7F, 0x817F7F7F, 0x7F7F7F81, 0x817F8181, 0x81818181, 0x81817F81, 0x7F818181, +0x81817F81, 0x817F8181, 0x7F81817F, 0x8181817F, 0x7F7F8181, 0x817F817F, 0x7F817F7F, 0x7F7F8181, +0x817F7F81, 0x817F8181, 0x7F817F81, 0x7F818181, 0x7F7F8181, 0x81817F81, 0x817F817F, 0x7F81817F, +0x7F818181, 0x7F7F7F81, 0x817F7F7F, 0x7F81817F, 0x817F7F7F, 0x8181817F, 0x81818181, 0x7F7F7F81, +0x7F817F81, 0x7F818181, 0x7F7F817F, 0x7F817F81, 0x7F7F7F81, 0x81817F7F, 0x7F7F7F81, 0x7F7F7F81, +0x7F817F81, 0x7F818181, 0x7F817F81, 0x7F7F7F7F, 0x7F81817F, 0x8181817F, 0x817F7F7F, 0x7F7F8181, +0x81817F7F, 0x81817F7F, 0x7F818181, 0x81817F81, 0x81817F81, 0x7F7F817F, 0x817F8181, 0x817F8181, +0x7F818181, 0x7F81817F, 0x8181817F, 0x7F7F817F, 0x81818181, 0x7F7F7F81, 0x81818181, 0x7F7F7F7F, +0x817F817F, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F, 0x7F818181, 0x817F7F81, 0x7F7F817F, 0x817F8181, +0x7F817F81, 0x817F8181, 0x8181817F, 0x81817F7F, 0x7F817F81, 0x7F7F8181, 0x7F7F8181, 0x7F818181, +0x817F8181, 0x7F7F7F81, 0x7F7F7F7F, 0x81818181, 0x7F7F7F81, 0x7F7F7F7F, 0x817F817F, 0x7F7F8181, +0x817F7F7F, 0x7F817F81, 0x81817F81, 0x7F81817F, 0x81817F7F, 0x817F7F7F, 0x7F81817F, 0x7F817F81, +0x7F7F7F7F, 0x817F7F7F, 0x7F817F81, 0x817F817F, 0x81817F81, 0x81817F7F, 0x7F817F81, 0x7F7F7F81, +0x7F7F7F7F, 0x8181817F, 0x817F7F81, 0x7F81817F, 0x7F81817F, 0x81817F7F, 0x8181817F, 0x81817F7F, +0x7F817F81, 0x7F818181, 0x817F817F, 0x81817F81, 0x7F7F8181, 0x817F7F81 + +output0 = +0x02524C20, 0xB9B1FEA2, 0xC1BAB7E5, 0xEF5714CB, 0x7DE6A64D, 0xA05F9DC9, 0x0747D1E3, 0x3B20BC86, +0x6FCBDB0F, 0xF2FB7A23, 0x79D5E062, 0x5BF4E7C3, 0xD4A68A37, 0x07B4A6AD, 0x37E911F9, 0x7FE7B30A, +0xBBC284A2, 0xD38D6136, 0x25FAB76B, 0xBEBBF534, 0x9A88F9DB, 0xE37FD52D, 0x691DD493, 0xED2F738C, +0x89A96EA0, 0xD981246A, 0x17CC820E, 0x07E3B463, 0xC9FC2590, 0x7475A33C, 0xA5151BB4, 0x1F7E759E, +0x9554F964, 0xD0FA01F4, 0xD31774D2, 0xEB73A9F6, 0x8C9FBCB1, 0xF83010FB, 0x1909E09F, 0xC46023EB, +0x02AEDC62, 0xC6352CC7, 0x674BDC6D, 0xE17CD747, 0x4E25B0B3, 0x4BFF6B17, 0x12C9AAA3, 0xC2BC91CD, +0x44BE23A2, 0x8A72A157, 0x6E0DAD1F, 0x6CA69A09, 0xB55B582E, 0x01818B31, 0x5CA5CAB6, 0x1917AB24, +0x38F98BCD, 0x01917487, 0x05906FDD, 0x760AFCBA, 0x19671085, 0x64E3546E, 0xEC10F922, 0x3CF286CA, +0x68E273EA, 0xF1001325, 0x5DCB3B49, 0xE9547370, 0x65D26AE6, 0xF621256C, 0x25D6D99C, 0x7862EBA0, +0x43365DB0, 0x4DBF06C5, 0x92FCAA02, 0xB0FD58FA, 0x910E80A6, 0x93D24A67, 0x6E39B144, 0x3D46D6F6, +0xEDC55081, 0x33CD70C7, 0xC74B6E8E, 0x91AA27B9, 0x55B3542D, 0xEBF8046A, 0xB9ABDB94, 0x97FC38A8, +0xD5837B4D, 0x764B1809, 0xFBE2096A, 0xC23887AC, 0x2A45029B, 0xCBB7DF70, 0x674654E1, 0x0C6A06BD, +0xB3E8853E, 0x03FCC4CE, 0x26806F2E, 0x2CEB35B0, 0x10538B03, 0x94B059B8, 0xA95E7FFA, 0x48AD3D0A, +0xEB9091E1, 0x972E31EF, 0x5EBC6F8F, 0x947FF108, 0xCB3123FA, 0xFEE1D939, 0xF3DC5C49, 0xA92927AE, +0xF49BB8D0, 0xAA59F730, 0x4A66D1CD, 0x030E1ADF, 0x238D5B19, 0x96F861F1, 0x915424E4, 0x9127880C, +0x8E779839, 0x87375FCE, 0x61FB3D79, 0x96B1EE83, 0x47BF6667, 0x19E7D408, 0x7E91137F, 0x0E4AD8E8, +0xDABD2E45, 0x9B60873F, 0xD0294A65, 0x2A38A862, 0x59DD046D, 0x9832BB79, 0xA5870DB6, 0xB3F1CC48, +0x7E9A8132, 0xEEA2E4BC, 0xF23ED87B, 0x550E011F, 0x9620E0C0, 0xE7CF0834, 0xDEE69623, 0x6184D512, +0xD3D55728, 0xFA7711D4, 0x9C77B0F9, 0x8A26462B, 0xB3F5C8D5, 0x1123246D, 0x78F36272, 0x940EE0F9, +0x757BF240, 0x7EE2B6D0, 0xD40FD5A1, 0xAB4205CA, 0x96E6B758, 0xAC5F4294, 0xC9268C66, 0xB48DC535, +0x3CF6ED4C, 0xF187EFED, 0x7A09B08D, 0x8709EFCE, 0x267B2468, 0x0015D770, 0xDF1B90BF, 0xA03DAD85, +0x2633012E, 0xE5437125, 0x58B79AFF, 0xB929C532, 0x6D890DC9, 0x89A59AD2, 0x2BB99316, 0x41B5B0EB, +0x7304B295, 0xB37F6708, 0x2F84A68E, 0x3637D79A, 0xDD36687B, 0x904BF7B6, 0x6A2CF453, 0x733DED54, +0x5DF48BAA, 0xC3FCC99F, 0x8E3BE1DB, 0x61D9CF2D, 0xB7DC202B, 0xA959FF95, 0x860D0F14, 0x4008C478, +0xD9325A51, 0x27A29D4C, 0x308FE6D4, 0x7A1AA889, 0x5BD38393, 0xCBFA5D + +basegraph= +1 + +z_c= +320 + +n_cb= +21120 + +q_m= +4 + +n_filler= +688 + +e = +21592 + +rv_index = +0 + +code_block_mode = +1 + +iter_max = +20 + +expected_iter_count = +3 + +op_flags = +RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK, RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP + +expected_status = +OK diff --git a/app/test-bbdev/test_vectors/ldpc_dec_v7813.data b/app/test-bbdev/test_vectors/ldpc_dec_v7813.data new file mode 100644 index 0000000..63bc8da --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_dec_v7813.data @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation +# Origin : FEC5G_UL_1/7813 + +op_type = +RTE_BBDEV_OP_LDPC_DEC + +input0 = +0x7F817F81, 0x7F81817F, 0x7F7F7F7F, 0x81818181, 0x7F81817F, 0x817F8181, 0x817F7F7F, 0x7F817F81, +0x817F7F7F, 0x8181817F, 0x8181817F + +output0 = +0x8C4DEB9F, 0x52 + +basegraph= +2 + +z_c= +7 + +n_cb= +350 + +q_m= +2 + +n_filler= +30 + +e = +44 + +rv_index = +0 + +code_block_mode = +1 + +iter_max = +8 + +expected_iter_count = +6 + +op_flags = +RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE + +expected_status = +OK diff --git a/app/test-bbdev/test_vectors/ldpc_dec_v8480.data b/app/test-bbdev/test_vectors/ldpc_dec_v8480.data new file mode 100644 index 0000000..aaa3c98 --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_dec_v8480.data @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation +# Origin : FEC5G_UL_1/8480 + +op_type = +RTE_BBDEV_OP_LDPC_DEC + +input0 = +0x81817F81, 0x817F7F7F, 0x7F817F7F, 0x7F817F7F, 0x8181817F, 0x817F817F, 0x817F817F, 0x7F818181, +0x7F817F7F, 0x81817F81, 0x81817F7F, 0x7F7F7F81, 0x7F817F81, 0x81817F7F, 0x8181817F, 0x81818181, +0x817F8181, 0x7F7F7F81, 0x7F818181, 0x817F7F7F, 0x7F7F7F7F, 0x7F7F7F81, 0x7F817F81, 0x817F7F81, +0x7F7F7F81, 0x817F8181, 0x7F818181, 0x817F817F, 0x7F7F817F, 0x7F817F7F, 0x7F817F7F, 0x7F81817F, +0x7F818181, 0x7F81817F, 0x81817F7F, 0x81817F7F, 0x7F81817F, 0x817F7F81, 0x81817F81, 0x817F817F, +0x7F7F8181, 0x817F7F81, 0x81818181, 0x7F7F7F7F, 0x7F7F7F7F, 0x817F817F, 0x7F81817F, 0x7F7F817F, +0x8181817F, 0x817F8181, 0x7F817F81, 0x817F8181, 0x8181817F, 0x817F8181, 0x7F817F81, 0x8181817F, +0x7F7F8181, 0x7F7F817F, 0x7F81817F, 0x81817F7F, 0x7F7F8181, 0x8181817F, 0x7F818181, 0x81817F81, +0x7F7F817F, 0x7F7F8181, 0x7F817F81, 0x7F81817F, 0x817F7F81, 0x81818181, 0x7F817F81, 0x7F7F7F7F, +0x7F817F7F, 0x81817F7F, 0x817F7F7F, 0x7F818181, 0x7F7F817F, 0x81817F81, 0x8181817F, 0x7F81817F, +0x8181817F, 0x817F8181, 0x7F817F7F, 0x817F817F, 0x81818181, 0x7F81817F, 0x817F817F, 0x81817F81, +0x7F7F8181, 0x817F7F7F, 0x7F818181, 0x7F7F8181, 0x81817F81, 0x7F81817F, 0x7F817F81, 0x81818181, +0x81817F81, 0x817F7F7F, 0x817F7F81, 0x7F7F817F, 0x7F818181, 0x7F817F7F, 0x817F817F, 0x7F7F817F, +0x81817F7F, 0x7F7F817F, 0x817F8181, 0x817F8181, 0x7F81817F, 0x817F817F, 0x817F7F7F, 0x81817F81, +0x81817F7F, 0x8181817F, 0x817F7F81, 0x81817F81, 0x7F7F817F, 0x7F7F8181, 0x7F7F817F, 0x81817F81, +0x81817F7F, 0x817F7F7F, 0x817F7F7F, 0x7F817F81, 0x8181817F, 0x81818181, 0x7F817F7F, 0x7F7F8181, +0x7F7F7F81, 0x7F7F7F81, 0x817F8181, 0x7F817F81, 0x81818181, 0x8181817F, 0x7F81817F, 0x7F818181, +0x7F7F817F, 0x7F7F7F81, 0x817F7F7F, 0x817F817F, 0x7F817F81, 0x817F7F7F, 0x7F81817F, 0x7F7F7F7F, +0x7F818181, 0x7F817F7F, 0x817F7F81, 0x7F81817F, 0x7F7F8181, 0x7F7F8181, 0x8181817F, 0x7F7F817F, +0x7F81817F, 0x7F81817F, 0x817F8181, 0x7F7F7F7F, 0x817F7F81, 0x7F7F8181, 0x817F8181, 0x817F7F7F, +0x7F7F817F, 0x817F8181, 0x81817F81, 0x81818181, 0x7F7F7F7F, 0x7F818181, 0x7F81817F, 0x81817F81, +0x7F7F817F, 0x8181817F, 0x817F817F, 0x7F7F7F7F, 0x7F818181, 0x7F7F817F, 0x7F818181, 0x817F7F81, +0x7F7F7F7F, 0x7F81817F, 0x817F7F7F, 0x81817F81, 0x7F817F81, 0x81818181, 0x7F7F8181, 0x817F817F, +0x7F817F81, 0x81817F81, 0x7F817F7F, 0x7F7F7F81, 0x7F7F7F7F, 0x81817F81, 0x817F7F81, 0x7F7F817F, +0x81818181, 0x7F7F7F7F, 0x817F817F, 0x817F7F81, 0x7F818181, 0x817F8181, 0x817F817F, 0x7F7F817F, +0x7F817F81 + +output0 = +0x76332859, 0x417B1254, 0xEC8A8CFE, 0xE7EFCD06, 0x43C5BDA2, 0x2EACD776, 0x6CD515AC, 0x6D6E04AC, +0xBC2D9F85, 0xD3643553, 0xD0C8DF8E, 0x235B434A, 0xD7AB7643, 0xA4D9C420, 0x372FA858, 0xF813CE10, +0xE0C238F6, 0x07853FD4, 0xE04E40F2, 0x0EE765A9, 0x6EEAFCBC, 0xA7059C68, 0xFBBC + +basegraph= +2 + +z_c= +72 + +n_cb= +3600 + +q_m= +2 + +n_filler= +0 + +e = +804 + +rv_index = +0 + +code_block_mode = +1 + +iter_max = +8 + +expected_iter_count = +3 + +op_flags = +RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE + +expected_status = +OK diff --git a/app/test-bbdev/test_vectors/ldpc_dec_v8568.data b/app/test-bbdev/test_vectors/ldpc_dec_v8568.data new file mode 100644 index 0000000..03422fb --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_dec_v8568.data @@ -0,0 +1,256 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation +# Origin : FEC5G_UL_1/8568 + +op_type = +RTE_BBDEV_OP_LDPC_DEC + +input0 = +0x7F7F7F7F, 0x7F7F7F7F, 0x8181817F, 0x7F7F8181, 0x817F7F7F, 0x7F817F81, 0x7F7F7F81, 0x81818181, +0x7F818181, 0x817F817F, 0x81818181, 0x7F7F7F7F, 0x7F81817F, 0x7F7F8181, 0x7F7F7F81, 0x81817F7F, +0x7F817F7F, 0x817F8181, 0x7F818181, 0x817F817F, 0x8181817F, 0x7F7F8181, 0x8181817F, 0x817F7F7F, +0x7F7F817F, 0x7F7F817F, 0x81818181, 0x81817F81, 0x7F7F7F81, 0x7F81817F, 0x7F818181, 0x7F818181, +0x7F817F7F, 0x817F817F, 0x817F7F7F, 0x7F818181, 0x7F81817F, 0x7F817F7F, 0x7F817F7F, 0x817F7F7F, +0x81817F81, 0x817F817F, 0x817F817F, 0x7F817F81, 0x7F7F817F, 0x7F817F7F, 0x817F817F, 0x7F7F7F81, +0x7F7F817F, 0x817F817F, 0x81818181, 0x7F81817F, 0x7F817F81, 0x7F7F7F7F, 0x7F818181, 0x7F7F8181, +0x7F818181, 0x7F81817F, 0x7F81817F, 0x81817F7F, 0x817F7F81, 0x7F818181, 0x7F817F81, 0x7F818181, +0x81817F81, 0x7F7F8181, 0x7F7F7F81, 0x7F7F817F, 0x8181817F, 0x817F8181, 0x7F817F7F, 0x7F7F7F81, +0x7F7F7F7F, 0x817F7F7F, 0x7F817F81, 0x7F7F817F, 0x817F7F7F, 0x817F7F81, 0x817F7F81, 0x81818181, +0x7F817F81, 0x81817F7F, 0x7F7F817F, 0x7F7F8181, 0x7F7F7F81, 0x7F7F8181, 0x817F8181, 0x7F81817F, +0x817F817F, 0x7F817F81, 0x7F7F8181, 0x7F817F81, 0x7F7F817F, 0x7F817F81, 0x81817F7F, 0x817F817F, +0x81818181, 0x7F7F7F81, 0x8181817F, 0x81818181, 0x7F7F7F81, 0x817F8181, 0x817F8181, 0x7F81817F, +0x7F7F817F, 0x817F817F, 0x7F7F817F, 0x7F81817F, 0x7F817F81, 0x7F7F7F81, 0x81818181, 0x7F817F81, +0x7F817F7F, 0x7F7F7F81, 0x81817F81, 0x7F7F8181, 0x7F7F7F7F, 0x817F8181, 0x7F7F8181, 0x81818181, +0x81818181, 0x7F7F7F7F, 0x817F817F, 0x7F7F7F7F, 0x81817F7F, 0x7F7F8181, 0x7F81817F, 0x817F7F81, +0x81817F7F, 0x7F7F8181, 0x817F8181, 0x7F817F7F, 0x81817F7F, 0x7F7F8181, 0x817F7F81, 0x7F817F81, +0x7F817F7F, 0x7F7F7F7F, 0x8181817F, 0x817F817F, 0x7F818181, 0x817F7F81, 0x817F817F, 0x8181817F, +0x817F7F81, 0x7F7F7F7F, 0x7F817F81, 0x81818181, 0x817F7F81, 0x81817F81, 0x817F7F81, 0x7F817F7F, +0x817F8181, 0x7F7F7F81, 0x7F817F81, 0x8181817F, 0x7F817F7F, 0x81817F81, 0x7F7F7F81, 0x7F818181, +0x7F7F7F81, 0x7F817F81, 0x81818181, 0x81817F81, 0x81818181, 0x7F7F7F7F, 0x817F817F, 0x7F818181, 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0x7F7F817F, 0x817F817F, 0x7F817F81, 0x817F817F, 0x7F7F7F81, 0x7F817F7F, +0x817F817F, 0x817F8181, 0x817F8181, 0x7F7F817F, 0x7F81817F, 0x817F8181, 0x817F817F, 0x81818181, +0x7F818181, 0x7F817F7F, 0x7F7F7F81, 0x81817F81, 0x7F818181, 0x7F7F817F, 0x8181817F, 0x7F817F81, +0x817F7F7F, 0x817F7F81, 0x81817F7F, 0x7F7F817F, 0x7F81817F, 0x817F817F, 0x7F7F817F, 0x7F7F8181, +0x7F7F7F81, 0x7F7F8181, 0x817F8181, 0x817F817F, 0x81817F7F, 0x7F817F7F, 0x81817F7F, 0x7F7F8181, +0x8181817F, 0x817F7F7F, 0x7F7F7F81, 0x7F7F8181, 0x8181817F, 0x7F7F7F81, 0x7F7F817F, 0x7F7F7F81, +0x7F817F81, 0x81817F7F, 0x817F817F, 0x7F7F817F, 0x7F817F81, 0x7F7F7F7F, 0x817F7F81, 0x8181817F, +0x81817F81, 0x7F7F817F, 0x7F7F817F, 0x81817F7F, 0x7F7F8181, 0x7F7F817F, 0x8181817F, 0x81818181, +0x817F7F81, 0x7F818181, 0x81818181, 0x81818181, 0x817F817F, 0x817F8181, 0x7F7F7F81, 0x7F7F7F7F, +0x7F7F8181, 0x7F81817F, 0x817F8181, 0x7F817F7F, 0x7F7F7F7F, 0x8181817F, 0x7F817F81, 0x7F81817F, +0x7F7F8181, 0x7F817F7F, 0x7F7F7F81, 0x7F817F7F, 0x817F8181, 0x7F817F81, 0x7F7F7F7F, 0x7F817F7F, +0x7F7F8181, 0x817F817F, 0x7F81817F, 0x7F7F817F, 0x7F7F817F, 0x7F81817F, 0x7F7F7F81, 0x7F7F7F81 + +output0 = +0xB6D49CE2, 0x3E96B93F, 0xF02009F6, 0x2DF3D30D, 0x3B06C160, 0x646C69CC, 0x54439F0F, 0xCE0D12C3, +0x66E8BFD5, 0xA9D22B0C, 0xA9E7343B, 0x2B6EEF01, 0x6B6966C0, 0xB98FE144, 0xC3BF7BAD, 0x1B40DF1C, +0x973B12DC, 0x46E25E90, 0xB324ACCA, 0x5F0ED2B9, 0xBB4F + +basegraph= +2 + +z_c= +72 + +n_cb= +3600 + +q_m= +2 + +n_filler= +64 + +e = +6624 + +rv_index = +0 + +code_block_mode = +1 + +iter_max = +20 + +expected_iter_count = +6 + +op_flags = +RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE + +expected_status = +OK diff --git a/app/test-bbdev/test_vectors/ldpc_dec_v9503.data b/app/test-bbdev/test_vectors/ldpc_dec_v9503.data new file mode 100644 index 0000000..f6de8db --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_dec_v9503.data @@ -0,0 +1,1216 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation +# Origin : FEC5G_UL_1/9503 + +op_type = +RTE_BBDEV_OP_LDPC_DEC + +input0 = +0x81818181, 0x7F818181, 0x7F81817F, 0x7F817F7F, 0x817F8181, 0x7F7F817F, 0x7F81817F, 0x7F818181, +0x8181817F, 0x7F7F7F7F, 0x7F81817F, 0x7F7F817F, 0x8181817F, 0x7F817F7F, 0x7F817F7F, 0x817F7F81, +0x7F7F8181, 0x817F7F7F, 0x7F7F7F81, 0x8181817F, 0x817F7F81, 0x7F7F8181, 0x7F818181, 0x7F7F817F, +0x817F817F, 0x7F818181, 0x8181817F, 0x7F817F7F, 0x817F7F81, 0x7F7F817F, 0x7F81817F, 0x817F817F, +0x7F818181, 0x817F7F7F, 0x817F7F7F, 0x7F817F81, 0x7F7F8181, 0x7F7F7F81, 0x7F81817F, 0x7F7F817F, +0x7F7F8181, 0x7F817F7F, 0x817F7F81, 0x817F7F7F, 0x7F7F7F7F, 0x7F7F8181, 0x7F817F81, 0x81817F7F, +0x7F817F81, 0x81817F81, 0x7F81817F, 0x817F7F7F, 0x7F7F817F, 0x7F817F7F, 0x817F817F, 0x81817F81, +0x7F817F81, 0x7F7F817F, 0x7F818181, 0x81817F7F, 0x7F7F817F, 0x7F7F817F, 0x8181817F, 0x7F817F81, +0x7F7F8181, 0x7F7F7F81, 0x81817F7F, 0x817F8181, 0x81817F81, 0x817F8181, 0x7F817F81, 0x7F7F8181, +0x81817F7F, 0x7F7F7F7F, 0x81818181, 0x817F817F, 0x817F7F81, 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0x7F817F7F, 0x8181817F, 0x817F817F, 0x7F817F7F, 0x81818181, 0x7F7F817F, 0x7F7F7F7F, +0x7F818181, 0x81818181, 0x7F7F7F81, 0x81817F81, 0x81817F81, 0x7F81817F, 0x817F817F, 0x7F817F81, +0x81817F7F, 0x817F817F, 0x81817F81, 0x8181817F, 0x817F817F, 0x817F817F, 0x817F817F, 0x817F817F, +0x81817F7F, 0x81818181, 0x7F81817F, 0x7F817F7F, 0x817F7F7F, 0x7F7F7F81, 0x817F817F, 0x817F7F81, +0x7F818181, 0x817F7F81, 0x81817F7F, 0x817F817F, 0x81817F7F, 0x8181817F, 0x817F7F81, 0x7F7F7F81, +0x81817F81, 0x7F7F7F81, 0x81818181, 0x817F7F7F, 0x81817F7F, 0x7F817F7F, 0x7F818181, 0x81817F7F, +0x7F817F7F, 0x7F7F7F81, 0x81817F7F, 0x7F7F8181, 0x817F8181, 0x7F7F7F81, 0x7F7F817F, 0x7F7F7F81, +0x7F818181, 0x7F817F7F, 0x7F7F7F81, 0x7F818181, 0x81817F7F, 0x817F7F7F, 0x7F7F7F81, 0x817F7F7F, +0x817F817F, 0x81817F7F, 0x7F817F81, 0x7F817F81, 0x81817F81, 0x7F7F7F81, 0x7F817F81, 0x81817F81, +0x7F7F8181, 0x7F818181, 0x7F7F8181, 0x81817F7F, 0x81818181, 0x7F7F7F7F, 0x7F7F7F7F, 0x817F7F7F, +0x7F81817F, 0x7F817F7F, 0x817F7F7F, 0x7F817F81, 0x7F817F7F, 0x817F7F81, 0x81817F81, 0x7F7F817F, +0x7F817F7F, 0x8181817F, 0x7F7F817F, 0x81818181, 0x81817F7F, 0x7F7F817F, 0x7F7F7F81, 0x817F7F81, +0x7F81817F, 0x7F7F8181, 0x7F818181, 0x7F817F81, 0x817F8181, 0x7F818181, 0x817F817F, 0x81818181, +0x7F7F7F81, 0x7F81817F, 0x7F817F7F, 0x81818181, 0x817F8181, 0x7F817F7F, 0x7F818181, 0x7F81817F, +0x817F8181, 0x7F7F8181, 0x7F7F8181, 0x8181817F, 0x7F7F7F81, 0x7F7F7F81, 0x817F7F81, 0x817F7F81, +0x81817F7F, 0x7F817F7F, 0x817F7F7F, 0x7F7F817F, 0x817F7F7F, 0x7F817F81, 0x7F7F7F7F, 0x817F817F, +0x81817F81, 0x7F7F8181, 0x7F81817F, 0x8181817F, 0x817F7F7F, 0x7F7F7F81, 0x7F818181, 0x817F7F7F, +0x7F818181, 0x81818181, 0x817F7F81, 0x7F818181, 0x7F817F81, 0x7F7F817F, 0x7F818181, 0x81818181, +0x8181817F, 0x817F7F81, 0x817F8181, 0x817F8181, 0x7F817F81, 0x7F817F81, 0x7F7F817F, 0x7F7F7F81, +0x81818181, 0x81817F7F, 0x81817F7F, 0x81817F81, 0x7F81817F, 0x81817F7F, 0x81817F7F, 0x81817F7F, +0x81817F81, 0x7F7F817F, 0x817F817F, 0x8181817F, 0x7F81817F, 0x81817F81, 0x7F817F81, 0x817F817F, +0x817F7F81, 0x81818181, 0x7F817F81, 0x81817F81, 0x817F817F, 0x81817F7F, 0x7F817F81, 0x7F817F7F, +0x7F7F7F7F, 0x7F817F81, 0x81817F7F, 0x7F7F817F, 0x7F7F8181, 0x7F7F7F81, 0x8181817F, 0x81818181, +0x81817F7F, 0x7F817F7F, 0x81817F81, 0x817F7F7F, 0x8181817F, 0x81817F7F, 0x7F817F81, 0x81817F81, +0x7F7F8181, 0x7F7F8181, 0x81817F81, 0x7F81817F, 0x817F8181, 0x81818181, 0x81818181, 0x817F7F7F, +0x817F8181, 0x7F817F81, 0x7F817F7F, 0x7F818181, 0x81818181, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F, +0x7F7F8181, 0x817F8181, 0x7F7F7F81, 0x7F817F7F, 0x7F81817F, 0x8181817F, 0x7F7F817F, 0x7F817F7F, +0x81817F7F, 0x817F817F, 0x7F7F7F81, 0x817F8181, 0x7F81817F, 0x7F7F817F, 0x81818181, 0x7F81817F, +0x7F817F81, 0x7F7F7F7F, 0x7F7F7F81, 0x7F7F7F81, 0x7F817F81, 0x81817F81, 0x81817F81, 0x7F7F817F, +0x7F7F7F81, 0x817F817F, 0x81817F81, 0x8181817F, 0x7F817F81, 0x8181817F, 0x817F7F81, 0x81817F81, +0x7F7F817F, 0x817F7F7F, 0x81817F7F, 0x81817F7F, 0x7F7F8181, 0x7F7F7F7F, 0x7F81817F, 0x8181817F, +0x81817F7F, 0x81817F7F, 0x7F817F7F, 0x817F8181, 0x7F81817F, 0x817F7F7F, 0x7F817F7F, 0x7F817F7F, +0x817F7F81, 0x7F7F7F7F, 0x817F8181, 0x7F7F817F, 0x7F817F7F, 0x7F818181, 0x817F8181, 0x81817F7F, +0x7F81817F, 0x7F817F81, 0x7F81817F, 0x81818181, 0x7F817F81, 0x817F817F, 0x7F817F81, 0x7F817F81, +0x7F7F8181, 0x817F8181, 0x817F8181, 0x7F7F7F81, 0x7F818181, 0x7F7F8181, 0x81817F7F, 0x8181817F, +0x7F7F817F, 0x7F7F7F7F, 0x7F7F7F81, 0x817F7F7F, 0x7F7F7F81, 0x7F818181, 0x817F817F, 0x817F7F7F, +0x817F7F7F, 0x7F7F8181, 0x81817F7F, 0x7F7F7F7F, 0x817F7F81, 0x7F7F7F7F, 0x8181817F, 0x81817F7F, +0x7F81817F, 0x7F817F7F, 0x817F7F81, 0x7F818181, 0x81817F7F, 0x7F817F81, 0x81817F81, 0x81817F7F, +0x817F8181, 0x7F7F817F, 0x7F817F7F, 0x7F7F7F7F, 0x7F7F817F, 0x7F817F7F, 0x7F817F7F, 0x7F7F817F, +0x817F7F7F, 0x7F81817F, 0x7F818181, 0x7F817F7F, 0x7F7F7F81, 0x7F817F81, 0x817F8181, 0x7F7F7F81, +0x7F818181, 0x7F817F81, 0x817F8181, 0x7F818181, 0x817F817F, 0x7F817F7F, 0x817F7F81, 0x8181817F, +0x817F817F, 0x7F7F7F7F, 0x7F817F7F, 0x81818181, 0x7F817F81, 0x7F817F7F, 0x81817F81, 0x7F7F7F81, +0x7F7F8181, 0x81817F81, 0x7F817F7F, 0x817F7F7F, 0x81817F81, 0x7F817F7F, 0x81817F81, 0x81818181, +0x7F817F81, 0x7F7F7F7F, 0x817F817F, 0x8181817F, 0x7F7F817F, 0x817F8181, 0x817F8181, 0x81817F81, +0x7F7F7F7F, 0x817F8181, 0x817F7F81, 0x7F817F81, 0x817F8181, 0x81817F7F, 0x7F7F7F7F, 0x7F817F7F, +0x7F7F7F7F, 0x7F7F7F7F, 0x817F7F7F, 0x81818181, 0x81817F7F, 0x817F7F7F, 0x7F7F7F81, 0x7F7F8181, +0x7F7F7F81, 0x7F7F8181, 0x8181817F, 0x7F7F817F, 0x817F7F81, 0x7F817F7F, 0x817F7F7F, 0x817F7F7F, +0x7F7F817F, 0x7F81817F, 0x817F817F, 0x7F7F817F, 0x817F817F, 0x7F7F7F7F, 0x81817F81, 0x817F7F81, +0x8181817F, 0x81817F81, 0x817F7F7F, 0x7F818181, 0x817F7F81, 0x7F7F8181, 0x7F7F817F, 0x7F81817F, +0x7F817F81, 0x7F81817F, 0x81818181, 0x817F7F81, 0x7F818181, 0x81818181, 0x81817F7F, 0x7F817F81, +0x7F818181, 0x7F7F7F81, 0x7F817F81, 0x81817F81, 0x817F8181, 0x817F817F, 0x8181817F, 0x7F7F8181, +0x81818181, 0x817F817F, 0x7F818181, 0x817F817F, 0x7F7F817F, 0x817F7F81, 0x817F8181, 0x7F7F7F81, +0x7F7F7F7F, 0x7F817F81, 0x81817F81, 0x81817F7F, 0x7F817F7F, 0x81818181, 0x817F7F7F, 0x7F818181, +0x817F8181, 0x7F7F7F81, 0x817F7F81, 0x81817F81, 0x7F7F7F81, 0x8181817F, 0x817F7F7F, 0x7F7F7F81, +0x7F81817F, 0x7F818181, 0x817F7F81, 0x7F81817F, 0x817F8181, 0x817F8181, 0x7F81817F, 0x817F8181, +0x7F7F7F81, 0x81818181, 0x7F7F817F, 0x81817F81, 0x81817F81, 0x817F8181, 0x7F7F8181, 0x817F7F81, +0x817F8181, 0x817F7F81, 0x7F7F8181, 0x7F7F8181, 0x7F818181, 0x81817F81, 0x7F7F8181, 0x7F818181, +0x7F7F817F, 0x7F81817F, 0x817F7F7F, 0x81817F7F, 0x7F7F7F81, 0x7F7F7F81, 0x7F7F7F7F, 0x817F8181, +0x7F817F7F, 0x7F7F7F7F + +output0 = +0x88CCED56, 0x1C072C76, 0xD4D23B69, 0x78C979BF, 0x60764BE3, 0x4470E86B, 0x20A46F84, 0xA0211B5C, +0xE1952001, 0xB77912DE, 0x52E8BA16, 0xE5BE8445, 0x95093ACF, 0xA8BE03D2, 0x49DBB5AB, 0xC3946403, +0x4DD44236, 0xC2833E65, 0x7288C53B, 0xD64FB75E, 0x7438C1EC, 0x71070BEC, 0xA40F8094, 0xABF43E46, +0x564487F5, 0x8435AC89, 0x2D98A4C3, 0x07CD13F4, 0xB44CEEA6, 0x2E00DD83, 0x12EF45EB, 0x01A047B8, +0xBC563FD5, 0xCA5C1136, 0x7AB9F2C8, 0xD62C59A9, 0x913DF674, 0xC900322A, 0xCF54042E, 0x6CAADB1E, +0x8077B98C, 0xBCB51468, 0x58339E5E, 0x1D176854, 0xF9E2D74A, 0x2994B28A, 0xD0E46263, 0xCD8A0FDB, +0x0119B915, 0x1E5433C9, 0xEA298A7D, 0x9EB4FC8D, 0xEF93B537, 0x6D441397, 0x6A4C8DB3, 0xB8E4AFE9, +0x1520BC1C, 0x8669961B, 0x5D484802, 0xC2793340, 0xB5FE7945, 0x43AC7CE2, 0xB74B70C1, 0xFCF56F87, +0x3E146A49, 0x0391D092, 0x672D2427, 0xDC91BB53, 0xEB24AC1F, 0xCE0D8E63, 0xF12F7ED8, 0xB3192024, +0x0697AE9C, 0x3415F178, 0xD8410FFC, 0xE34734DE, 0x6C6E6BF1, 0xDCD211C3, 0xBF6B0B87, 0xA1624F47, +0x3524BC4D, 0x4B4A1891, 0x8691223C, 0x12EB2DA4, 0x0B51F616, 0x31276F0E, 0x86CB4D17, 0x15CA0F9B, +0xEB989F98, 0x1141D335, 0x442C699F, 0x82E9758B, 0x267E6D4D, 0x71BAC54A, 0x2FBCBD52, 0xA0966795, +0xEB08B437, 0x1A9899A0, 0x26484B82, 0x3AEE43A8, 0xC409BE45, 0xCF8C6EC9, 0x098DE63F, 0xC3BEA60B, +0xCB7A5B6A, 0xCBF2A44B, 0x31E9FA4C, 0x34FD7E88, 0xA3C5AF89, 0xF13C8E2B, 0xC01C79FA, 0x622B9FD8, +0x692D4C4F, 0x712BC24C, 0x16FBD6C3, 0x7B1BBC38, 0x63F1E328, 0x824C6F4B, 0xDC + +basegraph= +2 + +z_c= +384 + +n_cb= +19200 + +q_m= +2 + +n_filler= +56 + +e = +36936 + +rv_index = +0 + +code_block_mode = +1 + +iter_max = +20 + +expected_iter_count = +3 + +op_flags = +RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK + +expected_status = +OK diff --git a/app/test-bbdev/test_vectors/ldpc_enc_v11835.data b/app/test-bbdev/test_vectors/ldpc_enc_v11835.data new file mode 100644 index 0000000..bc84e55 --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_enc_v11835.data @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2019 Intel Corporation +# Origin : FEC5G_DL_1/xxxx + +op_type = +RTE_BBDEV_OP_LDPC_ENC + +input0 = +0x44FB08C0, 0x661CCC + +output0 = +0x1BACEE95, 0x613ECD04, 0xC0 + +basegraph= +2 + +z_c= +10 + +n_cb= +500 + +q_m= +6 + +n_filler= +44 + +e= +66 + +rv_index= +0 + +code_block_mode= +1 + +op_flags= +RTE_BBDEV_LDPC_RATE_MATCH + +expected_status= +OK diff --git a/app/test-bbdev/test_vectors/ldpc_enc_v2342.data b/app/test-bbdev/test_vectors/ldpc_enc_v2342.data new file mode 100644 index 0000000..233d7a9 --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_enc_v2342.data @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation +# Origin : FEC5g_DL_1/2342 + +op_type = +RTE_BBDEV_OP_LDPC_ENC + +input0 = +0x02524C20, 0xB9B1FEA2, 0xC1BAB7E5, 0xEF5714CB, 0x7DE6A64D, 0xA05F9DC9, 0x0747D1E3, 0x3B20BC86, +0x6FCBDB0F, 0xF2FB7A23, 0x79D5E062, 0x5BF4E7C3, 0xD4A68A37, 0x07B4A6AD, 0x37E911F9, 0x7FE7B30A, +0xBBC284A2, 0xD38D6136, 0x25FAB76B, 0xBEBBF534, 0x9A88F9DB, 0xE37FD52D, 0x691DD493, 0xED2F738C, +0x89A96EA0, 0xD981246A, 0x17CC820E, 0x07E3B463, 0xC9FC2590, 0x7475A33C, 0xA5151BB4, 0x1F7E759E, +0x9554F964, 0xD0FA01F4, 0xD31774D2, 0xEB73A9F6, 0x8C9FBCB1, 0xF83010FB, 0x1909E09F, 0xC46023EB, +0x02AEDC62, 0xC6352CC7, 0x674BDC6D, 0xE17CD747, 0x4E25B0B3, 0x4BFF6B17, 0x12C9AAA3, 0xC2BC91CD, +0x44BE23A2, 0x8A72A157, 0x6E0DAD1F, 0x6CA69A09, 0xB55B582E, 0x01818B31, 0x5CA5CAB6, 0x1917AB24, +0x38F98BCD, 0x01917487, 0x05906FDD, 0x760AFCBA, 0x19671085, 0x64E3546E, 0xEC10F922, 0x3CF286CA, +0x68E273EA, 0xF1001325, 0x5DCB3B49, 0xE9547370, 0x65D26AE6, 0xF621256C, 0x25D6D99C, 0x7862EBA0, +0x43365DB0, 0x4DBF06C5, 0x92FCAA02, 0xB0FD58FA, 0x910E80A6, 0x93D24A67, 0x6E39B144, 0x3D46D6F6, +0xEDC55081, 0x33CD70C7, 0xC74B6E8E, 0x91AA27B9, 0x55B3542D, 0xEBF8046A, 0xB9ABDB94, 0x97FC38A8, +0xD5837B4D, 0x764B1809, 0xFBE2096A, 0xC23887AC, 0x2A45029B, 0xCBB7DF70, 0x674654E1, 0x0C6A06BD, +0xB3E8853E, 0x03FCC4CE, 0x26806F2E, 0x2CEB35B0, 0x10538B03, 0x94B059B8, 0xA95E7FFA, 0x48AD3D0A, +0xEB9091E1, 0x972E31EF, 0x5EBC6F8F, 0x947FF108, 0xCB3123FA, 0xFEE1D939, 0xF3DC5C49, 0xA92927AE, +0xF49BB8D0, 0xAA59F730, 0x4A66D1CD, 0x030E1ADF, 0x238D5B19, 0x96F861F1, 0x915424E4, 0x9127880C, +0x8E779839, 0x87375FCE, 0x61FB3D79, 0x96B1EE83, 0x47BF6667, 0x19E7D408, 0x7E91137F, 0x0E4AD8E8, +0xDABD2E45, 0x9B60873F, 0xD0294A65, 0x2A38A862, 0x59DD046D, 0x9832BB79, 0xA5870DB6, 0xB3F1CC48, +0x7E9A8132, 0xEEA2E4BC, 0xF23ED87B, 0x550E011F, 0x9620E0C0, 0xE7CF0834, 0xDEE69623, 0x6184D512, +0xD3D55728, 0xFA7711D4, 0x9C77B0F9, 0x8A26462B, 0xB3F5C8D5, 0x1123246D, 0x78F36272, 0x940EE0F9, +0x757BF240, 0x7EE2B6D0, 0xD40FD5A1, 0xAB4205CA, 0x96E6B758, 0xAC5F4294, 0xC9268C66, 0xB48DC535, +0x3CF6ED4C, 0xF187EFED, 0x7A09B08D, 0x8709EFCE, 0x267B2468, 0x0015D770, 0xDF1B90BF, 0xA03DAD85, +0x2633012E, 0xE5437125, 0x58B79AFF, 0xB929C532, 0x6D890DC9, 0x89A59AD2, 0x2BB99316, 0x41B5B0EB, +0x7304B295, 0xB37F6708, 0x2F84A68E, 0x3637D79A, 0xDD36687B, 0x904BF7B6, 0x6A2CF453, 0x733DED54, +0x5DF48BAA, 0xC3FCC99F, 0x8E3BE1DB, 0x61D9CF2D, 0xB7DC202B, 0xA959FF95, 0x860D0F14, 0x4008C478, +0xD9325A51, 0x27A29D4C, 0x308FE6D4, 0x7A1AA889, 0x5BD38393, 0xCBFA5D + +output0 = +0xADE67AA9, 0x1CB4EBDD, 0x74E76684, 0xE3941FC7, 0x48DAC304, 0x1E2C198D, 0xFE88B908, 0xEC21A3DE, +0xBF314AB7, 0x634E3DCB, 0x0DA84E23, 0x58B1B22B, 0x02B837A0, 0x8B04BF38, 0xFB8DB526, 0x1BFF82E9, +0x4226C4D0, 0xF7A9950E, 0x6DA4D0B2, 0x38E15395, 0x94C1A379, 0x243ED666, 0x3E7255B3, 0x7DB378DB, +0xA3CE1377, 0xE0137291, 0x42DB50AC, 0xEB2D0A13, 0xCA55944A, 0x223DF8E0, 0xB800D1CF, 0xAA2E7577, +0x50153EC5, 0x5E3C8557, 0x63DDEC8F, 0x49A256F8, 0x41ABFD56, 0xEB76A4D7, 0x4F4E9C7C, 0x3508DA39, +0x530F9DA0, 0xFFD20E32, 0x395F7963, 0x1C48B3F7, 0xD3BC29C7, 0x4D6ED90F, 0xC1C9EF58, 0x9B9D4A13, +0x417BF36E, 0x1BB5FDD8, 0x72793F28, 0x2F297FA5, 0x204AA988, 0x28317636, 0x87878EC8, 0x33024F9D, +0xE651388E, 0x560ACA6E, 0xEC3D0B64, 0xCB515AAE, 0xE42B9ECD, 0x2AE2B0D1, 0xCD659A28, 0x8BD5E4D8, +0x0D618DD6, 0x14CF8DB1, 0xE9F82BB6, 0x558C50A4, 0xA9809F8C, 0x15646823, 0x6037DB27, 0x26A0ABAA, +0xF8DC4AC6, 0x533494C9, 0x7BF60155, 0x7BB16D05, 0x89F7A1BA, 0xCB069606, 0x6572D71A, 0x001917EB, +0xD353913B, 0x128F78BD, 0x83BCE2A3, 0xE0065266, 0x9E7E608F, 0x25889472, 0x184ADD42, 0xD42B429B, +0x7A8D861F, 0x54C97AB8, 0xB8B04229, 0xDF3DE03A, 0xB97E311E, 0xBB2A1FF8, 0x53AC8D5B, 0x1825B5DC, +0x9843DD95, 0x0214EAA6, 0x3B1CF504, 0xD3BE316F, 0x9B1D3C64, 0x8EF4A268, 0xFACBC9AD, 0xDCC6033F, +0xF801E3D1, 0x92F3E3A1, 0x1EC121AC, 0xA6747F20, 0x6ACC34EF, 0x0F641DC0, 0x42CAB9C3, 0xE04036DD, +0x97739381, 0x9843A304, 0x929E9AB7, 0x600E057F, 0x892D5F1F, 0x0F718281, 0xD345AA58, 0xF39215C4, +0xBCAB0B51, 0x1EBEA1B0, 0x68885471, 0xB39AD728, 0x2FF70470, 0x80D01FE5, 0xB41A95C0, 0x01DB8079, +0xA4C9F364, 0x41860F1A, 0xEBE24F2B, 0x086BFFF0, 0x7B66DE40, 0xFFF665D6, 0x18324792, 0x1D253106, +0xC41B9BF0, 0xC79347BA, 0x6949A396, 0x279E7A4A, 0x4029B533, 0xE8B382E2, 0x89783E24, 0x3D945C74, +0x49BD75D8, 0xBAD731A0, 0x48B4AFAB, 0x4383B903, 0x8A6966A6, 0x170B9958, 0x58307AB6, 0x3B627463, +0x0B981BEA, 0xD8E9A038, 0x723219E7, 0x4F6E5470, 0xE4F3CF92, 0x37AACC8A, 0xA4E46500, 0xE44DDA39, +0x68690180, 0x33143C47, 0x9A6EE438, 0x5FA00F23, 0xD2CEE248, 0x46090D1A, 0xDE5491AE, 0x417D853E, +0xC607B731, 0x79D7DCCF, 0x13200C03, 0x07CAB5E9, 0xB59525EA, 0xE47B66A5, 0xB125AAAB, 0x20CCFE07, +0x82F1F4E8, 0xCF44BD2B, 0xC462D58D, 0x60A6A73B, 0x0D0CA712, 0xFE342922, 0x15123217, 0x7A02E89D, +0x49B44659, 0xB9F3AE54, 0xAFC472BC, 0x79AF1A6D, 0x7430BA59, 0xEA13F81C, 0x33592D7D, 0x1EF1E1DC, +0xF51FF0C8, 0x80F7B07E, 0xC1536EBB, 0x586CB41D, 0x10AF823C, 0x390EA571, 0x7D54C302, 0xA049ECBE, +0x368C3981, 0x38B72BEE, 0x833C5F98, 0x2E18D066, 0x5742B0D2, 0xA8F5F0B8, 0x9144935D, 0x7392A908, +0x3175DBC0, 0x29AA2F7C, 0xF53FED73, 0xFE41236B, 0x091E47EC, 0xD2195647, 0xCAAEA8B5, 0x0ED9750E, +0xF5027456, 0xF1838780, 0x16FFE8EE, 0xA21568C6, 0xC5E4FCAF, 0x27C24C4B, 0x3DE89E8E, 0x5464ADC6, +0x865C8493, 0x41032697, 0xD5F82075, 0x49167AF7, 0xED1AA45C, 0xA6B20018, 0xB1776BA9, 0x9F2129B6, +0x611C417D, 0x3B72E8B6, 0x1AA7DB22, 0xF4ADF40E, 0xA24B8EFB, 0xF25C5F9D, 0xE52C047E, 0x3B8C9A26, +0x4C0760E4, 0x73027C0E, 0x1F5977D8, 0x6CAF979D, 0xEF39719F, 0x70129F6A, 0x0CC821CD, 0x9853AE70, +0xC3EB24E5, 0xE4EED628, 0x9F904579, 0xFD680398, 0x2C84DF92, 0xF92DA147, 0xB2F7C7C3, 0x59052EB6, +0x4DF89375, 0x275D0C58, 0xBE32DA96, 0x7A3C4C7F, 0xC5C2B02F, 0x651B2665, 0x36E5DC9B, 0x98B1F08B, +0x175A5AE0, 0xBEC258CA, 0xDDF6B687, 0x49E3DBE6, 0x07C1C780, 0x63E3B861, 0x05FDAAEC, 0xFA7C38A4, +0x5EE93618, 0xF8B78C2B, 0xBB5035B7, 0x7E297AC8, 0x6CC27636, 0x30D44C50, 0xECB1065B, 0xB00AB96E, +0x87B3C67E, 0x0AA61403, 0xF514C18B, 0xDBF3CEEB, 0x62ACA4C1, 0x9A0D1691, 0x07E3DF50, 0xC42070E8, +0x98F349F7, 0xC1556162, 0x6F7D7109, 0xF6C7B215, 0x73748B4E, 0xAF9F5BFF, 0xDD1B8AE6, 0xA9C710AA, +0x5965A4DA, 0x762A0F38, 0xD42C7578, 0xBA69C66D, 0x2CCABCB7, 0x932E7065, 0xD6F3F37E, 0x729F1412, +0xE5EAEB07, 0x1C2D7291, 0x07E5E6C9, 0xCA16EED5, 0xD488558D, 0x235C11EB, 0x579B8BCA, 0xAC352250, +0x858BD553, 0xECCBE50A, 0x370421F0, 0xA66CD423, 0x1424CB84, 0x286FBE65, 0xDFF5A1E9, 0x71ABB615, +0xAE331217, 0xE8E333A5, 0x99044B7D, 0x26264E30, 0x35A7FEA1, 0x3E933B79, 0x4151D8A3, 0x672D78D6, +0xC586C999, 0xEFFEFF6F, 0xD1EC082A, 0x0EB38797, 0x85F77710, 0x5FEAE876, 0x78FBE4E2, 0x6284663A, +0x6E54B0AF, 0x5C107AF7, 0x24005DF7, 0xA994E2EC, 0xAFDDB6FF, 0x79019A53, 0xE1B8A123, 0x997B7B95, +0x9BFC63E3, 0xEAEEB40C, 0x14AECFE6, 0xC29A3F38, 0x21833356, 0x6B65DAAC, 0x9AEADA3F, 0x16582D82, +0xD6E7B8EC, 0xEE67A365, 0x3F33FD50, 0xABD603DC, 0x0DA08D72, 0x69E01AFD, 0x4862B58E, 0xE1DFCA98, +0x5FE11079, 0x40992E48, 0x0589689B, 0xE836FACC, 0x87FFD4D6, 0x9F5DF070, 0x6BC69520, 0x5CF6F087, +0x66523DC9, 0x54D0EEA3, 0xDD820FC2, 0x663BFA8E, 0x2561E952, 0xA82EDAB8, 0x3FC1092B, 0x8591A2C1, +0x0E9E67EF, 0x4A334D9C, 0x867BB16F, 0xB6A1713F, 0xED8D7EFE, 0xF2926C44, 0xD2E97512, 0xE8301103, +0x3DD30957, 0xEFB71B3F, 0x4AE801D5, 0x8F75F730, 0x0C34FBC9, 0x7A60C668, 0x77908ED9, 0x963C0DE4, +0x5279E29C, 0x6759B153, 0x747E5E7B, 0x4C510BE5, 0x32BE2132, 0x54B361E0, 0xCB4D9616, 0x3C404BA4, +0x4BA0E910, 0x05F06AD1, 0xAE3FBC5C, 0x82CB03B4, 0xF0EC45FF, 0x9888791B, 0xDE4B9813, 0xF83B4090, +0x3CC4BA28, 0x7CFE8854, 0x9CA7BC9D, 0x0E41843E, 0xF92535F6, 0xF19CC699, 0x0821CBF4, 0xF15F3F82, +0xCF6CC14C, 0xF27DA57E, 0xB8DB8982, 0xFC7E263D, 0x63C36111, 0x61587ABA, 0xB87CB18D, 0x2C806A64, +0xD8DFFF2C, 0xC8540E77, 0x1A340B85, 0xB6FBA97F, 0x77A1958D, 0x419648E8, 0x80A65729, 0xC3EC1141, +0x3909010F, 0x84F8C534, 0x2FEDE987, 0x83851AC8, 0xAE88B841, 0xE8284692, 0x3243F04B, 0x9C845E80, +0x4A7FC52E, 0xF6B1035A, 0x59E1C576, 0x21620CB8, 0xF047E16D, 0x079284B7, 0x00B6C955, 0xA7B19103, +0x7B9EB069, 0x733E2443, 0x489A6EAE, 0x7BB17B2C, 0x6AB4F848, 0xEFA299A2, 0xC464BE42, 0x36F27FC5, +0xE70CEAB2, 0x6FCB4031, 0x9C0A14C0, 0x682AA1A3, 0x36E7032C, 0x57BA22A8, 0x085288CE, 0xDE62ADD4, +0xC0138A07, 0x4A5576F5, 0xC0F33DE3, 0x919ECA7A, 0x14FFDE87, 0x362897AF, 0xD542F683, 0x86FBC0FC, +0x8CD6DD3E, 0x25832EDF, 0xC2C9EE74, 0xB244A89B, 0xFEAF2F44, 0x1D631217, 0x80BA2267, 0x097D3F4D, +0x406264AC, 0x0571B5FF, 0x55658770, 0xE12F6AA3, 0x666D9831, 0x37E17306, 0x88D926AB, 0xBB0CC6D9, +0xA857A201, 0xB24E5A82, 0xF259D2AE, 0xD09D0FAE, 0x87363A50, 0x583F1CC9, 0x653F73F3, 0x0D04970B, +0x64D1F222, 0xEF7E0E0B, 0x7F5D49DB, 0xAC4549D9, 0x707D1FCF, 0x3A151C06, 0xFE5DEC4A, 0xE3D6CCBA, +0x0AA3DA9B, 0x4665CBC5, 0xDF7BCD0F, 0x63DD0FF5, 0xC9C2A642, 0xB40B516D, 0xE259A165, 0xE2E454E1, +0x0A384EDD, 0x1287018F, 0x2A7A8DFD, 0xF854FCF1, 0x79CAA64E, 0x351AC522, 0xEE65C527, 0x7F160E51, +0xF465AF5C, 0xE671974B, 0xAF75CA8D, 0x47A5EC29, 0x5F93C8AD, 0x6420D4E9, 0xA5CA4610, 0x265F0BF4, +0x6622036C, 0xB542C8CB, 0xDFD1FA4F, 0x5869BE19, 0x14605EAE, 0xA438FEA7, 0x9523F5FA, 0xE18FCF2B, +0x5F11F7B1, 0x7A790EBA, 0xDBDD0005, 0x024E0D8B, 0xC387778B, 0x3C0F1274, 0xA722512C, 0xEAB3C2F3, +0x11B55F3A, 0x9C2DBBD6, 0xA76C80DC, 0xD63A5DD2, 0x320F7AF2, 0xA707544C, 0x889A3C58, 0x50CCA3B0, +0xD54FE248, 0x22EF12A3, 0xF618F564, 0x1D9266C8, 0x4E08FB46, 0x6D1D41EB, 0x5CFF2094, 0x116ECB97, +0x46FD4058, 0x38FBE5CC, 0xE008E8EF, 0x578FAF14, 0x3BEED1D9, 0x8C89B4CE, 0xFC0C33D7, 0x0913ECF8, +0x498D47D1, 0x5644A9B3, 0x6EA66735, 0xA0F3BA09, 0x948B258F, 0xFA8DE3BE, 0x2FB03145, 0x8D0B61B3, +0x42D6F53D, 0x031FD745, 0xFF86C938, 0xA32BB471, 0x50208969, 0x9F6909C9, 0x680C6D55, 0x13054044, +0xDFDEBEF7, 0x35600E83, 0xAFB26C47, 0xCAA86F9F, 0x5B5B65A7, 0x599DA0C3, 0x789EC931, 0x0163D6D4, +0xF7BBA271, 0x5A755052, 0xFA27CE77, 0xD66ED111, 0x7A5BD527, 0x1B26B948, 0xAA11725B, 0x4A6AC4AD, +0xDD8EA8DF, 0xF0C618D3, 0xF97999E5, 0x00C42C38, 0x8465BE06, 0x7B6912C9, 0x4AF1F070, 0x4F93EEB0, +0x19A400FC, 0x0F8A6744, 0x7FD642F2, 0x3AE8F32F, 0x84501DDA, 0xB39068C6, 0x2A5BE1A6, 0x08E231F0, +0xD52F4D13, 0x89326BE0, 0x3981DD90, 0xA986F547, 0xADF1B2E8, 0x6337CFB6, 0x595FCBC0, 0x2D774749, +0x1D6C5FF1, 0xF403CE90, 0x16792051, 0xCE248A7D, 0x43E76774, 0xA85ED14A, 0xCFBDEB69, 0xDF559AF6, +0xC3BF33D1, 0xF03BB486, 0x107D04B0, 0x9B9E9432, 0xE4873EC4, 0xFD7C2E89, 0xFA69FD26, 0xD04F8825, +0xB9C4FF1F, 0x30F0826C, 0x825A8A34, 0x5EBB4ADC, 0xA71C9FF5, 0xE90ECF8A, 0xFEF3270F, 0x25612AB6, +0xF8560C1F, 0x625A9ECE, 0x12B9B123, 0xA281D55C, 0x276F3B4A, 0x6CDE95D8, 0x7EE9F866, 0xDC769A4F, +0xC590E1F4, 0xEA845796, 0x013AFD9E, 0x6F8E1A4D, 0xBEDF18E1, 0x2CC567BD, 0x56CBAE9D, 0xF81716E8, +0x88834AAE, 0x1C67A0AE, 0xDDB4EB33, 0xF0F874E6, 0x4DE9C550, 0xCEAC73AD, 0x5C800FD8, 0x6A31B61A, +0xA8B3A501, 0x73639607, 0xC95BAE + +basegraph= +1 + +z_c= +320 + +n_cb= +21120 + +q_m= +4 + +n_filler= +688 + +e = +21592 + +rv_index = +0 + +code_block_mode = +1 + +op_flags = +RTE_BBDEV_LDPC_RATE_MATCH, RTE_BBDEV_LDPC_CRC_24B_ATTACH + +expected_status = +OK diff --git a/app/test-bbdev/test_vectors/ldpc_enc_v7813.data b/app/test-bbdev/test_vectors/ldpc_enc_v7813.data new file mode 100644 index 0000000..79294ec --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_enc_v7813.data @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation +# Origin : FEC5g_DL_1/7813 + +op_type = +RTE_BBDEV_OP_LDPC_ENC + +input0 = +0x8C4DEB9F, 0x52 + +output0 = +0x1A6D0FA6, 0x7017 + +basegraph= +2 + +z_c= +7 + +n_cb= +350 + +q_m= +2 + +n_filler= +30 + +e = +44 + +rv_index = +0 + +code_block_mode = +1 + +op_flags = +RTE_BBDEV_LDPC_RATE_MATCH + +expected_status = +OK diff --git a/app/test-bbdev/test_vectors/ldpc_enc_v8568.data b/app/test-bbdev/test_vectors/ldpc_enc_v8568.data new file mode 100644 index 0000000..c72680b --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_enc_v8568.data @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation +# Origin : FEC5g_DL_1/8568 + +op_type = +RTE_BBDEV_OP_LDPC_ENC + +input0 = +0xB6D49CE2, 0x3E96B93F, 0xF02009F6, 0x2DF3D30D, 0x3B06C160, 0x646C69CC, 0x54439F0F, 0xCE0D12C3, +0x66E8BFD5, 0xA9D22B0C, 0xA9E7343B, 0x2B6EEF01, 0x6B6966C0, 0xB98FE144, 0xC3BF7BAD, 0x1B40DF1C, +0x973B12DC, 0x46E25E90, 0xB324ACCA, 0x5F0ED2B9, 0xBB4F + +output0 = +0x8F1A7C00, 0x836CF0E5, 0x717CE52D, 0xEE86FB44, 0x21621E25, 0x58425AB5, 0xECA0F645, 0xAE9E63E6, +0x287D84BC, 0x9F19A401, 0xD68C4CA3, 0x354ACA5A, 0xD68D7FF8, 0xFAA84645, 0xCF0DBC28, 0x693C50F0, +0x9A3CD23C, 0x57E97520, 0x929BAF90, 0x8E2BA7D8, 0x5EF0FB8A, 0xFFE7B153, 0x9E164074, 0x4D06F0A2, +0x6BC68E5B, 0xB8274587, 0x69641DFC, 0xF5DC89A0, 0x4F8E741C, 0x1CB682DA, 0xEF36E914, 0x8BDEBA30, +0x4B6777E2, 0xEFBFD14C, 0x85F0DF67, 0x55DBD201, 0xCF29A01A, 0x862BD273, 0x1F43CFAF, 0x5CB128E9, +0x9C322654, 0xF8E4E47A, 0x0FCD1806, 0x0C7B6BC7, 0xF7B9748A, 0x6DE5D592, 0x0D119373, 0x5F7DC28C, +0x68F26F39, 0xAA47E18A, 0x479CDAAF, 0xE19DCBB3, 0xA72B475D, 0x2E781ED4, 0x4CBB910A, 0x5E5A5A1D, +0x2F668621, 0x86BD9FE1, 0xF1DC12E5, 0xB652E2C1, 0x2E0AC199, 0x059E43C4, 0x14F9B51E, 0x7DA378C5, +0x214E4D5F, 0x72ECE751, 0xF997A106, 0x3F362F62, 0x045DCA85, 0xAD27A58E, 0xB73B4390, 0xEB76C5D2, +0x58CE8B78, 0x73A1D1EA, 0x9705C8E4, 0x224703E8, 0xA0DE7885, 0x9CDBBEE0, 0xBAAFAE85, 0x1B5CFB8A, +0xF66B5209, 0x979335BB, 0x2AA6C7E2, 0x7E3958E7, 0xD39F8BC0, 0xD73BEA43, 0x24C74D3E, 0x9372C2D7, +0x49804670, 0xB3A983FC, 0xFA6DB662, 0x4E657550, 0xDDF757C2, 0xA7265DE7, 0x51BFA1A6, 0x63E1325D, +0x1FDBE953, 0x17348EDB, 0x6B6DC5C0, 0xE335772B, 0x32612617, 0xC13B63EB, 0x8C40891A, 0xF3566154, +0xF5345933, 0xAD9AB800, 0x4CF92B41, 0xF3B32673, 0x80577879, 0x19F8BB0E, 0xAD677483, 0x21B2EDC7, +0x3F96C8E2, 0x7B9211B7, 0x11909101, 0x6A9D9BF5, 0xC4A0E407, 0x5B013820, 0xD2102C31, 0xDC6F548A, +0xA4F6B72A, 0x79F19991, 0x6A21BE3C, 0x2E5CF7A5, 0xDCBB384B, 0xB05B5649, 0x1D61CCF1, 0x9DC122F3, +0x00CA6A82, 0xB7CECDF0, 0x605252A3, 0x0500B498, 0x61AA1618, 0x669788EF, 0xF0DB599F, 0x3ED04C4A, +0x17387F1E, 0xBDAC7B52, 0xEE7D1E0D, 0x58AF212C, 0x0CB064F8, 0x646239DB, 0x88CF9549, 0xD3C7C652, +0xB82109DB, 0x22225244, 0x305F8384, 0x9B4166D5, 0x704FA445, 0x956A0CA5, 0x89963D07, 0x5EF61FAB, +0xF71EAD06, 0xA47FB814, 0x86581A5C, 0xB81B9445, 0x4ECD608E, 0xE369E9A3, 0xFEB80EE5, 0x1399AB02, +0x30A74BEA, 0xCF08B948, 0xB0857028, 0xC81F8CD8, 0x64E13623, 0xAFF927F5, 0x592D7629, 0x7295DE02, +0xE98E2F04, 0x7407C828, 0x85EE9A47, 0xF9B6F671, 0x77F40DF0, 0x81CE7DA1, 0xB8732D5F, 0xC7AC742E, +0xF8623836, 0xE68F4E66, 0x18F29BB9, 0xF57E3350, 0x0E14399C, 0x114ACFA1, 0xFECFBDAA, 0xB0894694, +0xC8DF6D23, 0x7C71FB18, 0x91F00CF2, 0x6A45BC52, 0xFE99962D, 0x41FEBA3D, 0x5C1BB499, 0x51E50591, +0x04D9CDDE, 0x503FBB80, 0x2788B4EE, 0x82A545D8, 0x5F6DD45D, 0x7AE48BE2, 0x4C653419, 0x3C32D58C, +0x48788C71, 0x97A054A3, 0x7FC443B4, 0x805DFF9E, 0xA607D2C6, 0x02DA82C2, 0x884664C5 + +basegraph= +2 + +z_c= +72 + +n_cb= +3600 + +q_m= +2 + +n_filler= +64 + +e = +6624 + +rv_index = +0 + +code_block_mode = +1 + +op_flags = +RTE_BBDEV_LDPC_RATE_MATCH + +expected_status = +OK diff --git a/app/test-bbdev/test_vectors/ldpc_enc_v9503.data b/app/test-bbdev/test_vectors/ldpc_enc_v9503.data new file mode 100644 index 0000000..1426872 --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_enc_v9503.data @@ -0,0 +1,196 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation +# Origin : FEC5g_DL_1/9503 + +op_type = +RTE_BBDEV_OP_LDPC_ENC + +input0 = +0x88CCED56, 0x1C072C76, 0xD4D23B69, 0x78C979BF, 0x60764BE3, 0x4470E86B, 0x20A46F84, 0xA0211B5C, 0xE1952001, 0xB77912DE, 0x52E8BA16, +0xE5BE8445, 0x95093ACF, 0xA8BE03D2, 0x49DBB5AB, 0xC3946403, 0x4DD44236, 0xC2833E65, 0x7288C53B, 0xD64FB75E, 0x7438C1EC, 0x71070BEC, +0xA40F8094, 0xABF43E46, 0x564487F5, 0x8435AC89, 0x2D98A4C3, 0x07CD13F4, 0xB44CEEA6, 0x2E00DD83, 0x12EF45EB, 0x01A047B8, 0xBC563FD5, +0xCA5C1136, 0x7AB9F2C8, 0xD62C59A9, 0x913DF674, 0xC900322A, 0xCF54042E, 0x6CAADB1E, 0x8077B98C, 0xBCB51468, 0x58339E5E, 0x1D176854, +0xF9E2D74A, 0x2994B28A, 0xD0E46263, 0xCD8A0FDB, 0x0119B915, 0x1E5433C9, 0xEA298A7D, 0x9EB4FC8D, 0xEF93B537, 0x6D441397, 0x6A4C8DB3, +0xB8E4AFE9, 0x1520BC1C, 0x8669961B, 0x5D484802, 0xC2793340, 0xB5FE7945, 0x43AC7CE2, 0xB74B70C1, 0xFCF56F87, 0x3E146A49, 0x0391D092, +0x672D2427, 0xDC91BB53, 0xEB24AC1F, 0xCE0D8E63, 0xF12F7ED8, 0xB3192024, 0x0697AE9C, 0x3415F178, 0xD8410FFC, 0xE34734DE, 0x6C6E6BF1, +0xDCD211C3, 0xBF6B0B87, 0xA1624F47, 0x3524BC4D, 0x4B4A1891, 0x8691223C, 0x12EB2DA4, 0x0B51F616, 0x31276F0E, 0x86CB4D17, 0x15CA0F9B, +0xEB989F98, 0x1141D335, 0x442C699F, 0x82E9758B, 0x267E6D4D, 0x71BAC54A, 0x2FBCBD52, 0xA0966795, 0xEB08B437, 0x1A9899A0, 0x26484B82, +0x3AEE43A8, 0xC409BE45, 0xCF8C6EC9, 0x098DE63F, 0xC3BEA60B, 0xCB7A5B6A, 0xCBF2A44B, 0x31E9FA4C, 0x34FD7E88, 0xA3C5AF89, 0xF13C8E2B, +0xC01C79FA, 0x622B9FD8, 0x692D4C4F, 0x712BC24C, 0x16FBD6C3, 0x7B1BBC38, 0x63F1E328, 0x6F4B + +output0 = +0x6ED462FE, 0x29726470, 0xE49C87C1, 0x6594725E, 0x64C81AE1, 0xA30C91C2, 0x5B4261AB, 0x7A44E3A4, + 0xACBD3DC8, 0x319AF530, 0xF3B21EC1, 0xAC180011, 0x26319FF9, 0x5946FBFD, 0x6F31959A, 0x571501D9, + 0xFB1F62B7, 0xF19F6C36, 0x43436C4A, 0x8CA5F436, 0x18AF91B4, 0xD86ED79F, 0x8732D29C, 0x6CE3B559, + 0x2DEA712F, 0x52C2E21A, 0x5C4E884C, 0xD2F50500, 0x2140E848, 0xABE47066, 0x8AE3FC46, 0xF0298999, + 0x829FE184, 0x51D53B6B, 0x7546D03C, 0xF1CB22DA, 0xB9D6F966, 0x85660A1F, 0xC1296566, 0xB2122E16, + 0x2AA38C25, 0xD7AF18FC, 0x489BDDC5, 0x93183097, 0x4C694A3C, 0x40B325F8, 0xEE05DAB2, 0xA6E0C990, + 0x839A7753, 0x0251D207, 0x5E1EC6B5, 0xED523076, 0xD985E23A, 0x8CA88259, 0xB0EFF6D4, 0xA9D7749B, + 0x32CA6F0E, 0xAAA84E97, 0x0F137B83, 0xE73C3175, 0xA3940FDA, 0xD878B121, 0xFFC8D2EC, 0x95CB65AC, + 0xB1CBE446, 0x73520449, 0x7D929F16, 0x69D1873C, 0x85640C01, 0xF2228024, 0x0A5E0461, 0x58B0933A, + 0xD37E2375, 0x36CEECEF, 0xE57A48F8, 0x4A35B5C9, 0x016A16A0, 0x6F9BCF30, 0xEB7C3BD0, 0xB1AF27FE, + 0x9C389360, 0xA91F2142, 0x51E618D3, 0x5F045697, 0x654C6A49, 0x2E38E30C, 0x9E8F1E63, 0xF1B25686, + 0xA0CDFB02, 0xDAEC605D, 0xED910B79, 0xA8E1A341, 0xAD6BD0A3, 0x03BABB0D, 0x4059355C, 0x5ECB8646, + 0xFDD9E0C6, 0x69106FD2, 0x47BF857E, 0x740F6313, 0xAB15E1FF, 0x94B21225, 0x600FEDF3, 0x1EF83A71, + 0xCE6956EE, 0xE538FC7D, 0x47520BE0, 0xA1A20CF2, 0xCB452B91, 0xEACB9E3C, 0xBA242A34, 0x13C81868, + 0xA58AB271, 0x724B350D, 0x95131286, 0xCF74DD61, 0x1D0CF41B, 0x38D046D2, 0xB709708D, 0x4D479AA8, + 0x3CBF6817, 0xDF115777, 0xBE69B850, 0x071A2B4C, 0xF3246B56, 0x2881CBA0, 0xAE158E87, 0x36538CB0, + 0xEF879197, 0xDBA9C1C7, 0x4EF7235A, 0x56120670, 0xC22DBEC7, 0x7071A05C, 0x376ADBD4, 0x5DD586FC, + 0xA638A621, 0x6D49A92A, 0x66F0C925, 0x023FC9DE, 0xF7CA1D36, 0xAF19A18B, 0x2A787792, 0x518938D7, + 0x25DE7B4A, 0xDEBD9010, 0x9683558D, 0x9C5694C7, 0x8B2558D0, 0x790CD121, 0x0A35C0D8, 0xCD4FBCED, + 0xB89F3275, 0x64A49655, 0xED7992A1, 0xAFB0A4D0, 0x29A9EB1B, 0x9244B2C0, 0x2CD88F45, 0x4AA1E98E, + 0x8E32CC3C, 0x8BE5DC7B, 0x759C8B24, 0x8AA119BE, 0x9CFEA065, 0x071F86FD, 0xB83F8181, 0x604FF2FB, + 0xAACDC394, 0x0BCC72F5, 0xE9C0CB19, 0x56EAE15F, 0xD33B8DEF, 0x01A1B007, 0xBED7C1A3, 0x18788E49, + 0xB565EA30, 0xC269F619, 0x1CF1B024, 0x067E9F59, 0x78E61AB4, 0x3D46CFBB, 0xE58E910B, 0x8E7ACF53, + 0x1EB9C15D, 0x4E3C43BF, 0xEF3D8F20, 0x5CC0A030, 0xE10AE4E7, 0xABE24941, 0x9A0C4046, 0x24E090CF, + 0x3248C414, 0xAF76560F, 0xCD1B106C, 0x70438AD4, 0x3463D8B0, 0xD85860FE, 0xFCDF0D57, 0xA2DBC09E, + 0x44C728C1, 0xD8FEE73E, 0xB1E6B4A5, 0xD0CC95CD, 0xCCEF186F, 0x70AC5D98, 0x57D21267, 0x8543F446, + 0x15C8EAA9, 0x0DD357D4, 0x4CE9C090, 0x4E91FADF, 0xE0658E27, 0xFF7AA5D6, 0x176ED723, 0x70D009CB, + 0x416ADBAA, 0x1C45865D, 0x105F3A0E, 0x14730450, 0xD0FA1AC9, 0xB76F268C, 0x7B075289, 0xA9455796, + 0x65E02F3E, 0xB74521F2, 0xF6CAA6C7, 0x94ABFDAD, 0x1E6D1087, 0xC25A9257, 0x87FAF9A4, 0x5184A0FA, + 0x240023D7, 0x7AE0ED45, 0x06E0A838, 0xBB018F31, 0x0FA836D5, 0x09CF6AEC, 0x9BC4F2B2, 0xAE92D5BA, + 0xE724036E, 0xE5606DDE, 0x631448F9, 0xFD59B782, 0xF17052E4, 0x66EA4C50, 0xF72C1768, 0x5C24ECEC, + 0x6B01B118, 0x89F8A3AB, 0x465FF462, 0xC3896A00, 0xFEC06004, 0xE2DFC70C, 0x3ACF338F, 0x1552E9D0, + 0x9F699B77, 0x60AC6D29, 0xBF47FD38, 0x826B0CA8, 0x0515A7AC, 0x1380A222, 0x7D054EA0, 0x3D1BCEC0, + 0x21AB6CF3, 0xA889E915, 0xF09D9756, 0x08BA519A, 0xCFFB6BD3, 0x7D5EF4F9, 0x34A0E942, 0x8569A327, + 0xFDDC5269, 0x60D8D543, 0x88B34B88, 0x50DEAA10, 0xD0563E1F, 0x80CD122B, 0xDC11607F, 0xCD9D7E05, + 0xC0F3510E, 0x414A7545, 0xB8211557, 0x103E6F53, 0x08A47672, 0x04D9C391, 0x3281F25C, 0x7526AAD2, + 0x3C89B43B, 0xBA767E59, 0xA2788EAC, 0x5EF9DF3D, 0x8F72BBE6, 0xC4B52A2B, 0xE81A80E9, 0xCD6B24D5, + 0x4F934751, 0xA3FCC2B5, 0x1C4FB12A, 0x7C363E45, 0x237CB63A, 0x1F26D6FD, 0xAAF3FE61, 0x48D3B3A8, + 0xA2A77A81, 0xADCF4AB4, 0xDF94F9B4, 0x465EA838, 0xCE4BA15C, 0x75826F5A, 0xD537E32C, 0x85F8FECD, + 0xD07CAB1C, 0x34F91310, 0xC40B36CA, 0xCCE0297E, 0xFB276610, 0x67DF82EC, 0x8BB58FAA, 0xCEA3BDC2, + 0x02B21D68, 0xCC1F8A6C, 0xF902AF4E, 0x271828EA, 0x9028298A, 0xB5BF0156, 0x5A3B3188, 0x6CCB6806, + 0xE2F3A4A2, 0x3B776BB9, 0x66D01790, 0x133F2414, 0x1445FE7D, 0x5CC79E5B, 0xB95FD30F, 0x50971FC5, + 0x8D6AFECA, 0x3FB2427C, 0xC1A980EC, 0x54C9F2AF, 0x0F509DF3, 0x1B950AA4, 0x1E5B1596, 0x93E974B9, + 0x71D51A0F, 0xC973F4DD, 0x79BF62A6, 0xC72F58F9, 0xCAD478D6, 0x0F7C36C7, 0x05D08481, 0x43958D67, + 0x93F11E1A, 0xDCDDCE62, 0xB457AC62, 0xD4A98268, 0xA793471A, 0x7AB637E0, 0x1B9BA86C, 0x456B5EF7, + 0xD2E75711, 0xF95E6BCD, 0xD3043467, 0x056F1621, 0x21D58D4E, 0x0C9EF57E, 0x96B645B1, 0xF5A80340, + 0xBD9A4C7A, 0x4D94A305, 0x59D0F9B4, 0x113F56F9, 0xE0A948B5, 0xBF982299, 0xA05D1EA1, 0xE9C50F8A, + 0xAF6B8F04, 0x6B05485E, 0x17DD458A, 0xFB819464, 0x5CE2F61F, 0xECF95F48, 0xA26CFBA2, 0x6A0FD00F, + 0xA7A2CB0F, 0xFE10768D, 0x4A258743, 0xBBF2C41A, 0xF519DBEE, 0x9DA676B6, 0xE89449C9, 0x3E13EBE5, + 0x4A4A42A5, 0x42663182, 0xDAAF85AB, 0xCC671BCB, 0x217491EE, 0xDCC9B6F2, 0xE1A3A7EA, 0x7B13F2F9, + 0xCFFCBC9F, 0x3D8FF387, 0x71ABA888, 0x2D3FE4C1, 0x081AB3DC, 0xBF21BA4B, 0x4ACE0F00, 0x6F5AB592, + 0xD328F08C, 0x542388E9, 0xE7A4157A, 0xE8532856, 0xE8DC528E, 0x3F2356AE, 0x76867882, 0xEC11E6D0, + 0x0C2DD257, 0x40A7C558, 0x354F885C, 0x2A2E0757, 0x6C0A6D95, 0xE0C23A09, 0xD1F32FF7, 0x7E27842E, + 0x3CDFD97E, 0x2F6807FB, 0xDBED07BD, 0xA039645B, 0x324B0955, 0x73620D27, 0x0C47D75F, 0x511BD37A, + 0xE80C4C44, 0xA3D77AFE, 0x058B503D, 0x391AC187, 0xD7425F0B, 0x93876765, 0x10CADF4C, 0xC4F3539A, + 0xF17B776C, 0x017BDEFA, 0x74F4651F, 0x65FBC1E5, 0xF55CC6B6, 0x1752401A, 0x85FB6434, 0xB8FD0F06, + 0x4D0D80FF, 0x0DD8438D, 0x1C5844B7, 0x31ECF66B, 0xF8A8B528, 0xA9BE0373, 0xC401C7FC, 0x3BA1FFF4, + 0x63946BBD, 0x82514893, 0x9CE303D6, 0x51EA2484, 0x054CACA2, 0x3F812B32, 0x0F3C603F, 0x4B3D86B6, + 0xD33F5950, 0x3340BFC0, 0x47CEB79D, 0x1CAB5D3C, 0x74897EB5, 0x1C320D6D, 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0x8A6D4936, 0x4759E38B, 0xACFC5255, + 0x0C9D02B7, 0x1B52A34E, 0x3B0A60A1, 0x1DB4E220, 0x23DCD523, 0xEA42AD41, 0x9B3CB86B, 0x6C503824, + 0x41DC835D, 0x22A311A5, 0x7B7AD03E, 0x6AFA5972, 0x3E506D92, 0x04FED79C, 0xCE801EEF, 0x7BA17C52, + 0x3AFFBB6A, 0x96A23185, 0x74316B7B, 0x11D330F6, 0x8484E528, 0xB643261D, 0xCC076540, 0x9116E092, + 0x4B6D5634, 0xC9532DCB, 0x0CBBB981, 0xE8D8E41F, 0x7573408A, 0x684F202D, 0x9A92649E, 0xF2CF0C39, + 0xF6C540AE, 0x29368636, 0x6A5BD7FB, 0x5044B256, 0x35AEC028, 0x8C12E363, 0xE0A2FE6D, 0x9E8EB149, + 0x2ED1CF45, 0x54A9880B, 0x4E295354, 0x83730F2E, 0x279AD027, 0x7051921F, 0xC4E219AC, 0x8B540A9B, + 0x947E9DF5, 0x28B61847, 0xC4E32434, 0xF9227028, 0x3D489511, 0xD5A41195, 0xA03EE1BD, 0xD761441F, + 0x402F7502, 0x5AB68BEF, 0x5555B735, 0x5918623F, 0x983735E9, 0xE332F1B8, 0x48D83C28, 0x81318EE2, + 0xABB8AA53, 0x01F0C3CE, 0xB4291A62, 0x89344F27, 0x5FDEEA6C, 0xE6D22F86, 0x9988C7DC, 0x051A1432, + 0xE11867BC, 0xEFA49EEF, 0x48AADD79, 0x33633BF3, 0xA56B57B4, 0xA253AB9F, 0x7FC8340A, 0xAB73B132, + 0xF1DFB6CC, 0xC5F02EDA, 0x426782CD, 0xF6648D35, 0xB4AB88A0, 0x9BA7B785, 0x67C03341, 0x22612D33, + 0xD32ED490, 0xAAA56F6A, 0x37ECD8CD, 0x518E8140, 0x7390301C, 0xB33A9E62, 0x244220D4, 0xD88AE216, + 0x9752DEEA, 0xB8A22F50, 0xBFB221CB, 0xDB4D57A0, 0x02D39A0D, 0x8C311F00, 0x1192748C, 0xB9505446, + 0x469C1E7B, 0x3AEFF9A6, 0x7CD5ABE8, 0xD849E5F5, 0x1E2FB30A, 0x18879BD8, 0x6DDD966E, 0xC9BD4B8F, + 0xCEEBCCD9, 0x0D881346, 0x20 + +basegraph= +2 + +z_c= +384 + +n_cb= +19200 + +q_m= +2 + +n_filler= +56 + +e = +36936 + +rv_index = +0 + +code_block_mode = +1 + +op_flags = +RTE_BBDEV_LDPC_RATE_MATCH, RTE_BBDEV_LDPC_CRC_24B_ATTACH + +expected_status = +OK From patchwork Mon Jun 24 02:52:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 55231 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A23FF1BF94; Mon, 24 Jun 2019 04:53:27 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id BCA1C1BF0A for ; Mon, 24 Jun 2019 04:53:04 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jun 2019 19:53:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,410,1557212400"; d="scan'208";a="183991212" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga004.fm.intel.com with ESMTP; 23 Jun 2019 19:53:00 -0700 From: Nicolas Chautru To: akhil.goyal@nxp.com, dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@intel.com, amr.mokhtar@intel.com, Nicolas Chautru Date: Sun, 23 Jun 2019 19:52:56 -0700 Message-Id: <1561344776-43990-11-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> References: <1561136352-32198-2-git-send-email-nicolas.chautru@intel.com> <1561344776-43990-1-git-send-email-nicolas.chautru@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 10/10] doc: announce bbdev changes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Update of the release notes for BBDEV features add and extension of ABI in previous commit. Signed-off-by: Nicolas Chautru Acked-by: Amr Mokhtar --- doc/guides/rel_notes/release_19_08.rst | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst index 8c3932d..35d3a09 100644 --- a/doc/guides/rel_notes/release_19_08.rst +++ b/doc/guides/rel_notes/release_19_08.rst @@ -88,6 +88,19 @@ New Features * Added multi-queue support to allow one af_xdp vdev with multiple netdev queues +* **Added a FPGA_LTE_FEC bbdev PMD.** + + Added the new ``fpga_lte_fec`` bbdev driver for the Intel® FPGA PAC + (Programmable Acceleration Card) N3000. See the + :doc:`../bbdevs/fpga_lte_fec` BBDEV guide for more details on this new driver. + +* **Updated TURBO_SW bbdev PMD.** + + Updated the ``turbo_sw`` bbdev driver with changes including: + + * Added option to build the driver with or without dependency of external + SDK libraries. + * Added support for 5GNR encode/decode operations. Removed Items ------------- @@ -140,6 +153,8 @@ ABI Changes Also, make sure to start the actual text at the margin. ========================================================= +* bbdev: New parameters added to support 5GNR operations. + Shared Library Versions -----------------------