From patchwork Wed Jun 12 07:50:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 54730 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6B9161D162; Wed, 12 Jun 2019 09:52:30 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 856D91D15A for ; Wed, 12 Jun 2019 09:52:26 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2019 00:52:24 -0700 X-ExtLoop1: 1 Received: from map1.sh.intel.com ([10.67.111.124]) by orsmga003.jf.intel.com with ESMTP; 12 Jun 2019 00:52:24 -0700 From: Qiming Yang To: dev@dpdk.org Cc: wei zhao Date: Wed, 12 Jun 2019 15:50:27 +0800 Message-Id: <20190612075029.109914-2-qiming.yang@intel.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190612075029.109914-1-qiming.yang@intel.com> References: <1559552722-8970-1-git-send-email-qiming.yang@intel.com> <20190612075029.109914-1-qiming.yang@intel.com> Subject: [dpdk-dev] [PATCH v2 1/3] net/ice: enable switch filter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: wei zhao The patch enables the backend of rte_flow. It transfers rte_flow_xxx to device specific data structure and configures packet process engine's binary classifier (switch) properly. Signed-off-by: Wei Zhao --- drivers/net/ice/Makefile | 1 + drivers/net/ice/ice_ethdev.h | 6 + drivers/net/ice/ice_switch_filter.c | 502 ++++++++++++++++++++++++++++++++++++ drivers/net/ice/ice_switch_filter.h | 28 ++ drivers/net/ice/meson.build | 3 +- 5 files changed, 539 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ice/ice_switch_filter.c create mode 100644 drivers/net/ice/ice_switch_filter.h diff --git a/drivers/net/ice/Makefile b/drivers/net/ice/Makefile index 0e5c55e..b10d826 100644 --- a/drivers/net/ice/Makefile +++ b/drivers/net/ice/Makefile @@ -60,6 +60,7 @@ ifeq ($(CONFIG_RTE_ARCH_X86), y) SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice_rxtx_vec_sse.c endif +SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice_switch_filter.c ifeq ($(findstring RTE_MACHINE_CPUFLAG_AVX2,$(CFLAGS)),RTE_MACHINE_CPUFLAG_AVX2) CC_AVX2_SUPPORT=1 else diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index 1385afa..67a358a 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -234,6 +234,12 @@ struct ice_vsi { bool offset_loaded; }; +/* Struct to store flow created. */ +struct rte_flow { + TAILQ_ENTRY(rte_flow) node; +void *rule; +}; + struct ice_pf { struct ice_adapter *adapter; /* The adapter this PF associate to */ struct ice_vsi *main_vsi; /* pointer to main VSI structure */ diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c new file mode 100644 index 0000000..e679675 --- /dev/null +++ b/drivers/net/ice/ice_switch_filter.c @@ -0,0 +1,502 @@ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ice_logs.h" +#include "base/ice_type.h" +#include "ice_switch_filter.h" + +static int +ice_parse_switch_filter( + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow_error *error, + struct ice_adv_rule_info *rule_info, + struct ice_adv_lkup_elem **lkup_list, + uint16_t *lkups_num) +{ + const struct rte_flow_item *item = pattern; + enum rte_flow_item_type item_type; + const struct rte_flow_item_eth *eth_spec, *eth_mask; + const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask; + const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask; + const struct rte_flow_item_tcp *tcp_spec, *tcp_mask; + const struct rte_flow_item_udp *udp_spec, *udp_mask; + const struct rte_flow_item_sctp *sctp_spec, *sctp_mask; + const struct rte_flow_item_nvgre *nvgre_spec, *nvgre_mask; + const struct rte_flow_item_vxlan *vxlan_spec, *vxlan_mask; + struct ice_adv_lkup_elem *list; + uint16_t i, j, t = 0; + uint16_t item_num = 0; + enum ice_sw_tunnel_type tun_type = ICE_NON_TUN; + + for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { + if (item->type == RTE_FLOW_ITEM_TYPE_ETH || + item->type == RTE_FLOW_ITEM_TYPE_IPV4 || + item->type == RTE_FLOW_ITEM_TYPE_IPV6 || + item->type == RTE_FLOW_ITEM_TYPE_UDP || + item->type == RTE_FLOW_ITEM_TYPE_TCP || + item->type == RTE_FLOW_ITEM_TYPE_SCTP || + item->type == RTE_FLOW_ITEM_TYPE_VXLAN || + item->type == RTE_FLOW_ITEM_TYPE_NVGRE) + item_num++; + } + + list = rte_zmalloc(NULL, item_num * sizeof(*list), 0); + if (!list) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, actions, + "no memory malloc"); + goto out; + } + *lkup_list = list; + + for (item = pattern, i = 0; item->type != + RTE_FLOW_ITEM_TYPE_END; item++, i++) { + item_type = item->type; + + switch (item_type) { + case RTE_FLOW_ITEM_TYPE_ETH: + eth_spec = item->spec; + eth_mask = item->mask; + if (eth_spec && eth_mask) { + list[t].type = (tun_type == ICE_NON_TUN) ? + ICE_MAC_OFOS : ICE_MAC_IL; + for (j = 0; j < RTE_ETHER_ADDR_LEN; j++) { + if (eth_mask->src.addr_bytes[j] == + UINT8_MAX) { + list[t].h_u.eth_hdr. + src_addr[j] = + eth_spec->src.addr_bytes[j]; + list[t].m_u.eth_hdr. + src_addr[j] = + eth_mask->src.addr_bytes[j]; + } + if (eth_mask->dst.addr_bytes[j] == + UINT8_MAX) { + list[t].h_u.eth_hdr. + dst_addr[j] = + eth_spec->dst.addr_bytes[j]; + list[t].m_u.eth_hdr. + dst_addr[j] = + eth_mask->dst.addr_bytes[j]; + } + } + if (eth_mask->type == UINT16_MAX) { + list[t].h_u.eth_hdr.ethtype_id = + rte_be_to_cpu_16(eth_spec->type); + list[t].m_u.eth_hdr.ethtype_id = + UINT16_MAX; + } + t++; + } else if (!eth_spec && !eth_mask) { + list[t].type = (tun_type == ICE_NON_TUN) ? + ICE_MAC_OFOS : ICE_MAC_IL; + } + break; + + case RTE_FLOW_ITEM_TYPE_IPV4: + ipv4_spec = item->spec; + ipv4_mask = item->mask; + if (ipv4_spec && ipv4_mask) { + list[t].type = (tun_type == ICE_NON_TUN) ? + ICE_IPV4_OFOS : ICE_IPV4_IL; + if (ipv4_mask->hdr.src_addr == UINT32_MAX) { + list[t].h_u.ipv4_hdr.src_addr = + ipv4_spec->hdr.src_addr; + list[t].m_u.ipv4_hdr.src_addr = + UINT32_MAX; + } + if (ipv4_mask->hdr.dst_addr == UINT32_MAX) { + list[t].h_u.ipv4_hdr.dst_addr = + ipv4_spec->hdr.dst_addr; + list[t].m_u.ipv4_hdr.dst_addr = + UINT32_MAX; + } + if (ipv4_mask->hdr.time_to_live == UINT8_MAX) { + list[t].h_u.ipv4_hdr.time_to_live = + ipv4_spec->hdr.time_to_live; + list[t].m_u.ipv4_hdr.time_to_live = + UINT8_MAX; + } + if (ipv4_mask->hdr.next_proto_id == UINT8_MAX) { + list[t].h_u.ipv4_hdr.protocol = + ipv4_spec->hdr.next_proto_id; + list[t].m_u.ipv4_hdr.protocol = + UINT8_MAX; + } + if (ipv4_mask->hdr.type_of_service == + UINT8_MAX) { + list[t].h_u.ipv4_hdr.tos = + ipv4_spec->hdr.type_of_service; + list[t].m_u.ipv4_hdr.tos = UINT8_MAX; + } + t++; + } else if (!ipv4_spec && !ipv4_mask) { + list[t].type = (tun_type == ICE_NON_TUN) ? + ICE_IPV4_OFOS : ICE_IPV4_IL; + } + break; + + case RTE_FLOW_ITEM_TYPE_IPV6: + ipv6_spec = item->spec; + ipv6_mask = item->mask; + if (ipv6_spec && ipv6_mask) { + list[t].type = (tun_type == ICE_NON_TUN) ? + ICE_IPV6_OFOS : ICE_IPV6_IL; + for (j = 0; j < ICE_IPV6_ADDR_LENGTH; j++) { + if (ipv6_mask->hdr.src_addr[j] == + UINT8_MAX) { + list[t].h_u.ice_ipv6_ofos_hdr. + src_addr[j] = + ipv6_spec->hdr.src_addr[j]; + list[t].m_u.ice_ipv6_ofos_hdr. + src_addr[j] = + ipv6_mask->hdr.src_addr[j]; + } + if (ipv6_mask->hdr.dst_addr[j] == + UINT8_MAX) { + list[t].h_u.ice_ipv6_ofos_hdr. + dst_addr[j] = + ipv6_spec->hdr.dst_addr[j]; + list[t].m_u.ice_ipv6_ofos_hdr. + dst_addr[j] = + ipv6_mask->hdr.dst_addr[j]; + } + } + if (ipv6_mask->hdr.proto == UINT8_MAX) { + list[t].h_u.ice_ipv6_ofos_hdr.next_hdr = + ipv6_spec->hdr.proto; + list[t].m_u.ice_ipv6_ofos_hdr.next_hdr = + UINT8_MAX; + } + if (ipv6_mask->hdr.hop_limits == UINT8_MAX) { + list[t].h_u.ice_ipv6_ofos_hdr. + hop_limit = ipv6_spec->hdr.hop_limits; + list[t].m_u.ice_ipv6_ofos_hdr. + hop_limit = UINT8_MAX; + } + t++; + } else if (!ipv6_spec && !ipv6_mask) { + list[t].type = (tun_type == ICE_NON_TUN) ? + ICE_IPV4_OFOS : ICE_IPV4_IL; + } + break; + + case RTE_FLOW_ITEM_TYPE_UDP: + udp_spec = item->spec; + udp_mask = item->mask; + if (udp_spec && udp_mask) { + list[t].type = ICE_UDP_ILOS; + if (udp_mask->hdr.src_port == UINT16_MAX) { + list[t].h_u.l4_hdr.src_port = + udp_spec->hdr.src_port; + list[t].m_u.l4_hdr.src_port = + udp_mask->hdr.src_port; + } + if (udp_mask->hdr.dst_port == UINT16_MAX) { + list[t].h_u.l4_hdr.dst_port = + udp_spec->hdr.dst_port; + list[t].m_u.l4_hdr.dst_port = + udp_mask->hdr.dst_port; + } + t++; + } else if (!udp_spec && !udp_mask) { + list[t].type = ICE_UDP_ILOS; + } + break; + + case RTE_FLOW_ITEM_TYPE_TCP: + tcp_spec = item->spec; + tcp_mask = item->mask; + if (tcp_spec && tcp_mask) { + list[t].type = ICE_TCP_IL; + if (tcp_mask->hdr.src_port == UINT16_MAX) { + list[t].h_u.l4_hdr.src_port = + tcp_spec->hdr.src_port; + list[t].m_u.l4_hdr.src_port = + tcp_mask->hdr.src_port; + } + if (tcp_mask->hdr.dst_port == UINT16_MAX) { + list[t].h_u.l4_hdr.dst_port = + tcp_spec->hdr.dst_port; + list[t].m_u.l4_hdr.dst_port = + tcp_mask->hdr.dst_port; + } + t++; + } else if (!tcp_spec && !tcp_mask) { + list[t].type = ICE_TCP_IL; + } + break; + + case RTE_FLOW_ITEM_TYPE_SCTP: + sctp_spec = item->spec; + sctp_mask = item->mask; + if (sctp_spec && sctp_mask) { + list[t].type = ICE_SCTP_IL; + if (sctp_mask->hdr.src_port == UINT16_MAX) { + list[t].h_u.sctp_hdr.src_port = + sctp_spec->hdr.src_port; + list[t].m_u.sctp_hdr.src_port = + sctp_mask->hdr.src_port; + } + if (sctp_mask->hdr.dst_port == UINT16_MAX) { + list[t].h_u.sctp_hdr.dst_port = + sctp_spec->hdr.dst_port; + list[t].m_u.sctp_hdr.dst_port = + sctp_mask->hdr.dst_port; + } + t++; + } else if (!sctp_spec && !sctp_mask) { + list[t].type = ICE_SCTP_IL; + } + break; + + case RTE_FLOW_ITEM_TYPE_VXLAN: + vxlan_spec = item->spec; + vxlan_mask = item->mask; + tun_type = ICE_SW_TUN_VXLAN; + if (vxlan_spec && vxlan_mask) { + list[t].type = ICE_VXLAN; + if (vxlan_mask->vni[0] == UINT8_MAX && + vxlan_mask->vni[1] == UINT8_MAX && + vxlan_mask->vni[2] == UINT8_MAX) { + list[t].h_u.tnl_hdr.vni = + (vxlan_spec->vni[1] << 8) | + vxlan_spec->vni[0]; + list[t].m_u.tnl_hdr.vni = + UINT16_MAX; + } + t++; + } else if (!vxlan_spec && !vxlan_mask) { + list[t].type = ICE_VXLAN; + } + break; + + case RTE_FLOW_ITEM_TYPE_NVGRE: + nvgre_spec = item->spec; + nvgre_mask = item->mask; + tun_type = ICE_SW_TUN_NVGRE; + if (nvgre_spec && nvgre_mask) { + list[t].type = ICE_NVGRE; + if (nvgre_mask->tni[0] == UINT8_MAX && + nvgre_mask->tni[1] == UINT8_MAX && + nvgre_mask->tni[2] == UINT8_MAX) { + list[t].h_u.nvgre_hdr.tni = + (nvgre_spec->tni[1] << 8) | + nvgre_spec->tni[0]; + list[t].m_u.nvgre_hdr.tni = + UINT16_MAX; + } + t++; + } else if (!nvgre_spec && !nvgre_mask) { + list[t].type = ICE_NVGRE; + } + break; + + case RTE_FLOW_ITEM_TYPE_VOID: + case RTE_FLOW_ITEM_TYPE_END: + break; + + default: + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, actions, + "Invalid pattern item."); + goto out; + } + } + + rule_info->tun_type = tun_type; + *lkups_num = t; + + return 0; +out: + return -rte_errno; +} + +/* By now ice switch filter action code implement only +* supports QUEUE or DROP. +*/ +static int +ice_parse_switch_action(struct ice_pf *pf, + const struct rte_flow_action *actions, + struct rte_flow_error *error, + struct ice_adv_rule_info *rule_info) +{ + struct ice_hw *hw = ICE_PF_TO_HW(pf); + struct ice_vsi *vsi = pf->main_vsi; + const struct rte_flow_action *act; + const struct rte_flow_action_queue *act_q; + uint16_t base_queue, index = 0; + uint32_t reg; + + /* Check if the first non-void action is QUEUE or DROP. */ + NEXT_ITEM_OF_ACTION(act, actions, index); + if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE && + act->type != RTE_FLOW_ACTION_TYPE_DROP) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + return -rte_errno; + } + reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC); + if (reg & PFLAN_RX_QALLOC_VALID_M) { + base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M; + } else { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Invalid queue register"); + return -rte_errno; + } + if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) { + act_q = act->conf; + rule_info->sw_act.fltr_act = ICE_FWD_TO_Q; + rule_info->sw_act.fwd_id.q_id = base_queue + act_q->index; + if (act_q->index >= pf->dev_data->nb_rx_queues) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Invalid queue ID for" + " switch filter."); + return -rte_errno; + } + } else { + rule_info->sw_act.fltr_act = ICE_DROP_PACKET; + } + + rule_info->sw_act.vsi_handle = vsi->idx; + rule_info->rx = 1; + rule_info->sw_act.src = vsi->idx; + + /* Check if the next non-void item is END */ + index++; + NEXT_ITEM_OF_ACTION(act, actions, index); + if (act->type != RTE_FLOW_ACTION_TYPE_END) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + return -rte_errno; + } + + return 0; +} + +static int +ice_switch_rule_set(struct ice_pf *pf, + struct ice_adv_lkup_elem *list, + uint16_t lkups_cnt, + struct ice_adv_rule_info *rule_info, + struct rte_flow *flow) +{ + struct ice_hw *hw = ICE_PF_TO_HW(pf); + int ret; + struct ice_rule_query_data rule_added = {0}; + struct ice_rule_query_data *filter_ptr; + + if (lkups_cnt > ICE_MAX_CHAIN_WORDS) { + PMD_DRV_LOG(ERR, "item number too large for rule"); + return -ENOTSUP; + } + if (!list) { + PMD_DRV_LOG(ERR, "lookup list should not be NULL"); + return -ENOTSUP; + } + + ret = ice_add_adv_rule(hw, list, lkups_cnt, rule_info, &rule_added); + + if (!ret) { + filter_ptr = rte_zmalloc("ice_switch_filter", + sizeof(struct ice_rule_query_data), 0); + if (!filter_ptr) { + PMD_DRV_LOG(ERR, "failed to allocate memory"); + return -EINVAL; + } + flow->rule = filter_ptr; + rte_memcpy(filter_ptr, + &rule_added, + sizeof(struct ice_rule_query_data)); + } + + return ret; +} + +int +ice_create_switch_filter(struct ice_pf *pf, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow *flow, + struct rte_flow_error *error) +{ + int ret = 0; + struct ice_adv_rule_info rule_info = {0}; + struct ice_adv_lkup_elem *list = NULL; + uint16_t lkups_num = 0; + + ret = ice_parse_switch_filter(pattern, actions, error, + &rule_info, &list, &lkups_num); + if (ret) + goto out; + + ret = ice_parse_switch_action(pf, actions, error, &rule_info); + if (ret) + goto out; + + ret = ice_switch_rule_set(pf, list, lkups_num, &rule_info, flow); + if (ret) + goto out; + + rte_free(list); + return 0; + +out: + rte_free(list); + + return -rte_errno; +} + +int +ice_destroy_switch_filter(struct ice_pf *pf, + struct rte_flow *flow) +{ + struct ice_hw *hw = ICE_PF_TO_HW(pf); + int ret; + struct ice_rule_query_data *filter_ptr; + struct ice_rule_query_data rule_added; + + filter_ptr = (struct ice_rule_query_data *) + flow->rule; + rte_memcpy(&rule_added, filter_ptr, + sizeof(struct ice_rule_query_data)); + + if (!filter_ptr) { + PMD_DRV_LOG(ERR, "no such flow" + " create by switch filter"); + return -EINVAL; + } + + ret = ice_rem_adv_rule_by_id(hw, &rule_added); + + rte_free(filter_ptr); + + return ret; +} + +void +ice_free_switch_filter_rule(void *rule) +{ + struct ice_rule_query_data *filter_ptr; + + filter_ptr = (struct ice_rule_query_data *)rule; + + rte_free(filter_ptr); +} diff --git a/drivers/net/ice/ice_switch_filter.h b/drivers/net/ice/ice_switch_filter.h new file mode 100644 index 0000000..957d0d1 --- /dev/null +++ b/drivers/net/ice/ice_switch_filter.h @@ -0,0 +1,28 @@ +#ifndef _ICE_SWITCH_FILTER_H_ +#define _ICE_SWITCH_FILTER_H_ + +#include "base/ice_switch.h" +#include "base/ice_type.h" +#include "ice_ethdev.h" + +#define NEXT_ITEM_OF_ACTION(act, actions, index) \ + do { \ + act = actions + index; \ + while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ + index++; \ + act = actions + index; \ + } \ + } while (0) + +int +ice_create_switch_filter(struct ice_pf *pf, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow *flow, + struct rte_flow_error *error); +int +ice_destroy_switch_filter(struct ice_pf *pf, + struct rte_flow *flow); +void +ice_free_switch_filter_rule(void *rule); +#endif /* _ICE_SWITCH_FILTER_H_ */ diff --git a/drivers/net/ice/meson.build b/drivers/net/ice/meson.build index 2bec688..8697676 100644 --- a/drivers/net/ice/meson.build +++ b/drivers/net/ice/meson.build @@ -6,7 +6,8 @@ objs = [base_objs] sources = files( 'ice_ethdev.c', - 'ice_rxtx.c' + 'ice_rxtx.c', + 'ice_switch_filter.c' ) deps += ['hash'] From patchwork Wed Jun 12 07:50:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 54731 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 02EE31D16A; Wed, 12 Jun 2019 09:52:36 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 657C81D15A for ; Wed, 12 Jun 2019 09:52:27 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2019 00:52:26 -0700 X-ExtLoop1: 1 Received: from map1.sh.intel.com ([10.67.111.124]) by orsmga003.jf.intel.com with ESMTP; 12 Jun 2019 00:52:25 -0700 From: Qiming Yang To: dev@dpdk.org Cc: Qiming Yang Date: Wed, 12 Jun 2019 15:50:28 +0800 Message-Id: <20190612075029.109914-3-qiming.yang@intel.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190612075029.109914-1-qiming.yang@intel.com> References: <1559552722-8970-1-git-send-email-qiming.yang@intel.com> <20190612075029.109914-1-qiming.yang@intel.com> Subject: [dpdk-dev] [PATCH v2 2/3] net/ice: add generic flow API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds ice_flow_create, ice_flow_destroy, ice_flow_flush and ice_flow_validate support, these are going to used to handle all the generic filters. Signed-off-by: Qiming Yang --- drivers/net/ice/Makefile | 1 + drivers/net/ice/ice_ethdev.c | 44 +++ drivers/net/ice/ice_ethdev.h | 7 +- drivers/net/ice/ice_generic_flow.c | 567 +++++++++++++++++++++++++++++++++++++ drivers/net/ice/ice_generic_flow.h | 404 ++++++++++++++++++++++++++ 5 files changed, 1022 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ice/ice_generic_flow.c create mode 100644 drivers/net/ice/ice_generic_flow.h diff --git a/drivers/net/ice/Makefile b/drivers/net/ice/Makefile index b10d826..32abeb6 100644 --- a/drivers/net/ice/Makefile +++ b/drivers/net/ice/Makefile @@ -79,5 +79,6 @@ endif ifeq ($(CC_AVX2_SUPPORT), 1) SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice_rxtx_vec_avx2.c endif +SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice_generic_flow.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index bdbceb4..cf6bb1d 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -15,6 +15,7 @@ #include "base/ice_dcb.h" #include "ice_ethdev.h" #include "ice_rxtx.h" +#include "ice_switch_filter.h" #define ICE_MAX_QP_NUM "max_queue_pair_num" #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100 @@ -83,6 +84,10 @@ static int ice_xstats_get(struct rte_eth_dev *dev, static int ice_xstats_get_names(struct rte_eth_dev *dev, struct rte_eth_xstat_name *xstats_names, unsigned int limit); +static int ice_dev_filter_ctrl(struct rte_eth_dev *dev, + enum rte_filter_type filter_type, + enum rte_filter_op filter_op, + void *arg); static const struct rte_pci_id pci_id_ice_map[] = { { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, @@ -141,6 +146,7 @@ static const struct eth_dev_ops ice_eth_dev_ops = { .xstats_get = ice_xstats_get, .xstats_get_names = ice_xstats_get_names, .xstats_reset = ice_stats_reset, + .filter_ctrl = ice_dev_filter_ctrl, }; /* store statistics names and its offset in stats structure */ @@ -1460,6 +1466,8 @@ ice_dev_init(struct rte_eth_dev *dev) /* enable uio intr after callback register */ rte_intr_enable(intr_handle); + TAILQ_INIT(&pf->flow_list); + return 0; err_pf_setup: @@ -1602,6 +1610,8 @@ ice_dev_uninit(struct rte_eth_dev *dev) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct rte_flow *p_flow; ice_dev_close(dev); @@ -1619,6 +1629,13 @@ ice_dev_uninit(struct rte_eth_dev *dev) rte_intr_callback_unregister(intr_handle, ice_interrupt_handler, dev); + /* Remove all flows */ + while ((p_flow = TAILQ_FIRST(&pf->flow_list))) { + TAILQ_REMOVE(&pf->flow_list, p_flow, node); + ice_free_switch_filter_rule(p_flow->rule); + rte_free(p_flow); + } + return 0; } @@ -3603,6 +3620,33 @@ static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, } static int +ice_dev_filter_ctrl(struct rte_eth_dev *dev, + enum rte_filter_type filter_type, + enum rte_filter_op filter_op, + void *arg) +{ + int ret = 0; + + if (!dev) + return -EINVAL; + + switch (filter_type) { + case RTE_ETH_FILTER_GENERIC: + if (filter_op != RTE_ETH_FILTER_GET) + return -EINVAL; + *(const void **)arg = &ice_flow_ops; + break; + default: + PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", + filter_type); + ret = -EINVAL; + break; + } + + return ret; +} + +static int ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) { diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index 67a358a..0905ff9 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -234,12 +234,16 @@ struct ice_vsi { bool offset_loaded; }; +extern const struct rte_flow_ops ice_flow_ops; + /* Struct to store flow created. */ struct rte_flow { TAILQ_ENTRY(rte_flow) node; -void *rule; + void *rule; }; +TAILQ_HEAD(ice_flow_list, rte_flow); + struct ice_pf { struct ice_adapter *adapter; /* The adapter this PF associate to */ struct ice_vsi *main_vsi; /* pointer to main VSI structure */ @@ -265,6 +269,7 @@ struct ice_pf { struct ice_eth_stats internal_stats; bool offset_loaded; bool adapter_stopped; + struct ice_flow_list flow_list; }; /** diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c new file mode 100644 index 0000000..4fb50b2 --- /dev/null +++ b/drivers/net/ice/ice_generic_flow.c @@ -0,0 +1,567 @@ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "ice_ethdev.h" +#include "ice_generic_flow.h" +#include "ice_switch_filter.h" + +static int ice_flow_validate(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow_error *error); +static struct rte_flow *ice_flow_create(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow_error *error); +static int ice_flow_destroy(struct rte_eth_dev *dev, + struct rte_flow *flow, + struct rte_flow_error *error); +static int ice_flow_flush(struct rte_eth_dev *dev, + struct rte_flow_error *error); + +const struct rte_flow_ops ice_flow_ops = { + .validate = ice_flow_validate, + .create = ice_flow_create, + .destroy = ice_flow_destroy, + .flush = ice_flow_flush, +}; + +static int +ice_flow_valid_attr(const struct rte_flow_attr *attr, + struct rte_flow_error *error) +{ + /* Must be input direction */ + if (!attr->ingress) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, + attr, "Only support ingress."); + return -rte_errno; + } + + /* Not supported */ + if (attr->egress) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, + attr, "Not support egress."); + return -rte_errno; + } + + /* Not supported */ + if (attr->priority) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, + attr, "Not support priority."); + return -rte_errno; + } + + /* Not supported */ + if (attr->group) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_GROUP, + attr, "Not support group."); + return -rte_errno; + } + + return 0; +} + +/* Check if the pattern matches a supported item type array */ +static bool +ice_match_pattern(enum rte_flow_item_type *item_array, + const struct rte_flow_item *pattern) +{ + const struct rte_flow_item *item = pattern; + + while ((*item_array == item->type) && + (*item_array != RTE_FLOW_ITEM_TYPE_END)) { + item_array++; + item++; + } + + return (*item_array == RTE_FLOW_ITEM_TYPE_END && + item->type == RTE_FLOW_ITEM_TYPE_END); +} + +static uint64_t ice_flow_valid_pattern(const struct rte_flow_item pattern[], + struct rte_flow_error *error) +{ + uint16_t i = 0; + uint64_t inset; + + for (; i < RTE_DIM(ice_supported_patterns); i++) + if (ice_match_pattern(ice_supported_patterns[i].items, + pattern)) { + inset = ice_supported_patterns[i].sw_fields; + return inset; + } + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, + pattern, "Unsupported pattern"); + + return 0; +} + +static uint64_t ice_get_flow_field(const struct rte_flow_item pattern[], + struct rte_flow_error *error) +{ + const struct rte_flow_item *item = pattern; + const struct rte_flow_item_eth *eth_spec, *eth_mask; + const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask; + const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask; + const struct rte_flow_item_tcp *tcp_spec, *tcp_mask; + const struct rte_flow_item_udp *udp_spec, *udp_mask; + const struct rte_flow_item_sctp *sctp_spec, *sctp_mask; + const struct rte_flow_item_icmp *icmp_mask; + const struct rte_flow_item_icmp6 *icmp6_mask; + enum rte_flow_item_type item_type; + uint8_t ipv6_addr_mask[16] = { + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + uint64_t input_set = ICE_INSET_NONE; + bool outer_ip = true; + bool outer_l4 = true; + + for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Not support range"); + return 0; + } + item_type = item->type; + switch (item_type) { + case RTE_FLOW_ITEM_TYPE_ETH: + eth_spec = item->spec; + eth_mask = item->mask; + + if (eth_spec && eth_mask) { + if (rte_is_broadcast_ether_addr(ð_mask->src)) + input_set |= ICE_INSET_SMAC; + if (rte_is_broadcast_ether_addr(ð_mask->dst)) + input_set |= ICE_INSET_DMAC; + if (eth_mask->type == RTE_BE16(0xffff)) + input_set |= ICE_INSET_ETHERTYPE; + } + break; + case RTE_FLOW_ITEM_TYPE_IPV4: + ipv4_spec = item->spec; + ipv4_mask = item->mask; + + if (!(ipv4_spec && ipv4_mask)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid IPv4 spec or mask."); + return 0; + } + + /* Check IPv4 mask and update input set */ + if (ipv4_mask->hdr.version_ihl || + ipv4_mask->hdr.total_length || + ipv4_mask->hdr.packet_id || + ipv4_mask->hdr.hdr_checksum) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid IPv4 mask."); + return 0; + } + + if (outer_ip) { + if (ipv4_mask->hdr.src_addr == UINT32_MAX) + input_set |= ICE_INSET_IPV4_SRC; + if (ipv4_mask->hdr.dst_addr == UINT32_MAX) + input_set |= ICE_INSET_IPV4_DST; + if (ipv4_mask->hdr.type_of_service == UINT8_MAX) + input_set |= ICE_INSET_IPV4_TOS; + if (ipv4_mask->hdr.time_to_live == UINT8_MAX) + input_set |= ICE_INSET_IPV4_TTL; + if (ipv4_mask->hdr.fragment_offset == 0) + input_set |= ICE_INSET_IPV4_PROTO; + outer_ip = false; + } else { + if (ipv4_mask->hdr.src_addr == UINT32_MAX) + input_set |= ICE_INSET_TUN_IPV4_SRC; + if (ipv4_mask->hdr.dst_addr == UINT32_MAX) + input_set |= ICE_INSET_TUN_IPV4_DST; + if (ipv4_mask->hdr.time_to_live == UINT8_MAX) + input_set |= ICE_INSET_TUN_IPV4_TTL; + if (ipv4_mask->hdr.next_proto_id == UINT8_MAX) + input_set |= ICE_INSET_TUN_IPV4_PROTO; + } + break; + case RTE_FLOW_ITEM_TYPE_IPV6: + ipv6_spec = item->spec; + ipv6_mask = item->mask; + + if (!(ipv6_spec && ipv6_mask)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Invalid IPv6 spec or mask"); + return 0; + } + + if (ipv6_mask->hdr.payload_len || + ipv6_mask->hdr.vtc_flow) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid IPv6 mask"); + return 0; + } + + if (outer_ip) { + if (!memcmp(ipv6_mask->hdr.src_addr, + ipv6_addr_mask, + RTE_DIM(ipv6_mask->hdr.src_addr))) + input_set |= ICE_INSET_IPV6_SRC; + if (!memcmp(ipv6_mask->hdr.dst_addr, + ipv6_addr_mask, + RTE_DIM(ipv6_mask->hdr.dst_addr))) + input_set |= ICE_INSET_IPV6_DST; + if (ipv6_mask->hdr.proto == UINT8_MAX) + input_set |= ICE_INSET_IPV6_NEXT_HDR; + if (ipv6_mask->hdr.hop_limits == UINT8_MAX) + input_set |= ICE_INSET_IPV6_HOP_LIMIT; + outer_ip = false; + } else { + if (!memcmp(ipv6_mask->hdr.src_addr, + ipv6_addr_mask, + RTE_DIM(ipv6_mask->hdr.src_addr))) + input_set |= ICE_INSET_TUN_IPV6_SRC; + if (!memcmp(ipv6_mask->hdr.dst_addr, + ipv6_addr_mask, + RTE_DIM(ipv6_mask->hdr.dst_addr))) + input_set |= ICE_INSET_TUN_IPV6_DST; + if (ipv6_mask->hdr.proto == UINT8_MAX) + input_set |= ICE_INSET_TUN_IPV6_PROTO; + if (ipv6_mask->hdr.hop_limits == UINT8_MAX) + input_set |= ICE_INSET_TUN_IPV6_TTL; + } + + break; + case RTE_FLOW_ITEM_TYPE_UDP: + udp_spec = item->spec; + udp_mask = item->mask; + + if (!(udp_spec && udp_mask)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Invalid UDP mask"); + return 0; + } + + /* Check UDP mask and update input set*/ + if (udp_mask->hdr.dgram_len || + udp_mask->hdr.dgram_cksum) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid UDP mask"); + return 0; + } + + if (outer_l4) { + if (udp_mask->hdr.src_port == UINT16_MAX) + input_set |= ICE_INSET_SRC_PORT; + if (udp_mask->hdr.dst_port == UINT16_MAX) + input_set |= ICE_INSET_DST_PORT; + outer_l4 = false; + } else { + if (udp_mask->hdr.src_port == UINT16_MAX) + input_set |= ICE_INSET_TUN_SRC_PORT; + if (udp_mask->hdr.dst_port == UINT16_MAX) + input_set |= ICE_INSET_TUN_DST_PORT; + } + + break; + case RTE_FLOW_ITEM_TYPE_TCP: + tcp_spec = item->spec; + tcp_mask = item->mask; + + if (!(tcp_spec && tcp_mask)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Invalid TCP mask"); + return 0; + } + + /* Check TCP mask and update input set */ + if (tcp_mask->hdr.sent_seq || + tcp_mask->hdr.recv_ack || + tcp_mask->hdr.data_off || + tcp_mask->hdr.tcp_flags || + tcp_mask->hdr.rx_win || + tcp_mask->hdr.cksum || + tcp_mask->hdr.tcp_urp) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid TCP mask"); + return 0; + } + + if (outer_l4) { + if (tcp_mask->hdr.src_port == UINT16_MAX) + input_set |= ICE_INSET_SRC_PORT; + if (tcp_mask->hdr.dst_port == UINT16_MAX) + input_set |= ICE_INSET_DST_PORT; + outer_l4 = false; + } else { + if (tcp_mask->hdr.src_port == UINT16_MAX) + input_set |= ICE_INSET_TUN_SRC_PORT; + if (tcp_mask->hdr.dst_port == UINT16_MAX) + input_set |= ICE_INSET_TUN_DST_PORT; + } + + break; + case RTE_FLOW_ITEM_TYPE_SCTP: + sctp_spec = item->spec; + sctp_mask = item->mask; + + if (!(sctp_spec && sctp_mask)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Invalid SCTP mask"); + return 0; + } + + /* Check SCTP mask and update input set */ + if (sctp_mask->hdr.cksum) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid SCTP mask"); + return 0; + } + + if (outer_l4) { + if (sctp_mask->hdr.src_port == UINT16_MAX) + input_set |= ICE_INSET_SRC_PORT; + if (sctp_mask->hdr.dst_port == UINT16_MAX) + input_set |= ICE_INSET_DST_PORT; + outer_l4 = false; + } else { + if (sctp_mask->hdr.src_port == UINT16_MAX) + input_set |= ICE_INSET_TUN_SRC_PORT; + if (sctp_mask->hdr.dst_port == UINT16_MAX) + input_set |= ICE_INSET_TUN_DST_PORT; + } + + break; + case RTE_FLOW_ITEM_TYPE_ICMP: + icmp_mask = item->mask; + if (icmp_mask->hdr.icmp_code || + icmp_mask->hdr.icmp_cksum || + icmp_mask->hdr.icmp_ident || + icmp_mask->hdr.icmp_seq_nb) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid ICMP mask"); + return 0; + } + + if (icmp_mask->hdr.icmp_type == UINT8_MAX) + input_set |= ICE_INSET_ICMP; + break; + case RTE_FLOW_ITEM_TYPE_ICMP6: + icmp6_mask = item->mask; + if (icmp6_mask->code || + icmp6_mask->checksum) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid ICMP6 mask"); + return 0; + } + + if (icmp6_mask->type == UINT8_MAX) + input_set |= ICE_INSET_ICMP6; + break; + default: + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid mask no exist"); + break; + } + } + return input_set; +} + +static int ice_flow_valid_inset(const struct rte_flow_item pattern[], + uint64_t inset, struct rte_flow_error *error) +{ + uint64_t fields; + + /* get valid field */ + fields = ice_get_flow_field(pattern, error); + if ((!fields) || (fields && (!inset))) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + pattern, + "Invalid input set"); + return -rte_errno; + } + + return 0; +} + +static int ice_flow_valid_action(const struct rte_flow_action *actions, + struct rte_flow_error *error) +{ + switch (actions->type) { + case RTE_FLOW_ACTION_TYPE_QUEUE: + break; + case RTE_FLOW_ACTION_TYPE_DROP: + break; + default: + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, actions, + "Invalid action."); + return -rte_errno; + } + + return 0; +} + +static int +ice_flow_validate(__rte_unused struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow_error *error) +{ + uint64_t inset = 0; + int ret = ICE_ERR_NOT_SUPPORTED; + + if (!pattern) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM, + NULL, "NULL pattern."); + return -rte_errno; + } + + if (!actions) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION_NUM, + NULL, "NULL action."); + return -rte_errno; + } + + if (!attr) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, + NULL, "NULL attribute."); + return -rte_errno; + } + + ret = ice_flow_valid_attr(attr, error); + if (!ret) + return ret; + + inset = ice_flow_valid_pattern(pattern, error); + if (!inset) + return -rte_errno; + + ret = ice_flow_valid_inset(pattern, inset, error); + if (ret) + return ret; + + ret = ice_flow_valid_action(actions, error); + if (ret) + return ret; + + return 0; +} + +static struct rte_flow * +ice_flow_create(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow_error *error) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct rte_flow *flow = NULL; + int ret; + + flow = rte_zmalloc("ice_flow", sizeof(struct rte_flow), 0); + if (!flow) { + rte_flow_error_set(error, ENOMEM, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "Failed to allocate memory"); + return flow; + } + + ret = ice_flow_validate(dev, attr, pattern, actions, error); + if (ret < 0) + return NULL; + + ret = ice_create_switch_filter(pf, pattern, actions, flow, error); + if (ret) + goto free_flow; + + TAILQ_INSERT_TAIL(&pf->flow_list, flow, node); + return flow; + +free_flow: + rte_flow_error_set(error, -ret, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "Failed to create flow."); + rte_free(flow); + return NULL; +} + +static int +ice_flow_destroy(struct rte_eth_dev *dev, + struct rte_flow *flow, + struct rte_flow_error *error) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + int ret = 0; + + ret = ice_destroy_switch_filter(pf, flow); + + if (!ret) { + TAILQ_REMOVE(&pf->flow_list, flow, node); + rte_free(flow); + } else + rte_flow_error_set(error, -ret, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "Failed to destroy flow."); + + return ret; +} + +static int +ice_flow_flush(struct rte_eth_dev *dev, + struct rte_flow_error *error) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct rte_flow *p_flow; + int ret; + + TAILQ_FOREACH(p_flow, &pf->flow_list, node) { + ret = ice_flow_destroy(dev, p_flow, error); + if (ret) { + rte_flow_error_set(error, -ret, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "Failed to flush SW flows."); + return -rte_errno; + } + } + + return ret; +} diff --git a/drivers/net/ice/ice_generic_flow.h b/drivers/net/ice/ice_generic_flow.h new file mode 100644 index 0000000..46c3461 --- /dev/null +++ b/drivers/net/ice/ice_generic_flow.h @@ -0,0 +1,404 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Intel Corporation + */ + +#ifndef _ICE_GENERIC_FLOW_H_ +#define _ICE_GENERIC_FLOW_H_ + +#include + +struct ice_flow_pattern { + enum rte_flow_item_type *items; + uint64_t sw_fields; +}; + +#define ICE_INSET_NONE 0x00000000000000000ULL + +/* bit0 ~ bit 7 */ +#define ICE_INSET_SMAC 0x0000000000000001ULL +#define ICE_INSET_DMAC 0x0000000000000002ULL +#define ICE_INSET_ETHERTYPE 0x0000000000000020ULL + +/* bit 8 ~ bit 15 */ +#define ICE_INSET_IPV4_SRC 0x0000000000000100ULL +#define ICE_INSET_IPV4_DST 0x0000000000000200ULL +#define ICE_INSET_IPV6_SRC 0x0000000000000400ULL +#define ICE_INSET_IPV6_DST 0x0000000000000800ULL +#define ICE_INSET_SRC_PORT 0x0000000000001000ULL +#define ICE_INSET_DST_PORT 0x0000000000002000ULL +#define ICE_INSET_ARP 0x0000000000004000ULL + +/* bit 16 ~ bit 31 */ +#define ICE_INSET_IPV4_TOS 0x0000000000010000ULL +#define ICE_INSET_IPV4_PROTO 0x0000000000020000ULL +#define ICE_INSET_IPV4_TTL 0x0000000000040000ULL +#define ICE_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL +#define ICE_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL +#define ICE_INSET_ICMP 0x0000000001000000ULL +#define ICE_INSET_ICMP6 0x0000000002000000ULL + +/* bit 32 ~ bit 47, tunnel fields */ +#define ICE_INSET_TUN_SMAC 0x0000000100000000ULL +#define ICE_INSET_TUN_DMAC 0x0000000200000000ULL +#define ICE_INSET_TUN_IPV4_SRC 0x0000000400000000ULL +#define ICE_INSET_TUN_IPV4_DST 0x0000000800000000ULL +#define ICE_INSET_TUN_IPV4_TTL 0x0000001000000000ULL +#define ICE_INSET_TUN_IPV4_PROTO 0x0000002000000000ULL +#define ICE_INSET_TUN_IPV6_SRC 0x0000004000000000ULL +#define ICE_INSET_TUN_IPV6_DST 0x0000008000000000ULL +#define ICE_INSET_TUN_IPV6_TTL 0x0000010000000000ULL +#define ICE_INSET_TUN_IPV6_PROTO 0x0000020000000000ULL +#define ICE_INSET_TUN_SRC_PORT 0x0000040000000000ULL +#define ICE_INSET_TUN_DST_PORT 0x0000080000000000ULL +#define ICE_INSET_TUN_ID 0x0000100000000000ULL + +/* bit 48 ~ bit 55 */ +#define ICE_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL + +#define ICE_FLAG_VLAN_INNER 0x00000001ULL +#define ICE_FLAG_VLAN_OUTER 0x00000002ULL + +#define INSET_ETHER ( \ + ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE) +#define INSET_MAC_IPV4 ( \ + ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \ + ICE_INSET_IPV4_PROTO | ICE_INSET_IPV4_TOS) +#define INSET_MAC_IPV4_L4 ( \ + ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \ + ICE_INSET_IPV4_TOS | ICE_INSET_DST_PORT | \ + ICE_INSET_SRC_PORT) +#define INSET_MAC_IPV4_ICMP ( \ + ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \ + ICE_INSET_IPV4_TOS | ICE_INSET_ICMP) +#define INSET_MAC_IPV6 ( \ + ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \ + ICE_INSET_IPV6_NEXT_HDR | ICE_INSET_IPV6_HOP_LIMIT) +#define INSET_MAC_IPV6_L4 ( \ + ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \ + ICE_INSET_IPV6_HOP_LIMIT | ICE_INSET_DST_PORT | \ + ICE_INSET_SRC_PORT) +#define INSET_MAC_IPV6_ICMP ( \ + ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \ + ICE_INSET_IPV6_HOP_LIMIT | ICE_INSET_ICMP6) +#define INSET_TUNNEL_IPV4_TYPE1 ( \ + ICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \ + ICE_INSET_TUN_IPV4_TTL | ICE_INSET_TUN_IPV4_PROTO) +#define INSET_TUNNEL_IPV4_TYPE2 ( \ + ICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \ + ICE_INSET_TUN_IPV4_TTL | ICE_INSET_TUN_IPV4_PROTO | \ + ICE_INSET_TUN_SRC_PORT | ICE_INSET_TUN_DST_PORT) +#define INSET_TUNNEL_IPV4_TYPE3 ( \ + ICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \ + ICE_INSET_TUN_IPV4_TTL | ICE_INSET_ICMP) +#define INSET_TUNNEL_IPV6_TYPE1 ( \ + ICE_INSET_TUN_IPV6_SRC | ICE_INSET_TUN_IPV6_DST | \ + ICE_INSET_TUN_IPV6_TTL | ICE_INSET_TUN_IPV6_PROTO) +#define INSET_TUNNEL_IPV6_TYPE2 ( \ + ICE_INSET_TUN_IPV6_SRC | ICE_INSET_TUN_IPV6_DST | \ + ICE_INSET_TUN_IPV6_TTL | ICE_INSET_TUN_IPV6_PROTO | \ + ICE_INSET_TUN_SRC_PORT | ICE_INSET_TUN_DST_PORT) +#define INSET_TUNNEL_IPV6_TYPE3 ( \ + ICE_INSET_TUN_IPV6_SRC | ICE_INSET_TUN_IPV6_DST | \ + ICE_INSET_TUN_IPV6_TTL | ICE_INSET_ICMP6) + +/* L2 */ +static enum rte_flow_item_type pattern_ethertype[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_END, +}; + +/* non-tunnel IPv4 */ +static enum rte_flow_item_type pattern_ipv4[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_udp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tcp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_TCP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_sctp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_SCTP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_icmp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_ICMP, + RTE_FLOW_ITEM_TYPE_END, +}; + +/* non-tunnel IPv6 */ +static enum rte_flow_item_type pattern_ipv6[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv6_udp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv6_tcp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_TCP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv6_sctp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_SCTP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv6_icmp6[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_ICMP6, + RTE_FLOW_ITEM_TYPE_END, +}; + +/* IPv4 tunnel IPv4 */ +static enum rte_flow_item_type pattern_ipv4_tunnel_ipv4[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_ipv4_udp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_ipv4_tcp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_TCP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_ipv4_sctp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_SCTP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_ipv4_icmp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_ICMP, + RTE_FLOW_ITEM_TYPE_END, +}; + +/* IPv4 tunnel MAC IPv4 */ +static enum rte_flow_item_type pattern_ipv4_tunnel_eth_ipv4[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_eth_ipv4_udp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_eth_ipv4_tcp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_TCP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_eth_ipv4_sctp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_SCTP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_eth_ipv4_icmp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_ICMP, + RTE_FLOW_ITEM_TYPE_END, +}; + +/* IPv4 tunnel IPv6 */ +static enum rte_flow_item_type pattern_ipv4_tunnel_ipv6[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_ipv6_udp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_ipv6_tcp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_TCP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_ipv6_sctp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_SCTP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_ipv6_icmp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_ICMP, + RTE_FLOW_ITEM_TYPE_END, +}; + +/* IPv4 tunnel MAC IPv6 */ +static enum rte_flow_item_type pattern_ipv4_tunnel_eth_ipv6[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_eth_ipv6_udp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_eth_ipv6_tcp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_TCP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_eth_ipv6_sctp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_SCTP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static enum rte_flow_item_type pattern_ipv4_tunnel_eth_ipv6_icmp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_ICMP, + RTE_FLOW_ITEM_TYPE_END, +}; + +static struct ice_flow_pattern ice_supported_patterns[] = { + {pattern_ethertype, INSET_ETHER}, + {pattern_ipv4, INSET_MAC_IPV4}, + {pattern_ipv4_udp, INSET_MAC_IPV4_L4}, + {pattern_ipv4_sctp, INSET_MAC_IPV4_L4}, + {pattern_ipv4_tcp, INSET_MAC_IPV4_L4}, + {pattern_ipv4_icmp, INSET_MAC_IPV4_ICMP}, + {pattern_ipv6, INSET_MAC_IPV6}, + {pattern_ipv6_udp, INSET_MAC_IPV6_L4}, + {pattern_ipv6_sctp, INSET_MAC_IPV6_L4}, + {pattern_ipv6_tcp, INSET_MAC_IPV6_L4}, + {pattern_ipv6_icmp6, INSET_MAC_IPV6_ICMP}, + {pattern_ipv4_tunnel_ipv4, INSET_TUNNEL_IPV4_TYPE1}, + {pattern_ipv4_tunnel_ipv4_udp, INSET_TUNNEL_IPV4_TYPE2}, + {pattern_ipv4_tunnel_ipv4_tcp, INSET_TUNNEL_IPV4_TYPE2}, + {pattern_ipv4_tunnel_ipv4_sctp, INSET_TUNNEL_IPV4_TYPE2}, + {pattern_ipv4_tunnel_ipv4_icmp, INSET_TUNNEL_IPV4_TYPE3}, + {pattern_ipv4_tunnel_eth_ipv4, INSET_TUNNEL_IPV4_TYPE1}, + {pattern_ipv4_tunnel_eth_ipv4_udp, INSET_TUNNEL_IPV4_TYPE2}, + {pattern_ipv4_tunnel_eth_ipv4_tcp, INSET_TUNNEL_IPV4_TYPE2}, + {pattern_ipv4_tunnel_eth_ipv4_sctp, INSET_TUNNEL_IPV4_TYPE2}, + {pattern_ipv4_tunnel_eth_ipv4_icmp, INSET_TUNNEL_IPV4_TYPE3}, + {pattern_ipv4_tunnel_ipv6, INSET_TUNNEL_IPV6_TYPE1}, + {pattern_ipv4_tunnel_ipv6_udp, INSET_TUNNEL_IPV6_TYPE2}, + {pattern_ipv4_tunnel_ipv6_tcp, INSET_TUNNEL_IPV6_TYPE2}, + {pattern_ipv4_tunnel_ipv6_sctp, INSET_TUNNEL_IPV6_TYPE2}, + {pattern_ipv4_tunnel_ipv6_icmp, INSET_TUNNEL_IPV6_TYPE3}, + {pattern_ipv4_tunnel_eth_ipv6, INSET_TUNNEL_IPV6_TYPE1}, + {pattern_ipv4_tunnel_eth_ipv6_udp, INSET_TUNNEL_IPV6_TYPE2}, + {pattern_ipv4_tunnel_eth_ipv6_tcp, INSET_TUNNEL_IPV6_TYPE2}, + {pattern_ipv4_tunnel_eth_ipv6_sctp, INSET_TUNNEL_IPV6_TYPE2}, + {pattern_ipv4_tunnel_eth_ipv6_icmp, INSET_TUNNEL_IPV6_TYPE3}, +}; + +#endif From patchwork Wed Jun 12 07:50:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 54732 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1AA4D1D171; Wed, 12 Jun 2019 09:52:38 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 1DC741D15E for ; Wed, 12 Jun 2019 09:52:27 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2019 00:52:26 -0700 X-ExtLoop1: 1 Received: from map1.sh.intel.com ([10.67.111.124]) by orsmga003.jf.intel.com with ESMTP; 12 Jun 2019 00:52:27 -0700 From: Qiming Yang To: dev@dpdk.org Cc: Qiming Yang Date: Wed, 12 Jun 2019 15:50:29 +0800 Message-Id: <20190612075029.109914-4-qiming.yang@intel.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190612075029.109914-1-qiming.yang@intel.com> References: <1559552722-8970-1-git-send-email-qiming.yang@intel.com> <20190612075029.109914-1-qiming.yang@intel.com> Subject: [dpdk-dev] [PATCH v2 3/3] net/ice: add UDP tunnel port support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Enabled UDP tunnel port add and delete functions. Signed-off-by: Qiming Yang --- drivers/net/ice/ice_ethdev.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index cf6bb1d..833b724 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -88,6 +88,10 @@ static int ice_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type filter_type, enum rte_filter_op filter_op, void *arg); +static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, + struct rte_eth_udp_tunnel *udp_tunnel); +static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, + struct rte_eth_udp_tunnel *udp_tunnel); static const struct rte_pci_id pci_id_ice_map[] = { { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, @@ -147,6 +151,8 @@ static const struct eth_dev_ops ice_eth_dev_ops = { .xstats_get_names = ice_xstats_get_names, .xstats_reset = ice_stats_reset, .filter_ctrl = ice_dev_filter_ctrl, + .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add, + .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del, }; /* store statistics names and its offset in stats structure */ @@ -3646,6 +3652,54 @@ ice_dev_filter_ctrl(struct rte_eth_dev *dev, return ret; } +/* Add UDP tunneling port */ +static int +ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, + struct rte_eth_udp_tunnel *udp_tunnel) +{ + int ret = 0; + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (udp_tunnel == NULL) + return -EINVAL; + + switch (udp_tunnel->prot_type) { + case RTE_TUNNEL_TYPE_VXLAN: + ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port); + break; + default: + PMD_DRV_LOG(ERR, "Invalid tunnel type"); + ret = -1; + break; + } + + return ret; +} + +/* Delete UDP tunneling port */ +static int +ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, + struct rte_eth_udp_tunnel *udp_tunnel) +{ + int ret = 0; + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (udp_tunnel == NULL) + return -EINVAL; + + switch (udp_tunnel->prot_type) { + case RTE_TUNNEL_TYPE_VXLAN: + ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0); + break; + default: + PMD_DRV_LOG(ERR, "Invalid tunnel type"); + ret = -1; + break; + } + + return ret; +} + static int ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev)