From patchwork Tue Apr 9 19:06:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52496 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7FFA954AE; Tue, 9 Apr 2019 21:06:38 +0200 (CEST) Received: from mail-qt1-f194.google.com (mail-qt1-f194.google.com [209.85.160.194]) by dpdk.org (Postfix) with ESMTP id A51EF4F98 for ; Tue, 9 Apr 2019 21:06:34 +0200 (CEST) Received: by mail-qt1-f194.google.com with SMTP id w30so21163193qta.8 for ; Tue, 09 Apr 2019 12:06:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=CYAh6sQQhk56ewt8zoEACUwsrBuZatwgtDFTv69ngxU=; b=L/l6ld2Gnq1wi+tbdz6OlhVvSUrWzZ55b7twEGF+wchn1GozpLxpTDsBATtIRl7aT/ KdmQDetMLcs2GKY1G78fTCw9q+YQVBWmDgjqA83KoPU7g6aFKX1JOxENL+Gz1pxIK4Sd S4/P+88w4HQONSn9gDb+qFReQmG3MfIp7dE1WVBMjOrN7UN9TTsi5GS77CtGTzbPzrpu P3k3t24m7aZx+V1/wIWlZuWZiMQZalwqlk/6sdl49Jp1y3+7uUK9LcQFgbapgMT5C0xN tWMMi8OMpX45T7EPM/tiKdW88IjWSB2LqPW/2c+WPDy8B6UIeMSNMzUyQalNcZV2fKyW HttA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=CYAh6sQQhk56ewt8zoEACUwsrBuZatwgtDFTv69ngxU=; b=hPpXfaBe1uvlrbX5FOoerfsKMEGYab7EOD0nhNlMtOS3Zy1P0/D4eGLRh1JC2xxQ1P ayif0EyNyYv5Ukn9+xARmxDrjpdvbsueJGtNKpNbkxVsLRIqIRpZ76I1YKu9EHsmZRTP vfSvt0LrZSyyNXk2kSUJyk/SuDjEIXwDJ5sFs5+BWdxF0xzQf1eer8jSIa+qu4//Sjym trO8n4i2KnhT9eZVanW4F7dq06pGadA0IJd4ja1QoGAcNEsUidrO4gi6RlEhVxGvQO3d Om2QoP7Q+syS5iLh664/qFplBbh00o23863icfJ0AMLnMa5wy4L1CO5fOke206E/FGGg 1VRA== X-Gm-Message-State: APjAAAU0P0sfKaEfgYsmDS6q3vxSwnFj2UthqmDChKdQ9wAfPZMyQ5Mo EoxOOeHrZxJcAR06CVbq09h/RbmetXg= X-Google-Smtp-Source: APXvYqx8KzONIb7lZiolXX2iY3Ob8/rSj2A/XkL7St11Kd9UhiUHutKjmFnbmaoQpqTUEolFfI+mBw== X-Received: by 2002:ac8:3696:: with SMTP id a22mr30860327qtc.191.1554836793572; Tue, 09 Apr 2019 12:06:33 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:32 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:19 -0400 Message-Id: <20190409190630.31975-2-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 01/12] mk: introduce s390x architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add config and mk files to build DPDK on Linux on IBM Z (s390x). Signed-off-by: Vivian Kong --- config/defconfig_s390x-native-linux-gcc | 1 + config/defconfig_s390x-native-linuxapp-gcc | 33 ++++++++++++++++++++++ mk/arch/s390x/rte.vars.mk | 16 +++++++++++ mk/rte.cpuflags.mk | 5 ++++ 4 files changed, 55 insertions(+) create mode 120000 config/defconfig_s390x-native-linux-gcc create mode 100644 config/defconfig_s390x-native-linuxapp-gcc create mode 100644 mk/arch/s390x/rte.vars.mk diff --git a/config/defconfig_s390x-native-linux-gcc b/config/defconfig_s390x-native-linux-gcc new file mode 120000 index 000000000..28b9275cf --- /dev/null +++ b/config/defconfig_s390x-native-linux-gcc @@ -0,0 +1 @@ +defconfig_s390x-native-linuxapp-gcc \ No newline at end of file diff --git a/config/defconfig_s390x-native-linuxapp-gcc b/config/defconfig_s390x-native-linuxapp-gcc new file mode 100644 index 000000000..1241157d9 --- /dev/null +++ b/config/defconfig_s390x-native-linuxapp-gcc @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: BSD-3-Clause +# +# (c) Copyright IBM Corp. 2018, 2019 + +#include "common_linux" + +CONFIG_RTE_MACHINE="z13" + +CONFIG_RTE_ARCH="s390x" +CONFIG_RTE_ARCH_64=y +CONFIG_RTE_ARCH_S390X=y + +#CONFIG_RTE_MAX_LCORE=256 +#CONFIG_RTE_MAX_NUMA_NODES=32 +#CONFIG_RTE_CACHE_LINE_SIZE=128 + +CONFIG_RTE_TOOLCHAIN="gcc" +CONFIG_RTE_TOOLCHAIN_GCC=y +CONFIG_RTE_FORCE_INTRINSICS=y +# Note: Power doesn't have this support +CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n + +# Note: Initially, all of the PMD drivers compilation are turned off on s390x +# Will turn on them only after the successful testing on s390x +CONFIG_RTE_LIBRTE_IXGBE_PMD=n +CONFIG_RTE_LIBRTE_VIRTIO_PMD=y +CONFIG_RTE_LIBRTE_VMXNET3_PMD=n +CONFIG_RTE_LIBRTE_ENIC_PMD=n +CONFIG_RTE_LIBRTE_FM10K_PMD=n +CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n +CONFIG_RTE_LIBRTE_AVP_PMD=n +CONFIG_RTE_LIBRTE_BNXT_PMD=n +CONFIG_RTE_LIBRTE_ENETC_PMD=n diff --git a/mk/arch/s390x/rte.vars.mk b/mk/arch/s390x/rte.vars.mk new file mode 100644 index 000000000..9740c5684 --- /dev/null +++ b/mk/arch/s390x/rte.vars.mk @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause +# (c) Copyright IBM Corp. 2018, 2019 + +ARCH ?= s390 +CROSS ?= + +CPU_CFLAGS ?= -m64 +CPU_LDFLAGS ?= +CPU_ASFLAGS ?= -felf64 + +export ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS + +RTE_OBJCOPY_TARGET = elf64-s390 +RTE_OBJCOPY_ARCH = s390 + +export RTE_OBJCOPY_TARGET RTE_OBJCOPY_ARCH diff --git a/mk/rte.cpuflags.mk b/mk/rte.cpuflags.mk index 541211c61..195022926 100644 --- a/mk/rte.cpuflags.mk +++ b/mk/rte.cpuflags.mk @@ -93,6 +93,11 @@ ifneq ($(filter $(AUTO_CPUFLAGS),__builtin_vsx_xvnmaddadp),) CPUFLAGS += VSX endif +# s390x +ifneq ($(filter $(AUTO_CPUFLAGS),__s390x__),) +CPUFLAGS += ZARCH +endif + # ARM flags ifneq ($(filter __ARM_NEON __aarch64__,$(AUTO_CPUFLAGS)),) CPUFLAGS += NEON From patchwork Tue Apr 9 19:06:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52497 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4B9B55688; Tue, 9 Apr 2019 21:06:42 +0200 (CEST) Received: from mail-qt1-f196.google.com (mail-qt1-f196.google.com [209.85.160.196]) by dpdk.org (Postfix) with ESMTP id C85EC5398 for ; Tue, 9 Apr 2019 21:06:36 +0200 (CEST) Received: by mail-qt1-f196.google.com with SMTP id w5so21128599qtb.11 for ; Tue, 09 Apr 2019 12:06:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=6RRGwwVTBPCCenQtul9wGFvFLAD4/o+g6qH6+4VrFlM=; b=YZzPGeqe/nhz1TorawDzUx9hzmBXAuZEy22Z8N7FEZmyrDD/sxi3R7j1inb6Ukdhow BjMywiZCUuHZdB2wvF8AoXbKEDqm1W0sTjKbKEQqUN3rAypkJjWh6A3PfPQM9lNGIEcA UljNhHG7UnHrp6i/jCogFyKS/uH4+Xsun3+XJ39yb38t6ddWEPQ5Jofzzz+pePOWeXlw Ywjz0XDNVhQSHm0PnQFjc5smRy+UsmEoHL4l9d1pOUYCV746svz3TEpo+2ArTAOXNXh5 UyJziL7P1ES2xMj+EGUU9BqhcxyfpjEoCQvHfHX+h4UC4CfGMaGLdd1+DPTczZh0nit9 ENQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=6RRGwwVTBPCCenQtul9wGFvFLAD4/o+g6qH6+4VrFlM=; b=ZtP7A/iQSIJ+/kB7USHxH9QCNtKIMUnooIBC+TATgZuqwyD8em9JLgJE8T5mBmqN0w BdsK05llSayQYkZQK5N2wQVu0YIlyqfnH2B4fgXz59UG7bun3oAFNj6Ite0Dzi8ycrWp fq0Oq33VV2MFaOyfx4gvHTRHwPe0r5zmdAysI7DuykcRYfhmKdWY/lcAP9Q9aFMvAOZW uKkkrr5IjUUkyJcaXCtAQeILwc2XoShLsXtZmcTpdTURFBvCaarpWd4ABh2BDaVx/oTl U5lQoqmjOS2hBniUO+cNvJDIh45nTFWMOsvBetNPDvDmjipu+BB1aztCH+EBrdZeczTO u1dg== X-Gm-Message-State: APjAAAUDtgqLyouda5YZd9XhD916TVYRntIwMcvcxs+SeH7WNzQsKEB/ R1q7noMZIXEaHixBfZTHZiIv4x/+JjU= X-Google-Smtp-Source: APXvYqwpPFcjEV4iHB3ghFDCWBP/42fx5z3gnaVIMg92bOX3E57Ue5n+ppioz8rK9Rf3PPzYHIzvyw== X-Received: by 2002:ac8:3328:: with SMTP id t37mr31605281qta.246.1554836795196; Tue, 09 Apr 2019 12:06:35 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:33 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:20 -0400 Message-Id: <20190409190630.31975-3-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 02/12] eal: add support for s390x architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Implement DPDK EAL for s390x architecture. Signed-off-by: Vivian Kong --- .../common/arch/s390x/rte_cpuflags.c | 90 +++++++++++++++++++ lib/librte_eal/common/arch/s390x/rte_cycles.c | 11 +++ .../common/arch/s390x/rte_hypervisor.c | 11 +++ .../common/include/arch/s390x/rte_atomic.h | 47 ++++++++++ .../common/include/arch/s390x/rte_byteorder.h | 43 +++++++++ .../common/include/arch/s390x/rte_cpuflags.h | 42 +++++++++ .../common/include/arch/s390x/rte_cycles.h | 44 +++++++++ .../common/include/arch/s390x/rte_io.h | 18 ++++ .../common/include/arch/s390x/rte_memcpy.h | 55 ++++++++++++ .../common/include/arch/s390x/rte_pause.h | 22 +++++ .../common/include/arch/s390x/rte_prefetch.h | 40 +++++++++ .../common/include/arch/s390x/rte_rwlock.h | 42 +++++++++ .../common/include/arch/s390x/rte_spinlock.h | 85 ++++++++++++++++++ .../include/arch/s390x/rte_ticketlock.h | 18 ++++ .../common/include/arch/s390x/rte_vect.h | 33 +++++++ 15 files changed, 601 insertions(+) create mode 100644 lib/librte_eal/common/arch/s390x/rte_cpuflags.c create mode 100644 lib/librte_eal/common/arch/s390x/rte_cycles.c create mode 100644 lib/librte_eal/common/arch/s390x/rte_hypervisor.c create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_atomic.h create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_byteorder.h create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_cpuflags.h create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_cycles.h create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_io.h create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_memcpy.h create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_pause.h create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_prefetch.h create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_rwlock.h create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_spinlock.h create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_ticketlock.h create mode 100644 lib/librte_eal/common/include/arch/s390x/rte_vect.h diff --git a/lib/librte_eal/common/arch/s390x/rte_cpuflags.c b/lib/librte_eal/common/arch/s390x/rte_cpuflags.c new file mode 100644 index 000000000..1f8c6ef41 --- /dev/null +++ b/lib/librte_eal/common/arch/s390x/rte_cpuflags.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#include "rte_cpuflags.h" + +#include +#include +#include +#include + +/* Symbolic values for the entries in the auxiliary table */ +#define AT_HWCAP 16 +#define AT_HWCAP2 26 + +/* software based registers */ +enum cpu_register_t { + REG_NONE = 0, + REG_HWCAP, + REG_HWCAP2, + REG_MAX +}; + +typedef uint32_t hwcap_registers_t[REG_MAX]; + +struct feature_entry { + uint32_t reg; + uint32_t bit; +#define CPU_FLAG_NAME_MAX_LEN 64 + char name[CPU_FLAG_NAME_MAX_LEN]; +}; + +#define FEAT_DEF(name, reg, bit) \ + [RTE_CPUFLAG_##name] = {reg, bit, #name}, + +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(ESAN3, REG_HWCAP, 0) + FEAT_DEF(ZARCH, REG_HWCAP, 1) + FEAT_DEF(STFLE, REG_HWCAP, 2) + FEAT_DEF(MSA, REG_HWCAP, 3) + FEAT_DEF(LDISP, REG_HWCAP, 4) + FEAT_DEF(EIMM, REG_HWCAP, 5) + FEAT_DEF(DFP, REG_HWCAP, 6) + FEAT_DEF(HPAGE, REG_HWCAP, 7) + FEAT_DEF(ETF3EH, REG_HWCAP, 8) + FEAT_DEF(HIGH_GPRS, REG_HWCAP, 9) + FEAT_DEF(TE, REG_HWCAP, 10) + FEAT_DEF(VXRS, REG_HWCAP, 11) + FEAT_DEF(VXRS_BCD, REG_HWCAP, 12) + FEAT_DEF(VXRS_EXT, REG_HWCAP, 13) + FEAT_DEF(GS, REG_HWCAP, 14) +}; + +/* + * Read AUXV software register and get cpu features for Power + */ +static void +rte_cpu_get_features(hwcap_registers_t out) +{ + out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); + out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2); +} + +/* + * Checks if a particular flag is available on current machine. + */ +int +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) +{ + const struct feature_entry *feat; + hwcap_registers_t regs = {0}; + + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return -ENOENT; + + feat = &rte_cpu_feature_table[feature]; + if (feat->reg == REG_NONE) + return -EFAULT; + + rte_cpu_get_features(regs); + return (regs[feat->reg] >> feat->bit) & 1; +} + +const char * +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) +{ + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return NULL; + return rte_cpu_feature_table[feature].name; +} diff --git a/lib/librte_eal/common/arch/s390x/rte_cycles.c b/lib/librte_eal/common/arch/s390x/rte_cycles.c new file mode 100644 index 000000000..b29c4454a --- /dev/null +++ b/lib/librte_eal/common/arch/s390x/rte_cycles.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#include "eal_private.h" + +uint64_t +get_tsc_freq_arch(void) +{ + return 0; +} diff --git a/lib/librte_eal/common/arch/s390x/rte_hypervisor.c b/lib/librte_eal/common/arch/s390x/rte_hypervisor.c new file mode 100644 index 000000000..22b0c5cc4 --- /dev/null +++ b/lib/librte_eal/common/arch/s390x/rte_hypervisor.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#include "rte_hypervisor.h" + +enum rte_hypervisor +rte_hypervisor_get(void) +{ + return RTE_HYPERVISOR_UNKNOWN; +} diff --git a/lib/librte_eal/common/include/arch/s390x/rte_atomic.h b/lib/librte_eal/common/include/arch/s390x/rte_atomic.h new file mode 100644 index 000000000..5fce6d5f0 --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_atomic.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#ifndef _RTE_ATOMIC_S390X_H_ +#define _RTE_ATOMIC_S390X_H_ + +#ifndef RTE_FORCE_INTRINSICS +# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_atomic.h" + +//#define dsb(opt) asm volatile("" : : : "memory") +//#define dmb(opt) asm volatile("" : : : "memory") + +#define rte_mb() rte_compiler_barrier() //asm volatile("" : : : "memory") + +#define rte_wmb() rte_mb() + +#define rte_rmb() rte_mb() + +#define rte_smp_mb() rte_mb() + +#define rte_smp_wmb() rte_wmb() + +#define rte_smp_rmb() rte_rmb() + +#define rte_io_mb() rte_mb() + +#define rte_io_wmb() rte_wmb() + +#define rte_io_rmb() rte_rmb() + +#define rte_cio_wmb() rte_wmb() + +#define rte_cio_rmb() rte_rmb() + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_ATOMIC_S390X_H_ */ diff --git a/lib/librte_eal/common/include/arch/s390x/rte_byteorder.h b/lib/librte_eal/common/include/arch/s390x/rte_byteorder.h new file mode 100644 index 000000000..de6e410b4 --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_byteorder.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +/* Inspired from FreeBSD src/sys/powerpc/include/endian.h + * Copyright (c) 1987, 1991, 1993 + * The Regents of the University of California. All rights reserved. + */ + +#ifndef _RTE_BYTEORDER_S390X_H_ +#define _RTE_BYTEORDER_S390X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "generic/rte_byteorder.h" + +/* s390x is big endian + */ + +#define rte_cpu_to_le_16(x) rte_bswap16(x) +#define rte_cpu_to_le_32(x) rte_bswap32(x) +#define rte_cpu_to_le_64(x) rte_bswap64(x) + +#define rte_cpu_to_be_16(x) (x) +#define rte_cpu_to_be_32(x) (x) +#define rte_cpu_to_be_64(x) (x) + +#define rte_le_to_cpu_16(x) rte_bswap16(x) +#define rte_le_to_cpu_32(x) rte_bswap32(x) +#define rte_le_to_cpu_64(x) rte_bswap64(x) + +#define rte_be_to_cpu_16(x) (x) +#define rte_be_to_cpu_32(x) (x) +#define rte_be_to_cpu_64(x) (x) + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_BYTEORDER_S390X_H_ */ diff --git a/lib/librte_eal/common/include/arch/s390x/rte_cpuflags.h b/lib/librte_eal/common/include/arch/s390x/rte_cpuflags.h new file mode 100644 index 000000000..bfeff3f98 --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_cpuflags.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#ifndef _RTE_CPUFLAGS_S390X_H_ +#define _RTE_CPUFLAGS_S390X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Enumeration of all CPU features supported + */ +enum rte_cpu_flag_t { + RTE_CPUFLAG_ESAN3 = 0, + RTE_CPUFLAG_ZARCH, + RTE_CPUFLAG_STFLE, + RTE_CPUFLAG_MSA, + RTE_CPUFLAG_LDISP, + RTE_CPUFLAG_EIMM, + RTE_CPUFLAG_DFP, + RTE_CPUFLAG_HPAGE, //from elf.h + //RTE_CPUFLAG_EDAT, //from hwcap.h + RTE_CPUFLAG_ETF3EH, + RTE_CPUFLAG_HIGH_GPRS, + RTE_CPUFLAG_TE, + RTE_CPUFLAG_VXRS, + RTE_CPUFLAG_VXRS_BCD, + RTE_CPUFLAG_VXRS_EXT, + RTE_CPUFLAG_GS, + /* The last item */ + RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ +}; + +#include "generic/rte_cpuflags.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_CPUFLAGS_S390X_H_ */ diff --git a/lib/librte_eal/common/include/arch/s390x/rte_cycles.h b/lib/librte_eal/common/include/arch/s390x/rte_cycles.h new file mode 100644 index 000000000..211bbe448 --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_cycles.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#ifndef _RTE_CYCLES_S390X_H_ +#define _RTE_CYCLES_S390X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_cycles.h" + +#include + +/** + * Read the time base register. + * + * @return + * The time base for this lcore. + */ +static inline uint64_t +rte_rdtsc(void) +{ + uint64_t tsc; + asm volatile("stck %0" : "=Q"(tsc) : : "cc"); + return tsc; +} + +static inline uint64_t +rte_rdtsc_precise(void) +{ + rte_mb(); + return rte_rdtsc(); +} + +static inline uint64_t +rte_get_tsc_cycles(void) { return rte_rdtsc(); } + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_CYCLES_S390X_H_ */ diff --git a/lib/librte_eal/common/include/arch/s390x/rte_io.h b/lib/librte_eal/common/include/arch/s390x/rte_io.h new file mode 100644 index 000000000..e6b718ef3 --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_io.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#ifndef _RTE_IO_S390X_H_ +#define _RTE_IO_S390X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_io.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_IO_S390X_H_ */ diff --git a/lib/librte_eal/common/include/arch/s390x/rte_memcpy.h b/lib/librte_eal/common/include/arch/s390x/rte_memcpy.h new file mode 100644 index 000000000..1135b1af6 --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_memcpy.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#ifndef _RTE_MEMCPY_S390X_H_ +#define _RTE_MEMCPY_S390X_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_memcpy.h" + + +static inline void +rte_mov16(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 16); +} +static inline void +rte_mov32(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 32); +} +static inline void +rte_mov48(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 48); +} +static inline void +rte_mov64(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 64); +} +static inline void +rte_mov128(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 128); +} +static inline void +rte_mov256(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 256); +} +#define rte_memcpy(d, s, n) memcpy((d), (s), (n)) + + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_MEMCPY_S390X_H_ */ diff --git a/lib/librte_eal/common/include/arch/s390x/rte_pause.h b/lib/librte_eal/common/include/arch/s390x/rte_pause.h new file mode 100644 index 000000000..be90ce6a1 --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_pause.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#ifndef _RTE_PAUSE_S390X_H_ +#define _RTE_PAUSE_S390X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_pause.h" + +static inline void rte_pause(void) +{ +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_PAUSE_S390X_H_ */ diff --git a/lib/librte_eal/common/include/arch/s390x/rte_prefetch.h b/lib/librte_eal/common/include/arch/s390x/rte_prefetch.h new file mode 100644 index 000000000..c76c6d898 --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_prefetch.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#ifndef _RTE_PREFETCH_S390X_H_ +#define _RTE_PREFETCH_S390X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "generic/rte_prefetch.h" + +static inline void rte_prefetch0(const volatile void *p) +{ + asm volatile ("pfd 1, 0(%[p])" : : [p] "r" (p)); +} + +static inline void rte_prefetch1(const volatile void *p) +{ + asm volatile ("pfd 1, 0(%[p])" : : [p] "r" (p)); +} + +static inline void rte_prefetch2(const volatile void *p) +{ + asm volatile ("pfd 1, 0(%[p])" : : [p] "r" (p)); +} + +static inline void rte_prefetch_non_temporal(const volatile void *p) +{ + /* non-temporal version not available, fallback to rte_prefetch0 */ + rte_prefetch0(p); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_PREFETCH_S390X_H_ */ diff --git a/lib/librte_eal/common/include/arch/s390x/rte_rwlock.h b/lib/librte_eal/common/include/arch/s390x/rte_rwlock.h new file mode 100644 index 000000000..f649484f3 --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_rwlock.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#ifndef _RTE_RWLOCK_S390X_H_ +#define _RTE_RWLOCK_S390X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_rwlock.h" + +static inline void +rte_rwlock_read_lock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_read_lock(rwl); +} + +static inline void +rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_read_unlock(rwl); +} + +static inline void +rte_rwlock_write_lock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_write_lock(rwl); +} + +static inline void +rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_write_unlock(rwl); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_RWLOCK_S390X_H_ */ diff --git a/lib/librte_eal/common/include/arch/s390x/rte_spinlock.h b/lib/librte_eal/common/include/arch/s390x/rte_spinlock.h new file mode 100644 index 000000000..0434864fb --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_spinlock.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#ifndef _RTE_SPINLOCK_S390X_H_ +#define _RTE_SPINLOCK_S390X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "generic/rte_spinlock.h" + +#ifndef RTE_FORCE_INTRINSICS + +static inline void +rte_spinlock_lock(rte_spinlock_t *sl) +{ + while (__sync_lock_test_and_set(&sl->locked, 1)) + while (sl->locked) + rte_pause(); +} + +static inline void +rte_spinlock_unlock(rte_spinlock_t *sl) +{ + __sync_lock_release(&sl->locked); +} + +static inline int +rte_spinlock_trylock(rte_spinlock_t *sl) +{ + return __sync_lock_test_and_set(&sl->locked, 1) == 0; +} + +#endif + + +static inline int rte_tm_supported(void) +{ + return 0; +} + +static inline void +rte_spinlock_lock_tm(rte_spinlock_t *sl) +{ + rte_spinlock_lock(sl); /* fall-back */ +} + +static inline int +rte_spinlock_trylock_tm(rte_spinlock_t *sl) +{ + return rte_spinlock_trylock(sl); +} + +static inline void +rte_spinlock_unlock_tm(rte_spinlock_t *sl) +{ + rte_spinlock_unlock(sl); +} + +static inline void +rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr) +{ + rte_spinlock_recursive_lock(slr); /* fall-back */ +} + +static inline void +rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr) +{ + rte_spinlock_recursive_unlock(slr); +} + +static inline int +rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr) +{ + return rte_spinlock_recursive_trylock(slr); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_SPINLOCK_S390X_H_ */ diff --git a/lib/librte_eal/common/include/arch/s390x/rte_ticketlock.h b/lib/librte_eal/common/include/arch/s390x/rte_ticketlock.h new file mode 100644 index 000000000..0785363c9 --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_ticketlock.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2019 + */ + +#ifndef _RTE_TICKETLOCK_S390X_H_ +#define _RTE_TICKETLOCK_S390X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_ticketlock.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_TICKETLOCK_S390X_H_ */ diff --git a/lib/librte_eal/common/include/arch/s390x/rte_vect.h b/lib/librte_eal/common/include/arch/s390x/rte_vect.h new file mode 100644 index 000000000..459744aa4 --- /dev/null +++ b/lib/librte_eal/common/include/arch/s390x/rte_vect.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2018, 2019 + */ + +#ifndef _RTE_VECT_S390X_H_ +#define _RTE_VECT_S390X_H_ + +#include +#include "generic/rte_vect.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef int xmm_t __attribute__((vector_size(4*sizeof(int)))); + +#define XMM_SIZE (sizeof(xmm_t)) +#define XMM_MASK (XMM_SIZE - 1) + +typedef union rte_xmm { + xmm_t x; + uint8_t u8[XMM_SIZE / sizeof(uint8_t)]; + uint16_t u16[XMM_SIZE / sizeof(uint16_t)]; + uint32_t u32[XMM_SIZE / sizeof(uint32_t)]; + uint64_t u64[XMM_SIZE / sizeof(uint64_t)]; + double pd[XMM_SIZE / sizeof(double)]; +} __attribute__((aligned(16))) rte_xmm_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_VECT_S390X_H_ */ From patchwork Tue Apr 9 19:06:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52498 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4E48858CB; Tue, 9 Apr 2019 21:06:46 +0200 (CEST) Received: from mail-qt1-f194.google.com (mail-qt1-f194.google.com [209.85.160.194]) by dpdk.org (Postfix) with ESMTP id 896B154AE for ; Tue, 9 Apr 2019 21:06:37 +0200 (CEST) Received: by mail-qt1-f194.google.com with SMTP id x12so21153707qts.7 for ; Tue, 09 Apr 2019 12:06:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=nbi8ciZYHZiEavNR0hFcg7X/0A/LAumdrTKr6hSQXNc=; b=UalmOM7yPaxfxS7KEblIbqPKmWWP76Q5hVd2cXUYYiCP1JmxUpGzGEhyAHuNjnNUmD t5W3GSfc0KTK5hNiLhc8Nips/Q+yCtKGcSe7+e99rlw/liTN7D4yvDCPD9iz6XX01YmT LrXWLhhFAODJT3wR8KCZc8Y0Nfddf6ecZqB60KFvVPFJ5Isuy8QUEYudEvHVXeaj9Mg+ MXugLpAmJDYZYGmUT41hR56S1GgSGWa0CbH+hJcE+sR5EPQgpJ2dz7iyn5fDauiGYtJh VruK4R8djqd0XprcNcUB6d4M2Auvd9DIiWCb4hHuydrloZtFTX/ZLkDLBtsMKrAEy5xr 5uTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=nbi8ciZYHZiEavNR0hFcg7X/0A/LAumdrTKr6hSQXNc=; b=F0DV10y9QAVWtMESEIkxrz+pqRV3k8BVr+DIPOXGsH/uFnMLudRQRuy6+DX3KbAfdJ JPf4H0bJEsKvRgLrzJZ01jPjFYW+Pk0wGoty1pmqFo1uQVN/exJbdxOpoT31tw2IUyVP O3lA+ECI0cWCcX5eAA3g3iiYbbUv9XyvISMo97diXy0UcgZWCwQo5O0haVMPyDnjcpxx NJtRxPNTVRjPVAgAdMVudhOFujBvJI7O6M653BxPH1DoKo5yti5FnkOj4CCA6xRaveA4 gYptOrHpFRBRdJHdkCzlUyp9sSmmj9mkHKIm/Wfax1CaawxS4zbPFcO7MHQwTDCa1mVj Ar7A== X-Gm-Message-State: APjAAAWNNNoq2XJAXuFGnAxJdZ4upYaoWMCMoTNBC5hgSRgLAR76MOqV pQSBpuVG/jospGVB7bSYmqvt94hbspI= X-Google-Smtp-Source: APXvYqz4VugK7Re35n0MlYtcHzk3gkcMtltfTk8j9rFfRkZwPNh6i29xlQ7Eqk0+EEMdz9gOXdf68w== X-Received: by 2002:ac8:2c72:: with SMTP id e47mr31711658qta.189.1554836796500; Tue, 09 Apr 2019 12:06:36 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.35 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:35 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:21 -0400 Message-Id: <20190409190630.31975-4-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 03/12] acl: add support for s390x architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add big endian support for s390x architecture. Signed-off-by: Vivian Kong --- app/test-acl/main.c | 4 ++ lib/librte_acl/Makefile | 2 + lib/librte_acl/acl_bld.c | 69 +++++++++++++++++++++++++++------ lib/librte_acl/acl_gen.c | 9 +++++ lib/librte_acl/acl_run_scalar.c | 8 ++++ lib/librte_acl/rte_acl.c | 4 ++ lib/librte_acl/rte_acl.h | 1 + 7 files changed, 85 insertions(+), 12 deletions(-) diff --git a/app/test-acl/main.c b/app/test-acl/main.c index b80179417..b6c5c9abd 100644 --- a/app/test-acl/main.c +++ b/app/test-acl/main.c @@ -81,6 +81,10 @@ static const struct acl_alg acl_alg[] = { .name = "altivec", .alg = RTE_ACL_CLASSIFY_ALTIVEC, }, + { + .name = "s390x", + .alg = RTE_ACL_CLASSIFY_S390X, + }, }; static struct { diff --git a/lib/librte_acl/Makefile b/lib/librte_acl/Makefile index ea5edf00a..f87693d1e 100644 --- a/lib/librte_acl/Makefile +++ b/lib/librte_acl/Makefile @@ -30,6 +30,8 @@ CFLAGS_acl_run_neon.o += -Wno-maybe-uninitialized endif else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y) SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_altivec.c +else ifeq ($(CONFIG_RTE_ARCH_S390X),y) +SRCS-$(CONFIG_RTE_LIBRTE_ACL) += else SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_sse.c endif diff --git a/lib/librte_acl/acl_bld.c b/lib/librte_acl/acl_bld.c index b82191f42..16bf09304 100644 --- a/lib/librte_acl/acl_bld.c +++ b/lib/librte_acl/acl_bld.c @@ -777,6 +777,16 @@ acl_build_reset(struct rte_acl_ctx *ctx) sizeof(*ctx) - offsetof(struct rte_acl_ctx, num_categories)); } +static uint32_t get_le_byte_index(uint32_t index, int size) +{ +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + (void) size; + return index; +#else + return size - 1 - index; +#endif +} + static void acl_gen_range(struct acl_build_context *context, const uint8_t *hi, const uint8_t *lo, int size, int level, @@ -786,12 +796,19 @@ acl_gen_range(struct acl_build_context *context, uint32_t n; prev = root; + + /* On big endian min and max point to highest byte. + * Therefore iterate in opposite direction as on + * little endian with helper function. + */ for (n = size - 1; n > 0; n--) { + uint32_t le_idx = get_le_byte_index(n, size); node = acl_alloc_node(context, level++); - acl_add_ptr_range(context, prev, node, lo[n], hi[n]); + acl_add_ptr_range(context, prev, node, lo[le_idx], hi[le_idx]); prev = node; } - acl_add_ptr_range(context, prev, end, lo[0], hi[0]); + const uint32_t first_idx = get_le_byte_index(0, size); + acl_add_ptr_range(context, prev, end, lo[first_idx], hi[first_idx]); } static struct rte_acl_node * @@ -804,10 +821,16 @@ acl_gen_range_trie(struct acl_build_context *context, const uint8_t *lo = min; const uint8_t *hi = max; + /* On big endian min and max point to highest byte. + * Therefore iterate in opposite direction as on + * little endian. + */ + const int byte_index = get_le_byte_index(size-1, size); + *pend = acl_alloc_node(context, level+size); root = acl_alloc_node(context, level++); - if (lo[size - 1] == hi[size - 1]) { + if (lo[byte_index] == hi[byte_index]) { acl_gen_range(context, hi, lo, size, level, root, *pend); } else { uint8_t limit_lo[64]; @@ -819,27 +842,29 @@ acl_gen_range_trie(struct acl_build_context *context, memset(limit_hi, UINT8_MAX, RTE_DIM(limit_hi)); for (n = size - 2; n >= 0; n--) { - hi_ff = (uint8_t)(hi_ff & hi[n]); - lo_00 = (uint8_t)(lo_00 | lo[n]); + const uint32_t le_idx = get_le_byte_index(n, size); + hi_ff = (uint8_t)(hi_ff & hi[le_idx]); + lo_00 = (uint8_t)(lo_00 | lo[le_idx]); } if (hi_ff != UINT8_MAX) { - limit_lo[size - 1] = hi[size - 1]; + limit_lo[byte_index] = hi[byte_index]; acl_gen_range(context, hi, limit_lo, size, level, root, *pend); } if (lo_00 != 0) { - limit_hi[size - 1] = lo[size - 1]; + limit_hi[byte_index] = lo[byte_index]; acl_gen_range(context, limit_hi, lo, size, level, root, *pend); } - if (hi[size - 1] - lo[size - 1] > 1 || + if (hi[byte_index] - lo[byte_index] > 1 || lo_00 == 0 || hi_ff == UINT8_MAX) { - limit_lo[size-1] = (uint8_t)(lo[size-1] + (lo_00 != 0)); - limit_hi[size-1] = (uint8_t)(hi[size-1] - + limit_lo[byte_index] = (uint8_t)(lo[byte_index] + + (lo_00 != 0)); + limit_hi[byte_index] = (uint8_t)(hi[byte_index] - (hi_ff != UINT8_MAX)); acl_gen_range(context, limit_hi, limit_lo, size, level, root, *pend); @@ -863,13 +888,17 @@ acl_gen_mask_trie(struct acl_build_context *context, root = acl_alloc_node(context, level++); prev = root; + /* On big endian val and msk point to highest byte. + * Therefore iterate in opposite direction as on + * little endian with helper function + */ for (n = size - 1; n >= 0; n--) { + uint32_t le_idx = get_le_byte_index(n, size); node = acl_alloc_node(context, level++); - acl_gen_mask(&bits, val[n] & msk[n], msk[n]); + acl_gen_mask(&bits, val[le_idx] & msk[le_idx], msk[le_idx]); acl_add_ptr(context, prev, node, &bits); prev = node; } - *pend = prev; return root; } @@ -927,6 +956,14 @@ build_trie(struct acl_build_context *context, struct rte_acl_build_rule *head, fld->mask_range.u32, rule->config->defs[n].size); + /* Fields are aligned highest to lowest bit. + * Masked needs to be shifted to follow same + * convention + */ +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + mask = mask << 32; +#endif + /* gen a mini-trie for this field */ merge = acl_gen_mask_trie(context, &fld->value, @@ -1017,6 +1054,14 @@ acl_calc_wildness(struct rte_acl_build_rule *head, uint32_t bit_len = CHAR_BIT * config->defs[n].size; uint64_t msk_val = RTE_LEN2MASK(bit_len, typeof(msk_val)); + + /* Fields are aligned highest to lowest bit. + * Masked needs to be shifted to follow same + * convention + */ + if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) + msk_val <<= 32; + double size = bit_len; int field_index = config->defs[n].field_index; const struct rte_acl_field *fld = rule->f->field + diff --git a/lib/librte_acl/acl_gen.c b/lib/librte_acl/acl_gen.c index 35a0140b4..b4e8df0ce 100644 --- a/lib/librte_acl/acl_gen.c +++ b/lib/librte_acl/acl_gen.c @@ -360,7 +360,16 @@ acl_gen_node(struct rte_acl_node *node, uint64_t *node_array, array_ptr = &node_array[index->quad_index]; acl_add_ptrs(node, array_ptr, no_match, 0); qtrp = (uint32_t *)node->transitions; + + /* Swap qtrp on big endian that transitions[0] + * is at least signifcant byte. + */ +#if __BYTE_ORDER == __ORDER_BIG_ENDIAN__ + node->node_index = __bswap_32(qtrp[0]); +#else node->node_index = qtrp[0]; +#endif + node->node_index <<= sizeof(index->quad_index) * CHAR_BIT; node->node_index |= index->quad_index | node->node_type; index->quad_index += node->fanout; diff --git a/lib/librte_acl/acl_run_scalar.c b/lib/librte_acl/acl_run_scalar.c index 3d61e7940..9f01ef8d8 100644 --- a/lib/librte_acl/acl_run_scalar.c +++ b/lib/librte_acl/acl_run_scalar.c @@ -141,6 +141,14 @@ rte_acl_classify_scalar(const struct rte_acl_ctx *ctx, const uint8_t **data, input0 = GET_NEXT_4BYTES(parms, 0); input1 = GET_NEXT_4BYTES(parms, 1); + /* input needs to be swapped because the rules get + * swapped while building the trie. + */ +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + input0 = __bswap_32(input0); + input1 = __bswap_32(input1); +#endif + for (n = 0; n < 4; n++) { transition0 = scalar_transition(flows.trans, diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c index c436a9bfd..6d4d3f239 100644 --- a/lib/librte_acl/rte_acl.c +++ b/lib/librte_acl/rte_acl.c @@ -64,6 +64,8 @@ static const rte_acl_classify_t classify_fns[] = { [RTE_ACL_CLASSIFY_AVX2] = rte_acl_classify_avx2, [RTE_ACL_CLASSIFY_NEON] = rte_acl_classify_neon, [RTE_ACL_CLASSIFY_ALTIVEC] = rte_acl_classify_altivec, + /* use scalar for s390x for now */ + [RTE_ACL_CLASSIFY_S390X] = rte_acl_classify_scalar, }; /* by default, use always available scalar code path. */ @@ -103,6 +105,8 @@ RTE_INIT(rte_acl_init) alg = RTE_ACL_CLASSIFY_NEON; #elif defined(RTE_ARCH_PPC_64) alg = RTE_ACL_CLASSIFY_ALTIVEC; +#elif defined(RTE_ARCH_S390X) + alg = RTE_ACL_CLASSIFY_S390X; #else #ifdef CC_AVX2_SUPPORT if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) diff --git a/lib/librte_acl/rte_acl.h b/lib/librte_acl/rte_acl.h index aa22e70c6..9537196db 100644 --- a/lib/librte_acl/rte_acl.h +++ b/lib/librte_acl/rte_acl.h @@ -241,6 +241,7 @@ enum rte_acl_classify_alg { RTE_ACL_CLASSIFY_AVX2 = 3, /**< requires AVX2 support. */ RTE_ACL_CLASSIFY_NEON = 4, /**< requires NEON support. */ RTE_ACL_CLASSIFY_ALTIVEC = 5, /**< requires ALTIVEC support. */ + RTE_ACL_CLASSIFY_S390X = 6, /**< requires s390x z13 support. */ RTE_ACL_CLASSIFY_NUM /* should always be the last one. */ }; From patchwork Tue Apr 9 19:06:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52499 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BE77A5B12; Tue, 9 Apr 2019 21:06:49 +0200 (CEST) Received: from mail-qt1-f172.google.com (mail-qt1-f172.google.com [209.85.160.172]) by dpdk.org (Postfix) with ESMTP id F0D295592 for ; Tue, 9 Apr 2019 21:06:38 +0200 (CEST) Received: by mail-qt1-f172.google.com with SMTP id k2so21221822qtm.1 for ; Tue, 09 Apr 2019 12:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=zVUjx3HOTjedokw5s2Af2gBPczyuoMlPhCX6K8N66Vw=; b=qIv9LkTwcW//F6vpdnq2zt+bk/HxBfK1L7vDRsK3ZJIxNwHZFBCT1YTpc2XwMmYPIZ n4U/fY+bdj9FkmYa6YY0JXggNas9BdPpX234mimP5eipFiPbSh8/HZTbsNcDF+kPhIS8 dY5MkDL0HpKTXDINcEeQQl3yNS8j2sbw830pqdMQkcmzVyKOwIq0vl5jDIGZ1BXa6Koq JJmzxj02uwJudqG8p9n5qrw2Qm/6/5DS5dCPCjSQoHFHt4eUjjnYDmddDXwtpYbZ4lRG GjYFqGjMlbNmFv2OBn3j9zQ7VGGaPM8uga9EEXbrwWV+0mgoT7JvkhWiV7U74gOglUjX jI8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=zVUjx3HOTjedokw5s2Af2gBPczyuoMlPhCX6K8N66Vw=; b=qy09vSZ1NGuuF5jcDNeA06pc/yM4C2JVKt//rEdF9OvBwF5Rh2Vyy5njkRHAuqg0+5 Szowpy8L3CCI6SL1ibinU9A6mEWJLOHWo2MslYinIIGYPqJNnTJbCP8gRHAa2pgZPmjw WhjhmVjDWsZh24g8FxV4y711qYAMtqRyYg4bnXCBMzudXaI87IHhvUzMc6fJ6VPPVLUV JfqmUQtX0nIbWp/8YDyBAfzVAscoQGTDD2thjiBoLhJjVX5fWZ8QFBDRg/96ANMhjrot FT8T9nWtdFGzFXmSEHMhAKtA2/UoqhhaXy98Za5fekJdFnM2t/G3CGvwBrvslziERRiw PUDw== X-Gm-Message-State: APjAAAVAhZhAnuspVGYvDhfgNjGca/ye4mZimQwYaC+kWkjpkBjUvjnz 4gDMPHGJz33vhFa04VNYfddLJXOlfDI= X-Google-Smtp-Source: APXvYqzfenXk5RbqKZYl+jrrBQYqI+CaiqgApYXxNWjDzZJjAeKlghAEHFbHhOhqj6v6Jp1su6mOvg== X-Received: by 2002:ac8:348d:: with SMTP id w13mr33086249qtb.329.1554836797928; Tue, 09 Apr 2019 12:06:37 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.36 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:36 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:22 -0400 Message-Id: <20190409190630.31975-5-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 04/12] lpm: add support for s390x architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add big endian support for s390x architecture. Signed-off-by: Vivian Kong --- lib/librte_lpm/Makefile | 2 + lib/librte_lpm/meson.build | 2 +- lib/librte_lpm/rte_lpm.h | 2 + lib/librte_lpm/rte_lpm6.c | 26 ++++++- lib/librte_lpm/rte_lpm_s390x.h | 130 +++++++++++++++++++++++++++++++++ 5 files changed, 157 insertions(+), 5 deletions(-) create mode 100644 lib/librte_lpm/rte_lpm_s390x.h diff --git a/lib/librte_lpm/Makefile b/lib/librte_lpm/Makefile index a7946a1c5..16b868304 100644 --- a/lib/librte_lpm/Makefile +++ b/lib/librte_lpm/Makefile @@ -26,6 +26,8 @@ else ifeq ($(CONFIG_RTE_ARCH_X86),y) SYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include += rte_lpm_sse.h else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y) SYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include += rte_lpm_altivec.h +else ifeq ($(CONFIG_RTE_ARCH_S390X),y) +SYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include += rte_lpm_s390x.h endif include $(RTE_SDK)/mk/rte.lib.mk diff --git a/lib/librte_lpm/meson.build b/lib/librte_lpm/meson.build index a5176d8ae..68317ed52 100644 --- a/lib/librte_lpm/meson.build +++ b/lib/librte_lpm/meson.build @@ -6,5 +6,5 @@ sources = files('rte_lpm.c', 'rte_lpm6.c') headers = files('rte_lpm.h', 'rte_lpm6.h') # since header files have different names, we can install all vector headers # without worrying about which architecture we actually need -headers += files('rte_lpm_altivec.h', 'rte_lpm_neon.h', 'rte_lpm_sse.h') +headers += files('rte_lpm_s390x.h', 'rte_lpm_altivec.h', 'rte_lpm_neon.h', 'rte_lpm_sse.h') deps += ['hash'] diff --git a/lib/librte_lpm/rte_lpm.h b/lib/librte_lpm/rte_lpm.h index 21550444d..aa8a43968 100644 --- a/lib/librte_lpm/rte_lpm.h +++ b/lib/librte_lpm/rte_lpm.h @@ -459,6 +459,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], #include "rte_lpm_neon.h" #elif defined(RTE_ARCH_PPC_64) #include "rte_lpm_altivec.h" +#elif defined(RTE_ARCH_S390X) +#include "rte_lpm_s390x.h" #else #include "rte_lpm_sse.h" #endif diff --git a/lib/librte_lpm/rte_lpm6.c b/lib/librte_lpm/rte_lpm6.c index a91803113..7aead4035 100644 --- a/lib/librte_lpm/rte_lpm6.c +++ b/lib/librte_lpm/rte_lpm6.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2010-2014 Intel Corporation */ + #include #include #include @@ -24,6 +25,7 @@ #include #include #include +#include #include "rte_lpm6.h" @@ -58,17 +60,33 @@ static struct rte_tailq_elem rte_lpm6_tailq = { }; EAL_REGISTER_TAILQ(rte_lpm6_tailq) +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + /** Tbl entry structure. It is the same for both tbl24 and tbl8 */ struct rte_lpm6_tbl_entry { - uint32_t next_hop: 21; /**< Next hop / next table to be checked. */ - uint32_t depth :8; /**< Rule depth. */ + uint32_t next_hop :21; /**< Next hop / next table to be checked. */ + uint32_t depth :8; /**< Rule depth. */ + + /* Flags. */ + uint32_t valid :1; /**< Validation flag. */ + uint32_t valid_group :1; /**< Group validation flag. */ + uint32_t ext_entry :1; /**< External entry. */ +}; + +#else +struct rte_lpm6_tbl_entry { /* Flags. */ - uint32_t valid :1; /**< Validation flag. */ + uint32_t ext_entry :1; /**< External entry. */ uint32_t valid_group :1; /**< Group validation flag. */ - uint32_t ext_entry :1; /**< External entry. */ + uint32_t valid :1; /**< Validation flag. */ + + uint32_t depth :8; /**< Rule depth. */ + uint32_t next_hop :21; /**< Next hop / next table to be checked. */ }; +#endif + /** Rules tbl entry structure. */ struct rte_lpm6_rule { uint8_t ip[RTE_LPM6_IPV6_ADDR_SIZE]; /**< Rule IP address. */ diff --git a/lib/librte_lpm/rte_lpm_s390x.h b/lib/librte_lpm/rte_lpm_s390x.h new file mode 100644 index 000000000..eb1fdd450 --- /dev/null +++ b/lib/librte_lpm/rte_lpm_s390x.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * (c) Copyright IBM Corp. 2016, 2018 + */ + +#ifndef _RTE_LPM_S390X_H_ +#define _RTE_LPM_S390X_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void +rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], + uint32_t defv) +{ + typedef int vector_signed_int + __attribute__((vector_size(4*sizeof(int)))); + vector_signed_int i24; + rte_xmm_t i8; + uint32_t tbl[4]; + uint64_t idx, pt, pt2; + const uint32_t *ptbl; + + const uint32_t mask = UINT8_MAX; + const vector_signed_int mask8 = (xmm_t){mask, mask, mask, mask}; + + /* + * RTE_LPM_VALID_EXT_ENTRY_BITMASK for 2 LPM entries + * as one 64-bit value (0x0300000003000000). + */ + const uint64_t mask_xv = + ((uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK | + (uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 32); + + /* + * RTE_LPM_LOOKUP_SUCCESS for 2 LPM entries + * as one 64-bit value (0x0100000001000000). + */ + const uint64_t mask_v = + ((uint64_t)RTE_LPM_LOOKUP_SUCCESS | + (uint64_t)RTE_LPM_LOOKUP_SUCCESS << 32); + + /* get 4 indexes for tbl24[]. */ + i24[0] = (uint32_t)ip[0] >> 8; + i24[1] = (uint32_t)ip[1] >> 8; + i24[2] = (uint32_t)ip[2] >> 8; + i24[3] = (uint32_t)ip[3] >> 8; + + /* extract values from tbl24[] */ + idx = (uint32_t)i24[0]; + idx = idx < (1<<24) ? idx : (1<<24)-1; + ptbl = (const uint32_t *)&lpm->tbl24[idx]; + tbl[0] = *ptbl; + + idx = (uint32_t) i24[1]; + idx = idx < (1<<24) ? idx : (1<<24)-1; + ptbl = (const uint32_t *)&lpm->tbl24[idx]; + tbl[1] = *ptbl; + + idx = (uint32_t) i24[2]; + idx = idx < (1<<24) ? idx : (1<<24)-1; + ptbl = (const uint32_t *)&lpm->tbl24[idx]; + tbl[2] = *ptbl; + + idx = (uint32_t) i24[3]; + idx = idx < (1<<24) ? idx : (1<<24)-1; + ptbl = (const uint32_t *)&lpm->tbl24[idx]; + tbl[3] = *ptbl; + + /* get 4 indexes for tbl8[]. */ + i8.x = vec_and(ip, mask8); + + pt = (uint64_t)tbl[0] | + (uint64_t)tbl[1] << 32; + pt2 = (uint64_t)tbl[2] | + (uint64_t)tbl[3] << 32; + + /* search successfully finished for all 4 IP addresses. */ + if (likely((pt & mask_xv) == mask_v) && + likely((pt2 & mask_xv) == mask_v)) { + *(uint64_t *)hop = pt & RTE_LPM_MASKX4_RES; + *(uint64_t *)(hop + 2) = pt2 & RTE_LPM_MASKX4_RES; + return; + } + + if (unlikely((pt & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[0] = i8.u32[0] + + (uint8_t)tbl[0] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[0]]; + tbl[0] = *ptbl; + } + if (unlikely((pt >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[1] = i8.u32[1] + + (uint8_t)tbl[1] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[1]]; + tbl[1] = *ptbl; + } + if (unlikely((pt2 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[2] = i8.u32[2] + + (uint8_t)tbl[2] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[2]]; + tbl[2] = *ptbl; + } + if (unlikely((pt2 >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[3] = i8.u32[3] + + (uint8_t)tbl[3] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[3]]; + tbl[3] = *ptbl; + } + + hop[0] = (tbl[0] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[0] & 0x00FFFFFF : defv; + hop[1] = (tbl[1] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[1] & 0x00FFFFFF : defv; + hop[2] = (tbl[2] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[2] & 0x00FFFFFF : defv; + hop[3] = (tbl[3] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[3] & 0x00FFFFFF : defv; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_LPM_S390X_H_ */ From patchwork Tue Apr 9 19:06:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52500 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7F7255B1E; Tue, 9 Apr 2019 21:06:53 +0200 (CEST) Received: from mail-qk1-f193.google.com (mail-qk1-f193.google.com [209.85.222.193]) by dpdk.org (Postfix) with ESMTP id 792445592 for ; Tue, 9 Apr 2019 21:06:40 +0200 (CEST) Received: by mail-qk1-f193.google.com with SMTP id z76so10948216qkb.12 for ; Tue, 09 Apr 2019 12:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=AxiKphG82uiqiMvMNBUOW46rprdwlz2bWijFChj0I00=; b=XPKIafs4yAUSI0J+OkaBGjYhdoBcacHaWOS3IPVOVluDKmZWIGv8BoZ5h5GBwTYl2x 5EgnbQo2gdfxyAmWpeBrKg/UvWPF+fVupxdli9qa7T5RhvndGi1m+H0Xbz0ZXxlMDusP u1gCggXhf6N0z0no/y2DuJyyyPELSSHzGNa+tqCCrEy9uYv8DgCy3VQLNTT+/PZuiIYG iN92THYNwJDms+EuTBToF40/yXHKUDrDTIgewq/4LZVgTv/glaA6gMALqyqBU021eC/F yoiF7TygIz+rgq/+zL9V8NS0CTwVej/ROm/yQNYTT/B4caHt7TJwF+IK6myAcHQuu8OL xZjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=AxiKphG82uiqiMvMNBUOW46rprdwlz2bWijFChj0I00=; b=Npuzo7u+8UZ4oA9KNJp8WuejBibc2+XgDGByBwNLsZWTvOfonbqa1UQAY9k0vm+D5k 7Ugi6EAl5y7w0o753VvG22raWL0x6H73chLJNvwNXmFGLM6JR+nPoAcsplnPyG4nQbur +VEdED7x4hO9uD3RQ+m3os1kt/rPV2iJpr1zqvsw11ppKcA/XpiI1W6mTSupt4gx4bIJ y+WHxSEJ4ilsMysm5+Dux4L4HrcqOkOESG8sF2Lc7oRAPV03e20k78Sun1K2GEo4nRcZ 14L/UP2pbu3reqNxB0Msja/jcayY5eTD5I9uvkMvbQamYLZjFdn+JM694mH+18/GU/eZ QYgA== X-Gm-Message-State: APjAAAWetOmheWELzs1msY1Dcz7JMzzb64zHKwfjOa47N9iYgswKjkXx Opgdl3XyHC6oD13LfYJj56p/hFkrVoc= X-Google-Smtp-Source: APXvYqwzBI6cfbZEzCTopb4+yTSP+BbLYJ8+buVU5dBa1SEQLqRYutKwT4EepQU5ecdMROni7NPl2Q== X-Received: by 2002:a37:4f95:: with SMTP id d143mr30222430qkb.253.1554836799343; Tue, 09 Apr 2019 12:06:39 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:38 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:23 -0400 Message-Id: <20190409190630.31975-6-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 05/12] examples/l3fwd: add support for s390x architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add s390x specific implementation. Signed-off-by: Vivian Kong --- examples/l3fwd/l3fwd_em.c | 8 + examples/l3fwd/l3fwd_lpm_s390x.h | 137 ++++++++++++++++ examples/l3fwd/l3fwd_s390x.h | 259 +++++++++++++++++++++++++++++++ 3 files changed, 404 insertions(+) create mode 100644 examples/l3fwd/l3fwd_lpm_s390x.h create mode 100644 examples/l3fwd/l3fwd_s390x.h diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c index fa8f82be6..a486a9c57 100644 --- a/examples/l3fwd/l3fwd_em.c +++ b/examples/l3fwd/l3fwd_em.c @@ -240,6 +240,14 @@ em_mask_key(void *key, xmm_t mask) return vec_and(data, mask); } +#elif defined(RTE_MACHINE_CPUFLAG_ZARCH) +static inline xmm_t +em_mask_key(void *key, xmm_t mask) +{ + xmm_t data = (xmm_t) vec_xld2(0, (unsigned int *)(key)); + + return data + mask; +} #else #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain #endif diff --git a/examples/l3fwd/l3fwd_lpm_s390x.h b/examples/l3fwd/l3fwd_lpm_s390x.h new file mode 100644 index 000000000..858f696ba --- /dev/null +++ b/examples/l3fwd/l3fwd_lpm_s390x.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2010-2016 Intel Corporation. + * (c) Copyright IBM Corp. 2017, 2019 + */ +#ifndef __L3FWD_LPM_S390X_H__ +#define __L3FWD_LPM_S390X_H__ + +#include "l3fwd_s390x.h" + +typedef unsigned char vector_unsigned_char + __attribute__((vector_size(16*sizeof(unsigned char)))); + +/* + * Read packet_type and destination IPV4 addresses from 4 mbufs. + */ +static inline void +processx4_step1(struct rte_mbuf *pkt[FWDSTEP], + vector_unsigned_int *dip, + uint32_t *ipv4_flag) +{ + struct ipv4_hdr *ipv4_hdr; + struct ether_hdr *eth_hdr; + uint32_t x0, x1, x2, x3; + + eth_hdr = rte_pktmbuf_mtod(pkt[0], struct ether_hdr *); + ipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1); + x0 = ipv4_hdr->dst_addr; + ipv4_flag[0] = pkt[0]->packet_type & RTE_PTYPE_L3_IPV4; + + rte_compiler_barrier(); + eth_hdr = rte_pktmbuf_mtod(pkt[1], struct ether_hdr *); + ipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1); + x1 = ipv4_hdr->dst_addr; + ipv4_flag[0] &= pkt[1]->packet_type; + + rte_compiler_barrier(); + eth_hdr = rte_pktmbuf_mtod(pkt[2], struct ether_hdr *); + ipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1); + x2 = ipv4_hdr->dst_addr; + ipv4_flag[0] &= pkt[2]->packet_type; + + rte_compiler_barrier(); + eth_hdr = rte_pktmbuf_mtod(pkt[3], struct ether_hdr *); + ipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1); + x3 = ipv4_hdr->dst_addr; + ipv4_flag[0] &= pkt[3]->packet_type; + + rte_compiler_barrier(); + dip[0] = (vector_unsigned_int){x0, x1, x2, x3}; +} + +/* + * Lookup into LPM for destination port. + * If lookup fails, use incoming port (portid) as destination port. + */ +static inline void +processx4_step2(const struct lcore_conf *qconf, + vector_unsigned_int dip, + uint32_t ipv4_flag, + uint8_t portid, + struct rte_mbuf *pkt[FWDSTEP], + uint16_t dprt[FWDSTEP]) +{ + rte_xmm_t dst; + const vector_unsigned_char bswap_mask = (vector_unsigned_char){ + 3, 2, 1, 0, + 7, 6, 5, 4, + 11, 10, 9, 8, + 15, 14, 13, 12}; + + /* Byte swap 4 IPV4 addresses. */ + dip = (vector_unsigned_int)vec_perm(*(vector_unsigned_char *)&dip, + (vector_unsigned_char){}, bswap_mask); + + /* if all 4 packets are IPV4. */ + if (likely(ipv4_flag)) { + rte_lpm_lookupx4(qconf->ipv4_lookup_struct, (xmm_t)dip, + (uint32_t *)&dst, portid); + /* get rid of unused upper 16 bit for each dport. */ + dst.x = (xmm_t)vec_packs(dst.x, dst.x); + *(uint64_t *)dprt = dst.u64[0]; + } else { + dst.x = (xmm_t)dip; + dprt[0] = lpm_get_dst_port_with_ipv4(qconf, pkt[0], + dst.u32[0], portid); + dprt[1] = lpm_get_dst_port_with_ipv4(qconf, pkt[1], + dst.u32[1], portid); + dprt[2] = lpm_get_dst_port_with_ipv4(qconf, pkt[2], + dst.u32[2], portid); + dprt[3] = lpm_get_dst_port_with_ipv4(qconf, pkt[3], + dst.u32[3], portid); + } +} + +/* + * Buffer optimized handling of packets, invoked + * from main_loop. + */ +static inline void +l3fwd_lpm_send_packets(int nb_rx, struct rte_mbuf **pkts_burst, + uint8_t portid, struct lcore_conf *qconf) +{ + int32_t j; + uint16_t dst_port[MAX_PKT_BURST]; + vector_unsigned_int dip[MAX_PKT_BURST / FWDSTEP]; + uint32_t ipv4_flag[MAX_PKT_BURST / FWDSTEP]; + const int32_t k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP); + + for (j = 0; j != k; j += FWDSTEP) + processx4_step1(&pkts_burst[j], &dip[j / FWDSTEP], + &ipv4_flag[j / FWDSTEP]); + + for (j = 0; j != k; j += FWDSTEP) + processx4_step2(qconf, dip[j / FWDSTEP], + ipv4_flag[j / FWDSTEP], + portid, &pkts_burst[j], &dst_port[j]); + + /* Classify last up to 3 packets one by one */ + switch (nb_rx % FWDSTEP) { + case 3: + dst_port[j] = lpm_get_dst_port(qconf, pkts_burst[j], portid); + j++; + /* fall-through */ + case 2: + dst_port[j] = lpm_get_dst_port(qconf, pkts_burst[j], portid); + j++; + /* fall-through */ + case 1: + dst_port[j] = lpm_get_dst_port(qconf, pkts_burst[j], portid); + j++; + /* fall-through */ + } + + send_packets_multi(qconf, pkts_burst, dst_port, nb_rx); +} + +#endif /* __L3FWD_LPM_S390X_H__ */ diff --git a/examples/l3fwd/l3fwd_s390x.h b/examples/l3fwd/l3fwd_s390x.h new file mode 100644 index 000000000..d027092a4 --- /dev/null +++ b/examples/l3fwd/l3fwd_s390x.h @@ -0,0 +1,259 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2016 Intel Corporation. + * (c) Copyright IBM Corp. 2017, 2019 + */ +#ifndef _L3FWD_S390X_H_ +#define _L3FWD_S390X_H_ + +#include "l3fwd.h" +#include "l3fwd_common.h" + +#define vec_sro(a, b) vec_srb(a, (b) << 64) // Vector Shift Right by Octet +typedef unsigned int vector_unsigned_int + __attribute__((vector_size(4*sizeof(unsigned int)))); +typedef unsigned short vector_unsigned_short + __attribute__((vector_size(8*sizeof(unsigned short)))); + +/* + * Update source and destination MAC addresses in the ethernet header. + * Perform RFC1812 checks and updates for IPV4 packets. + */ +static inline void +processx4_step3(struct rte_mbuf *pkt[FWDSTEP], uint16_t dst_port[FWDSTEP]) +{ + vector_unsigned_int te[FWDSTEP]; + vector_unsigned_int ve[FWDSTEP]; + vector_unsigned_int *p[FWDSTEP]; + + p[0] = rte_pktmbuf_mtod(pkt[0], vector_unsigned_int *); + p[1] = rte_pktmbuf_mtod(pkt[1], vector_unsigned_int *); + p[2] = rte_pktmbuf_mtod(pkt[2], vector_unsigned_int *); + p[3] = rte_pktmbuf_mtod(pkt[3], vector_unsigned_int *); + + ve[0] = (vector_unsigned_int)val_eth[dst_port[0]]; + te[0] = *p[0]; + + ve[1] = (vector_unsigned_int)val_eth[dst_port[1]]; + te[1] = *p[1]; + + ve[2] = (vector_unsigned_int)val_eth[dst_port[2]]; + te[2] = *p[2]; + + ve[3] = (vector_unsigned_int)val_eth[dst_port[3]]; + te[3] = *p[3]; + + /* Update first 12 bytes, keep rest bytes intact. */ + te[0] = (vector_unsigned_int)vec_sel( + (vector_unsigned_short)ve[0], + (vector_unsigned_short)te[0], + (vector_unsigned_short) {0, 0, 0, 0, + 0, 0, 0xffff, 0xffff}); + + te[1] = (vector_unsigned_int)vec_sel( + (vector_unsigned_short)ve[1], + (vector_unsigned_short)te[1], + (vector_unsigned_short) {0, 0, 0, 0, + 0, 0, 0xffff, 0xffff}); + + te[2] = (vector_unsigned_int)vec_sel( + (vector_unsigned_short)ve[2], + (vector_unsigned_short)te[2], + (vector_unsigned_short) {0, 0, 0, 0, 0, + 0, 0xffff, 0xffff}); + + te[3] = (vector_unsigned_int)vec_sel( + (vector_unsigned_short)ve[3], + (vector_unsigned_short)te[3], + (vector_unsigned_short) {0, 0, 0, 0, + 0, 0, 0xffff, 0xffff}); + + *p[0] = te[0]; + *p[1] = te[1]; + *p[2] = te[2]; + *p[3] = te[3]; + + rfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[0] + 1), + &dst_port[0], pkt[0]->packet_type); + rfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[1] + 1), + &dst_port[1], pkt[1]->packet_type); + rfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[2] + 1), + &dst_port[2], pkt[2]->packet_type); + rfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[3] + 1), + &dst_port[3], pkt[3]->packet_type); +} + +/* + * Group consecutive packets with the same destination port in bursts of 4. + * Suppose we have array of destination ports: + * dst_port[] = {a, b, c, d,, e, ... } + * dp1 should contain: , dp2: . + * We doing 4 comparisons at once and the result is 4 bit mask. + * This mask is used as an index into prebuild array of pnum values. + */ +static inline uint16_t * +port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp, vector_unsigned_short dp1, + vector_unsigned_short dp2) +{ + union { + uint16_t u16[FWDSTEP + 1]; + uint64_t u64; + } *pnum = (void *)pn; + + int32_t v; + + v = vec_any_eq(dp1, dp2); + + + /* update last port counter. */ + lp[0] += gptbl[v].lpv; + + /* if dest port value has changed. */ + if (v != GRPMSK) { + pnum->u64 = gptbl[v].pnum; + pnum->u16[FWDSTEP] = 1; + lp = pnum->u16 + gptbl[v].idx; + } + + return lp; +} + +/** + * Process one packet: + * Update source and destination MAC addresses in the ethernet header. + * Perform RFC1812 checks and updates for IPV4 packets. + */ +static inline void +process_packet(struct rte_mbuf *pkt, uint16_t *dst_port) +{ + struct ether_hdr *eth_hdr; + vector_unsigned_int te, ve; + + eth_hdr = rte_pktmbuf_mtod(pkt, struct ether_hdr *); + + te = *(vector_unsigned_int *)eth_hdr; + ve = (vector_unsigned_int)val_eth[dst_port[0]]; + + rfc1812_process((struct ipv4_hdr *)(eth_hdr + 1), dst_port, + pkt->packet_type); + + /* dynamically vec_sel te and ve for MASK_ETH (0x3f) */ + te = (vector_unsigned_int)vec_sel( + (vector_unsigned_short)ve, + (vector_unsigned_short)te, + (vector_unsigned_short){0, 0, 0, 0, + 0, 0, 0xffff, 0xffff}); + + *(vector_unsigned_int *)eth_hdr = te; +} + +/** + * Send packets burst from pkts_burst to the ports in dst_port array + */ +static __rte_always_inline void +send_packets_multi(struct lcore_conf *qconf, struct rte_mbuf **pkts_burst, + uint16_t dst_port[MAX_PKT_BURST], int nb_rx) +{ + int32_t k; + int j = 0; + uint16_t dlp; + uint16_t *lp; + uint16_t pnum[MAX_PKT_BURST + 1]; + + /* + * Finish packet processing and group consecutive + * packets with the same destination port. + */ + k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP); + if (k != 0) { + vector_unsigned_short dp1, dp2; + + lp = pnum; + lp[0] = 1; + + processx4_step3(pkts_burst, dst_port); + + /* dp1: */ + dp1 = *(vector_unsigned_short *)dst_port; + + for (j = FWDSTEP; j != k; j += FWDSTEP) { + processx4_step3(&pkts_burst[j], &dst_port[j]); + + /* + * dp2: + * + */ + dp2 = *((vector_unsigned_short *) + &dst_port[j - FWDSTEP + 1]); + lp = port_groupx4(&pnum[j - FWDSTEP], lp, dp1, dp2); + + /* + * dp1: + * + */ + dp1 = vec_sro(dp2, (vector unsigned char) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, (FWDSTEP - 1) * sizeof(dst_port[0])}); + } + + /* + * dp2: + */ + dp2 = vec_perm(dp1, (vector_unsigned_short){}, + (vector unsigned char) {0xf9}); + lp = port_groupx4(&pnum[j - FWDSTEP], lp, dp1, dp2); + + /* + * remove values added by the last repeated + * dst port. + */ + lp[0]--; + dlp = dst_port[j - 1]; + } else { + /* set dlp and lp to the never used values. */ + dlp = BAD_PORT - 1; + lp = pnum + MAX_PKT_BURST; + } + + /* Process up to last 3 packets one by one. */ + switch (nb_rx % FWDSTEP) { + case 3: + process_packet(pkts_burst[j], dst_port + j); + GROUP_PORT_STEP(dlp, dst_port, lp, pnum, j); + j++; + /* fall-through */ + case 2: + process_packet(pkts_burst[j], dst_port + j); + GROUP_PORT_STEP(dlp, dst_port, lp, pnum, j); + j++; + /* fall-through */ + case 1: + process_packet(pkts_burst[j], dst_port + j); + GROUP_PORT_STEP(dlp, dst_port, lp, pnum, j); + j++; + } + + /* + * Send packets out, through destination port. + * Consecutive packets with the same destination port + * are already grouped together. + * If destination port for the packet equals BAD_PORT, + * then free the packet without sending it out. + */ + for (j = 0; j < nb_rx; j += k) { + + int32_t m; + uint16_t pn; + + pn = dst_port[j]; + k = pnum[j]; + + if (likely(pn != BAD_PORT)) + send_packetsx4(qconf, pn, pkts_burst + j, k); + else + for (m = j; m != j + k; m++) + rte_pktmbuf_free(pkts_burst[m]); + + } +} + +#endif /* _L3FWD_S390X_H_ */ From patchwork Tue Apr 9 19:06:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52501 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1D0625B34; Tue, 9 Apr 2019 21:06:57 +0200 (CEST) Received: from mail-qt1-f195.google.com (mail-qt1-f195.google.com [209.85.160.195]) by dpdk.org (Postfix) with ESMTP id 510445689 for ; Tue, 9 Apr 2019 21:06:42 +0200 (CEST) Received: by mail-qt1-f195.google.com with SMTP id v20so21113561qtv.12 for ; Tue, 09 Apr 2019 12:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=MrwCmaa8+w4XyKn78I56FttoUZvb8kjswQcVZcFFDZQ=; b=l6Ktc9pnUVtyyOLFis/pkHQvA8ElRDK+HcFjQPCn1o1Zt88IaBQKjFIpI3qUDVPtYK yaGVbDbRmi450+mhEWryFzVENcAihLBIZfwR0y6sddCIEazQXJcGMTJAsyVcTdx4MNrk ZvOPD82ekgJLbLV8Lkrc6rFI6bqzKmc+zexyAH530vS9MSlQLIu/or1PRbhqJbju8PUN c3rw26NePCZFzbyt4o1baC2BsTPaGspa6FHQHs7RpXTDiYemB+z/JwOKT0jYLJ0Uapey JBYSoF01sML93d5fujLzUGf9QjG2Cjp/xkQI3FeN1DBTl0NbCquFm3nOPACnt8F9BtZ3 dKEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=MrwCmaa8+w4XyKn78I56FttoUZvb8kjswQcVZcFFDZQ=; b=lZ2bv8YsOxLucXYmFsGvxwvcfVt5VyBZHg93NGssciZ6KIc1o2y0Kj18DwAThxoanT ijERp07jhky4OannDOa1n106O5vT7mXaRAdLJzskiAw355kvAqt9lNdqPbCUByUHA7xj x6kbaULT9wVXrdKSYr26EcTLddh3KDRzUqF9cigKJWcDwvTxBbinv3N8hpijXwS4f9kw NXphcjPjUWVVwQ1oO7jeyxZtl84dih2DzZ+6cgxK5Q94VkBvCCjQZQPshMzu2YPJKerD /33QvRirzCNU1FOzsvUVF2hlJBxD2clZG0Ptb5Gk83e0lzuxDTVVjI3uoeMp2ZCgv+jx DZlQ== X-Gm-Message-State: APjAAAUlhIGionQuYmqP7RP3sYR3acJIuJIPdxadfoNg1TulW2rWDwqq /1I6WP5zYgs0ScWPTl+c/T2mrtzm6Mg= X-Google-Smtp-Source: APXvYqyBpaUw4lKvYSulISN2RZazJNpQPgpGV13hpcyNl3CVLTzC5Yp3DezSvxrpUeYqX07dnd8Z2A== X-Received: by 2002:ac8:8b9:: with SMTP id v54mr32965250qth.64.1554836800965; Tue, 09 Apr 2019 12:06:40 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.39 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:39 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:24 -0400 Message-Id: <20190409190630.31975-7-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 06/12] net/i40e: add support for s390x architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Enable i40e and i40e vector support on s390x. Signed-off-by: Vivian Kong --- doc/guides/nics/features/i40e.ini | 1 + doc/guides/nics/features/i40e_vec.ini | 1 + drivers/net/i40e/Makefile | 2 + drivers/net/i40e/i40e_rxtx_vec_s390x.c | 631 +++++++++++++++++++++++++ 4 files changed, 635 insertions(+) create mode 100644 drivers/net/i40e/i40e_rxtx_vec_s390x.c diff --git a/doc/guides/nics/features/i40e.ini b/doc/guides/nics/features/i40e.ini index 16eab7f43..0c1acfc23 100644 --- a/doc/guides/nics/features/i40e.ini +++ b/doc/guides/nics/features/i40e.ini @@ -55,3 +55,4 @@ x86-32 = Y x86-64 = Y ARMv8 = Y Power8 = Y +s390x = Y diff --git a/doc/guides/nics/features/i40e_vec.ini b/doc/guides/nics/features/i40e_vec.ini index c65e8b036..8c5062698 100644 --- a/doc/guides/nics/features/i40e_vec.ini +++ b/doc/guides/nics/features/i40e_vec.ini @@ -43,3 +43,4 @@ x86-32 = Y x86-64 = Y ARMv8 = Y Power8 = Y +s390x = Y diff --git a/drivers/net/i40e/Makefile b/drivers/net/i40e/Makefile index 3f869a8d6..d13223cc9 100644 --- a/drivers/net/i40e/Makefile +++ b/drivers/net/i40e/Makefile @@ -78,6 +78,8 @@ ifeq ($(CONFIG_RTE_ARCH_ARM64),y) SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_neon.c else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y) SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_altivec.c +else ifeq ($(CONFIG_RTE_ARCH_S390X),y) +SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_s390x.c else SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_sse.c endif diff --git a/drivers/net/i40e/i40e_rxtx_vec_s390x.c b/drivers/net/i40e/i40e_rxtx_vec_s390x.c new file mode 100644 index 000000000..b35ab0678 --- /dev/null +++ b/drivers/net/i40e/i40e_rxtx_vec_s390x.c @@ -0,0 +1,631 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * (c) Copyright IBM Corp. 2017, 2019 + */ + +#include +#include +#include +#include + +#include "base/i40e_prototype.h" +#include "base/i40e_type.h" +#include "i40e_ethdev.h" +#include "i40e_rxtx.h" +#include "i40e_rxtx_vec_common.h" + +#pragma GCC diagnostic ignored "-Wcast-qual" + +typedef unsigned long long vector_unsigned_long_long + __attribute__((vector_size(2 * sizeof(unsigned long long)))); +typedef unsigned int vector_unsigned_int + __attribute__((vector_size(4 * sizeof(unsigned int)))); +typedef unsigned short vector_unsigned_short + __attribute__((vector_size(8 * sizeof(unsigned short)))); +typedef unsigned char vector_unsigned_char + __attribute__((vector_size(16 * sizeof(unsigned char)))); + + +static inline void +i40e_rxq_rearm(struct i40e_rx_queue *rxq) +{ + int i; + uint16_t rx_id; + volatile union i40e_rx_desc *rxdp; + + struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start]; + struct rte_mbuf *mb0, *mb1; + + vector_unsigned_long_long hdr_room = (vector_unsigned_long_long){ + RTE_PKTMBUF_HEADROOM, + RTE_PKTMBUF_HEADROOM}; + vector_unsigned_long_long dma_addr0, dma_addr1; + + rxdp = rxq->rx_ring + rxq->rxrearm_start; + + /* Pull 'n' more MBUFs into the software ring */ + if (rte_mempool_get_bulk(rxq->mp, + (void *)rxep, + RTE_I40E_RXQ_REARM_THRESH) < 0) { + if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >= + rxq->nb_rx_desc) { + dma_addr0 = (vector_unsigned_long_long){}; + for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) { + rxep[i].mbuf = &rxq->fake_mbuf; + vec_xstd2(dma_addr0, 0, + (unsigned long long *)&rxdp[i].read); + } + } + rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed += + RTE_I40E_RXQ_REARM_THRESH; + return; + } + + /* Initialize the mbufs in vector, process 2 mbufs in one loop */ + for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) { + vector_unsigned_long_long vaddr0, vaddr1; + uintptr_t p0, p1; + + mb0 = rxep[0].mbuf; + mb1 = rxep[1].mbuf; + + /* Flush mbuf with pkt template. + * Data to be rearmed is 6 bytes long. + * Though, RX will overwrite ol_flags that are coming next + * anyway. So overwrite whole 8 bytes with one load: + * 6 bytes of rearm_data plus first 2 bytes of ol_flags. + */ + p0 = (uintptr_t)&mb0->rearm_data; + *(uint64_t *)p0 = rxq->mbuf_initializer; + p1 = (uintptr_t)&mb1->rearm_data; + *(uint64_t *)p1 = rxq->mbuf_initializer; + + /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */ + vaddr0 = vec_xld2(0, (unsigned long long *)&mb0->buf_addr); + vaddr1 = vec_xld2(0, (unsigned long long *)&mb1->buf_addr); + + /* convert pa to dma_addr hdr/data */ + dma_addr0 = vec_mergel(vaddr0, vaddr0); + dma_addr1 = vec_mergel(vaddr1, vaddr1); + + /* add headroom to pa values */ + dma_addr0 = dma_addr0 + hdr_room; + dma_addr1 = dma_addr1 + hdr_room; + + /* flush desc with pa dma_addr */ + vec_xstd2(dma_addr0, 0, (unsigned long long *)&rxdp++->read); + vec_xstd2(dma_addr1, 0, (unsigned long long *)&rxdp++->read); + } + + rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH; + if (rxq->rxrearm_start >= rxq->nb_rx_desc) + rxq->rxrearm_start = 0; + + rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH; + + rx_id = (uint16_t)((rxq->rxrearm_start == 0) ? + (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1)); + + /* Update the tail pointer on the NIC */ + I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id); +} + +static inline void +desc_to_olflags_v(vector_unsigned_long_long descs[4], struct rte_mbuf **rx_pkts) +{ + vector_unsigned_int vlan0, vlan1, rss, l3_l4e; + + /* mask everything except RSS, flow director and VLAN flags + * bit2 is for VLAN tag, bit11 for flow director indication + * bit13:12 for RSS indication. + */ + const vector_unsigned_int rss_vlan_msk = (vector_unsigned_int){ + (int32_t)0x1c03804, (int32_t)0x1c03804, + (int32_t)0x1c03804, (int32_t)0x1c03804}; + + /* map rss and vlan type to rss hash and vlan flag */ + const vector_unsigned_char vlan_flags = (vector_unsigned_char){ + 0, 0, 0, 0, + PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0}; + + const vector_unsigned_char rss_flags = (vector_unsigned_char){ + 0, PKT_RX_FDIR, 0, 0, + 0, 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH | PKT_RX_FDIR, + 0, 0, 0, 0, + 0, 0, 0, 0}; + + const vector_unsigned_char l3_l4e_flags = (vector_unsigned_char){ + 0, + PKT_RX_IP_CKSUM_BAD, + PKT_RX_L4_CKSUM_BAD, + PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD, + PKT_RX_EIP_CKSUM_BAD, + PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD, + PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD, + PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD + | PKT_RX_IP_CKSUM_BAD, + 0, 0, 0, 0, 0, 0, 0, 0}; + + vlan0 = (vector_unsigned_int)vec_mergel(descs[0], descs[1]); + vlan1 = (vector_unsigned_int)vec_mergel(descs[2], descs[3]); + vlan0 = (vector_unsigned_int)vec_mergeh(vlan0, vlan1); + + vlan1 = vec_and(vlan0, rss_vlan_msk); + vlan0 = (vector_unsigned_int)vec_perm(vlan_flags, + (vector_unsigned_char){}, + *(vector_unsigned_char *)&vlan1); + + rss[0] = (uint32_t)vlan1[0] >> 11; + rss[1] = (uint32_t)vlan1[1] >> 11; + rss[2] = (uint32_t)vlan1[2] >> 11; + rss[3] = (uint32_t)vlan1[3] >> 11; + rss = (vector_unsigned_int)vec_perm(rss_flags, (vector_unsigned_char){}, + *(vector_unsigned_char *)&rss); + + l3_l4e[0] = (uint32_t)vlan1[0] >> 22; + l3_l4e[1] = (uint32_t)vlan1[1] >> 22; + l3_l4e[2] = (uint32_t)vlan1[2] >> 22; + l3_l4e[3] = (uint32_t)vlan1[3] >> 22; + + l3_l4e = (vector_unsigned_int)vec_perm(l3_l4e_flags, + (vector_unsigned_char){}, + *(vector_unsigned_char *)&l3_l4e); + + vlan0 = vec_or(vlan0, rss); + vlan0 = vec_or(vlan0, l3_l4e); + + rx_pkts[0]->ol_flags = (uint64_t)vlan0[2]; + rx_pkts[1]->ol_flags = (uint64_t)vlan0[3]; + rx_pkts[2]->ol_flags = (uint64_t)vlan0[0]; + rx_pkts[3]->ol_flags = (uint64_t)vlan0[1]; +} + +#define PKTLEN_SHIFT 10 + +static inline void +desc_to_ptype_v(vector_unsigned_long_long descs[4], struct rte_mbuf **rx_pkts, + uint32_t *ptype_tbl) +{ + vector_unsigned_long_long ptype0 = vec_mergel(descs[0], descs[1]); + vector_unsigned_long_long ptype1 = vec_mergel(descs[2], descs[3]); + + ptype0[0] = ptype0[0] >> 30; + ptype0[1] = ptype0[1] >> 30; + + ptype1[0] = ptype1[0] >> 30; + ptype1[1] = ptype1[1] >> 30; + + rx_pkts[0]->packet_type = + ptype_tbl[(*(vector_unsigned_char *)&ptype0)[0]]; + rx_pkts[1]->packet_type = + ptype_tbl[(*(vector_unsigned_char *)&ptype0)[8]]; + rx_pkts[2]->packet_type = + ptype_tbl[(*(vector_unsigned_char *)&ptype1)[0]]; + rx_pkts[3]->packet_type = + ptype_tbl[(*(vector_unsigned_char *)&ptype1)[8]]; +} + + /* Notice: + * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet + * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST + * numbers of DD bits + */ +static inline uint16_t +_recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts, uint8_t *split_packet) +{ + volatile union i40e_rx_desc *rxdp; + struct i40e_rx_entry *sw_ring; + uint16_t nb_pkts_recd; + int pos; + uint64_t var; + vector_unsigned_char shuf_msk; + uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; + + vector_unsigned_short crc_adjust = (vector_unsigned_short){ + 0, 0, /* ignore pkt_type field */ + rxq->crc_len, /* sub crc on pkt_len */ + 0, /* ignore high-16bits of pkt_len */ + rxq->crc_len, /* sub crc on data_len */ + 0, 0, 0 /* ignore non-length fields */ + }; + vector_unsigned_long_long dd_check, eop_check; + + /* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */ + nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST); + + /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */ + nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP); + + /* Just the act of getting into the function from the application is + * going to cost about 7 cycles + */ + rxdp = rxq->rx_ring + rxq->rx_tail; + + rte_prefetch0(rxdp); + + /* See if we need to rearm the RX queue - gives the prefetch a bit + * of time to act + */ + if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH) + i40e_rxq_rearm(rxq); + + /* Before we start moving massive data around, check to see if + * there is actually a packet available + */ + if (!(rxdp->wb.qword1.status_error_len & + rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT))) + return 0; + + /* 4 packets DD mask */ + dd_check = (vector_unsigned_long_long){0x0000000100000001ULL, + 0x0000000100000001ULL}; + + /* 4 packets EOP mask */ + eop_check = (vector_unsigned_long_long){0x0000000200000002ULL, + 0x0000000200000002ULL}; + + /* mask to shuffle from desc. to mbuf */ + shuf_msk = (vector_unsigned_char){ + 0xFF, 0xFF, /* pkt_type set as unknown */ + 0xFF, 0xFF, /* pkt_type set as unknown */ + 14, 15, /* octet 15~14, low 16 bits pkt_len */ + 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */ + 14, 15, /* octet 15~14, 16 bits data_len */ + 2, 3, /* octet 2~3, low 16 bits vlan_macip */ + 4, 5, 6, 7 /* octet 4~7, 32bits rss */ + }; + + /* Cache is empty -> need to scan the buffer rings, but first move + * the next 'n' mbufs into the cache + */ + sw_ring = &rxq->sw_ring[rxq->rx_tail]; + + /* A. load 4 packet in one loop + * [A*. mask out 4 unused dirty field in desc] + * B. copy 4 mbuf point from swring to rx_pkts + * C. calc the number of DD bits among the 4 packets + * [C*. extract the end-of-packet bit, if requested] + * D. fill info. from desc to mbuf + */ + + for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts; + pos += RTE_I40E_DESCS_PER_LOOP, + rxdp += RTE_I40E_DESCS_PER_LOOP) { + vector_unsigned_long_long descs[RTE_I40E_DESCS_PER_LOOP]; + vector_unsigned_char pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4; + vector_unsigned_short staterr, sterr_tmp1, sterr_tmp2; + vector_unsigned_long_long mbp1, mbp2; /* two mbuf pointer + * in one XMM reg. + */ + + /* B.1 load 1 mbuf point */ + mbp1 = *(vector_unsigned_long_long *)&sw_ring[pos]; + /* Read desc statuses backwards to avoid race condition */ + /* A.1 load 4 pkts desc */ + descs[3] = *(vector_unsigned_long_long *)(rxdp + 3); + rte_compiler_barrier(); + + /* B.2 copy 2 mbuf point into rx_pkts */ + *(vector_unsigned_long_long *)&rx_pkts[pos] = mbp1; + + /* B.1 load 1 mbuf point */ + mbp2 = *(vector_unsigned_long_long *)&sw_ring[pos + 2]; + + descs[2] = *(vector_unsigned_long_long *)(rxdp + 2); + rte_compiler_barrier(); + /* B.1 load 2 mbuf point */ + descs[1] = *(vector_unsigned_long_long *)(rxdp + 1); + rte_compiler_barrier(); + descs[0] = *(vector_unsigned_long_long *)(rxdp); + + /* B.2 copy 2 mbuf point into rx_pkts */ + *(vector_unsigned_long_long *)&rx_pkts[pos + 2] = mbp2; + + if (split_packet) { + rte_mbuf_prefetch_part2(rx_pkts[pos]); + rte_mbuf_prefetch_part2(rx_pkts[pos + 1]); + rte_mbuf_prefetch_part2(rx_pkts[pos + 2]); + rte_mbuf_prefetch_part2(rx_pkts[pos + 3]); + } + + /* avoid compiler reorder optimization */ + rte_compiler_barrier(); + + /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/ + vector_unsigned_int len3_temp = vec_xld2(0, + (unsigned int *)&descs[3]); + len3_temp[3] = len3_temp[3] << PKTLEN_SHIFT; + const vector_unsigned_int len3 = len3_temp; + + vector_unsigned_int len2_temp = vec_xld2(0, + (unsigned int *)&descs[2]); + len2_temp[3] = len2_temp[3] << PKTLEN_SHIFT; + const vector_unsigned_int len2 = len2_temp; + + /* merge the now-aligned packet length fields back in */ + descs[3] = (vector_unsigned_long_long)len3; + descs[2] = (vector_unsigned_long_long)len2; + + /* D.1 pkt 3,4 convert format from desc to pktmbuf */ + pkt_mb4 = vec_perm((vector_unsigned_char)descs[3], + (vector_unsigned_char){}, shuf_msk); + pkt_mb3 = vec_perm((vector_unsigned_char)descs[2], + (vector_unsigned_char){}, shuf_msk); + + /* C.1 4=>2 filter staterr info only */ + sterr_tmp2 = vec_mergel((vector_unsigned_short)descs[3], + (vector_unsigned_short)descs[2]); + /* C.1 4=>2 filter staterr info only */ + sterr_tmp1 = vec_mergel((vector_unsigned_short)descs[1], + (vector_unsigned_short)descs[0]); + /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */ + pkt_mb4 = (vector_unsigned_char)((vector_unsigned_short)pkt_mb4 + - crc_adjust); + pkt_mb3 = (vector_unsigned_char)((vector_unsigned_short)pkt_mb3 + - crc_adjust); + + /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/ + const vector_unsigned_int len1 = + vec_sll(vec_xld2(0, (unsigned int *)&descs[1]), + (vector_unsigned_int){0, 0, 0, PKTLEN_SHIFT}); + const vector_unsigned_int len0 = + vec_sll(vec_xld2(0, (unsigned int *)&descs[0]), + (vector_unsigned_int){0, 0, 0, PKTLEN_SHIFT}); + + /* merge the now-aligned packet length fields back in */ + descs[1] = (vector_unsigned_long_long)len1; + descs[0] = (vector_unsigned_long_long)len0; + + /* D.1 pkt 1,2 convert format from desc to pktmbuf */ + pkt_mb2 = vec_perm((vector_unsigned_char)descs[1], + (vector_unsigned_char){}, shuf_msk); + pkt_mb1 = vec_perm((vector_unsigned_char)descs[0], + (vector_unsigned_char){}, shuf_msk); + + /* C.2 get 4 pkts staterr value */ + staterr = (vector_unsigned_short)vec_mergeh(sterr_tmp1, + sterr_tmp2); + + /* D.3 copy final 3,4 data to rx_pkts */ + vec_xstd2(pkt_mb4, 0, (unsigned char *)&rx_pkts[pos + 3] + ->rx_descriptor_fields1); + vec_xstd2(pkt_mb3, 0, (unsigned char *)&rx_pkts[pos + 2] + ->rx_descriptor_fields1); + + /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */ + pkt_mb2 = (vector_unsigned_char)((vector_unsigned_short)pkt_mb2 + - crc_adjust); + pkt_mb1 = (vector_unsigned_char)((vector_unsigned_short)pkt_mb1 + - crc_adjust); + + /* C* extract and record EOP bit */ + if (split_packet) { + vector_unsigned_char eop_shuf_mask = + (vector_unsigned_char){ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0x04, 0x0C, 0x00, 0x08 + }; + + /* and with mask to extract bits, flipping 1-0 */ + vector_unsigned_char eop_bits = + vec_and((vector_unsigned_char)vec_nor(staterr, + staterr), (vector_unsigned_char)eop_check); + /* the staterr values are not in order, as the count + * count of dd bits doesn't care. However, for end of + * packet tracking, we do care, so shuffle. This also + * compresses the 32-bit values to 8-bit + */ + eop_bits = vec_perm(eop_bits, (vector_unsigned_char){}, + eop_shuf_mask); + /* store the resulting 32-bit value */ + *split_packet = (vec_xld2(0, + (unsigned int *)&eop_bits))[0]; + split_packet += RTE_I40E_DESCS_PER_LOOP; + + /* zero-out next pointers */ + rx_pkts[pos]->next = NULL; + rx_pkts[pos + 1]->next = NULL; + rx_pkts[pos + 2]->next = NULL; + rx_pkts[pos + 3]->next = NULL; + } + + /* C.3 calc available number of desc */ + staterr = vec_and(staterr, (vector_unsigned_short)dd_check); + + /* D.3 copy final 1,2 data to rx_pkts */ + vec_xstd2(pkt_mb2, 0, (unsigned char *)&rx_pkts[pos + 1] + ->rx_descriptor_fields1); + vec_xstd2(pkt_mb1, 0, (unsigned char *)&rx_pkts[pos] + ->rx_descriptor_fields1); + + desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl); + desc_to_olflags_v(descs, &rx_pkts[pos]); + + /* C.4 calc avaialbe number of desc */ + var = __builtin_popcountll((vec_xld2(0, + (unsigned long long *)&staterr)[0])); + nb_pkts_recd += var; + if (likely(var != RTE_I40E_DESCS_PER_LOOP)) + break; + } + + /* Update our internal tail pointer */ + rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd); + rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1)); + rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd); + + return nb_pkts_recd; +} + + /* Notice: + * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet + * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST + * numbers of DD bits + */ +uint16_t +i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts) +{ + return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL); +} + + /* vPMD receive routine that reassembles scattered packets + * Notice: + * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet + * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST + * numbers of DD bits + */ +uint16_t +i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts) +{ + struct i40e_rx_queue *rxq = rx_queue; + uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0}; + + /* get some new buffers */ + uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts, + split_flags); + if (nb_bufs == 0) + return 0; + + /* happy day case, full burst + no packets to be joined */ + const uint64_t *split_fl64 = (uint64_t *)split_flags; + + if (rxq->pkt_first_seg == NULL && + split_fl64[0] == 0 && split_fl64[1] == 0 && + split_fl64[2] == 0 && split_fl64[3] == 0) + return nb_bufs; + + /* reassemble any packets that need reassembly*/ + unsigned int i = 0; + + if (!rxq->pkt_first_seg) { + /* find the first split flag, and only reassemble then*/ + while (i < nb_bufs && !split_flags[i]) + i++; + if (i == nb_bufs) + return nb_bufs; + } + return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i, + &split_flags[i]); +} + +static inline void +vtx1(volatile struct i40e_tx_desc *txdp, + struct rte_mbuf *pkt, uint64_t flags) +{ + uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA | + ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) | + ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT)); + + vector_unsigned_long_long descriptor = (vector_unsigned_long_long){ + pkt->buf_iova + pkt->data_off, high_qw}; + *(vector_unsigned_long_long *)txdp = descriptor; +} + +static inline void +vtx(volatile struct i40e_tx_desc *txdp, + struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags) +{ + int i; + + for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt) + vtx1(txdp, *pkt, flags); +} + +uint16_t +i40e_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts) +{ + struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue; + volatile struct i40e_tx_desc *txdp; + struct i40e_tx_entry *txep; + uint16_t n, nb_commit, tx_id; + uint64_t flags = I40E_TD_CMD; + uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD; + int i; + + /* cross rx_thresh boundary is not allowed */ + nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh); + + if (txq->nb_tx_free < txq->tx_free_thresh) + i40e_tx_free_bufs(txq); + + nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts); + nb_commit = nb_pkts; + if (unlikely(nb_pkts == 0)) + return 0; + + tx_id = txq->tx_tail; + txdp = &txq->tx_ring[tx_id]; + txep = &txq->sw_ring[tx_id]; + + txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts); + + n = (uint16_t)(txq->nb_tx_desc - tx_id); + if (nb_commit >= n) { + tx_backlog_entry(txep, tx_pkts, n); + + for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp) + vtx1(txdp, *tx_pkts, flags); + + vtx1(txdp, *tx_pkts++, rs); + + nb_commit = (uint16_t)(nb_commit - n); + + tx_id = 0; + txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1); + + /* avoid reach the end of ring */ + txdp = &txq->tx_ring[tx_id]; + txep = &txq->sw_ring[tx_id]; + } + + tx_backlog_entry(txep, tx_pkts, nb_commit); + + vtx(txdp, tx_pkts, nb_commit, flags); + + tx_id = (uint16_t)(tx_id + nb_commit); + if (tx_id > txq->tx_next_rs) { + txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |= + rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) << + I40E_TXD_QW1_CMD_SHIFT); + txq->tx_next_rs = + (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh); + } + + txq->tx_tail = tx_id; + + I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail); + + return nb_pkts; +} + +void __attribute__((cold)) +i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq) +{ + _i40e_rx_queue_release_mbufs_vec(rxq); +} + +int __attribute__((cold)) +i40e_rxq_vec_setup(struct i40e_rx_queue *rxq) +{ + return i40e_rxq_vec_setup_default(rxq); +} + +int __attribute__((cold)) +i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused * txq) +{ + return 0; +} + +int __attribute__((cold)) +i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev) +{ + return i40e_rx_vec_dev_conf_condition_check_default(dev); +} From patchwork Tue Apr 9 19:06:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52502 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 488055F14; Tue, 9 Apr 2019 21:07:00 +0200 (CEST) Received: from mail-qt1-f193.google.com (mail-qt1-f193.google.com [209.85.160.193]) by dpdk.org (Postfix) with ESMTP id 13BE25689 for ; Tue, 9 Apr 2019 21:06:43 +0200 (CEST) Received: by mail-qt1-f193.google.com with SMTP id w30so21163759qta.8 for ; Tue, 09 Apr 2019 12:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=kKo99JY69sqsDAQW6vWtxBehSgnXVqEE9ossRf7HUvk=; b=EsUgEhDSvOtkcdm+jyA044zK3DIGKbYcO5ktf7uz08+6xhZek8lTP6sPIKTJ7Ur5Vj 5d2J+PkXsTPG7sUrywJqv1tX8ciITMF+DbGQPAayfhlhfJ0qu3xWAwz1bpjCfjMgX2vk SVFK4sCLVwbNHwkQWC31L7YhON7lUDx3pLk/wXfdgh9bSuZmaqzOCxn+DEzv7Dc31WPZ 6qPHTQB6m78o606a6Gym+ScUaq9PO2feHz/mVJ0EHY7xwxmlUu1VAPaleyDbODAvPT1M YX3G1+0C9L9B6+e64KM58Q/TsA8TDmmYNTVcDVSoawWFOrCB8gNzXeNwlM0Ucf3cr7/u LLPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=kKo99JY69sqsDAQW6vWtxBehSgnXVqEE9ossRf7HUvk=; b=LGl/EGBx2U4DGlB1zq4H16zekKi3dl38+LjnKd0er9w/T/Hr2oxpd+01x3IqK+Z0Pv Fn2pVQngDfAIXGtplPekr+CfTKV2TFn1IhLdxvQSEoTsIQZp9exzMiS38qw+UX0PLi5V u5VSobCX4kIuYn8bPvz2gl0bK2bWU23kLGvcCdm/qkjrK88z0vAE7EdgQF3zkbWhkBA4 RSE+MYXh9tepOC1HU8JyYwcXgOzeiEIny3X4AFLsK/rWfBArRpwzNfy1rpWtuwSIZvI6 wTYUoKevEcu4UCbsAXOn5IRoJv7cRbKy+O/OvalqdXTpZt4ZHjOHeKpfqeQ8v4+d8+ma Uf4Q== X-Gm-Message-State: APjAAAVBDy/dcur/CSu07d5ozFmnBMQBDHOUEQE+UwzFdEea+/Zb5QN+ u7gKYLnBk3L8N5mL3c/NNaws3gvvj+k= X-Google-Smtp-Source: APXvYqwl5ovg7zax+elDYGc6t++ve3f5Tt+S/RFrQz8cji+WwpH20EtfXijEvUwyCEpl74WR7y8LYQ== X-Received: by 2002:aed:3e94:: with SMTP id n20mr32502036qtf.268.1554836802013; Tue, 09 Apr 2019 12:06:42 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:41 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:25 -0400 Message-Id: <20190409190630.31975-8-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 07/12] test: add support for s390x architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add big endian support for s390x architecture. Signed-off-by: Vivian Kong --- app/test/test_cmdline_ipaddr.c | 13 +++- app/test/test_cmdline_num.c | 111 +++++++++++++++++++++++++++++++++ app/test/test_xmmt_ops.h | 14 +++++ 3 files changed, 137 insertions(+), 1 deletion(-) diff --git a/app/test/test_cmdline_ipaddr.c b/app/test/test_cmdline_ipaddr.c index 8ee7f6288..5e7629bba 100644 --- a/app/test/test_cmdline_ipaddr.c +++ b/app/test/test_cmdline_ipaddr.c @@ -6,6 +6,7 @@ #include #include #include +#include #ifndef __linux__ #ifndef __FreeBSD__ @@ -22,7 +23,8 @@ #include "test_cmdline.h" -#define IP4(a,b,c,d) {((uint32_t)(((a) & 0xff)) | \ +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN +#define IP4(a, b, c, d) {((uint32_t)(((a) & 0xff)) | \ (((b) & 0xff) << 8) | \ (((c) & 0xff) << 16) | \ ((d) & 0xff) << 24)} @@ -30,6 +32,15 @@ #define U16_SWAP(x) \ (((x & 0xFF) << 8) | ((x & 0xFF00) >> 8)) +#else +#define IP4(a, b, c, d) {((uint32_t)(((a) & 0xff) << 24) | \ + (((b) & 0xff) << 16) | \ + (((c) & 0xff) << 8) | \ + ((d) & 0xff))} + +#define U16_SWAP(x) x +#endif + /* create IPv6 address, swapping bytes where needed */ #ifndef s6_addr16 # define s6_addr16 __u6_addr.__u6_addr16 diff --git a/app/test/test_cmdline_num.c b/app/test/test_cmdline_num.c index 4c97caf3d..9e80397ac 100644 --- a/app/test/test_cmdline_num.c +++ b/app/test/test_cmdline_num.c @@ -11,6 +11,8 @@ #include #include + +#include #include "test_cmdline.h" struct num_unsigned_str { @@ -451,6 +453,48 @@ test_parse_num_valid(void) /* check if result matches what it should have matched * since unsigned numbers don't care about number of bits, we can just convert * everything to uint64_t without any worries. */ + #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + switch (type) { + case UINT8: + { + uint8_t *temp = (uint8_t *)&result; + result = *temp; + break; + } + case UINT16: + { + uint16_t *temp = (uint16_t *)&result; + result = *temp; + break; + } + case UINT32: + { + uint32_t *temp = (uint32_t *)&result; + result = *temp; + break; + } + case INT8: + { + int8_t *temp = (int8_t *)&result; + result = *temp; + break; + } + case INT16: + { + int16_t *temp = (int16_t *)&result; + result = *temp; + break; + } + case INT32: + { + int32_t *temp = (int32_t *)&result; + result = *temp; + break; + } + default: + break; + } + #endif if (ret > 0 && num_valid_positive_strs[i].result != result) { printf("Error: parsing %s as %s failed: result mismatch!\n", num_valid_positive_strs[i].str, buf); @@ -480,6 +524,7 @@ test_parse_num_valid(void) * the result is signed in this case, so we have to account for that */ if (ret > 0) { /* detect negative */ + #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN switch (type) { case INT8: result = (int8_t) result; @@ -493,6 +538,30 @@ test_parse_num_valid(void) default: break; } + #else + switch (type) { + case INT8: + { + int8_t *temp = (int8_t *)&result; + result = *temp; + break; + } + case INT16: + { + int16_t *temp = (int16_t *)&result; + result = *temp; + break; + } + case INT32: + { + int32_t *temp = (int32_t *)&result; + result = *temp; + break; + } + default: + break; + } + #endif if (num_valid_negative_strs[i].result == (int64_t) result) continue; printf("Error: parsing %s as %s failed: result mismatch!\n", @@ -529,6 +598,48 @@ test_parse_num_valid(void) /* check if result matches what it should have matched * since unsigned numbers don't care about number of bits, we can just convert * everything to uint64_t without any worries. */ + #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + switch (type) { + case UINT8: + { + uint8_t *temp = (uint8_t *)&result; + result = *temp; + break; + } + case UINT16: + { + uint16_t *temp = (uint16_t *)&result; + result = *temp; + break; + } + case UINT32: + { + uint32_t *temp = (uint32_t *)&result; + result = *temp; + break; + } + case INT8: + { + int8_t *temp = (int8_t *)&result; + result = *temp; + break; + } + case INT16: + { + int16_t *temp = (int16_t *)&result; + result = *temp; + break; + } + case INT32: + { + int32_t *temp = (int32_t *)&result; + result = *temp; + break; + } + default: + break; + } + #endif if (ret > 0 && num_garbage_positive_strs[i].result != result) { printf("Error: parsing %s as %s failed: result mismatch!\n", num_garbage_positive_strs[i].str, buf); diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h index 8bcf0b261..6d8cd1998 100644 --- a/app/test/test_xmmt_ops.h +++ b/app/test/test_xmmt_ops.h @@ -49,6 +49,20 @@ vect_set_epi32(int i3, int i2, int i1, int i0) return data; } +#elif defined(RTE_ARCH_S390X) + +/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/ +#define vect_loadu_sil128(p) vec_xld2(0, (signed int *)p) + +/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */ +static __rte_always_inline xmm_t +vect_set_epi32(int i3, int i2, int i1, int i0) +{ + xmm_t data = (xmm_t){i0, i1, i2, i3}; + + return data; +} + #endif #endif /* _TEST_XMMT_OPS_H_ */ From patchwork Tue Apr 9 19:06:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52503 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AB8075F1B; Tue, 9 Apr 2019 21:07:02 +0200 (CEST) Received: from mail-qt1-f193.google.com (mail-qt1-f193.google.com [209.85.160.193]) by dpdk.org (Postfix) with ESMTP id 50BF75689 for ; Tue, 9 Apr 2019 21:06:44 +0200 (CEST) Received: by mail-qt1-f193.google.com with SMTP id p20so21142234qtc.9 for ; Tue, 09 Apr 2019 12:06:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=D1GLWxvrYQT9Y/1LIEQXZEP5rNp6P52u208lq3BvheA=; b=jOYxAeSpgiQS3Nn/vvrVNQ/rDu4soHxd/o1wqpzqWaYgysZjqwzDJX4ZYAC1rGJ2vF Vadjcusr7q3BCqpzq6OGnxOsOL6J7CwO8XTKU7iXUSEyBtRG/lRJwUbe1wREmIBjuN4p ZohxmBYLHSaeVl1gFF9m8E7DE81PYCyV2XF4zw1yIcvXdjTsvf3iuJYyd5XDlLmbLdG5 qZtBgwF0HTVipzEF9Cpk2Qe3Snm593T7Igtxl6fLYP3Jv2y950/qXjASyIs8b92rTsL4 LtkEmRt+Rb9s/92/VvHmP+9nL1wFDMnQHhzwRWXP43LFYQoHg7XwsFMZ72qsHEzMYxWE xibQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=D1GLWxvrYQT9Y/1LIEQXZEP5rNp6P52u208lq3BvheA=; b=MYK/7Npg8vqZmNUNhr4uKxyNzcAPrZ4AbqJUbnuwr/z/RUS824GScyUnl16NrA2uCj W+wK9UfcnWzXz7bsoHpWGat6jQYi+UjJhvESS8rPU2UoiNAggEn8N+BjBSwpN8s7Pf8f HS0u7loDAWQrLk+v8TSZGUWrwpSCQv5bIiCIhKMBSNRUfk/CDSTutWYyhwkF2U3AY9tr 6y4fpJBEEJ0eTuZaJHOs0lxUbb3oV7/J8UMLXTmiEs0XGSdJst7M+vM85JcHVGnpWOQe 9IRlId4qL6nu4NMyfWov7SIQeuL0ac0PpT8Wx0K2W+cZSwScs7oPpSsJP0bgo5eKeozU IVPA== X-Gm-Message-State: APjAAAVQV4gYGat5kpeXfz5eGZaRnnl4zr60eOFygsHdl2aWU4+VMZoY osdDCXTNEs3tmYiFiiNgTn8G4H0ipQc= X-Google-Smtp-Source: APXvYqyCOdiZJetBZuoxEWcfRhQwH+vYpmIzUuuJBhBz6pgUdskYCzv4Hr1HaHEM7fW9KFC9n77iuQ== X-Received: by 2002:ac8:168c:: with SMTP id r12mr30606033qtj.300.1554836803423; Tue, 09 Apr 2019 12:06:43 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:42 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:26 -0400 Message-Id: <20190409190630.31975-9-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 08/12] hash: add support for s390x architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add big endian support for s390x architecture. Signed-off-by: Vivian Kong --- lib/librte_hash/rte_fbk_hash.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lib/librte_hash/rte_fbk_hash.h b/lib/librte_hash/rte_fbk_hash.h index c4d6976d2..5e49950a7 100644 --- a/lib/librte_hash/rte_fbk_hash.h +++ b/lib/librte_hash/rte_fbk_hash.h @@ -125,9 +125,16 @@ rte_fbk_hash_add_key_with_bucket(struct rte_fbk_hash_table *ht, * corrupted due to race conditions, but it's still possible to * overwrite entries that have just been made valid. */ + #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN const uint64_t new_entry = ((uint64_t)(key) << 32) | ((uint64_t)(value) << 16) | 1; /* 1 = is_entry bit. */ + #else + const uint64_t new_entry = + ((uint64_t)(1) << 48) | /* 1 = is_entry bit. */ + ((uint64_t)(value) << 32) | + (uint64_t)(key); + #endif uint32_t i; for (i = 0; i < ht->entries_per_bucket; i++) { From patchwork Tue Apr 9 19:06:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52504 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 65CD75F24; Tue, 9 Apr 2019 21:07:05 +0200 (CEST) Received: from mail-qk1-f179.google.com (mail-qk1-f179.google.com [209.85.222.179]) by dpdk.org (Postfix) with ESMTP id B749A5592 for ; Tue, 9 Apr 2019 21:06:45 +0200 (CEST) Received: by mail-qk1-f179.google.com with SMTP id z76so10948404qkb.12 for ; Tue, 09 Apr 2019 12:06:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=27axLjngdlwWO2qT++yVYdwKM6XBYezSeBp+UXB2Ek0=; b=IMF+tqG42tYU6ed/OrzSGYCCJANbpQt+xDvmdHN5DVJg/ictBWIbLbthMypH6mPcxI 8PeMTPcDNjUWWbIDXr2jEUIBWmOFjBKi4IgHf8j8DhCZ0hk87w53R1GvTVyQtsYUPxwa uOa8vFKnxip00SqB5XWV5KWBD3B3SlYwYJUSCX5YhbGiU06pxP4T9aIsFDEUAkNUkvuj quCGFJbG0hydfbjxO5+V84MV0VLYnv0qKLZMinAUdBcaiJ+EHSR9PHOPQvWhU43RXkmj PWYquASfoDog0wnYAoNCvQLt+950UoF+kRMfsdrJQXT+oDB2tIYgprmU9pJsFzmZZWww zy9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=27axLjngdlwWO2qT++yVYdwKM6XBYezSeBp+UXB2Ek0=; b=SJjmfb1APA6bF4LbeTD57Z6KRc8oFonjgXg390hPRHxPDesN1s9ycDquuTRAKuMeAD WIor8xjaotAc2P7CuDbbEe3kyuLV852xjAdy0L3e1WKwCdrc9HPD7eD/T/d2sxE8aQZh v7pm6HKMH76z16knD8dSovsZIoZc1JDf+BxVRZJu9iKaVK778RR1Qs4BsHGixpLywNHA 61PDHZZCYIcarUrrt+b/nReYj1HkYDW+sCsNGEjBGuD1t9dJJnsDDEPjtaPJA0T8B34j yJuO83KkR3jfF4/hS8a+5LHRH3uNSoa1m3Azc36ZxWj9gNWvD/g1oKbKGFa71hdaN9dO y2VQ== X-Gm-Message-State: APjAAAWD9o4DLo5D0Sw3PBcFLrpmSHUhEBZ81vfDPmxwKMYeJNoDFcX+ iZ7qyG+YMf+tj9Vlk9qsUy0SHsI3YC4= X-Google-Smtp-Source: APXvYqw1IsuWHguo1Mc5VULKBVkNjWO3OPR6Jjk9Ev3zxjZC8EZWRwv5dPdZ6i3BLpSnUxHKdBUdcQ== X-Received: by 2002:a05:620a:101b:: with SMTP id z27mr29073389qkj.160.1554836804782; Tue, 09 Apr 2019 12:06:44 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.43 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:43 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:27 -0400 Message-Id: <20190409190630.31975-10-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 09/12] doc: introduce s390x architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Vivian Kong --- MAINTAINERS | 9 +++++++++ doc/guides/rel_notes/release_19_05.rst | 3 +++ 2 files changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9774344dd..6d4c51215 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -248,6 +248,15 @@ F: lib/librte_eal/common/include/arch/ppc_64/ F: drivers/net/i40e/i40e_rxtx_vec_altivec.c F: examples/l3fwd/*altivec.h +Linux on IBM Z (s390x) +M: Vivian Kong +F: lib/librte_eal/common/arch/s390x/ +F: lib/librte_eal/common/include/arch/s390x/ +F: lib/librte_lpm/rte_lpm_s390x.h +F: drivers/net/i40e/i40e_rxtx_vec_s390x.c +F: examples/l3fwd/*s390x.h +F: mk/arch/s390x/rte.vars.mk + Intel x86 M: Bruce Richardson M: Konstantin Ananyev diff --git a/doc/guides/rel_notes/release_19_05.rst b/doc/guides/rel_notes/release_19_05.rst index dbdf07a0c..2e0b39ee5 100644 --- a/doc/guides/rel_notes/release_19_05.rst +++ b/doc/guides/rel_notes/release_19_05.rst @@ -155,6 +155,9 @@ New Features Improved testpmd application performance on ARM platform. For ``macswap`` forwarding mode, NEON intrinsics were used to do swap to save CPU cycles. +* **Added support for Linux on IBM Z (s390x).** + + Added initial support for Linux on IBM Z (s390x). Removed Items ------------- From patchwork Tue Apr 9 19:06:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52505 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EB4705F2A; Tue, 9 Apr 2019 21:07:08 +0200 (CEST) Received: from mail-qt1-f170.google.com (mail-qt1-f170.google.com [209.85.160.170]) by dpdk.org (Postfix) with ESMTP id 10EB45592 for ; Tue, 9 Apr 2019 21:06:47 +0200 (CEST) Received: by mail-qt1-f170.google.com with SMTP id t28so21156414qte.6 for ; Tue, 09 Apr 2019 12:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=reycIkNaHrXDVIazgLj/BB5Ki56XKYnREYyUIIhfv5M=; b=FknVffJ9POBcC+eDMhMov1aLsoaF17DZTIJga6f0GIDHz5lqgqv7o7t235RBsVx0qP cDK2M9Fo0Yz5JG/jp0bPy5+daRxq8BENKmo0It9V93WV8JKeEM9GtKqhrpq5aGYevpcv OEeFVWohU+hGKb7kf9T18hNI9qYZiE2RHn4yQA9t0uWKE+XDSTJhmNgDFkGZmvDERNM+ MA06BAQRhIzBNd0LVcdq6/OT3AlA4h3BHcdjkh+EojQkwz99FY8pQ4lUcvLtZy4LMzNJ aD3bXdWbmBiwL/9uqs5ma+OfHes5efSMHYSKuC/wN+d9R4/VUBmEXIJYyg1e0CviilsD 7O4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=reycIkNaHrXDVIazgLj/BB5Ki56XKYnREYyUIIhfv5M=; b=GUpZ/ZscW/TgO/VdTwWbzmy7bH2HoPg8FHF94KaaRM41RszZlEg2kc02sZB6veXsBL IPPLovipRq4wx1iZ6cx0ezOw0Yih2hr/RYaMNCKBH3CGIEk3bm8RZtx/IpHQ3Io2sAhq 3wP61jTG0UL5ci+CYGpXvNb/4twYMWNZpGF8U2ZASgiKRIO3rTJVlu9BQI7kgEWo9djF fr+UtzPzhY21esfXCjcjQl0+MNdzo8LT8F2ssrwSiAHeShlB8ya/9TaghW004k3QQefH kOleB/wZmrHwY3ITqM2SqYJJLEQ8AtLZhagK7zL3yA5HbioR5sVVhWMiqO+LqEP2uMzN L19A== X-Gm-Message-State: APjAAAW9+DQQu66Dvg9zus5+eI5zBEQkkVXM6k0cP4FaG7JOPfSAyKUH v1DWka5G8MDmZ3Yfj6bOzGcjfMQZdnU= X-Google-Smtp-Source: APXvYqwetpURBxBwJ0Zg4FrzhtfpCsGn3CGvMX7nL60FycAvlQMSwWsj6XdANpf7AKTda/Q2jlDrng== X-Received: by 2002:ac8:2d56:: with SMTP id o22mr30337491qta.321.1554836806039; Tue, 09 Apr 2019 12:06:46 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:45 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:28 -0400 Message-Id: <20190409190630.31975-11-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 10/12] ethdev: add cast for bus_device X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Vivian Kong --- lib/librte_ethdev/rte_ethdev_pci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/librte_ethdev/rte_ethdev_pci.h b/lib/librte_ethdev/rte_ethdev_pci.h index 23257e986..80bd120b9 100644 --- a/lib/librte_ethdev/rte_ethdev_pci.h +++ b/lib/librte_ethdev/rte_ethdev_pci.h @@ -72,7 +72,7 @@ rte_eth_copy_pci_info(struct rte_eth_dev *eth_dev, static inline int eth_dev_pci_specific_init(struct rte_eth_dev *eth_dev, void *bus_device) { - struct rte_pci_device *pci_dev = bus_device; + struct rte_pci_device *pci_dev = (struct rte_pci_device *) bus_device; if (!pci_dev) return -ENODEV; From patchwork Tue Apr 9 19:06:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52506 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 76B2E5F72; Tue, 9 Apr 2019 21:07:12 +0200 (CEST) Received: from mail-qt1-f170.google.com (mail-qt1-f170.google.com [209.85.160.170]) by dpdk.org (Postfix) with ESMTP id 678F558FE for ; Tue, 9 Apr 2019 21:06:48 +0200 (CEST) Received: by mail-qt1-f170.google.com with SMTP id s15so12822918qtn.3 for ; Tue, 09 Apr 2019 12:06:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=HD7mDLIa5srh/fO8d/19SaLlBk5bYmQyrOrqT+ju1s4=; b=f7dW2CbBHMZ70E+1TRCdkLyFHlVsIsxq9tdoP1dBijlEZQSl64QVcKjr+XGlCAJAjp Z7HvN7N3D/ALRoZWw6BdZJurUuh793hfoYvI6EdQSwUiubYvkTtSsWuVb5ALQxGqfqWe wd7zDB36gK4Y6U7h+JN4HcJIgV0lSNj2wUwyAayvdGB1K1DJXhlN9aBHVVck9XG+pgUY CXtW8cLSTqAPUBeb55MdBOmTJNYI2z2c2dAtwak/Uz/OcNBhv6mhQVJ/4vSL5++qaxHJ 8+XZ83hnFKmQBL2cIPl0TGJTAih/Muij1HbyxEarzvAeXcJje2GQM4ESK9VSd6yjdALI +AxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=HD7mDLIa5srh/fO8d/19SaLlBk5bYmQyrOrqT+ju1s4=; b=RoT56X3wDmFL3oJmlqG59qAIdi6fVX0WYIShX3h4GY9hcZmQwMgDErlPSrSPvrlLtN 7H4y2uDwjbX8VagobryDTT9elQPkANnziijTbu5WfWlqMbvSH7N0iryqX2u6u4RKa6aM RxsqnswC1EwAdRE2980G2QaO9sFpG3bUwrh2Mp/sj6qThq1ZgBDv8CB6DRvrGZip0r0Y viAFwiSxFfGQs8ttFs1TxknUgHlFDKdF0pgYV24u6LZsJniyRmoK2lH5lTwzWYp+Dxd+ rntPxwnKl9Kl3Olxc/shKM7vI0Mxvy08OFTdB76gIcN41DYrneJbYaAFJXZX+zRFkeQw MMLQ== X-Gm-Message-State: APjAAAW4mx1dqioICLsgKz3k8HPbjmONQjDAM2c3olv8jp0N4WS3XnuG UxQXOSp38fJQ9OGJHiAWD+tuxgg+DsA= X-Google-Smtp-Source: APXvYqwhQK49ncsA39gBbVi/VpIO/KjN0+dINEgjUk7Wl6vkiiIA/OjdD4TbPJLswEd1CKqi/ob6+w== X-Received: by 2002:ac8:27a6:: with SMTP id w35mr30779205qtw.157.1554836807488; Tue, 09 Apr 2019 12:06:47 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.46 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:46 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:29 -0400 Message-Id: <20190409190630.31975-12-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 11/12] mbuf: trivial fix X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Vivian Kong --- lib/librte_mbuf/rte_mbuf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h index f7886dcb3..7dd2e7fb3 100644 --- a/lib/librte_mbuf/rte_mbuf.h +++ b/lib/librte_mbuf/rte_mbuf.h @@ -500,7 +500,7 @@ enum { RTE_MBUF_OUTL2_LEN_BITS, #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN RTE_MBUF_L2_LEN_OFS = - sizeof(uint64_t) * CHAR_BIT - RTE_MBUF_L2_LEN_BITS + sizeof(uint64_t) * CHAR_BIT - RTE_MBUF_L2_LEN_BITS, RTE_MBUF_L3_LEN_OFS = RTE_MBUF_L2_LEN_OFS - RTE_MBUF_L3_LEN_BITS, RTE_MBUF_L4_LEN_OFS = RTE_MBUF_L3_LEN_OFS - RTE_MBUF_L4_LEN_BITS, RTE_MBUF_TSO_SEGSZ_OFS = RTE_MBUF_L4_LEN_OFS - RTE_MBUF_TSO_SEGSZ_BITS, From patchwork Tue Apr 9 19:06:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivian Kong X-Patchwork-Id: 52507 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 28F186904; Tue, 9 Apr 2019 21:07:15 +0200 (CEST) Received: from mail-qt1-f196.google.com (mail-qt1-f196.google.com [209.85.160.196]) by dpdk.org (Postfix) with ESMTP id A2E8658C6 for ; Tue, 9 Apr 2019 21:06:49 +0200 (CEST) Received: by mail-qt1-f196.google.com with SMTP id s15so12823002qtn.3 for ; Tue, 09 Apr 2019 12:06:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=lU2iJQQ2ovpyMmKIvsrFqsFQs0Nte4p4gYh7t9ZZNT8=; b=cz/hWyMxuj3i8qH82BMMDIxRazvAmCPJT4y2n89zc9aNBScfvnFRS0FnoJMvGIvJ34 jMTQurcuRwlJIowad9Tebpq7CDqQ3D96DyZXaWNe5Qkm3loUc8CqS0vqfW6TLMa0qMsI UfCkwOHxplMSGk5oxiw+hLNVsejtB+ANjRj36mb551FPKlJe0ZGDgxmUKpkkqz7wOVjC ZhGxsEokxZlYMA/0zhpQsHwNyQqt0DJXlw6OwigFueLO4ceHQQux9aWej+xY2tiQabSS pPzYr9v/dfAzDTXp6PjXELv/xg7WREbpqxqK72SF1xW992Yv119VKtUV46c6znH89YBg fopw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=lU2iJQQ2ovpyMmKIvsrFqsFQs0Nte4p4gYh7t9ZZNT8=; b=s8xNKe5pQBJvhHVE3mshBiVrQZeal7R8OFdJ9KB6lERfAsaqLWtoiRj2Rh2UPQ93G/ +MqRkXPCJ51E6Sr5yGZc4jAML5JUFmMYjuZZCiTmyTbWhBnKltB8R09XjpojtnzLacK1 igVYEt/pHeIGn9XWGrtokwOG90kZxIqLBTVI6cFoiCcUPmxbSsM+EaS7NX6066iQFIJK ZSH8msi2RcWyIWvK/MxqmuXbV4qhQf34/cYVHE8sMw5wRVssuhrxf5D6cZWgt9FABQBU WhPj702ID3fNKLLUPV+0E9cEQtvWapJlSjXFJPclpM3uR1XfApdVRsPVmLuQYcmxP3CY dQlw== X-Gm-Message-State: APjAAAVAY4IshVy/ozAzl7WnP9Vyq10SASgUcgJJzaT1E52OAEVPRleO GGSFTOZYNhJyxQaQA8rCuX5zBm0ByVw= X-Google-Smtp-Source: APXvYqzHnmCs45XeWywm4QeuMmSyDTu68+QYDTUmJA5Jw9txJjXeQqF3GUvwXJDLS4POoiwC6iO7Cg== X-Received: by 2002:ac8:276b:: with SMTP id h40mr32284491qth.319.1554836808732; Tue, 09 Apr 2019 12:06:48 -0700 (PDT) Received: from csz25116.canlab.ibm.com ([199.246.40.57]) by smtp.gmail.com with ESMTPSA id q23sm17934789qkc.16.2019.04.09.12.06.47 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 12:06:47 -0700 (PDT) From: Vivian Kong X-Google-Original-From: Vivian Kong To: dev@dpdk.org Date: Tue, 9 Apr 2019 15:06:30 -0400 Message-Id: <20190409190630.31975-13-vivkong@ca.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190409190630.31975-1-vivkong@ca.ibm.com> References: <20190409190630.31975-1-vivkong@ca.ibm.com> Subject: [dpdk-dev] [RFC 12/12] test: miscellaneous test fixes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: vivkong@ca.ibm.com List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Minor test case fixes. Signed-off-by: Vivian Kong --- app/test/autotest_data.py | 2 +- app/test/test_cmdline.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/app/test/autotest_data.py b/app/test/autotest_data.py index db2527489..72c56e528 100644 --- a/app/test/autotest_data.py +++ b/app/test/autotest_data.py @@ -175,7 +175,7 @@ "Command": "ticketlock_autotest", "Func": ticketlock_autotest, "Report": None, - } + }, { "Name": "Byte order autotest", "Command": "byteorder_autotest", diff --git a/app/test/test_cmdline.c b/app/test/test_cmdline.c index 115bee966..e0720ff34 100644 --- a/app/test/test_cmdline.c +++ b/app/test/test_cmdline.c @@ -10,21 +10,21 @@ static int test_cmdline(void) { - printf("Testind parsing ethernet addresses...\n"); + printf("Testing parsing ethernet addresses...\n"); if (test_parse_etheraddr_valid() < 0) return -1; if (test_parse_etheraddr_invalid_data() < 0) return -1; if (test_parse_etheraddr_invalid_param() < 0) return -1; - printf("Testind parsing port lists...\n"); + printf("Testing parsing port lists...\n"); if (test_parse_portlist_valid() < 0) return -1; if (test_parse_portlist_invalid_data() < 0) return -1; if (test_parse_portlist_invalid_param() < 0) return -1; - printf("Testind parsing numbers...\n"); + printf("Testing parsing numbers...\n"); if (test_parse_num_valid() < 0) return -1; if (test_parse_num_invalid_data() < 0)