From patchwork Tue Mar 19 16:36:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 51350 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3D7D52C30; Tue, 19 Mar 2019 17:36:26 +0100 (CET) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id BBE2A11A4; Tue, 19 Mar 2019 17:36:24 +0100 (CET) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us2.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 6197C680090; Tue, 19 Mar 2019 16:36:23 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 19 Mar 2019 09:36:07 -0700 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 19 Mar 2019 09:36:07 -0700 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id x2JGa6bo008794; Tue, 19 Mar 2019 16:36:06 GMT Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 466CD1627FE; Tue, 19 Mar 2019 16:36:06 +0000 (GMT) From: Andrew Rybchenko To: CC: Date: Tue, 19 Mar 2019 16:36:00 +0000 Message-ID: <1553013360-12880-1-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24498.005 X-TM-AS-Result: No-0.462400-4.000000-10 X-TMASE-MatchedRID: uDF9NFwYvA1veCKWtaLcaOEbUg4xvs+wgIIo4X9yrRz2KZeV5IFRY7vE kLvfXxgz6BzqZfWXA0eAMuqetGVethtouMvD9sV53QfwsVk0UbuZ/dgf3Hl0lbm7Gd8cfu6nj3o 2SBb7VDWzuByf3ARedRVCRaNINIcdSXrEityo+KJFKgUviSVfgYV2BzVGf8847QD7xzCwXlUz94 zXM5CzMA9cvEd/Et5dVEc5IqztENReYfSkFq6uAb7jE6+wkCSeiTSgm8kJVKRDDKa3G4nrLQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10-0.462400-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24498.005 X-MDID: 1553013383-4CayO7dwWAwB Subject: [dpdk-dev] [PATCH] net/sfc: fix speed capabilities reported in device info X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Phy capabilities are bit offsets in libefx, but was used as bit masks. Fixes: d23f3a89ab54 ("net/sfc: support link speed and duplex settings") Fixes: f82e33afbbb9 ("net/sfc: support link speeds up to 100G") Cc: stable@dpdk.org Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/sfc_ethdev.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c index e7bfd8917..2675d4a8c 100644 --- a/drivers/net/sfc/sfc_ethdev.c +++ b/drivers/net/sfc/sfc_ethdev.c @@ -96,17 +96,17 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) /* Autonegotiation may be disabled */ dev_info->speed_capa = ETH_LINK_SPEED_FIXED; - if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_1000FDX) + if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_1000FDX)) dev_info->speed_capa |= ETH_LINK_SPEED_1G; - if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_10000FDX) + if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_10000FDX)) dev_info->speed_capa |= ETH_LINK_SPEED_10G; - if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_25000FDX) + if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_25000FDX)) dev_info->speed_capa |= ETH_LINK_SPEED_25G; - if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_40000FDX) + if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_40000FDX)) dev_info->speed_capa |= ETH_LINK_SPEED_40G; - if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_50000FDX) + if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_50000FDX)) dev_info->speed_capa |= ETH_LINK_SPEED_50G; - if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_100000FDX) + if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_100000FDX)) dev_info->speed_capa |= ETH_LINK_SPEED_100G; dev_info->max_rx_queues = sa->rxq_max;