From patchwork Wed Nov 27 00:52:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148869 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5223545D31; Wed, 27 Nov 2024 01:53:17 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4BF3A427C8; Wed, 27 Nov 2024 01:53:08 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 2109C427C2 for ; Wed, 27 Nov 2024 01:53:03 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 13F0520545B6; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 13F0520545B6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=uAjlWMqVp2nIxFPT5Zo5R9BDpPXdhP6WfwUTZRbllCY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C7IN4/ANrrIFd/Wso/Q6SzySwQKGNvLptLKiwwrhbXr6DBqL63oulu3L/tnnEtJJF P8OP88fre88hbjDX+BXRPkHAYJlQ23LwpObAj/L+dX2IY8AX1KsipfldAvrJZcfzMt 99f5JvylLWXH26HGn8dhDf3jIiSyb8o/4dHnMuOM= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 01/30] devtools: check packed attributes Date: Tue, 26 Nov 2024 16:52:12 -0800 Message-Id: <1732668761-5556-2-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Ensure __rte_packed_begin and __rte_packed_end show up in pairs when checking patches. Signed-off-by: Andre Muezerie Acked-by: Tyler Retzlaff --- devtools/checkpatches.sh | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/devtools/checkpatches.sh b/devtools/checkpatches.sh index 4a8591be22..d304a84df3 100755 --- a/devtools/checkpatches.sh +++ b/devtools/checkpatches.sh @@ -362,6 +362,21 @@ check_aligned_attributes() { # return $res } +check_packed_attributes() { # + res=0 + + begin_count=$(grep '__rte_packed_begin' "$1" | \ + wc -l) + end_count=$(grep '__rte_packed_end' "$1" | \ + wc -l) + if [ $begin_count != $end_count ]; then + echo "__rte_packed_begin and __rte_packed_end mismatch. They should always be used in pairs." + res=1 + fi + + return $res +} + check_release_notes() { # rel_notes_prefix=doc/guides/rel_notes/release_ IFS=. read year month release < VERSION @@ -479,6 +494,14 @@ check () { # ret=1 fi + ! $verbose || printf '\nChecking packed attributes:\n' + report=$(check_packed_attributes "$tmpinput") + if [ $? -ne 0 ] ; then + $headline_printed || print_headline "$subject" + printf '%s\n' "$report" + ret=1 + fi + ! $verbose || printf '\nChecking release notes updates:\n' report=$(check_release_notes "$tmpinput") if [ $? -ne 0 ] ; then From patchwork Wed Nov 27 00:52:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148868 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0F8D745D31; Wed, 27 Nov 2024 01:53:11 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0003A427C3; Wed, 27 Nov 2024 01:53:06 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id ECE82402E0 for ; Wed, 27 Nov 2024 01:53:02 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 22DA820545B7; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 22DA820545B7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=ZCU1KydXC22LyTJuY6NcSUFqZsZaY8RbOp6LEyJoulY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YDD7uZs9rd5xfeMhUmmSqB+ayEUbE38H8P2Ep53OCJfRH9aj5FCkfmzGAmVkwVgFD /UO6JsrDzGdoYuAMygG02dBWdWOPWIdtnGclAevXnQwKyNWO4vMEOB8vmh7m6+UjoU lbDuZ66RU9s1H3wqU9dyyzzzel7jI6I9XEntS3MQ= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 02/30] eal/include: add new packing macros Date: Tue, 26 Nov 2024 16:52:13 -0800 Message-Id: <1732668761-5556-3-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Add macro __rte_packed_begin which can be used to push existing pack value and set packing to 1-byte. Add macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Macro __rte_packed will be removed in a subsequent patch. Signed-off-by: Andre Muezerie Acked-by: Tyler Retzlaff --- lib/eal/include/rte_common.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/lib/eal/include/rte_common.h b/lib/eal/include/rte_common.h index 4d299f2b36..affdcaf3c1 100644 --- a/lib/eal/include/rte_common.h +++ b/lib/eal/include/rte_common.h @@ -108,6 +108,17 @@ typedef uint16_t unaligned_uint16_t; #define __rte_packed __attribute__((__packed__)) #endif +/** + * Force a structure to be packed + */ +#ifdef RTE_TOOLCHAIN_MSVC +#define __rte_packed_begin __pragma(pack(push, 1)) +#define __rte_packed_end __pragma(pack(pop)) +#else +#define __rte_packed_begin +#define __rte_packed_end __attribute__((__packed__)) +#endif + /** * Macro to mark a type that is not subject to type-based aliasing rules */ From patchwork Wed Nov 27 00:52:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148870 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DA7BB45D31; Wed, 27 Nov 2024 01:53:22 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA565427D0; Wed, 27 Nov 2024 01:53:09 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 1C2BE427BF for ; Wed, 27 Nov 2024 01:53:03 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 327D820545B8; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 327D820545B8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=rINLAlORiJ1ambAWqTvmhYZOFfU1YCBFEIo46794MtQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qto17hEbuvtmu+udMr5dbphexJ5V9rsncEHYhpIri+hyRwaI+5AshNDIIs4V97XsZ MDVXs4zFLA9UGd8YjpF1AKFjVJ6sWzdbuk2AZocCYDoFrzmpB9/EUT8DDizE3fM/sw 7EGRFjNuwmnyGNeNHkeoLjEFq/lthlDli75j78Qw= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 03/30] app/test-pmd: remove unnecessary packed attributes Date: Tue, 26 Nov 2024 16:52:14 -0800 Message-Id: <1732668761-5556-4-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Removed __rte_packed attribute from structure that is naturally packed already. Signed-off-by: Andre Muezerie --- app/test-pmd/csumonly.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/app/test-pmd/csumonly.c b/app/test-pmd/csumonly.c index 2246c22e8e..d77a140641 100644 --- a/app/test-pmd/csumonly.c +++ b/app/test-pmd/csumonly.c @@ -92,7 +92,7 @@ struct testpmd_offload_info { struct simple_gre_hdr { uint16_t flags; uint16_t proto; -} __rte_packed; +}; static uint16_t get_udptcp_checksum(struct rte_mbuf *m, void *l3_hdr, uint16_t l4_off, From patchwork Wed Nov 27 00:52:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148871 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E66445D31; Wed, 27 Nov 2024 01:53:29 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1341F427D7; Wed, 27 Nov 2024 01:53:11 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 2391C427C3 for ; Wed, 27 Nov 2024 01:53:03 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 40A9E20545B9; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 40A9E20545B9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=QZ6nJH655IW0sVrK89EQqRWt/VPjbkFEvJmuE9YtFJg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PQCzjGhBe2VoMuJIUaEHXMtt1cj06EufQKCQsmAGPv30zNK6U8z+W+CoqmEGHe/zK wCMF2dtxo+IyC4lqw3IMyyThwDMbiTDBW+FKr1AQDSvHC3LbeD4NDSdLANa98DfDye u3XCynP4LgaKQf81ZdQ0fZkloq9fS04wExWhgvyc= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 04/30] app/test: replace packed attributes Date: Tue, 26 Nov 2024 16:52:15 -0800 Message-Id: <1732668761-5556-5-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retzlaff --- app/test/test_efd.c | 3 ++- app/test/test_hash.c | 3 ++- app/test/test_member.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/app/test/test_efd.c b/app/test/test_efd.c index 1c0986b9bc..0c4444c764 100644 --- a/app/test/test_efd.c +++ b/app/test/test_efd.c @@ -33,13 +33,14 @@ test_efd(void) static unsigned int test_socket_id; /* 5-tuple key type */ +__rte_packed_begin struct flow_key { uint32_t ip_src; uint32_t ip_dst; uint16_t port_src; uint16_t port_dst; uint8_t proto; -} __rte_packed; +} __rte_packed_end; RTE_LOG_REGISTER(efd_logtype_test, test.efd, INFO); diff --git a/app/test/test_hash.c b/app/test/test_hash.c index 65b9cad93c..6dbd038efd 100644 --- a/app/test/test_hash.c +++ b/app/test/test_hash.c @@ -79,13 +79,14 @@ static uint32_t hashtest_key_lens[] = {0, 2, 4, 5, 6, 7, 8, 10, 11, 15, 16, 21, * Should be packed to avoid holes with potentially * undefined content in the middle. */ +__rte_packed_begin struct flow_key { uint32_t ip_src; uint32_t ip_dst; uint16_t port_src; uint16_t port_dst; uint32_t proto; -} __rte_packed; +} __rte_packed_end; /* * Hash function that always returns the same value, to easily test what diff --git a/app/test/test_member.c b/app/test/test_member.c index 5a4d2750db..72ea7c239a 100644 --- a/app/test/test_member.c +++ b/app/test/test_member.c @@ -32,13 +32,14 @@ struct rte_member_setsum *setsum_vbf; struct rte_member_setsum *setsum_sketch; /* 5-tuple key type */ +__rte_packed_begin struct flow_key { uint32_t ip_src; uint32_t ip_dst; uint16_t port_src; uint16_t port_dst; uint8_t proto; -} __rte_packed; +} __rte_packed_end; /* Set ID Macros for multimatch test usage */ #define M_MATCH_S 1 /* Not start with 0 since by default 0 means no match */ From patchwork Wed Nov 27 00:52:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148880 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7023945D31; Wed, 27 Nov 2024 01:54:29 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2549C42D83; Wed, 27 Nov 2024 01:53:22 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id E0603427C3 for ; Wed, 27 Nov 2024 01:53:03 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 4F5EE20545BA; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 4F5EE20545BA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=g3WhUkpUG9NiJHWnDcJN7x0PuEUlaVT5PLDi7NrI1qI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q06onQYBdh5ap8UjGfUfvtrAzFzSUQgX4wnv3vwB6cDqaM47CUUZVJQthEvkyDTlg w/HXYGHN2VOAxRggsn5LfHFCxMkeyNthEM3FPmHp93VYp0gL2HROa9LELUzjvb7Esq zXCiiNmacqr9ursRmB3FFPWhArrGammRrAvKSC4c= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 05/30] doc/guides: replace packed attributes Date: Tue, 26 Nov 2024 16:52:16 -0800 Message-Id: <1732668761-5556-6-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Acked-by: Tyler Retzlaff --- doc/guides/nics/ark.rst | 3 ++- doc/guides/prog_guide/packet_classif_access_ctrl.rst | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/ark.rst b/doc/guides/nics/ark.rst index a9f6d4cdb8..0cb5460199 100644 --- a/doc/guides/nics/ark.rst +++ b/doc/guides/nics/ark.rst @@ -172,10 +172,11 @@ during RX from user meta data coming from FPGA hardware. }; /* RX tuser field based on user's hardware */ + __rte_packed_begin struct user_rx_meta { uint64_t timestamp; uint32_t rss; - } __rte_packed; + } __rte_packed_end; /* Create ark_user_extension object for use in other hook functions */ void *rte_pmd_ark_dev_init(struct rte_eth_dev * dev, diff --git a/doc/guides/prog_guide/packet_classif_access_ctrl.rst b/doc/guides/prog_guide/packet_classif_access_ctrl.rst index c8844d0616..55db983a05 100644 --- a/doc/guides/prog_guide/packet_classif_access_ctrl.rst +++ b/doc/guides/prog_guide/packet_classif_access_ctrl.rst @@ -154,6 +154,7 @@ To define classification for the IPv6 2-tuple: o .. code-block:: c + __rte_packed_begin struct rte_ipv6_hdr { uint32_t vtc_flow; /* IP version, traffic class & flow label. */ uint16_t payload_len; /* IP packet length - includes sizeof(ip_header). */ @@ -161,7 +162,7 @@ To define classification for the IPv6 2-tuple: o uint8_t hop_limits; /* Hop limits. */ uint8_t src_addr[16]; /* IP address of source host. */ uint8_t dst_addr[16]; /* IP address of destination host(s). */ - } __rte_packed; + } __rte_packed_end; The following array of field definitions can be used: From patchwork Wed Nov 27 00:52:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148873 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BD73945D31; Wed, 27 Nov 2024 01:53:41 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 748C7427E3; Wed, 27 Nov 2024 01:53:13 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id C33C8402E0 for ; Wed, 27 Nov 2024 01:53:03 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 5EF3020545BB; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 5EF3020545BB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=8pDd4rW21Amh7pp2Q5SbX8UkqDaX4fBhOI4464GNYtQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dq0AZIXtrnw9EtpZOhBDMlRhYU+yPh0Q6SDrGUPnavZ4AbxWkzMt0o6TlJMDE7fjl uMzjD8qyiDpCuUwR83xX1kwiq40qckpBpOUbe+0Upg9968p9V+hxAU1yDLEDGpfW83 0qKqIfPQa3njndkvYXCvQUAQyK//5UfYc5MaPcQo= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 06/30] drivers/baseband: replace packed attributes Date: Tue, 26 Nov 2024 16:52:17 -0800 Message-Id: <1732668761-5556-7-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retlzaff --- drivers/baseband/acc/acc_common.h | 59 +++++++++++-------- drivers/baseband/fpga_5gnr_fec/agx100_pmd.h | 16 ++--- .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h | 4 +- drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h | 8 +-- drivers/baseband/fpga_lte_fec/fpga_lte_fec.c | 12 ++-- drivers/baseband/la12xx/bbdev_la12xx_ipc.h | 32 +++++----- 6 files changed, 72 insertions(+), 59 deletions(-) diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index bf218332be..74c6787e4b 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -160,6 +160,7 @@ extern int acc_common_logtype; RTE_LOG_LINE(level, ACC_COMMON, __VA_ARGS__) /* ACC100 DMA Descriptor triplet */ +__rte_packed_begin struct acc_dma_triplet { uint64_t address; uint32_t blen:20, @@ -168,7 +169,7 @@ struct acc_dma_triplet { dma_ext:1, res1:2, blkid:4; -} __rte_packed; +} __rte_packed_end; /* ACC100 Queue Manager Enqueue PCI Register */ @@ -183,7 +184,8 @@ union acc_enqueue_reg_fmt { }; /* FEC 4G Uplink Frame Control Word */ -struct __rte_packed acc_fcw_td { +__rte_packed_begin +struct acc_fcw_td { uint8_t fcw_ver:4, num_maps:4; /* Unused in ACC100 */ uint8_t filler:6, /* Unused in ACC100 */ @@ -220,10 +222,11 @@ struct __rte_packed acc_fcw_td { rsrvd4:10; }; }; -}; +} __rte_packed_end; /* FEC 4G Downlink Frame Control Word */ -struct __rte_packed acc_fcw_te { +__rte_packed_begin +struct acc_fcw_te { uint16_t k_neg; uint16_t k_pos; uint8_t c_neg; @@ -251,10 +254,11 @@ struct __rte_packed acc_fcw_te { uint8_t code_block_mode:1, rsrvd8:7; uint64_t rsrvd9; -}; +} __rte_packed_end; /* FEC 5GNR Downlink Frame Control Word */ -struct __rte_packed acc_fcw_le { +__rte_packed_begin +struct acc_fcw_le { uint32_t FCWversion:4, qm:4, nfiller:11, @@ -279,10 +283,11 @@ struct __rte_packed acc_fcw_le { uint32_t res6; uint32_t res7; uint32_t res8; -}; +} __rte_packed_end; /* FEC 5GNR Uplink Frame Control Word */ -struct __rte_packed acc_fcw_ld { +__rte_packed_begin +struct acc_fcw_ld { uint32_t FCWversion:4, qm:4, nfiller:11, @@ -326,10 +331,11 @@ struct __rte_packed acc_fcw_ld { tb_crc_select:2, /* Not supported in ACC100 */ dec_llrclip:2, /* Not supported in VRB1 */ tb_trailer_size:20; /* Not supported in ACC100 */ -}; +} __rte_packed_end; /* FFT Frame Control Word */ -struct __rte_packed acc_fcw_fft { +__rte_packed_begin +struct acc_fcw_fft { uint32_t in_frame_size:16, leading_pad_size:16; uint32_t out_frame_size:16, @@ -351,10 +357,11 @@ struct __rte_packed acc_fcw_fft { power_shift:4, power_en:1, res:19; -}; +} __rte_packed_end; /* FFT Frame Control Word. */ -struct __rte_packed acc_fcw_fft_3 { +__rte_packed_begin +struct acc_fcw_fft_3 { uint32_t in_frame_size:16, leading_pad_size:16; uint32_t out_frame_size:16, @@ -381,11 +388,12 @@ struct __rte_packed acc_fcw_fft_3 { uint16_t cs_theta_0[ACC_MAX_CS]; uint32_t cs_theta_d[ACC_MAX_CS]; int8_t cs_time_offset[ACC_MAX_CS]; -}; +} __rte_packed_end; /* MLD-TS Frame Control Word */ -struct __rte_packed acc_fcw_mldts { +__rte_packed_begin +struct acc_fcw_mldts { uint32_t fcw_version:4, res0:12, nrb:13, /* 1 to 1925 */ @@ -409,7 +417,7 @@ struct __rte_packed acc_fcw_mldts { uint32_t pad2; uint32_t pad3; uint32_t pad4; -}; +} __rte_packed_end; /* DMA Response Descriptor */ union acc_dma_rsp_desc { @@ -435,7 +443,8 @@ union acc_dma_rsp_desc { }; /* DMA Request Descriptor */ -struct __rte_packed acc_dma_req_desc { +__rte_packed_begin +struct acc_dma_req_desc { union { struct{ uint32_t type:4, @@ -496,7 +505,7 @@ struct __rte_packed acc_dma_req_desc { }; uint64_t pad3[ACC_DMA_DESC_PADDINGS]; /* pad to 64 bits */ }; -}; +} __rte_packed_end; /* ACC100 DMA Descriptor */ union acc_dma_desc { @@ -506,6 +515,7 @@ union acc_dma_desc { }; /* Union describing Info Ring entry */ +__rte_packed_begin union acc_info_ring_data { uint32_t val; struct { @@ -534,25 +544,28 @@ union acc_info_ring_data { uint32_t loop_vrb2: 1; uint32_t valid_vrb2: 1; }; -} __rte_packed; +} __rte_packed_end; -struct __rte_packed acc_pad_ptr { +__rte_packed_begin +struct acc_pad_ptr { void *op_addr; uint64_t pad1; /* pad to 64 bits */ -}; +} __rte_packed_end; -struct __rte_packed acc_ptrs { +__rte_packed_begin +struct acc_ptrs { struct acc_pad_ptr ptr[ACC_COMPANION_PTRS]; -}; +} __rte_packed_end; /* Union describing Info Ring entry */ +__rte_packed_begin union acc_harq_layout_data { uint32_t val; struct { uint16_t offset; uint16_t size0; }; -} __rte_packed; +} __rte_packed_end; /** * Structure with details about RTE_BBDEV_EVENT_DEQUEUE event. It's passed to diff --git a/drivers/baseband/fpga_5gnr_fec/agx100_pmd.h b/drivers/baseband/fpga_5gnr_fec/agx100_pmd.h index 5e562376c9..b6ef1d3f20 100644 --- a/drivers/baseband/fpga_5gnr_fec/agx100_pmd.h +++ b/drivers/baseband/fpga_5gnr_fec/agx100_pmd.h @@ -49,7 +49,7 @@ enum { }; /* AGX100 TX Slice Descriptor. */ -struct __rte_packed agx100_input_slice_desc { +__rte_packed_begin struct agx100_input_slice_desc { uint32_t input_start_addr_lo; uint32_t input_start_addr_hi; uint32_t input_slice_length:21, @@ -58,10 +58,10 @@ struct __rte_packed agx100_input_slice_desc { start_of_pkt:1; uint32_t input_slice_time_stamp:31, input_c:1; -}; +} __rte_packed_end; /* AGX100 RX Slice Descriptor. */ -struct __rte_packed agx100_output_slice_desc { +__rte_packed_begin struct agx100_output_slice_desc { uint32_t output_start_addr_lo; uint32_t output_start_addr_hi; uint32_t output_slice_length:21, @@ -70,10 +70,10 @@ struct __rte_packed agx100_output_slice_desc { start_of_pkt:1; uint32_t output_slice_time_stamp:31, output_c:1; -}; +} __rte_packed_end; /* AGX100 DL DMA Encoding Request Descriptor. */ -struct __rte_packed agx100_dma_enc_desc { +__rte_packed_begin struct agx100_dma_enc_desc { uint32_t done:1, /**< 0: not completed 1: completed. */ rsrvd0:17, error_msg:2, @@ -161,10 +161,10 @@ struct __rte_packed agx100_dma_enc_desc { uint8_t sw_ctxt[AGX100_RING_DESC_LEN_UNIT_BYTES * (AGX100_RING_DESC_ENTRY_LENGTH - 1)]; }; -}; +} __rte_packed_end; /* AGX100 UL DMA Decoding Request Descriptor. */ -struct __rte_packed agx100_dma_dec_desc { +__rte_packed_begin struct agx100_dma_dec_desc { uint32_t done:1, /**< 0: not completed 1: completed. */ tb_crc_pass:1, /**< 0: doesn't pass 1: pass. */ cb_crc_all_pass:1, /**< 0: doesn't pass 1: pass. */ @@ -262,7 +262,7 @@ struct __rte_packed agx100_dma_dec_desc { uint8_t sw_ctxt[AGX100_RING_DESC_LEN_UNIT_BYTES * (AGX100_RING_DESC_ENTRY_LENGTH - 1)]; }; -}; +} __rte_packed_end; /* AGX100 DMA Descriptor. */ union agx100_dma_desc { diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h index 10a19e4dec..24797b8ef3 100644 --- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h +++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h @@ -89,7 +89,7 @@ enum { }; /* FPGA 5GNR Ring Control Register. */ -struct __rte_packed fpga_5gnr_ring_ctrl_reg { +__rte_packed_begin struct fpga_5gnr_ring_ctrl_reg { uint64_t ring_base_addr; uint64_t ring_head_addr; uint16_t ring_size:11; @@ -107,7 +107,7 @@ struct __rte_packed fpga_5gnr_ring_ctrl_reg { uint16_t rsrvd3; uint16_t head_point; uint16_t rsrvd4; -}; +} __rte_packed_end; /* Private data structure for each FPGA 5GNR device. */ struct fpga_5gnr_fec_device { diff --git a/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h b/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h index 9a488ae8d6..ca05ddd593 100644 --- a/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h +++ b/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h @@ -46,7 +46,7 @@ enum { }; /* VC 5GNR FPGA FEC DMA Encoding Request Descriptor. */ -struct __rte_packed vc_5gnr_dma_enc_desc { +__rte_packed_begin struct vc_5gnr_dma_enc_desc { uint32_t done:1, rsrvd0:7, error:4, @@ -84,10 +84,10 @@ struct __rte_packed vc_5gnr_dma_enc_desc { uint8_t sw_ctxt[VC_5GNR_RING_DESC_LEN_UNIT_BYTES * (VC_5GNR_RING_DESC_ENTRY_LENGTH - 1)]; }; -}; +} __rte_packed_end; /* VC 5GNR FPGA DPC FEC DMA Decoding Request Descriptor. */ -struct __rte_packed vc_5gnr_dma_dec_desc { +__rte_packed_begin struct vc_5gnr_dma_dec_desc { uint32_t done:1, iter:5, et_pass:1, @@ -128,7 +128,7 @@ struct __rte_packed vc_5gnr_dma_dec_desc { uint32_t sw_ctxt[8 * (VC_5GNR_RING_DESC_ENTRY_LENGTH - 1)]; }; -}; +} __rte_packed_end; /* Vista Creek 5GNR DMA Descriptor. */ union vc_5gnr_dma_desc { diff --git a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c index ed21a18b62..c67027618c 100644 --- a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c +++ b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c @@ -114,7 +114,7 @@ enum { }; /* FPGA LTE FEC DMA Encoding Request Descriptor */ -struct __rte_packed fpga_dma_enc_desc { +__rte_packed_begin struct fpga_dma_enc_desc { uint32_t done:1, rsrvd0:11, error:4, @@ -148,10 +148,10 @@ struct __rte_packed fpga_dma_enc_desc { uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES * (FPGA_RING_DESC_ENTRY_LENGTH - 1)]; }; -}; +} __rte_packed_end; /* FPGA LTE FEC DMA Decoding Request Descriptor */ -struct __rte_packed fpga_dma_dec_desc { +__rte_packed_begin struct fpga_dma_dec_desc { uint32_t done:1, iter:5, rsrvd0:2, @@ -188,7 +188,7 @@ struct __rte_packed fpga_dma_dec_desc { uint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)]; }; -}; +} __rte_packed_end; /* FPGA LTE DMA Descriptor */ union fpga_dma_desc { @@ -197,7 +197,7 @@ union fpga_dma_desc { }; /* FPGA LTE FEC Ring Control Register */ -struct __rte_packed fpga_ring_ctrl_reg { +__rte_packed_begin struct fpga_ring_ctrl_reg { uint64_t ring_base_addr; uint64_t ring_head_addr; uint16_t ring_size:11; @@ -216,7 +216,7 @@ struct __rte_packed fpga_ring_ctrl_reg { uint16_t head_point; uint16_t rsrvd4; -}; +} __rte_packed_end; /* Private data structure for each FPGA FEC device */ struct fpga_lte_fec_device { diff --git a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h index b6a7f677d0..b915a71cca 100644 --- a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h +++ b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h @@ -93,7 +93,7 @@ typedef struct { #define IPC_GET_CI_INDEX(x) (x & IPC_PI_CI_INDEX_MASK) /** buffer ring common metadata */ -typedef struct ipc_bd_ring_md { +typedef __rte_packed_begin struct ipc_bd_ring_md { volatile uint32_t pi; /**< Producer index and flag (MSB) * which flip for each Ring wrapping */ @@ -102,10 +102,10 @@ typedef struct ipc_bd_ring_md { */ uint32_t ring_size; /**< depth (Used to roll-over pi/ci) */ uint32_t msg_size; /**< Size of the each buffer */ -} __rte_packed ipc_br_md_t; +} __rte_packed_end ipc_br_md_t; /** IPC buffer descriptor */ -typedef struct ipc_buffer_desc { +typedef __rte_packed_begin struct ipc_buffer_desc { union { uint64_t host_virt; /**< msg's host virtual address */ struct { @@ -115,9 +115,9 @@ typedef struct ipc_buffer_desc { }; uint32_t modem_ptr; /**< msg's modem physical address */ uint32_t len; /**< msg len */ -} __rte_packed ipc_bd_t; +} __rte_packed_end ipc_bd_t; -typedef struct ipc_channel { +typedef __rte_packed_begin struct ipc_channel { uint32_t ch_id; /**< Channel id */ ipc_br_md_t md; /**< Metadata for BD ring */ ipc_bd_t bd_h[IPC_MAX_DEPTH]; /**< Buffer Descriptor on Host */ @@ -134,22 +134,22 @@ typedef struct ipc_channel { * circular buffer size */ uint32_t host_ipc_params; /**< Address for host IPC parameters */ -} __rte_packed ipc_ch_t; +} __rte_packed_end ipc_ch_t; -typedef struct ipc_instance { +typedef __rte_packed_begin struct ipc_instance { uint32_t instance_id; /**< instance id, use to init this * instance by ipc_init API */ uint32_t initialized; /**< Set in ipc_init */ ipc_ch_t ch_list[IPC_MAX_CHANNEL_COUNT]; /**< Channel descriptors in this instance */ -} __rte_packed ipc_instance_t; +} __rte_packed_end ipc_instance_t; -typedef struct ipc_metadata { +typedef __rte_packed_begin struct ipc_metadata { uint32_t ipc_host_signature; /**< IPC host signature, Set by host/L2 */ uint32_t ipc_geul_signature; /**< IPC geul signature, Set by modem */ ipc_instance_t instance_list[IPC_MAX_INSTANCE_COUNT]; -} __rte_packed ipc_metadata_t; +} __rte_packed_end ipc_metadata_t; typedef struct ipc_channel_us_priv { int32_t eventfd; @@ -221,24 +221,24 @@ struct bbdev_ipc_dequeue_op { * of the parameters which are also part of Shared BD ring. Read access * of these parameters from the host side would not be over PCI. */ -typedef struct host_ipc_params { +typedef __rte_packed_begin struct host_ipc_params { volatile uint32_t pi; volatile uint32_t ci; volatile uint32_t bd_m_modem_ptr[IPC_MAX_DEPTH]; -} __rte_packed host_ipc_params_t; +} __rte_packed_end host_ipc_params_t; -struct hif_ipc_regs { +__rte_packed_begin struct hif_ipc_regs { uint32_t ipc_mdata_offset; uint32_t ipc_mdata_size; -} __rte_packed; +} __rte_packed_end; -struct gul_hif { +__rte_packed_begin struct gul_hif { uint32_t ver; uint32_t hif_ver; uint32_t status; volatile uint32_t host_ready; volatile uint32_t mod_ready; struct hif_ipc_regs ipc_regs; -} __rte_packed; +} __rte_packed_end; #endif From patchwork Wed Nov 27 00:52:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148876 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8454245D31; Wed, 27 Nov 2024 01:54:03 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4937342D26; Wed, 27 Nov 2024 01:53:17 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id ED52C427C4 for ; Wed, 27 Nov 2024 01:53:03 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 6DB3E20545BC; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 6DB3E20545BC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=Nv0AHZftUuKGv90VAre+BW/rCB5mIrRuVYsn6b2gFZg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T19srqIH7NGLReQWJD0UVWl0rzTGI1FD/OaI53KPUw+Jap+JkhA2ZAwJmzbprTkrG Gk1zZKBRcILKIVZrwq2Rbm96dU9H5Gtw412prn/JRXCTJKllY1KPX3PdJk4b3pg67f DYcLQj4Zy+POgirvd9ZO1dwkrUZWIgunE0yrT2B8= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 07/30] drivers/bus: replace packed attributes Date: Tue, 26 Nov 2024 16:52:18 -0800 Message-Id: <1732668761-5556-8-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retzlaff --- drivers/bus/dpaa/include/fsl_bman.h | 15 ++- drivers/bus/dpaa/include/fsl_fman.h | 4 +- drivers/bus/dpaa/include/fsl_qman.h | 155 ++++++++++++++------------- drivers/bus/ifpga/bus_ifpga_driver.h | 8 +- drivers/bus/vmbus/rte_vmbus_reg.h | 108 +++++++++---------- 5 files changed, 150 insertions(+), 140 deletions(-) diff --git a/drivers/bus/dpaa/include/fsl_bman.h b/drivers/bus/dpaa/include/fsl_bman.h index 34d7eb32ce..9d3fc9f395 100644 --- a/drivers/bus/dpaa/include/fsl_bman.h +++ b/drivers/bus/dpaa/include/fsl_bman.h @@ -86,6 +86,7 @@ static inline dma_addr_t bm_buf_addr(const struct bm_buffer *buf) } while (0) /* See 1.5.3.5.4: "Release Command" */ +__rte_packed_begin struct bm_rcr_entry { union { struct { @@ -95,7 +96,7 @@ struct bm_rcr_entry { }; struct bm_buffer bufs[8]; }; -} __packed; +} __rte_packed_end; #define BM_RCR_VERB_VBIT 0x80 #define BM_RCR_VERB_CMD_MASK 0x70 /* one of two values; */ #define BM_RCR_VERB_CMD_BPID_SINGLE 0x20 @@ -104,20 +105,23 @@ struct bm_rcr_entry { /* See 1.5.3.1: "Acquire Command" */ /* See 1.5.3.2: "Query Command" */ +__rte_packed_begin struct bm_mcc_acquire { u8 bpid; u8 __reserved1[62]; -} __packed; +} __rte_packed_end; +__rte_packed_begin struct bm_mcc_query { u8 __reserved2[63]; -} __packed; +} __rte_packed_end; +__rte_packed_begin struct bm_mc_command { u8 __dont_write_directly__verb; union { struct bm_mcc_acquire acquire; struct bm_mcc_query query; }; -} __packed; +} __rte_packed_end; #define BM_MCC_VERB_VBIT 0x80 #define BM_MCC_VERB_CMD_MASK 0x70 /* where the verb contains; */ #define BM_MCC_VERB_CMD_ACQUIRE 0x10 @@ -136,6 +140,7 @@ struct bm_pool_state { } as, ds; }; +__rte_packed_begin struct bm_mc_result { union { struct { @@ -152,7 +157,7 @@ struct bm_mc_result { } acquire; struct bm_pool_state query; }; -} __packed; +} __rte_packed_end; #define BM_MCR_VERB_VBIT 0x80 #define BM_MCR_VERB_CMD_MASK BM_MCC_VERB_CMD_MASK #define BM_MCR_VERB_CMD_ACQUIRE BM_MCC_VERB_CMD_ACQUIRE diff --git a/drivers/bus/dpaa/include/fsl_fman.h b/drivers/bus/dpaa/include/fsl_fman.h index 5a9750ad0c..513d14cced 100644 --- a/drivers/bus/dpaa/include/fsl_fman.h +++ b/drivers/bus/dpaa/include/fsl_fman.h @@ -12,7 +12,7 @@ /* Status field in FD is updated on Rx side by FMAN with following information. * Refer to field description in FM BG. */ -struct fm_status_t { +__rte_packed_begin struct fm_status_t { unsigned int reserved0:3; unsigned int dcl4c:1; /* Don't Check L4 Checksum */ unsigned int reserved1:1; @@ -38,7 +38,7 @@ struct fm_status_t { unsigned int phe:1; /* Header Error during parsing */ unsigned int frdr:1; /* Frame Dropped by disabled port */ unsigned int reserved5:4; -} __rte_packed; +} __rte_packed_end; /* Set MAC address for a particular interface */ __rte_internal diff --git a/drivers/bus/dpaa/include/fsl_qman.h b/drivers/bus/dpaa/include/fsl_qman.h index 25dbf72fd4..7886d466d1 100644 --- a/drivers/bus/dpaa/include/fsl_qman.h +++ b/drivers/bus/dpaa/include/fsl_qman.h @@ -221,6 +221,7 @@ static inline dma_addr_t qm_fd_addr(const struct qm_fd *fd) } while (0) /* Scatter/Gather table entry */ +__rte_packed_begin struct qm_sg_entry { union { struct { @@ -273,7 +274,7 @@ struct qm_sg_entry { }; u16 val_off; }; -} __packed; +} __rte_packed_end; static inline u64 qm_sg_entry_get64(const struct qm_sg_entry *sg) { return sg->addr; @@ -292,6 +293,7 @@ static inline dma_addr_t qm_sg_addr(const struct qm_sg_entry *sg) } while (0) /* See 1.5.8.1: "Enqueue Command" */ +__rte_packed_begin struct __rte_aligned(8) qm_eqcr_entry { u8 __dont_write_directly__verb; u8 dca; @@ -301,7 +303,7 @@ struct __rte_aligned(8) qm_eqcr_entry { u32 tag; struct qm_fd fd; /* this has alignment 8 */ u8 __reserved3[32]; -} __packed; +} __rte_packed_end; /* "Frame Dequeue Response" */ @@ -330,8 +332,9 @@ struct __rte_aligned(8) qm_dqrr_entry { /* "ERN Message Response" */ /* "FQ State Change Notification" */ -struct __rte_aligned(8) qm_mr_entry { +__rte_packed_begin struct __rte_aligned(8) qm_mr_entry { union { + __rte_packed_begin alignas(8) struct { u8 verb; u8 dca; @@ -341,7 +344,8 @@ struct __rte_aligned(8) qm_mr_entry { u32 fqid; /* 24-bit */ u32 tag; struct qm_fd fd; /* this has alignment 8 */ - } __packed ern; + } __rte_packed_end ern; + __rte_packed_begin alignas(8) struct { u8 verb; #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ @@ -359,7 +363,8 @@ struct __rte_aligned(8) qm_mr_entry { u32 fqid; /* 24-bit */ u32 tag; struct qm_fd fd; /* this has alignment 8 */ - } __packed dcern; + } __rte_packed_end dcern; + __rte_packed_begin alignas(8) struct { u8 verb; u8 fqs; /* Frame Queue Status */ @@ -367,10 +372,10 @@ struct __rte_aligned(8) qm_mr_entry { u32 fqid; /* 24-bit */ u32 contextB; u8 __reserved2[16]; - } __packed fq; /* FQRN/FQRNI/FQRL/FQPN */ + } __rte_packed_end fq; /* FQRN/FQRNI/FQRL/FQPN */ }; u8 __reserved2[32]; -} __packed; +} __rte_packed_end; #define QM_MR_VERB_VBIT 0x80 /* * ERNs originating from direct-connect portals ("dcern") use 0x20 as a verb @@ -405,7 +410,7 @@ struct __rte_aligned(8) qm_mr_entry { * latter has two inlines to assist with converting to/from the mant+exp * representation. */ -struct qm_fqd_stashing { +__rte_packed_begin struct qm_fqd_stashing { /* See QM_STASHING_EXCL_<...> */ #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ u8 exclusive; @@ -421,8 +426,8 @@ struct qm_fqd_stashing { u8 __reserved1:2; u8 exclusive; #endif -} __packed; -struct qm_fqd_taildrop { +} __rte_packed_end; +__rte_packed_begin struct qm_fqd_taildrop { #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ u16 __reserved1:3; u16 mant:8; @@ -432,8 +437,8 @@ struct qm_fqd_taildrop { u16 mant:8; u16 __reserved1:3; #endif -} __packed; -struct qm_fqd_oac { +} __rte_packed_end; +__rte_packed_begin struct qm_fqd_oac { /* "Overhead Accounting Control", see QM_OAC_<...> */ #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ u8 oac:2; /* "Overhead Accounting Control" */ @@ -444,11 +449,11 @@ struct qm_fqd_oac { #endif /* Two's-complement value (-128 to +127) */ signed char oal; /* "Overhead Accounting Length" */ -} __packed; -struct qm_fqd { +} __rte_packed_end; +__rte_packed_begin struct qm_fqd { union { u8 orpc; - struct { + __rte_packed_begin struct { #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ u8 __reserved1:2; u8 orprws:3; @@ -460,13 +465,13 @@ struct qm_fqd { u8 orprws:3; u8 __reserved1:2; #endif - } __packed; + } __rte_packed_end; }; u8 cgid; u16 fq_ctrl; /* See QM_FQCTRL_<...> */ union { u16 dest_wq; - struct { + __rte_packed_begin struct { #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ u16 channel:13; /* qm_channel */ u16 wq:3; @@ -474,7 +479,7 @@ struct qm_fqd { u16 wq:3; u16 channel:13; /* qm_channel */ #endif - } __packed dest; + } __rte_packed_end dest; }; #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ u16 __reserved2:1; @@ -509,7 +514,7 @@ struct qm_fqd { }; /* Treat it as s/w portal stashing config */ /* see "FQD Context_A field used for [...]" */ - struct { + __rte_packed_begin struct { #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ struct qm_fqd_stashing stashing; /* @@ -523,10 +528,10 @@ struct qm_fqd { u16 context_hi; struct qm_fqd_stashing stashing; #endif - } __packed; + } __rte_packed_end; } context_a; struct qm_fqd_oac oac_query; -} __packed; +} __rte_packed_end; /* 64-bit converters for context_hi/lo */ static inline u64 qm_fqd_stashing_get64(const struct qm_fqd *fqd) { @@ -618,10 +623,10 @@ static inline u32 qm_fqd_taildrop_get(const struct qm_fqd_taildrop *td) * Slope = SA / (2 ^ Sn) * MaxP = 4 * (Pn + 1) */ -struct qm_cgr_wr_parm { +__rte_packed_begin struct qm_cgr_wr_parm { union { u32 word; - struct { + __rte_packed_begin struct { #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ u32 MA:8; u32 Mn:5; @@ -635,9 +640,9 @@ struct qm_cgr_wr_parm { u32 Mn:5; u32 MA:8; #endif - } __packed; + } __rte_packed_end; }; -} __packed; +} __rte_packed_end; /* * This struct represents the 13-bit "CS_THRES" CGR field. In the corresponding * management commands, this is padded to a 16-bit structure field, so that's @@ -645,10 +650,10 @@ struct qm_cgr_wr_parm { * these fields as follows; * CS threshold = TA * (2 ^ Tn) */ -struct qm_cgr_cs_thres { +__rte_packed_begin struct qm_cgr_cs_thres { union { u16 hword; - struct { + __rte_packed_begin struct { #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ u16 __reserved:3; u16 TA:8; @@ -658,15 +663,15 @@ struct qm_cgr_cs_thres { u16 TA:8; u16 __reserved:3; #endif - } __packed; + } __rte_packed_end; }; -} __packed; +} __rte_packed_end; /* * This identical structure of CGR fields is present in the "Init/Modify CGR" * commands and the "Query CGR" result. It's suctioned out here into its own * struct. */ -struct __qm_mc_cgr { +__rte_packed_begin struct __qm_mc_cgr { struct qm_cgr_wr_parm wr_parm_g; struct qm_cgr_wr_parm wr_parm_y; struct qm_cgr_wr_parm wr_parm_r; @@ -694,7 +699,7 @@ struct __qm_mc_cgr { u16 __cs_thres; }; u8 mode; /* QMAN_CGR_MODE_FRAME not supported in rev1.0 */ -} __packed; +} __rte_packed_end; #define QM_CGR_EN 0x01 /* For wr_en_*, cscn_en, cstd_en */ #define QM_CGR_TARG_UDP_CTRL_WRITE_BIT 0x8000 /* value written to portal bit*/ #define QM_CGR_TARG_UDP_CTRL_DCP 0x4000 /* 0: SWP, 1: DCP */ @@ -733,25 +738,25 @@ static inline int qm_cgr_cs_thres_set64(struct qm_cgr_cs_thres *th, u64 val, /* See 1.5.8.6.2: "CGR Test Write" */ /* See 1.5.8.6.3: "Query CGR" */ /* See 1.5.8.6.4: "Query Congestion Group State" */ -struct qm_mcc_initfq { +__rte_packed_begin struct qm_mcc_initfq { u8 __reserved1; u16 we_mask; /* Write Enable Mask */ u32 fqid; /* 24-bit */ u16 count; /* Initialises 'count+1' FQDs */ struct qm_fqd fqd; /* the FQD fields go here */ u8 __reserved3[30]; -} __packed; -struct qm_mcc_queryfq { +} __rte_packed_end; +__rte_packed_begin struct qm_mcc_queryfq { u8 __reserved1[3]; u32 fqid; /* 24-bit */ u8 __reserved2[56]; -} __packed; -struct qm_mcc_queryfq_np { +} __rte_packed_end; +__rte_packed_begin struct qm_mcc_queryfq_np { u8 __reserved1[3]; u32 fqid; /* 24-bit */ u8 __reserved2[56]; -} __packed; -struct qm_mcc_alterfq { +} __rte_packed_end; +__rte_packed_begin struct qm_mcc_alterfq { u8 __reserved1[3]; u32 fqid; /* 24-bit */ u8 __reserved2; @@ -759,37 +764,37 @@ struct qm_mcc_alterfq { u8 __reserved3[10]; u32 context_b; /* frame queue context b */ u8 __reserved4[40]; -} __packed; -struct qm_mcc_initcgr { +} __rte_packed_end; +__rte_packed_begin struct qm_mcc_initcgr { u8 __reserved1; u16 we_mask; /* Write Enable Mask */ struct __qm_mc_cgr cgr; /* CGR fields */ u8 __reserved2[2]; u8 cgid; u8 __reserved4[32]; -} __packed; -struct qm_mcc_cgrtestwrite { +} __rte_packed_end; +__rte_packed_begin struct qm_mcc_cgrtestwrite { u8 __reserved1[2]; u8 i_bcnt_hi:8;/* high 8-bits of 40-bit "Instant" */ u32 i_bcnt_lo; /* low 32-bits of 40-bit */ u8 __reserved2[23]; u8 cgid; u8 __reserved3[32]; -} __packed; -struct qm_mcc_querycgr { +} __rte_packed_end; +__rte_packed_begin struct qm_mcc_querycgr { u8 __reserved1[30]; u8 cgid; u8 __reserved2[32]; -} __packed; -struct qm_mcc_querycongestion { +} __rte_packed_end; +__rte_packed_begin struct qm_mcc_querycongestion { u8 __reserved[63]; -} __packed; -struct qm_mcc_querywq { +} __rte_packed_end; +__rte_packed_begin struct qm_mcc_querywq { u8 __reserved; /* select channel if verb != QUERYWQ_DEDICATED */ union { u16 channel_wq; /* ignores wq (3 lsbits) */ - struct { + __rte_packed_begin struct { #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ u16 id:13; /* qm_channel */ u16 __reserved1:3; @@ -797,12 +802,12 @@ struct qm_mcc_querywq { u16 __reserved1:3; u16 id:13; /* qm_channel */ #endif - } __packed channel; + } __rte_packed_end channel; }; u8 __reserved2[60]; -} __packed; +} __rte_packed_end; -struct qm_mc_command { +__rte_packed_begin struct qm_mc_command { u8 __dont_write_directly__verb; union { struct qm_mcc_initfq initfq; @@ -815,7 +820,7 @@ struct qm_mc_command { struct qm_mcc_querycongestion querycongestion; struct qm_mcc_querywq querywq; }; -} __packed; +} __rte_packed_end; /* INITFQ-specific flags */ #define QM_INITFQ_WE_MASK 0x01ff /* 'Write Enable' flags; */ @@ -842,15 +847,15 @@ struct qm_mc_command { #define QM_CGR_WE_CS_THRES 0x0002 #define QM_CGR_WE_MODE 0x0001 -struct qm_mcr_initfq { +__rte_packed_begin struct qm_mcr_initfq { u8 __reserved1[62]; -} __packed; -struct qm_mcr_queryfq { +} __rte_packed_end; +__rte_packed_begin struct qm_mcr_queryfq { u8 __reserved1[8]; struct qm_fqd fqd; /* the FQD fields are here */ u8 __reserved2[30]; -} __packed; -struct qm_mcr_queryfq_np { +} __rte_packed_end; +__rte_packed_begin struct qm_mcr_queryfq_np { u8 __reserved1; u8 state; /* QM_MCR_NP_STATE_*** */ #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ @@ -929,16 +934,16 @@ struct qm_mcr_queryfq_np { u16 od2_sfdr; /* QM_MCR_NP_OD2_*** */ u16 od3_sfdr; /* QM_MCR_NP_OD3_*** */ #endif -} __packed; +} __rte_packed_end; -struct qm_mcr_alterfq { +__rte_packed_begin struct qm_mcr_alterfq { u8 fqs; /* Frame Queue Status */ u8 __reserved1[61]; -} __packed; -struct qm_mcr_initcgr { +} __rte_packed_end; +__rte_packed_begin struct qm_mcr_initcgr { u8 __reserved1[62]; -} __packed; -struct qm_mcr_cgrtestwrite { +} __rte_packed_end; +__rte_packed_begin struct qm_mcr_cgrtestwrite { u16 __reserved1; struct __qm_mc_cgr cgr; /* CGR fields */ u8 __reserved2[3]; @@ -953,8 +958,8 @@ struct qm_mcr_cgrtestwrite { u16 wr_prob_y; u16 wr_prob_r; u8 __reserved5[8]; -} __packed; -struct qm_mcr_querycgr { +} __rte_packed_end; +__rte_packed_begin struct qm_mcr_querycgr { u16 __reserved1; struct __qm_mc_cgr cgr; /* CGR fields */ u8 __reserved2[3]; @@ -990,21 +995,21 @@ struct qm_mcr_querycgr { u32 cscn_targ_swp[4]; u8 __reserved5[16]; }; -} __packed; +} __rte_packed_end; struct __qm_mcr_querycongestion { u32 state[8]; }; -struct qm_mcr_querycongestion { +__rte_packed_begin struct qm_mcr_querycongestion { u8 __reserved[30]; /* Access this struct using QM_MCR_QUERYCONGESTION() */ struct __qm_mcr_querycongestion state; -} __packed; -struct qm_mcr_querywq { +} __rte_packed_end; +__rte_packed_begin struct qm_mcr_querywq { union { u16 channel_wq; /* ignores wq (3 lsbits) */ - struct { + __rte_packed_begin struct { #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ u16 id:13; /* qm_channel */ u16 __reserved:3; @@ -1012,13 +1017,13 @@ struct qm_mcr_querywq { u16 __reserved:3; u16 id:13; /* qm_channel */ #endif - } __packed channel; + } __rte_packed_end channel; }; u8 __reserved[28]; u32 wq_len[8]; -} __packed; +} __rte_packed_end; -struct qm_mc_result { +__rte_packed_begin struct qm_mc_result { u8 verb; u8 result; union { @@ -1032,7 +1037,7 @@ struct qm_mc_result { struct qm_mcr_querycongestion querycongestion; struct qm_mcr_querywq querywq; }; -} __packed; +} __rte_packed_end; #define QM_MCR_VERB_RRID 0x80 #define QM_MCR_VERB_MASK QM_MCC_VERB_MASK diff --git a/drivers/bus/ifpga/bus_ifpga_driver.h b/drivers/bus/ifpga/bus_ifpga_driver.h index af151ffd4b..c292144130 100644 --- a/drivers/bus/ifpga/bus_ifpga_driver.h +++ b/drivers/bus/ifpga/bus_ifpga_driver.h @@ -29,10 +29,10 @@ struct rte_afu_driver; #define IFPGA_BUS_BITSTREAM_PATH_MAX_LEN 256 -struct rte_afu_uuid { +__rte_packed_begin struct rte_afu_uuid { uint64_t uuid_low; uint64_t uuid_high; -} __rte_packed; +} __rte_packed_end; #define IFPGA_BUS_DEV_PORT_MAX 4 @@ -40,10 +40,10 @@ struct rte_afu_uuid { * A structure describing an ID for a AFU driver. Each driver provides a * table of these IDs for each device that it supports. */ -struct rte_afu_id { +__rte_packed_begin struct rte_afu_id { struct rte_afu_uuid uuid; int port; /**< port number */ -} __rte_packed; +} __rte_packed_end; /** * A structure PR (Partial Reconfiguration) configuration AFU driver. diff --git a/drivers/bus/vmbus/rte_vmbus_reg.h b/drivers/bus/vmbus/rte_vmbus_reg.h index e3299aa871..239ddbe5f0 100644 --- a/drivers/bus/vmbus/rte_vmbus_reg.h +++ b/drivers/bus/vmbus/rte_vmbus_reg.h @@ -12,14 +12,14 @@ #define VMBUS_MSG_DSIZE_MAX 240 #define VMBUS_MSG_SIZE 256 -struct vmbus_message { +__rte_packed_begin struct vmbus_message { uint32_t type; /* HYPERV_MSGTYPE_ */ uint8_t dsize; /* data size */ uint8_t flags; /* VMBUS_MSGFLAG_ */ uint16_t rsvd; uint64_t id; uint8_t data[VMBUS_MSG_DSIZE_MAX]; -} __rte_packed; +} __rte_packed_end; #define VMBUS_MSGFLAG_PENDING 0x01 @@ -27,10 +27,10 @@ struct vmbus_message { * Hyper-V Monitor Notification Facility */ -struct vmbus_mon_trig { +__rte_packed_begin struct vmbus_mon_trig { RTE_ATOMIC(uint32_t) pending; uint32_t armed; -} __rte_packed; +} __rte_packed_end; #define VMBUS_MONTRIGS_MAX 4 #define VMBUS_MONTRIG_LEN 32 @@ -38,13 +38,13 @@ struct vmbus_mon_trig { /* * Hyper-V Monitor Notification Facility */ -struct hyperv_mon_param { +__rte_packed_begin struct hyperv_mon_param { uint32_t connid; uint16_t evtflag_ofs; uint16_t rsvd; -} __rte_packed; +} __rte_packed_end; -struct vmbus_mon_page { +__rte_packed_begin struct vmbus_mon_page { uint32_t state; uint32_t rsvd1; @@ -57,13 +57,13 @@ struct vmbus_mon_page { struct hyperv_mon_param param[VMBUS_MONTRIGS_MAX][VMBUS_MONTRIG_LEN]; uint8_t rsvd4[1984]; -} __rte_packed; +} __rte_packed_end; /* * Buffer ring */ -struct vmbus_bufring { +__rte_packed_begin struct vmbus_bufring { volatile uint32_t windex; volatile uint32_t rindex; @@ -108,7 +108,7 @@ struct vmbus_bufring { * !!! DO NOT place any fields below this !!! */ uint8_t data[]; -} __rte_packed; +} __rte_packed_end; /* * Channel packets @@ -137,26 +137,26 @@ vmbus_chanpkt_getlen(uint16_t pktlen) /* * GPA stuffs. */ -struct vmbus_gpa_range { +__rte_packed_begin struct vmbus_gpa_range { uint32_t len; uint32_t ofs; uint64_t page[]; -} __rte_packed; +} __rte_packed_end; /* This is actually vmbus_gpa_range.gpa_page[1] */ -struct vmbus_gpa { +__rte_packed_begin struct vmbus_gpa { uint32_t len; uint32_t ofs; uint64_t page; -} __rte_packed; +} __rte_packed_end; -struct vmbus_chanpkt_hdr { +__rte_packed_begin struct vmbus_chanpkt_hdr { uint16_t type; /* VMBUS_CHANPKT_TYPE_ */ uint16_t hlen; /* header len, in 8 bytes */ uint16_t tlen; /* total len, in 8 bytes */ uint16_t flags; /* VMBUS_CHANPKT_FLAG_ */ uint64_t xactid; -} __rte_packed; +} __rte_packed_end; static inline uint32_t vmbus_chanpkt_datalen(const struct vmbus_chanpkt_hdr *pkt) @@ -165,29 +165,29 @@ vmbus_chanpkt_datalen(const struct vmbus_chanpkt_hdr *pkt) - vmbus_chanpkt_getlen(pkt->hlen); } -struct vmbus_chanpkt { +__rte_packed_begin struct vmbus_chanpkt { struct vmbus_chanpkt_hdr hdr; -} __rte_packed; +} __rte_packed_end; -struct vmbus_rxbuf_desc { +__rte_packed_begin struct vmbus_rxbuf_desc { uint32_t len; uint32_t ofs; -} __rte_packed; +} __rte_packed_end; -struct vmbus_chanpkt_rxbuf { +__rte_packed_begin struct vmbus_chanpkt_rxbuf { struct vmbus_chanpkt_hdr hdr; uint16_t rxbuf_id; uint16_t rsvd; uint32_t rxbuf_cnt; struct vmbus_rxbuf_desc rxbuf[]; -} __rte_packed; +} __rte_packed_end; -struct vmbus_chanpkt_sglist { +__rte_packed_begin struct vmbus_chanpkt_sglist { struct vmbus_chanpkt_hdr hdr; uint32_t rsvd; uint32_t gpa_cnt; struct vmbus_gpa gpa[]; -} __rte_packed; +} __rte_packed_end; /* * Channel messages @@ -213,39 +213,39 @@ struct vmbus_chanpkt_sglist { #define VMBUS_CHANMSG_TYPE_DISCONNECT 16 /* REQ */ #define VMBUS_CHANMSG_TYPE_MAX 22 -struct vmbus_chanmsg_hdr { +__rte_packed_begin struct vmbus_chanmsg_hdr { uint32_t type; /* VMBUS_CHANMSG_TYPE_ */ uint32_t rsvd; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_CONNECT */ -struct vmbus_chanmsg_connect { +__rte_packed_begin struct vmbus_chanmsg_connect { struct vmbus_chanmsg_hdr hdr; uint32_t ver; uint32_t rsvd; uint64_t evtflags; uint64_t mnf1; uint64_t mnf2; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_CONNECT_RESP */ -struct vmbus_chanmsg_connect_resp { +__rte_packed_begin struct vmbus_chanmsg_connect_resp { struct vmbus_chanmsg_hdr hdr; uint8_t done; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_CHREQUEST */ -struct vmbus_chanmsg_chrequest { +__rte_packed_begin struct vmbus_chanmsg_chrequest { struct vmbus_chanmsg_hdr hdr; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_DISCONNECT */ -struct vmbus_chanmsg_disconnect { +__rte_packed_begin struct vmbus_chanmsg_disconnect { struct vmbus_chanmsg_hdr hdr; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_CHOPEN */ -struct vmbus_chanmsg_chopen { +__rte_packed_begin struct vmbus_chanmsg_chopen { struct vmbus_chanmsg_hdr hdr; uint32_t chanid; uint32_t openid; @@ -254,73 +254,73 @@ struct vmbus_chanmsg_chopen { uint32_t txbr_pgcnt; #define VMBUS_CHANMSG_CHOPEN_UDATA_SIZE 120 uint8_t udata[VMBUS_CHANMSG_CHOPEN_UDATA_SIZE]; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_CHOPEN_RESP */ -struct vmbus_chanmsg_chopen_resp { +__rte_packed_begin struct vmbus_chanmsg_chopen_resp { struct vmbus_chanmsg_hdr hdr; uint32_t chanid; uint32_t openid; uint32_t status; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_GPADL_CONN */ -struct vmbus_chanmsg_gpadl_conn { +__rte_packed_begin struct vmbus_chanmsg_gpadl_conn { struct vmbus_chanmsg_hdr hdr; uint32_t chanid; uint32_t gpadl; uint16_t range_len; uint16_t range_cnt; struct vmbus_gpa_range range; -} __rte_packed; +} __rte_packed_end; #define VMBUS_CHANMSG_GPADL_CONN_PGMAX 26 /* VMBUS_CHANMSG_TYPE_GPADL_SUBCONN */ -struct vmbus_chanmsg_gpadl_subconn { +__rte_packed_begin struct vmbus_chanmsg_gpadl_subconn { struct vmbus_chanmsg_hdr hdr; uint32_t msgno; uint32_t gpadl; uint64_t gpa_page[]; -} __rte_packed; +} __rte_packed_end; #define VMBUS_CHANMSG_GPADL_SUBCONN_PGMAX 28 /* VMBUS_CHANMSG_TYPE_GPADL_CONNRESP */ -struct vmbus_chanmsg_gpadl_connresp { +__rte_packed_begin struct vmbus_chanmsg_gpadl_connresp { struct vmbus_chanmsg_hdr hdr; uint32_t chanid; uint32_t gpadl; uint32_t status; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_CHCLOSE */ -struct vmbus_chanmsg_chclose { +__rte_packed_begin struct vmbus_chanmsg_chclose { struct vmbus_chanmsg_hdr hdr; uint32_t chanid; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_GPADL_DISCONN */ -struct vmbus_chanmsg_gpadl_disconn { +__rte_packed_begin struct vmbus_chanmsg_gpadl_disconn { struct vmbus_chanmsg_hdr hdr; uint32_t chanid; uint32_t gpadl; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_CHFREE */ -struct vmbus_chanmsg_chfree { +__rte_packed_begin struct vmbus_chanmsg_chfree { struct vmbus_chanmsg_hdr hdr; uint32_t chanid; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_CHRESCIND */ -struct vmbus_chanmsg_chrescind { +__rte_packed_begin struct vmbus_chanmsg_chrescind { struct vmbus_chanmsg_hdr hdr; uint32_t chanid; -} __rte_packed; +} __rte_packed_end; /* VMBUS_CHANMSG_TYPE_CHOFFER */ -struct vmbus_chanmsg_choffer { +__rte_packed_begin struct vmbus_chanmsg_choffer { struct vmbus_chanmsg_hdr hdr; rte_uuid_t chtype; rte_uuid_t chinst; @@ -337,7 +337,7 @@ struct vmbus_chanmsg_choffer { uint8_t flags1; /* VMBUS_CHOFFER_FLAG1_ */ uint16_t flags2; uint32_t connid; -} __rte_packed; +} __rte_packed_end; #define VMBUS_CHOFFER_FLAG1_HASMNF 0x01 From patchwork Wed Nov 27 00:52:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148874 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7413845D31; Wed, 27 Nov 2024 01:53:48 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AB8A8427E7; Wed, 27 Nov 2024 01:53:14 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id BFBE5402A7 for ; Wed, 27 Nov 2024 01:53:03 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 7D79B20545BD; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 7D79B20545BD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=aEaZ+q886/XvkaBbDHyTSpXRJc7ZRy8uNG7byavCZkM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ojhx4MWL8XD4yhFJKGY9mxDwWkNNL8b/KPfgYSA5WjcAr8tQysxml07UDVZ53vmJ2 eMyG5p0pKERdKtnEQ9A9eZBkDpZ/tmhttt3F2mECLqNIPwcdDuWYbY0AoG+v1EtNs3 0cAKcfFPyNrs5bbi2QOYj4I+CPolWX5Q/lGnXNm4= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 08/30] drivers/common: replace packed attributes Date: Tue, 26 Nov 2024 16:52:19 -0800 Message-Id: <1732668761-5556-9-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retzlaff --- drivers/common/cnxk/hw/sdp.h | 4 +- drivers/common/cnxk/roc_npc.h | 16 ++-- drivers/common/cnxk/roc_npc_mcam_dump.c | 4 +- drivers/common/cnxk/roc_platform.h | 3 +- drivers/common/dpaax/compat.h | 3 - drivers/common/iavf/iavf_osdep.h | 8 +- drivers/common/iavf/virtchnl_inline_ipsec.h | 44 +++++----- drivers/common/idpf/base/idpf_osdep.h | 8 +- drivers/common/mlx5/mlx5_common_mr.h | 12 ++- drivers/common/mlx5/mlx5_common_utils.h | 3 +- drivers/common/mlx5/mlx5_prm.h | 90 ++++++++++++++------- drivers/common/qat/qat_adf/icp_qat_fw_la.h | 8 +- drivers/common/qat/qat_common.h | 8 +- 13 files changed, 122 insertions(+), 89 deletions(-) diff --git a/drivers/common/cnxk/hw/sdp.h b/drivers/common/cnxk/hw/sdp.h index 686f516097..c5b42c08f6 100644 --- a/drivers/common/cnxk/hw/sdp.h +++ b/drivers/common/cnxk/hw/sdp.h @@ -156,7 +156,7 @@ #define SDP_VF_R_OUT_INT_LEVELS_TIMET (32) /* SDP Instruction Header */ -struct sdp_instr_ih { +__plt_packed_begin struct sdp_instr_ih { /* Data Len */ uint64_t tlen : 16; @@ -177,6 +177,6 @@ struct sdp_instr_ih { /* Reserved2 */ uint64_t rsvd2 : 1; -} __plt_packed; +} __plt_packed_end; #endif /* __SDP_HW_H_ */ diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h index bf8c65aa9c..4f7247f867 100644 --- a/drivers/common/cnxk/roc_npc.h +++ b/drivers/common/cnxk/roc_npc.h @@ -97,10 +97,10 @@ struct roc_npc_flow_item_eth { uint32_t reserved : 31; /**< Reserved, must be zero. */ }; -struct roc_vlan_hdr { +__plt_packed_begin struct roc_vlan_hdr { uint16_t vlan_tci; /**< Priority (3) + CFI (1) + Identifier Code (12) */ uint16_t eth_proto; /**< Ethernet type of encapsulated frame. */ -} __plt_packed; +} __plt_packed_end; struct roc_npc_flow_item_vlan { union { @@ -115,23 +115,23 @@ struct roc_npc_flow_item_vlan { uint32_t reserved : 31; /**< Reserved, must be zero. */ }; -struct roc_ipv6_hdr { +__plt_packed_begin struct roc_ipv6_hdr { uint32_t vtc_flow; /**< IP version, traffic class & flow label. */ uint16_t payload_len; /**< IP payload size, including ext. headers */ uint8_t proto; /**< Protocol, next header. */ uint8_t hop_limits; /**< Hop limits. */ uint8_t src_addr[16]; /**< IP address of source host. */ uint8_t dst_addr[16]; /**< IP address of destination host(s). */ -} __plt_packed; +} __plt_packed_end; -struct roc_ipv6_fragment_ext { +__plt_packed_begin struct roc_ipv6_fragment_ext { uint8_t next_header; /**< Next header type */ uint8_t reserved; /**< Reserved */ uint16_t frag_data; /**< All fragmentation data */ uint32_t id; /**< Packet ID */ -} __plt_packed; +} __plt_packed_end; -struct roc_ipv6_routing_ext { +__plt_packed_begin struct roc_ipv6_routing_ext { uint8_t next_hdr; /**< Protocol, next header. */ uint8_t hdr_len; /**< Header length. */ uint8_t type; /**< Extension header type. */ @@ -145,7 +145,7 @@ struct roc_ipv6_routing_ext { }; }; /* Next are 128-bit IPv6 address fields to describe segments. */ -} __plt_packed; +} __plt_packed_end; struct roc_flow_item_ipv6_ext { uint8_t next_hdr; /**< Next header. */ diff --git a/drivers/common/cnxk/roc_npc_mcam_dump.c b/drivers/common/cnxk/roc_npc_mcam_dump.c index ebd2dd69c2..ca566d2b44 100644 --- a/drivers/common/cnxk/roc_npc_mcam_dump.c +++ b/drivers/common/cnxk/roc_npc_mcam_dump.c @@ -35,7 +35,7 @@ #define NIX_TX_VTAGACT_VTAG1_OP_MASK GENMASK(45, 44) #define NIX_TX_VTAGACT_VTAG1_DEF_MASK GENMASK(57, 48) -struct npc_rx_parse_nibble_s { +__plt_packed_begin struct npc_rx_parse_nibble_s { uint16_t chan : 3; uint16_t errlev : 1; uint16_t errcode : 2; @@ -56,7 +56,7 @@ struct npc_rx_parse_nibble_s { uint16_t lgtype : 1; uint16_t lhflags : 2; uint16_t lhtype : 1; -} __plt_packed; +} __plt_packed_end; static const char *const intf_str[] = { "NIX-RX", diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index df4f88f288..d6f3ea9acc 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -97,7 +97,8 @@ #define __plt_cache_aligned __rte_cache_aligned #define __plt_always_inline __rte_always_inline -#define __plt_packed __rte_packed +#define __plt_packed_begin __rte_packed_begin +#define __plt_packed_end __rte_packed_end #define __plt_unused __rte_unused #define __roc_api __rte_internal #define plt_iova_t rte_iova_t diff --git a/drivers/common/dpaax/compat.h b/drivers/common/dpaax/compat.h index 7c8d82c2b2..28bffde2a7 100644 --- a/drivers/common/dpaax/compat.h +++ b/drivers/common/dpaax/compat.h @@ -53,9 +53,6 @@ #ifndef __always_unused #define __always_unused __rte_unused #endif -#ifndef __packed -#define __packed __rte_packed -#endif #ifndef noinline #define noinline __rte_noinline #endif diff --git a/drivers/common/iavf/iavf_osdep.h b/drivers/common/iavf/iavf_osdep.h index 1f2b7889cb..91f77948bb 100644 --- a/drivers/common/iavf/iavf_osdep.h +++ b/drivers/common/iavf/iavf_osdep.h @@ -158,17 +158,17 @@ do { \ } while (0) /* memory allocation tracking */ -struct iavf_dma_mem { +__rte_packed_begin struct iavf_dma_mem { void *va; u64 pa; u32 size; const void *zone; -} __rte_packed; +} __rte_packed_end; -struct iavf_virt_mem { +__rte_packed_begin struct iavf_virt_mem { void *va; u32 size; -} __rte_packed; +} __rte_packed_end; #define iavf_allocate_dma_mem(h, m, unused, s, a) \ iavf_allocate_dma_mem_d(h, m, s, a) diff --git a/drivers/common/iavf/virtchnl_inline_ipsec.h b/drivers/common/iavf/virtchnl_inline_ipsec.h index 2f4bf15725..61e1d648ea 100644 --- a/drivers/common/iavf/virtchnl_inline_ipsec.h +++ b/drivers/common/iavf/virtchnl_inline_ipsec.h @@ -109,7 +109,7 @@ enum inline_ipsec_ops { }; /* Not all valid, if certain field is invalid, set 1 for all bits */ -struct virtchnl_algo_cap { +__rte_packed_begin struct virtchnl_algo_cap { u32 algo_type; u16 block_size; @@ -129,20 +129,20 @@ struct virtchnl_algo_cap { u16 min_aad_size; u16 max_aad_size; u16 inc_aad_size; -} __rte_packed; +} __rte_packed_end; /* vf record the capability of crypto from the virtchnl */ -struct virtchnl_sym_crypto_cap { +__rte_packed_begin struct virtchnl_sym_crypto_cap { u8 crypto_type; u8 algo_cap_num; struct virtchnl_algo_cap algo_cap_list[VIRTCHNL_IPSEC_MAX_ALGO_CAP_NUM]; -} __rte_packed; +} __rte_packed_end; /* VIRTCHNL_OP_GET_IPSEC_CAP * VF pass virtchnl_ipsec_cap to PF * and PF return capability of ipsec from virtchnl. */ -struct virtchnl_ipsec_cap { +__rte_packed_begin struct virtchnl_ipsec_cap { /* max number of SA per VF */ u16 max_sa_num; @@ -169,10 +169,10 @@ struct virtchnl_ipsec_cap { /* crypto capabilities */ struct virtchnl_sym_crypto_cap cap[VIRTCHNL_IPSEC_MAX_CRYPTO_CAP_NUM]; -} __rte_packed; +} __rte_packed_end; /* configuration of crypto function */ -struct virtchnl_ipsec_crypto_cfg_item { +__rte_packed_begin struct virtchnl_ipsec_crypto_cfg_item { u8 crypto_type; u32 algo_type; @@ -191,7 +191,7 @@ struct virtchnl_ipsec_crypto_cfg_item { /* key data buffer */ u8 key_data[VIRTCHNL_IPSEC_MAX_KEY_LEN]; -} __rte_packed; +} __rte_packed_end; struct virtchnl_ipsec_sym_crypto_cfg { struct virtchnl_ipsec_crypto_cfg_item @@ -203,7 +203,7 @@ struct virtchnl_ipsec_sym_crypto_cfg { * PF create SA as configuration and PF driver will return * an unique index (sa_idx) for the created SA. */ -struct virtchnl_ipsec_sa_cfg { +__rte_packed_begin struct virtchnl_ipsec_sa_cfg { /* IPsec SA Protocol - AH/ESP */ u8 virtchnl_protocol_type; @@ -292,17 +292,17 @@ struct virtchnl_ipsec_sa_cfg { /* crypto configuration */ struct virtchnl_ipsec_sym_crypto_cfg crypto_cfg; -} __rte_packed; +} __rte_packed_end; /* VIRTCHNL_OP_IPSEC_SA_UPDATE * VF send configuration of index of SA to PF * PF will update SA according to configuration */ -struct virtchnl_ipsec_sa_update { +__rte_packed_begin struct virtchnl_ipsec_sa_update { u32 sa_index; /* SA to update */ u32 esn_hi; /* high 32 bits of esn */ u32 esn_low; /* low 32 bits of esn */ -} __rte_packed; +} __rte_packed_end; /* VIRTCHNL_OP_IPSEC_SA_DESTROY * VF send configuration of index of SA to PF @@ -310,7 +310,7 @@ struct virtchnl_ipsec_sa_update { * flag bitmap indicate all SA or just selected SA will * be destroyed */ -struct virtchnl_ipsec_sa_destroy { +__rte_packed_begin struct virtchnl_ipsec_sa_destroy { /* All zero bitmap indicates all SA will be destroyed. * Non-zero bitmap indicates the selected SA in * array sa_index will be destroyed. @@ -319,13 +319,13 @@ struct virtchnl_ipsec_sa_destroy { /* selected SA index */ u32 sa_index[VIRTCHNL_IPSEC_MAX_SA_DESTROY_NUM]; -} __rte_packed; +} __rte_packed_end; /* VIRTCHNL_OP_IPSEC_SA_READ * VF send this SA configuration to PF using virtchnl; * PF read SA and will return configuration for the created SA. */ -struct virtchnl_ipsec_sa_read { +__rte_packed_begin struct virtchnl_ipsec_sa_read { /* SA valid - invalid/valid */ u8 valid; @@ -424,14 +424,14 @@ struct virtchnl_ipsec_sa_read { /* crypto configuration. Salt and keys are set to 0 */ struct virtchnl_ipsec_sym_crypto_cfg crypto_cfg; -} __rte_packed; +} __rte_packed_end; #define VIRTCHNL_IPSEC_INBOUND_SPD_TBL_IPV4 (0) #define VIRTCHNL_IPSEC_INBOUND_SPD_TBL_IPV6 (1) /* Add allowlist entry in IES */ -struct virtchnl_ipsec_sp_cfg { +__rte_packed_begin struct virtchnl_ipsec_sp_cfg { u32 spi; u32 dip[4]; @@ -455,15 +455,15 @@ struct virtchnl_ipsec_sp_cfg { /* NAT-T UDP port number. Only valid in case NAT-T supported */ u16 udp_port; -} __rte_packed; +} __rte_packed_end; /* Delete allowlist entry in IES */ -struct virtchnl_ipsec_sp_destroy { +__rte_packed_begin struct virtchnl_ipsec_sp_destroy { /* 0 for IPv4 table, 1 for IPv6 table. */ u8 table_id; u32 rule_id; -} __rte_packed; +} __rte_packed_end; /* Response from IES to allowlist operations */ struct virtchnl_ipsec_sp_cfg_resp { @@ -494,7 +494,7 @@ struct virtchnl_ipsec_resp { }; /* Internal message descriptor for VF <-> IPsec communication */ -struct inline_ipsec_msg { +__rte_packed_begin struct inline_ipsec_msg { u16 ipsec_opcode; u16 req_id; @@ -520,7 +520,7 @@ struct inline_ipsec_msg { /* Reserved */ struct virtchnl_ipsec_sa_read sa_read[0]; } ipsec_data; -} __rte_packed; +} __rte_packed_end; static inline u16 virtchnl_inline_ipsec_val_msg_len(u16 opcode) { diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h index cf9e553906..a3a232ac7f 100644 --- a/drivers/common/idpf/base/idpf_osdep.h +++ b/drivers/common/idpf/base/idpf_osdep.h @@ -180,17 +180,17 @@ static inline uint64_t idpf_read_addr64(volatile void *addr) #define BITS_PER_BYTE 8 /* memory allocation tracking */ -struct idpf_dma_mem { +__rte_packed_begin struct idpf_dma_mem { void *va; u64 pa; u32 size; const void *zone; -} __rte_packed; +} __rte_packed_end; -struct idpf_virt_mem { +__rte_packed_begin struct idpf_virt_mem { void *va; u32 size; -} __rte_packed; +} __rte_packed_end; #define idpf_malloc(h, s) rte_zmalloc(NULL, s, 0) #define idpf_calloc(h, c, s) rte_zmalloc(NULL, (c) * (s), 0) diff --git a/drivers/common/mlx5/mlx5_common_mr.h b/drivers/common/mlx5/mlx5_common_mr.h index a7f1042037..299d38b78b 100644 --- a/drivers/common/mlx5/mlx5_common_mr.h +++ b/drivers/common/mlx5/mlx5_common_mr.h @@ -49,22 +49,25 @@ struct mlx5_mr { }; /* Cache entry for Memory Region. */ +__rte_packed_begin struct mr_cache_entry { uintptr_t start; /* Start address of MR. */ uintptr_t end; /* End address of MR. */ uint32_t lkey; /* rte_cpu_to_be_32(lkey). */ -} __rte_packed; +} __rte_packed_end; /* MR Cache table for Binary search. */ +__rte_packed_begin struct mlx5_mr_btree { uint32_t len; /* Number of entries. */ uint32_t size; /* Total number of entries. */ struct mr_cache_entry (*table)[]; -} __rte_packed; +} __rte_packed_end; struct mlx5_common_device; /* Per-queue MR control descriptor. */ +__rte_packed_begin struct mlx5_mr_ctrl { uint32_t *dev_gen_ptr; /* Generation number of device to poll. */ uint32_t cur_gen; /* Generation number saved to flush caches. */ @@ -72,12 +75,13 @@ struct mlx5_mr_ctrl { uint16_t head; /* Index of the oldest entry in top-half cache. */ struct mr_cache_entry cache[MLX5_MR_CACHE_N]; /* Cache for top-half. */ struct mlx5_mr_btree cache_bh; /* Cache for bottom-half. */ -} __rte_packed; +} __rte_packed_end; LIST_HEAD(mlx5_mr_list, mlx5_mr); LIST_HEAD(mlx5_mempool_reg_list, mlx5_mempool_reg); /* Global per-device MR cache. */ +__rte_packed_begin struct mlx5_mr_share_cache { uint32_t dev_gen; /* Generation number to flush local caches. */ rte_rwlock_t rwlock; /* MR cache Lock. */ @@ -88,7 +92,7 @@ struct mlx5_mr_share_cache { struct mlx5_mempool_reg_list mempool_reg_list; /* Mempool database. */ mlx5_reg_mr_t reg_mr_cb; /* Callback to reg_mr func */ mlx5_dereg_mr_t dereg_mr_cb; /* Callback to dereg_mr func */ -} __rte_packed; +} __rte_packed_end; /* Multi-Packet RQ buffer header. */ struct __rte_cache_aligned mlx5_mprq_buf { diff --git a/drivers/common/mlx5/mlx5_common_utils.h b/drivers/common/mlx5/mlx5_common_utils.h index 9139bc6829..70d9c6d69e 100644 --- a/drivers/common/mlx5/mlx5_common_utils.h +++ b/drivers/common/mlx5/mlx5_common_utils.h @@ -27,6 +27,7 @@ struct mlx5_list; * Structure of the entry in the mlx5 list, user should define its own struct * that contains this in order to store the data. */ +__rte_packed_begin struct mlx5_list_entry { LIST_ENTRY(mlx5_list_entry) next; /* Entry pointers in the list. */ alignas(8) RTE_ATOMIC(uint32_t) ref_cnt; /* 0 means, entry is invalid. */ @@ -35,7 +36,7 @@ struct mlx5_list_entry { struct mlx5_list_entry *gentry; uint32_t bucket_idx; }; -} __rte_packed; +} __rte_packed_end; struct __rte_cache_aligned mlx5_list_cache { LIST_HEAD(mlx5_list_head, mlx5_list_entry) h; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 2d82807bc2..82005a8567 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -323,12 +323,13 @@ enum mlx5_mpw_mode { }; /* WQE Control segment. */ +__rte_packed_begin struct __rte_aligned(MLX5_WSEG_SIZE) mlx5_wqe_cseg { uint32_t opcode; uint32_t sq_ds; uint32_t flags; uint32_t misc; -} __rte_packed; +} __rte_packed_end; /* * WQE CSEG opcode field size is 32 bits, divided: @@ -340,20 +341,24 @@ struct __rte_aligned(MLX5_WSEG_SIZE) mlx5_wqe_cseg { #define WQE_CSEG_WQE_INDEX_OFFSET 8 /* Header of data segment. Minimal size Data Segment */ +__rte_packed_begin struct mlx5_wqe_dseg { uint32_t bcount; union { uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE]; + __rte_packed_begin struct { uint32_t lkey; uint64_t pbuf; - } __rte_packed; + } __rte_packed_end; }; -} __rte_packed; +} __rte_packed_end; /* Subset of struct WQE Ethernet Segment. */ +__rte_packed_begin struct mlx5_wqe_eseg { union { + __rte_packed_begin struct { uint32_t swp_offs; uint8_t cs_flags; @@ -365,23 +370,26 @@ struct mlx5_wqe_eseg { uint16_t inline_data; uint16_t vlan_tag; }; - } __rte_packed; + } __rte_packed_end; + __rte_packed_begin struct { uint32_t offsets; uint32_t flags; uint32_t flow_metadata; uint32_t inline_hdr; - } __rte_packed; + } __rte_packed_end; }; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct mlx5_wqe_qseg { uint32_t reserved0; uint32_t reserved1; uint32_t max_index; uint32_t qpn_cqn; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct mlx5_wqe_wseg { uint32_t operation; uint32_t lkey; @@ -389,9 +397,10 @@ struct mlx5_wqe_wseg { uint32_t va_low; uint64_t value; uint64_t mask; -} __rte_packed; +} __rte_packed_end; /* The title WQEBB, header of WQE. */ +__rte_packed_begin struct mlx5_wqe { union { struct mlx5_wqe_cseg cseg; @@ -402,7 +411,7 @@ struct mlx5_wqe { struct mlx5_wqe_dseg dseg[2]; uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE]; }; -} __rte_packed; +} __rte_packed_end; /* WQE for Multi-Packet RQ. */ struct mlx5_wqe_mprq { @@ -464,10 +473,11 @@ struct mlx5_cqe { uint8_t lro_num_seg; union { uint8_t user_index_bytes[3]; + __rte_packed_begin struct { uint8_t user_index_hi; uint16_t user_index_low; - } __rte_packed; + } __rte_packed_end; }; uint32_t flow_table_metadata; uint8_t rsvd4[4]; @@ -487,11 +497,12 @@ struct mlx5_cqe_ts { uint8_t op_own; }; +__rte_packed_begin struct mlx5_wqe_rseg { uint64_t raddr; uint32_t rkey; uint32_t reserved; -} __rte_packed; +} __rte_packed_end; #define MLX5_UMRC_IF_OFFSET 31u #define MLX5_UMRC_KO_OFFSET 16u @@ -506,13 +517,15 @@ struct mlx5_wqe_rseg { #define MLX5_UMR_KLM_NUM_ALIGN \ (MLX5_UMR_KLM_PTR_ALIGN / sizeof(struct mlx5_klm)) +__rte_packed_begin struct mlx5_wqe_umr_cseg { uint32_t if_cf_toe_cq_res; uint32_t ko_to_bs; uint64_t mkey_mask; uint32_t rsvd1[8]; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct mlx5_wqe_mkey_cseg { uint32_t fr_res_af_sf; uint32_t qpn_mkey; @@ -525,7 +538,7 @@ struct mlx5_wqe_mkey_cseg { uint32_t translations_octword_size; uint32_t res4_lps; uint32_t reserved; -} __rte_packed; +} __rte_packed_end; enum { MLX5_BSF_SIZE_16B = 0x0, @@ -576,6 +589,7 @@ enum { #define MLX5_CRYPTO_MMO_TYPE_OFFSET 24 #define MLX5_CRYPTO_MMO_OP_OFFSET 20 +__rte_packed_begin struct mlx5_wqe_umr_bsf_seg { /* * bs_bpt_eo_es contains: @@ -603,12 +617,13 @@ struct mlx5_wqe_umr_bsf_seg { uint32_t reserved1; uint64_t keytag; uint32_t reserved2[4]; -} __rte_packed; +} __rte_packed_end; #ifdef PEDANTIC #pragma GCC diagnostic ignored "-Wpedantic" #endif +__rte_packed_begin struct mlx5_umr_wqe { struct mlx5_wqe_cseg ctr; struct mlx5_wqe_umr_cseg ucseg; @@ -617,24 +632,27 @@ struct mlx5_umr_wqe { struct mlx5_wqe_dseg kseg[0]; struct mlx5_wqe_umr_bsf_seg bsf[0]; }; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct mlx5_rdma_write_wqe { struct mlx5_wqe_cseg ctr; struct mlx5_wqe_rseg rseg; struct mlx5_wqe_dseg dseg[]; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct mlx5_wqe_send_en_seg { uint32_t reserve[2]; uint32_t sqnpc; uint32_t qpn; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct mlx5_wqe_send_en_wqe { struct mlx5_wqe_cseg ctr; struct mlx5_wqe_send_en_seg sseg; -} __rte_packed; +} __rte_packed_end; #ifdef PEDANTIC #pragma GCC diagnostic error "-Wpedantic" @@ -677,6 +695,7 @@ struct mlx5_wqe_metadata_seg { uint64_t addr; }; +__rte_packed_begin struct mlx5_gga_wqe { uint32_t opcode; uint32_t sq_ds; @@ -687,40 +706,45 @@ struct mlx5_gga_wqe { uint64_t opaque_vaddr; struct mlx5_wqe_dseg gather; struct mlx5_wqe_dseg scatter; -} __rte_packed; +} __rte_packed_end; union mlx5_gga_compress_opaque { + __rte_packed_begin struct { uint32_t syndrome; uint32_t reserved0; uint32_t scattered_length; union { + __rte_packed_begin struct { uint32_t reserved1[5]; uint32_t crc32; uint32_t adler32; - } v1 __rte_packed; + } v1 __rte_packed_end; + __rte_packed_begin struct { uint32_t crc32; uint32_t adler32; uint32_t crc32c; uint32_t xxh32; - } v2 __rte_packed; + } v2 __rte_packed_end; }; - } __rte_packed; + } __rte_packed_end; uint32_t data[64]; }; union mlx5_gga_crypto_opaque { + __rte_packed_begin struct { uint32_t syndrome; uint32_t reserved0[2]; + __rte_packed_begin struct { uint32_t iv[3]; uint32_t tag_size; uint32_t aad_size; - } cp __rte_packed; - } __rte_packed; + } cp __rte_packed_end; + } __rte_packed_end; uint8_t data[64]; }; @@ -931,6 +955,7 @@ mlx5_regc_value(uint8_t regc_ix) /* Modification sub command. */ struct mlx5_modification_cmd { + __rte_packed_begin union { uint32_t data0; struct { @@ -941,7 +966,8 @@ struct mlx5_modification_cmd { unsigned int field:12; unsigned int action_type:4; }; - } __rte_packed; + } __rte_packed_end; + __rte_packed_begin union { uint32_t data1; uint8_t data[4]; @@ -952,7 +978,7 @@ struct mlx5_modification_cmd { unsigned int dst_field:12; unsigned int rsvd4:4; }; - } __rte_packed; + } __rte_packed_end; }; typedef uint64_t u64; @@ -4191,6 +4217,7 @@ enum mlx5_aso_op { #define MLX5_ASO_CSEG_READ_ENABLE 1 /* ASO WQE CTRL segment. */ +__rte_packed_begin struct mlx5_aso_cseg { uint32_t va_h; uint32_t va_l_r; @@ -4202,11 +4229,12 @@ struct mlx5_aso_cseg { uint32_t condition_1_mask; uint64_t bitwise_data; uint64_t data_mask; -} __rte_packed; +} __rte_packed_end; #define MLX5_MTR_MAX_TOKEN_VALUE INT32_MAX /* A meter data segment - 2 per ASO WQE. */ +__rte_packed_begin struct mlx5_aso_mtr_dseg { uint32_t v_bo_sc_bbog_mm; /* @@ -4227,7 +4255,7 @@ struct mlx5_aso_mtr_dseg { */ uint32_t e_tokens; uint64_t timestamp; -} __rte_packed; +} __rte_packed_end; #define ASO_DSEG_VALID_OFFSET 31 #define ASO_DSEG_BO_OFFSET 30 @@ -4248,19 +4276,21 @@ struct mlx5_aso_mtr_dseg { #define MLX5_ASO_MTRS_PER_POOL 128 /* ASO WQE data segment. */ +__rte_packed_begin struct mlx5_aso_dseg { union { uint8_t data[MLX5_ASO_WQE_DSEG_SIZE]; struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE]; }; -} __rte_packed; +} __rte_packed_end; /* ASO WQE. */ +__rte_packed_begin struct mlx5_aso_wqe { struct mlx5_wqe_cseg general_cseg; struct mlx5_aso_cseg aso_cseg; struct mlx5_aso_dseg aso_dseg; -} __rte_packed; +} __rte_packed_end; enum { MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h index fe32b66c50..30a93549cf 100644 --- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h +++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h @@ -357,7 +357,7 @@ struct icp_qat_fw_cipher_auth_cd_ctrl_hdr { #define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET 24 #define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0) -struct icp_qat_fw_la_cipher_req_params { +__rte_packed_begin struct icp_qat_fw_la_cipher_req_params { uint32_t cipher_offset; uint32_t cipher_length; union { @@ -372,9 +372,9 @@ struct icp_qat_fw_la_cipher_req_params { uint16_t spc_aad_sz; uint8_t reserved; uint8_t spc_auth_res_sz; -} __rte_packed; +} __rte_packed_end; -struct icp_qat_fw_la_auth_req_params { +__rte_packed_begin struct icp_qat_fw_la_auth_req_params { uint32_t auth_off; uint32_t auth_len; union { @@ -389,7 +389,7 @@ struct icp_qat_fw_la_auth_req_params { uint8_t resrvd1; uint8_t hash_state_sz; uint8_t auth_res_sz; -} __rte_packed; +} __rte_packed_end; struct icp_qat_fw_la_auth_req_params_resrvd_flds { uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_6]; diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h index 703534dc15..272a799640 100644 --- a/drivers/common/qat/qat_common.h +++ b/drivers/common/qat/qat_common.h @@ -57,11 +57,11 @@ enum qat_svc_list { }; /**< Common struct for scatter-gather list operations */ -struct qat_flat_buf { +__rte_packed_begin struct qat_flat_buf { uint32_t len; uint32_t resrvd; uint64_t addr; -} __rte_packed; +} __rte_packed_end; #define qat_sgl_hdr struct { \ uint64_t resrvd; \ @@ -70,11 +70,11 @@ struct qat_flat_buf { } __extension__ -struct __rte_cache_aligned qat_sgl { +__rte_packed_begin struct __rte_cache_aligned qat_sgl { qat_sgl_hdr; /* flexible array of flat buffers*/ struct qat_flat_buf buffers[0]; -} __rte_packed; +} __rte_packed_end; /** Common, i.e. not service-specific, statistics */ struct qat_common_stats { From patchwork Wed Nov 27 00:52:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148872 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 99EE745D31; Wed, 27 Nov 2024 01:53:35 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4AAF0427DC; Wed, 27 Nov 2024 01:53:12 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id D64F2427BF for ; Wed, 27 Nov 2024 01:53:03 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 8C10D20545BE; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 8C10D20545BE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=2wIePYS2gR7xjvFv3m5ZGU0/UBiN72x34EtlWi9/94E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sqE/oUXlF+UU8Wsh5pbfgJvzd11o9dPwC8dMciaHyb6jmxhTAx0FEweJGo96MHzLE oVZTwb+yjJSaS4L6gDghZ1E8pM6o8qN9BcbFBzdVo0/qFh5JguNey3QE/TB9nUcvWN TOIY8vWe9r+xgAUnhEVN2LFkPX+61m7fhsAQzD8A= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 09/30] drivers/compress: replace packed attributes Date: Tue, 26 Nov 2024 16:52:20 -0800 Message-Id: <1732668761-5556-10-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retzlaff --- drivers/compress/qat/qat_comp.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h index 1da4770b1c..90231ad42a 100644 --- a/drivers/compress/qat/qat_comp.h +++ b/drivers/compress/qat/qat_comp.h @@ -50,10 +50,10 @@ struct array_of_ptrs { phys_addr_t pointer[0]; }; -struct __rte_cache_aligned qat_inter_sgl { +__rte_packed_begin struct __rte_cache_aligned qat_inter_sgl { qat_sgl_hdr; struct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL]; -} __rte_packed; +} __rte_packed_end; struct qat_comp_op_cookie { From patchwork Wed Nov 27 00:52:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148879 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6AB5F45D31; Wed, 27 Nov 2024 01:54:23 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C933442D78; Wed, 27 Nov 2024 01:53:20 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id F0A1C427C5 for ; Wed, 27 Nov 2024 01:53:03 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 99C8220545BF; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 99C8220545BF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=WToM5KbLxhK0AjyBdzwc3M+Jd5uw+SqIIxIfdC7ZZGA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QlPQPnDkA6HLDT033hGJho6dr+ML02XYya5urDy8ykBh/dfeKDyhUZScik9Dspz/g 7LtmLgHCYCsHHXvThBK8jSn/VJYdZWcQACYGaiRWJ+lfTR+dA80T3ftdPA8B2+QLqr ciqJ+uPfczWEyIdevzmqqZQVMSP5tcsJVanrpMkk= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 10/30] drivers/crypto: replace packed attributes Date: Tue, 26 Nov 2024 16:52:21 -0800 Message-Id: <1732668761-5556-11-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retzlaff --- drivers/crypto/caam_jr/caam_jr.c | 4 +- drivers/crypto/caam_jr/caam_jr_desc.h | 64 ++++++++++---------- drivers/crypto/caam_jr/caam_jr_hw_specific.h | 48 +++++++-------- drivers/crypto/dpaa_sec/dpaa_sec.h | 12 ++-- drivers/crypto/ionic/ionic_crypto_if.h | 36 +++++------ drivers/crypto/mlx5/mlx5_crypto.h | 6 +- drivers/crypto/mlx5/mlx5_crypto_gcm.c | 3 +- drivers/crypto/qat/qat_sym.h | 7 ++- drivers/crypto/qat/qat_sym_session.h | 4 +- 9 files changed, 94 insertions(+), 90 deletions(-) diff --git a/drivers/crypto/caam_jr/caam_jr.c b/drivers/crypto/caam_jr/caam_jr.c index 4082b3f422..fedeefdf80 100644 --- a/drivers/crypto/caam_jr/caam_jr.c +++ b/drivers/crypto/caam_jr/caam_jr.c @@ -53,10 +53,10 @@ static enum sec_driver_state_e g_driver_state = SEC_DRIVER_STATE_IDLE; static int g_job_rings_no; static int g_job_rings_max; -struct sec_outring_entry { +__rte_packed_begin struct sec_outring_entry { phys_addr_t desc; /* Pointer to completed descriptor */ uint32_t status; /* Status for completed descriptor */ -} __rte_packed; +} __rte_packed_end; /* virtual address conversin when mempool support is available for ctx */ static inline phys_addr_t diff --git a/drivers/crypto/caam_jr/caam_jr_desc.h b/drivers/crypto/caam_jr/caam_jr_desc.h index a4507613be..76cc07a94b 100644 --- a/drivers/crypto/caam_jr/caam_jr_desc.h +++ b/drivers/crypto/caam_jr/caam_jr_desc.h @@ -123,8 +123,8 @@ } /* Union describing a descriptor header. */ -struct descriptor_header_s { - union { +__rte_packed_begin struct descriptor_header_s { + __rte_packed_begin union { uint32_t word; struct { /* 4 */ unsigned int ctype:5; @@ -162,15 +162,15 @@ struct descriptor_header_s { /* 26 */ unsigned int res1:1; /* 27 */ unsigned int ctype:5; } jd; - } __rte_packed command; -} __rte_packed; + } __rte_packed_end command; +} __rte_packed_end; /* Union describing a KEY command in a descriptor. */ -struct key_command_s { - union { +__rte_packed_begin struct key_command_s { + __rte_packed_begin union { uint32_t word; - struct { + __rte_packed_begin struct { unsigned int ctype:5; unsigned int cls:2; unsigned int sgf:1; @@ -182,30 +182,30 @@ struct key_command_s { unsigned int tk:1; unsigned int rsvd1:5; unsigned int length:10; - } __rte_packed field; - } __rte_packed command; -} __rte_packed; + } __rte_packed_end field; + } __rte_packed_end command; +} __rte_packed_end; /* Union describing a PROTOCOL command * in a descriptor. */ -struct protocol_operation_command_s { - union { +__rte_packed_begin struct protocol_operation_command_s { + __rte_packed_begin union { uint32_t word; - struct { + __rte_packed_begin struct { unsigned int ctype:5; unsigned int optype:3; unsigned char protid; unsigned short protinfo; - } __rte_packed field; - } __rte_packed command; -} __rte_packed; + } __rte_packed_end field; + } __rte_packed_end command; +} __rte_packed_end; /* Union describing a SEQIN command in a * descriptor. */ -struct seq_in_command_s { - union { +__rte_packed_begin struct seq_in_command_s { + __rte_packed_begin union { uint32_t word; struct { unsigned int ctype:5; @@ -219,14 +219,14 @@ struct seq_in_command_s { unsigned int res2:4; unsigned int length:16; } field; - } __rte_packed command; -} __rte_packed; + } __rte_packed_end command; +} __rte_packed_end; /* Union describing a SEQOUT command in a * descriptor. */ -struct seq_out_command_s { - union { +__rte_packed_begin struct seq_out_command_s { + __rte_packed_begin union { uint32_t word; struct { unsigned int ctype:5; @@ -238,11 +238,11 @@ struct seq_out_command_s { unsigned int res2:5; unsigned int length:16; } field; - } __rte_packed command; -} __rte_packed; + } __rte_packed_end command; +} __rte_packed_end; -struct load_command_s { - union { +__rte_packed_begin struct load_command_s { + __rte_packed_begin union { uint32_t word; struct { unsigned int ctype:5; @@ -253,23 +253,23 @@ struct load_command_s { unsigned char offset; unsigned char length; } fields; - } __rte_packed command; -} __rte_packed; + } __rte_packed_end command; +} __rte_packed_end; /* Structure encompassing a general shared descriptor of maximum * size (64 WORDs). Usually, other specific shared descriptor structures * will be type-casted to this one * this one. */ -struct __rte_aligned(64) sec_sd_t { +__rte_packed_begin struct __rte_aligned(64) sec_sd_t { uint32_t rsvd[MAX_DESC_SIZE_WORDS]; -} __rte_packed; +} __rte_packed_end; /* Structure encompassing a job descriptor which processes * a single packet from a context. The job descriptor references * a shared descriptor from a SEC context. */ -struct __rte_aligned(64) sec_job_descriptor_t { +__rte_packed_begin struct __rte_aligned(64) sec_job_descriptor_t { struct descriptor_header_s deschdr; dma_addr_t sd_ptr; struct seq_out_command_s seq_out; @@ -280,6 +280,6 @@ struct __rte_aligned(64) sec_job_descriptor_t { uint32_t in_ext_length; struct load_command_s load_dpovrd; uint32_t dpovrd; -} __rte_packed; +} __rte_packed_end; #endif diff --git a/drivers/crypto/caam_jr/caam_jr_hw_specific.h b/drivers/crypto/caam_jr/caam_jr_hw_specific.h index 6ee7f7cef3..d3c102bdf0 100644 --- a/drivers/crypto/caam_jr/caam_jr_hw_specific.h +++ b/drivers/crypto/caam_jr/caam_jr_hw_specific.h @@ -275,8 +275,8 @@ typedef enum sec_job_ring_state_e { /* code or cmd block to caam */ struct sec_cdb { - struct { - union { + __rte_packed_begin struct { + __rte_packed_begin union { uint32_t word; struct { #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN @@ -289,9 +289,9 @@ struct sec_cdb { uint16_t rsvd63_48; #endif } field; - } __rte_packed hi; + } __rte_packed_end hi; - union { + __rte_packed_begin union { uint32_t word; struct { #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN @@ -314,8 +314,8 @@ struct sec_cdb { unsigned int rsvd31_30:2; #endif } field; - } __rte_packed lo; - } __rte_packed sh_hdr; + } __rte_packed_end lo; + } __rte_packed_end sh_hdr; uint32_t sh_desc[SEC_JOB_DESCRIPTOR_SIZE]; }; @@ -390,54 +390,54 @@ struct sec_job_ring_t { /* Union describing the possible error codes that * can be set in the descriptor status word */ -union hw_error_code { +__rte_packed_begin union hw_error_code { uint32_t error; - union { - struct { + __rte_packed_begin union { + __rte_packed_begin struct { uint32_t ssrc:4; uint32_t ssed_val:28; - } __rte_packed value; - struct { + } __rte_packed_end value; + __rte_packed_begin struct { uint32_t ssrc:4; uint32_t res:28; - } __rte_packed no_status_src; - struct { + } __rte_packed_end no_status_src; + __rte_packed_begin struct { uint32_t ssrc:4; uint32_t jmp:1; uint32_t res:11; uint32_t desc_idx:8; uint32_t cha_id:4; uint32_t err_id:4; - } __rte_packed ccb_status_src; - struct { + } __rte_packed_end ccb_status_src; + __rte_packed_begin struct { uint32_t ssrc:4; uint32_t jmp:1; uint32_t res:11; uint32_t desc_idx:8; uint32_t offset:8; - } __rte_packed jmp_halt_user_src; - struct { + } __rte_packed_end jmp_halt_user_src; + __rte_packed_begin struct { uint32_t ssrc:4; uint32_t jmp:1; uint32_t res:11; uint32_t desc_idx:8; uint32_t desc_err:8; - } __rte_packed deco_src; - struct { + } __rte_packed_end deco_src; + __rte_packed_begin struct { uint32_t ssrc:4; uint32_t res:17; uint32_t naddr:3; uint32_t desc_err:8; - } __rte_packed jr_src; - struct { + } __rte_packed_end jr_src; + __rte_packed_begin struct { uint32_t ssrc:4; uint32_t jmp:1; uint32_t res:11; uint32_t desc_idx:8; uint32_t cond:8; - } __rte_packed jmp_halt_cond_src; - } __rte_packed error_desc; -} __rte_packed; + } __rte_packed_end jmp_halt_cond_src; + } __rte_packed_end error_desc; +} __rte_packed_end; /* @brief Initialize a job ring/channel in SEC device. * Write configuration register/s to properly initialize a job ring. diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.h b/drivers/crypto/dpaa_sec/dpaa_sec.h index 64d9e22159..f8b0147845 100644 --- a/drivers/crypto/dpaa_sec/dpaa_sec.h +++ b/drivers/crypto/dpaa_sec/dpaa_sec.h @@ -62,8 +62,8 @@ enum dpaa_sec_op_type { #define DPAA_SEC_MAX_DESC_SIZE 64 /* code or cmd block to caam */ struct sec_cdb { - struct { - union { + __rte_packed_begin struct { + __rte_packed_begin union { uint32_t word; struct { #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN @@ -76,9 +76,9 @@ struct sec_cdb { uint16_t rsvd63_48; #endif } field; - } __packed hi; + } __rte_packed_end hi; - union { + __rte_packed_begin union { uint32_t word; struct { #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN @@ -101,8 +101,8 @@ struct sec_cdb { unsigned int rsvd31_30:2; #endif } field; - } __packed lo; - } __packed sh_hdr; + } __rte_packed_end lo; + } __rte_packed_end sh_hdr; uint32_t sh_desc[DPAA_SEC_MAX_DESC_SIZE]; }; diff --git a/drivers/crypto/ionic/ionic_crypto_if.h b/drivers/crypto/ionic/ionic_crypto_if.h index ea418f3d4b..eef2b6a6d9 100644 --- a/drivers/crypto/ionic/ionic_crypto_if.h +++ b/drivers/crypto/ionic/ionic_crypto_if.h @@ -263,13 +263,13 @@ struct iocpt_lif_setattr_cmd { u8 opcode; u8 attr; __le16 lif_index; - union { + __rte_packed_begin union { u8 state; char name[IOCPT_IFNAMSIZ]; __le64 features; u8 stats_ctl; u8 rsvd[60]; - } __rte_packed; + } __rte_packed_end; }; /** @@ -283,10 +283,10 @@ struct iocpt_lif_setattr_comp { u8 status; u8 rsvd; __le16 comp_index; - union { + __rte_packed_begin union { __le64 features; u8 rsvd2[11]; - } __rte_packed; + } __rte_packed_end; u8 color; }; @@ -316,11 +316,11 @@ struct iocpt_lif_getattr_comp { u8 status; u8 rsvd; __le16 comp_index; - union { + __rte_packed_begin union { u8 state; __le64 features; u8 rsvd2[11]; - } __rte_packed; + } __rte_packed_end; u8 color; }; @@ -396,7 +396,7 @@ struct iocpt_q_identify_comp { * @cq_ring_base: Completion queue ring base address * @sg_ring_base: Scatter/Gather ring base address */ -struct iocpt_q_init_cmd { +__rte_packed_begin struct iocpt_q_init_cmd { u8 opcode; u8 type; __le16 lif_index; @@ -417,7 +417,7 @@ struct iocpt_q_init_cmd { __le64 cq_ring_base; __le64 sg_ring_base; u8 rsvd2[20]; -} __rte_packed; +} __rte_packed_end; /** * struct iocpt_q_init_comp - Queue init command completion @@ -469,7 +469,7 @@ enum iocpt_desc_opcode { * @intr_ctx_addr: Completion interrupt context address * @intr_ctx_data: Completion interrupt context data */ -struct iocpt_crypto_desc { +__rte_packed_begin struct iocpt_crypto_desc { uint8_t opcode; uint8_t flags; uint8_t num_src_dst_sgs; @@ -481,7 +481,7 @@ struct iocpt_crypto_desc { __le32 session_tag; __le64 intr_ctx_addr; __le64 intr_ctx_data; -} __rte_packed; +} __rte_packed_end; static inline uint8_t iocpt_encode_nsge_src_dst(uint8_t src, uint8_t dst) { @@ -765,14 +765,14 @@ struct iocpt_log_event { * @queue_count: Queue counts per queue-type */ union iocpt_lif_config { - struct { + __rte_packed_begin struct { u8 state; u8 rsvd[3]; char name[IOCPT_IFNAMSIZ]; u8 rsvd2[12]; __le64 features; __le32 queue_count[IOCPT_QTYPE_MAX]; - } __rte_packed; + } __rte_packed_end; __le32 words[56]; }; @@ -876,14 +876,14 @@ union iocpt_dev_info_regs { * @data: Opcode-specific side-data */ union iocpt_dev_cmd_regs { - struct { + __rte_packed_begin struct { u32 doorbell; u32 done; union iocpt_dev_cmd cmd; union iocpt_dev_cmd_comp comp; u8 rsvd[48]; u32 data[478]; - } __rte_packed; + } __rte_packed_end; u32 words[512]; }; @@ -893,10 +893,10 @@ union iocpt_dev_cmd_regs { * @devcmd: Device command registers */ union iocpt_dev_regs { - struct { + __rte_packed_begin struct { union iocpt_dev_info_regs info; union iocpt_dev_cmd_regs devcmd; - } __rte_packed; + } __rte_packed_end; __le32 words[1024]; }; @@ -971,7 +971,7 @@ union iocpt_dev_identity { * @config: LIF config struct with features, q counts */ union iocpt_lif_identity { - struct { + __rte_packed_begin struct { __le64 features; u8 version; @@ -980,7 +980,7 @@ union iocpt_lif_identity { __le32 max_nb_sessions; u8 rsvd2[120]; union iocpt_lif_config config; - } __rte_packed; + } __rte_packed_end; __le32 words[90]; }; diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index 547bb490e2..28eef9ef55 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -32,9 +32,10 @@ enum mlx5_crypto_mode { MLX5_CRYPTO_IPSEC_OPT, }; +__rte_packed_begin struct mlx5_crypto_ipsec_mem { uint8_t mem[MLX5_CRYPTO_GCM_IPSEC_IV_SIZE]; -} __rte_packed; +} __rte_packed_end; struct mlx5_crypto_priv { TAILQ_ENTRY(mlx5_crypto_priv) next; @@ -108,6 +109,7 @@ struct mlx5_crypto_devarg_params { enum mlx5_crypto_mode crypto_mode; }; +__rte_packed_begin struct mlx5_crypto_session { union { /**< AES-XTS configuration. */ @@ -145,7 +147,7 @@ struct mlx5_crypto_session { /**< Initialisation Vector length. */ struct mlx5_crypto_dek *dek; /**< Pointer to dek struct. */ uint32_t dek_id; /**< DEK ID */ -} __rte_packed; +} __rte_packed_end; struct mlx5_crypto_dek_ctx { struct rte_crypto_sym_xform *xform; diff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c b/drivers/crypto/mlx5/mlx5_crypto_gcm.c index cd21605bd2..b62e60854a 100644 --- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c +++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c @@ -62,10 +62,11 @@ struct mlx5_crypto_gcm_data { uint32_t dst_mkey; }; +__rte_packed_begin struct mlx5_crypto_gcm_tag_cpy_info { void *digest; uint8_t tag_len; -} __rte_packed; +} __rte_packed_end; static struct rte_cryptodev_capabilities mlx5_crypto_gcm_caps[] = { { diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h index eedf5de755..622161ad56 100644 --- a/drivers/crypto/qat/qat_sym.h +++ b/drivers/crypto/qat/qat_sym.h @@ -103,10 +103,10 @@ struct qat_sym_session; -struct __rte_cache_aligned qat_sym_sgl { +__rte_packed_begin struct __rte_cache_aligned qat_sym_sgl { qat_sgl_hdr; struct qat_flat_buf buffers[QAT_SYM_SGL_MAX_NUMBER]; -} __rte_packed; +} __rte_packed_end; struct qat_sym_op_cookie { struct qat_sym_sgl qat_sgl_src; @@ -116,8 +116,9 @@ struct qat_sym_op_cookie { union { /* Used for Single-Pass AES-GMAC only */ struct { + __rte_packed_begin alignas(RTE_CACHE_LINE_SIZE) struct icp_qat_hw_cipher_algo_blk cd_cipher - __rte_packed; + __rte_packed_end; phys_addr_t cd_phys_addr; } spc_gmac; } opt; diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h index f2634774ec..2b85062170 100644 --- a/drivers/crypto/qat/qat_sym_session.h +++ b/drivers/crypto/qat/qat_sym_session.h @@ -92,7 +92,7 @@ typedef int (*qat_sym_build_request_t)(void *in_op, struct qat_sym_session *ctx, uint8_t *out_msg, void *op_cookie); /* Common content descriptor */ -struct __rte_cache_aligned qat_sym_cd { +__rte_packed_begin struct __rte_cache_aligned qat_sym_cd { struct icp_qat_hw_cipher_algo_blk cipher; union { struct icp_qat_hw_auth_algo_blk hash; @@ -100,7 +100,7 @@ struct __rte_cache_aligned qat_sym_cd { struct icp_qat_hw_gen3_crc_cd crc_gen3; struct icp_qat_hw_gen4_crc_cd crc_gen4; }; -} __rte_packed; +} __rte_packed_end; struct qat_sym_session { enum icp_qat_fw_la_cmd_id qat_cmd; From patchwork Wed Nov 27 00:52:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148875 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 50D2545D31; Wed, 27 Nov 2024 01:53:56 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 238794281D; Wed, 27 Nov 2024 01:53:16 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id E01F9427C2 for ; Wed, 27 Nov 2024 01:53:03 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id A8B89205721B; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com A8B89205721B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=P1si3iJYESKc/Y+TFw6m+VY0lw5juamfIAk+qH8VFqE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZG6O44y2roFjeVQSIw2l8zSM6R3vRjDMl6RaP6VSL/fJ0PEDDjLxX0j5P5U3lj4tm GfxV31kgFyY2BNPKQc2kVy88lsYCjxJkz95oXyS2eiNz/VRJfoJ2NOK79Z55+1v0gp Dowd5RfrptPK8iR/WGdPDpyvcrhxqKSZyyFlH+Ew= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 11/30] drivers/dma: replace packed attributes Date: Tue, 26 Nov 2024 16:52:22 -0800 Message-Id: <1732668761-5556-12-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retzlaff --- drivers/dma/dpaa/dpaa_qdma.h | 20 ++++++++++---------- drivers/dma/dpaa2/dpaa2_qdma.h | 16 ++++++++-------- drivers/dma/ioat/ioat_hw_defs.h | 3 ++- 3 files changed, 20 insertions(+), 19 deletions(-) diff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h index 91eaf1455a..579483ac34 100644 --- a/drivers/dma/dpaa/dpaa_qdma.h +++ b/drivers/dma/dpaa/dpaa_qdma.h @@ -119,7 +119,7 @@ (((fsl_qdma_engine)->block_offset) * (x)) /* qDMA Command Descriptor Formats */ -struct fsl_qdma_comp_cmd_desc { +__rte_packed_begin struct fsl_qdma_comp_cmd_desc { uint8_t status; uint32_t rsv0:22; uint32_t ser:1; @@ -132,9 +132,9 @@ struct fsl_qdma_comp_cmd_desc { uint8_t queue:3; uint8_t rsv4:3; uint8_t dd:2; -} __rte_packed; +} __rte_packed_end; -struct fsl_qdma_comp_sg_desc { +__rte_packed_begin struct fsl_qdma_comp_sg_desc { uint32_t offset:13; uint32_t rsv0:19; uint32_t length:30; @@ -143,9 +143,9 @@ struct fsl_qdma_comp_sg_desc { uint32_t addr_lo; uint8_t addr_hi; uint32_t rsv1:24; -} __rte_packed; +} __rte_packed_end; -struct fsl_qdma_sdf { +__rte_packed_begin struct fsl_qdma_sdf { uint32_t rsv0; uint32_t ssd:12; uint32_t sss:12; @@ -160,9 +160,9 @@ struct fsl_qdma_sdf { uint32_t sqos:3; uint32_t ns:1; uint32_t srttype:4; -} __rte_packed; +} __rte_packed_end; -struct fsl_qdma_ddf { +__rte_packed_begin struct fsl_qdma_ddf { uint32_t rsv0; uint32_t dsd:12; uint32_t dss:12; @@ -177,7 +177,7 @@ struct fsl_qdma_ddf { uint32_t dqos:3; uint32_t ns:1; uint32_t dwttype:4; -} __rte_packed; +} __rte_packed_end; struct fsl_qdma_df { struct fsl_qdma_sdf sdf; @@ -186,7 +186,7 @@ struct fsl_qdma_df { #define FSL_QDMA_SG_MAX_ENTRY 64 #define FSL_QDMA_MAX_DESC_NUM (FSL_QDMA_SG_MAX_ENTRY * QDMA_QUEUE_SIZE) -struct fsl_qdma_cmpd_ft { +__rte_packed_begin struct fsl_qdma_cmpd_ft { struct fsl_qdma_comp_sg_desc desc_buf; struct fsl_qdma_comp_sg_desc desc_sbuf; struct fsl_qdma_comp_sg_desc desc_dbuf; @@ -197,7 +197,7 @@ struct fsl_qdma_cmpd_ft { uint64_t phy_ssge; uint64_t phy_dsge; uint64_t phy_df; -} __rte_packed; +} __rte_packed_end; #define FSL_QDMA_ERR_REG_STATUS_OFFSET 0xe00 diff --git a/drivers/dma/dpaa2/dpaa2_qdma.h b/drivers/dma/dpaa2/dpaa2_qdma.h index 0fd1debaf8..664304e1ff 100644 --- a/drivers/dma/dpaa2/dpaa2_qdma.h +++ b/drivers/dma/dpaa2/dpaa2_qdma.h @@ -39,7 +39,7 @@ #define DPAA2_QDMA_BMT_DISABLE 0x0 /** Source/Destination Descriptor */ -struct qdma_sdd { +__rte_packed_begin struct qdma_sdd { uint32_t rsv; /** Stride configuration */ uint32_t stride; @@ -85,7 +85,7 @@ struct qdma_sdd { uint32_t wrttype:4; } write_cmd; }; -} __rte_packed; +} __rte_packed_end; #define QDMA_SG_FMT_SDB 0x0 /* single data buffer */ #define QDMA_SG_FMT_FDS 0x1 /* frame data section */ @@ -96,7 +96,7 @@ struct qdma_sdd { #define QDMA_SG_BMT_ENABLE DPAA2_QDMA_BMT_ENABLE #define QDMA_SG_BMT_DISABLE DPAA2_QDMA_BMT_DISABLE -struct qdma_sg_entry { +__rte_packed_begin struct qdma_sg_entry { uint32_t addr_lo; /* address 0:31 */ uint32_t addr_hi:17; /* address 32:48 */ uint32_t rsv:15; @@ -122,7 +122,7 @@ struct qdma_sg_entry { uint32_t f:1; } ctrl; }; -} __rte_packed; +} __rte_packed_end; struct dpaa2_qdma_rbp { uint32_t use_ultrashort:1; @@ -213,19 +213,19 @@ enum { DPAA2_QDMA_MAX_SDD }; -struct qdma_cntx_fle_sdd { +__rte_packed_begin struct qdma_cntx_fle_sdd { struct qbman_fle fle[DPAA2_QDMA_MAX_FLE]; struct qdma_sdd sdd[DPAA2_QDMA_MAX_SDD]; -} __rte_packed; +} __rte_packed_end; -struct qdma_cntx_sg { +__rte_packed_begin struct qdma_cntx_sg { struct qdma_cntx_fle_sdd fle_sdd; struct qdma_sg_entry sg_src_entry[RTE_DPAAX_QDMA_JOB_SUBMIT_MAX]; struct qdma_sg_entry sg_dst_entry[RTE_DPAAX_QDMA_JOB_SUBMIT_MAX]; uint16_t cntx_idx[RTE_DPAAX_QDMA_JOB_SUBMIT_MAX]; uint16_t job_nb; uint16_t rsv[3]; -} __rte_packed; +} __rte_packed_end; #define DPAA2_QDMA_IDXADDR_FROM_SG_FLAG(flag) \ ((void *)(uintptr_t)((flag) - ((flag) & RTE_DPAAX_QDMA_SG_IDX_ADDR_MASK))) diff --git a/drivers/dma/ioat/ioat_hw_defs.h b/drivers/dma/ioat/ioat_hw_defs.h index 11893951f2..e9c3ae236e 100644 --- a/drivers/dma/ioat/ioat_hw_defs.h +++ b/drivers/dma/ioat/ioat_hw_defs.h @@ -52,6 +52,7 @@ extern "C" { #define IOAT_DMACAP_PQ (1 << 9) #define IOAT_DMACAP_DMA_DIF (1 << 10) +__rte_packed_begin struct ioat_registers { uint8_t chancnt; uint8_t xfercap; @@ -75,7 +76,7 @@ struct ioat_registers { uint8_t reserved2[0x8]; /* 0xA0 */ uint32_t chanerr; /* 0xA8 */ uint32_t chanerrmask; /* 0xAC */ -} __rte_packed; +} __rte_packed_end; #define IOAT_CHANCMD_RESET 0x20 #define IOAT_CHANCMD_SUSPEND 0x04 From patchwork Wed Nov 27 00:52:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148878 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0990D45D31; Wed, 27 Nov 2024 01:54:18 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 971B342D68; Wed, 27 Nov 2024 01:53:19 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 12564427C6 for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id B7189205721D; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com B7189205721D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=R8adi69/x1IbKfPQtANGYABaV7GXn0hgKwUhNSu0yzE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pIvx5BSvt3ujSaGmSoZBT3MneVnnCz0ohFwmN9W7UY4y/2VxSA0hKqmGp2khuXLWV qi7O0NdWQ46I1bDAfC/HgK/1Vsjd+dfV83c2JJg3aXfdRdGtnvtTciUeUaJfMJdE4r TpX00Y7E871kbgGzBNfI9zJ5faADqv1+uGgl1CDk= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 12/30] drivers/event: replace packed attributes Date: Tue, 26 Nov 2024 16:52:23 -0800 Message-Id: <1732668761-5556-13-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retzlaff --- drivers/event/octeontx/timvf_evdev.c | 4 ++-- drivers/event/octeontx/timvf_evdev.h | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/event/octeontx/timvf_evdev.c b/drivers/event/octeontx/timvf_evdev.c index 82f17144a6..9339b13941 100644 --- a/drivers/event/octeontx/timvf_evdev.c +++ b/drivers/event/octeontx/timvf_evdev.c @@ -9,10 +9,10 @@ RTE_LOG_REGISTER_SUFFIX(otx_logtype_timvf, timer, NOTICE); static struct rte_eventdev *event_dev; -struct __rte_packed timvf_mbox_dev_info { +__rte_packed_begin struct timvf_mbox_dev_info { uint64_t ring_active[4]; uint64_t clk_freq; -}; +} __rte_packed_end; /* Response messages */ enum { diff --git a/drivers/event/octeontx/timvf_evdev.h b/drivers/event/octeontx/timvf_evdev.h index 44a4ee41c4..0dd3734773 100644 --- a/drivers/event/octeontx/timvf_evdev.h +++ b/drivers/event/octeontx/timvf_evdev.h @@ -123,7 +123,7 @@ enum timvf_clk_src { }; /* TIM_MEM_BUCKET */ -struct __rte_aligned(8) tim_mem_bucket { +__rte_packed_begin struct __rte_aligned(8) tim_mem_bucket { uint64_t first_chunk; union { RTE_ATOMIC(uint64_t) w1; @@ -139,19 +139,19 @@ struct __rte_aligned(8) tim_mem_bucket { }; uint64_t current_chunk; uint64_t pad; -} __rte_packed; +} __rte_packed_end; -struct tim_mem_entry { +__rte_packed_begin struct tim_mem_entry { uint64_t w0; uint64_t wqe; -} __rte_packed; +} __rte_packed_end; -struct timvf_ctrl_reg { +__rte_packed_begin struct timvf_ctrl_reg { uint64_t rctrl0; uint64_t rctrl1; uint64_t rctrl2; uint8_t use_pmu; -} __rte_packed; +} __rte_packed_end; struct timvf_ring; From patchwork Wed Nov 27 00:52:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148877 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3556345D31; Wed, 27 Nov 2024 01:54:11 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6DEE142D35; Wed, 27 Nov 2024 01:53:18 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 1CE66427C8 for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id C56C5205721E; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com C56C5205721E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=41QqEvKhdTUbVHkr0I9R+3kOXu21RJHhLQiKu8HITp8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eJB2mVEitTOGOfGbW5RBUHeE+RuR4x7zcMn1I3ATH1PRzmD5Zz5u0LzAZQsOYGsyG 3mKCXg6RUAfwkuTrrEF4Wm1ja8jRP5LZVCxZGr/xIoHwiIg4Ow4AK4LE7LOpP1YI6M zN83SDRBRtkVo/nCUsOvDzPLLQgwn9aammfCj3B0= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 13/30] drivers/mempool: replace packed attributes Date: Tue, 26 Nov 2024 16:52:24 -0800 Message-Id: <1732668761-5556-14-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retzlaff --- drivers/mempool/octeontx/octeontx_fpavf.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/mempool/octeontx/octeontx_fpavf.c b/drivers/mempool/octeontx/octeontx_fpavf.c index 966fee8bfe..d2eb837c17 100644 --- a/drivers/mempool/octeontx/octeontx_fpavf.c +++ b/drivers/mempool/octeontx/octeontx_fpavf.c @@ -46,20 +46,20 @@ struct octeontx_mbox_fpa_cfg { uint64_t aura_cfg; }; -struct __rte_packed gen_req { +__rte_packed_begin struct gen_req { uint32_t value; -}; +} __rte_packed_end; -struct __rte_packed idn_req { +__rte_packed_begin struct idn_req { uint8_t domain_id; -}; +} __rte_packed_end; -struct __rte_packed gen_resp { +__rte_packed_begin struct gen_resp { uint16_t domain_id; uint16_t vfid; -}; +} __rte_packed_end; -struct __rte_packed dcfg_resp { +__rte_packed_begin struct dcfg_resp { uint8_t sso_count; uint8_t ssow_count; uint8_t fpa_count; @@ -67,7 +67,7 @@ struct __rte_packed dcfg_resp { uint8_t tim_count; uint8_t net_port_count; uint8_t virt_port_count; -}; +} __rte_packed_end; #define FPA_MAX_POOL 32 #define FPA_PF_PAGE_SZ 4096 From patchwork Wed Nov 27 00:52:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148893 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C508945D31; Wed, 27 Nov 2024 01:55:34 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0C5C642E3A; Wed, 27 Nov 2024 01:53:40 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 1791D427C7 for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id D44CE205721F; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com D44CE205721F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668782; bh=BG9S/4o4ubMQfyaVRUzPSfmnyjbUsXbg6tpAPVXw/jA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WjBox15yTmLIbK5S74Tuzy3ulianGWP024R+SeRZuPohTQRMZynT90W0zWOOAUsdb S2O70cZtzl343LNQeGRNkut74856nakpFkOOVqPitsJePuDbB6eFYi//zSLfA3kKP1 okssDQiFKV+xJICnwYjhEPSRSsiKFDCBROoSkyB4= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 14/30] drivers/net: replace packed attributes Date: Tue, 26 Nov 2024 16:52:25 -0800 Message-Id: <1732668761-5556-15-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie --- drivers/net/ark/ark_ddm.h | 4 +- drivers/net/ark/ark_pktchkr.h | 8 +- drivers/net/ark/ark_pktdir.h | 5 +- drivers/net/ark/ark_pktgen.h | 4 +- drivers/net/ark/ark_udm.h | 4 +- drivers/net/atlantic/hw_atl/hw_atl_utils.h | 120 +- .../net/atlantic/hw_atl/hw_atl_utils_fw2x.c | 8 +- drivers/net/avp/rte_avp_common.h | 12 +- drivers/net/bnxt/bnxt.h | 8 +- drivers/net/bnxt/hsi_struct_def_dpdk.h | 3344 ++++++++--------- drivers/net/bnxt/tf_core/tf_resources.h | 32 +- drivers/net/bnxt/tf_core/v3/tfc_mpc_table.c | 20 +- drivers/net/bonding/rte_eth_bond_8023ad.h | 32 +- drivers/net/cnxk/cn10k_rxtx.h | 4 +- drivers/net/cnxk/cn20k_rxtx.h | 4 +- drivers/net/cnxk/cn9k_ethdev.h | 4 +- drivers/net/cnxk/cnxk_rep_msg.h | 64 +- drivers/net/dpaa/dpaa_rxtx.h | 28 +- drivers/net/dpaa/fmlib/fm_ext.h | 4 +- drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h | 4 +- drivers/net/dpaa2/dpaa2_recycle.c | 16 +- drivers/net/enic/base/vnic_devcmd.h | 40 +- drivers/net/enic/base/vnic_flowman.h | 120 +- drivers/net/gve/base/gve_desc.h | 16 +- drivers/net/gve/base/gve_desc_dqo.h | 32 +- drivers/net/gve/base/gve_osdep.h | 3 - drivers/net/hns3/hns3_mbx.h | 8 +- drivers/net/hns3/hns3_rxtx.h | 4 +- drivers/net/i40e/base/i40e_osdep.h | 6 +- drivers/net/iavf/iavf_ipsec_crypto.h | 8 +- drivers/net/iavf/iavf_rxtx.c | 2 +- drivers/net/ice/base/ice_osdep.h | 9 +- drivers/net/ionic/ionic_if.h | 72 +- drivers/net/memif/memif.h | 36 +- drivers/net/mlx4/mlx4_mr.h | 12 +- drivers/net/mlx5/hws/mlx5dr.h | 3 +- drivers/net/mlx5/mlx5.h | 3 +- drivers/net/mlx5/mlx5_flow.h | 12 +- drivers/net/mlx5/mlx5_hws_cnt.h | 3 +- drivers/net/mlx5/mlx5_utils.h | 12 +- drivers/net/netvsc/hn_nvs.h | 72 +- drivers/net/netvsc/ndis.h | 8 +- drivers/net/nfp/flower/nfp_flower_cmsg.h | 4 +- drivers/net/nfp/flower/nfp_flower_flow.h | 4 +- drivers/net/nfp/nfd3/nfp_nfd3.h | 4 +- drivers/net/nfp/nfp_rxtx.h | 8 +- drivers/net/nfp/nfpcore/nfp_nsp.c | 4 +- drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c | 12 +- drivers/net/octeon_ep/otx_ep_mbox.h | 3 +- drivers/net/octeontx/base/octeontx_pki_var.h | 4 +- drivers/net/pfe/pfe_hif.h | 4 +- drivers/net/virtio/virtio.h | 4 +- drivers/net/virtio/virtio_cvq.h | 8 +- drivers/net/virtio/virtio_user/vhost_user.c | 4 +- drivers/net/zxdh/zxdh_common.c | 8 +- drivers/net/zxdh/zxdh_msg.h | 16 +- drivers/net/zxdh/zxdh_pci.h | 4 +- drivers/net/zxdh/zxdh_queue.h | 64 +- drivers/net/zxdh/zxdh_rxtx.h | 8 +- 59 files changed, 2193 insertions(+), 2180 deletions(-) diff --git a/drivers/net/ark/ark_ddm.h b/drivers/net/ark/ark_ddm.h index 84beeb063a..345b4dbbcc 100644 --- a/drivers/net/ark/ark_ddm.h +++ b/drivers/net/ark/ark_ddm.h @@ -17,7 +17,7 @@ */ /* struct defining Tx meta data -- fixed in FPGA -- 8 bytes */ -union ark_tx_meta { +__rte_packed_begin union ark_tx_meta { uint64_t physaddr; struct { uint32_t usermeta0; @@ -31,7 +31,7 @@ union ark_tx_meta { uint8_t meta_cnt; uint32_t user1; }; -} __rte_packed; +} __rte_packed_end; /* * DDM core hardware structures diff --git a/drivers/net/ark/ark_pktchkr.h b/drivers/net/ark/ark_pktchkr.h index b362281776..00e548d8a1 100644 --- a/drivers/net/ark/ark_pktchkr.h +++ b/drivers/net/ark/ark_pktchkr.h @@ -23,7 +23,7 @@ typedef void *ark_pkt_chkr_t; * This are overlay structures to a memory mapped FPGA device. These * structs will never be instantiated in ram memory */ -struct ark_pkt_chkr_stat_regs { +__rte_packed_begin struct ark_pkt_chkr_stat_regs { uint32_t r0; uint32_t pkt_start_stop; uint32_t pkt_ctrl; @@ -37,9 +37,9 @@ struct ark_pkt_chkr_stat_regs { uint32_t pkts_missing; uint32_t min_latency; uint32_t max_latency; -} __rte_packed; +} __rte_packed_end; -struct ark_pkt_chkr_ctl_regs { +__rte_packed_begin struct ark_pkt_chkr_ctl_regs { uint32_t pkt_ctrl; uint32_t pkt_payload; uint32_t pkt_size_min; @@ -53,7 +53,7 @@ struct ark_pkt_chkr_ctl_regs { uint32_t dst_mac_addr_h; uint32_t eth_type; uint32_t hdr_dw[7]; -} __rte_packed; +} __rte_packed_end; struct ark_pkt_chkr_inst { struct rte_eth_dev_info *dev_info; diff --git a/drivers/net/ark/ark_pktdir.h b/drivers/net/ark/ark_pktdir.h index b5577cebb3..d84fa322b5 100644 --- a/drivers/net/ark/ark_pktdir.h +++ b/drivers/net/ark/ark_pktdir.h @@ -6,6 +6,7 @@ #define _ARK_PKTDIR_H_ #include +#include #define ARK_PKT_DIR_INIT_VAL 0x0110 @@ -22,11 +23,11 @@ typedef void *ark_pkt_dir_t; * This is an overlay structures to a memory mapped FPGA device. These * structs will never be instantiated in ram memory */ -struct ark_pkt_dir_regs { +__rte_packed_begin struct ark_pkt_dir_regs { uint32_t ctrl; uint32_t status; uint32_t stall_cnt; -} __rte_packed; +} __rte_packed_end; struct ark_pkt_dir_inst { volatile struct ark_pkt_dir_regs *regs; diff --git a/drivers/net/ark/ark_pktgen.h b/drivers/net/ark/ark_pktgen.h index 925058367c..183154ffa8 100644 --- a/drivers/net/ark/ark_pktgen.h +++ b/drivers/net/ark/ark_pktgen.h @@ -22,7 +22,7 @@ typedef void *ark_pkt_gen_t; * This is an overlay structure to a memory mapped FPGA device. These * structs will never be instantiated in ram memory */ -struct ark_pkt_gen_regs { +__rte_packed_begin struct ark_pkt_gen_regs { uint32_t r0; volatile uint32_t pkt_start_stop; volatile uint32_t pkt_ctrl; @@ -41,7 +41,7 @@ struct ark_pkt_gen_regs { uint32_t hdr_dw[7]; uint32_t start_offset; uint32_t bytes_per_cycle; -} __rte_packed; +} __rte_packed_end; struct ark_pkt_gen_inst { struct rte_eth_dev_info *dev_info; diff --git a/drivers/net/ark/ark_udm.h b/drivers/net/ark/ark_udm.h index ec53ec7e79..aac89c31f0 100644 --- a/drivers/net/ark/ark_udm.h +++ b/drivers/net/ark/ark_udm.h @@ -18,12 +18,12 @@ /* Meta data structure passed from FPGA, must match layout in FPGA * -- 32 bytes */ -struct ark_rx_meta { +__rte_packed_begin struct ark_rx_meta { uint32_t user_meta[5]; /* user defined based on fpga code */ uint32_t pkt_len32; uint8_t reserved[6]; uint16_t pkt_len; -} __rte_packed; +} __rte_packed_end; /* * UDM hardware structures diff --git a/drivers/net/atlantic/hw_atl/hw_atl_utils.h b/drivers/net/atlantic/hw_atl/hw_atl_utils.h index 12ac9b041e..0d1bd46606 100644 --- a/drivers/net/atlantic/hw_atl/hw_atl_utils.h +++ b/drivers/net/atlantic/hw_atl/hw_atl_utils.h @@ -12,11 +12,11 @@ #define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); } /* Hardware tx descriptor */ -struct hw_atl_txd_s { +__rte_packed_begin struct hw_atl_txd_s { u64 buf_addr; union { - struct { + __rte_packed_begin struct { u32 type:3; u32:1; u32 len:16; @@ -27,19 +27,19 @@ struct hw_atl_txd_s { u32 ct_idx:1; u32 ct_en:1; u32 pay_len:18; - } __rte_packed; + } __rte_packed_end; u64 flags; }; -} __rte_packed; +} __rte_packed_end; /* Hardware tx context descriptor */ -union hw_atl_txc_s { +__rte_packed_begin union hw_atl_txc_s { struct { u64 flags1; u64 flags2; }; - struct { + __rte_packed_begin struct { u64:40; u32 tun_len:8; u32 out_len:16; @@ -51,8 +51,8 @@ union hw_atl_txc_s { u32 l3_len:9; u32 l4_len:8; u32 mss_len:16; - } __rte_packed; -} __rte_packed; + } __rte_packed_end; +} __rte_packed_end; enum aq_tx_desc_type { tx_desc_type_desc = 1, @@ -70,13 +70,13 @@ enum aq_tx_desc_cmd { /* Hardware rx descriptor */ -struct hw_atl_rxd_s { +__rte_packed_begin struct hw_atl_rxd_s { u64 buf_addr; u64 hdr_addr; -} __rte_packed; +} __rte_packed_end; /* Hardware rx descriptor writeback */ -struct hw_atl_rxd_wb_s { +__rte_packed_begin struct hw_atl_rxd_wb_s { u32 rss_type:4; u32 pkt_type:8; u32 type:20; @@ -89,9 +89,9 @@ struct hw_atl_rxd_wb_s { u16 pkt_len; u16 next_desc_ptr; u16 vlan; -} __rte_packed; +} __rte_packed_end; -struct hw_atl_stats_s { +__rte_packed_begin struct hw_atl_stats_s { u32 uprc; u32 mprc; u32 bprc; @@ -107,9 +107,9 @@ struct hw_atl_stats_s { u32 ubrc; u32 ubtc; u32 dpc; -} __rte_packed; +} __rte_packed_end; -union ip_addr { +__rte_packed_begin union ip_addr { struct { u8 addr[16]; } v6; @@ -117,9 +117,9 @@ union ip_addr { u8 padding[12]; u8 addr[4]; } v4; -} __rte_packed; +} __rte_packed_end; -struct hw_aq_atl_utils_fw_rpc { +__rte_packed_begin struct hw_aq_atl_utils_fw_rpc { u32 msg_id; union { @@ -226,15 +226,15 @@ struct hw_aq_atl_utils_fw_rpc { } msg_del_id; }; -} __rte_packed; +} __rte_packed_end; -struct hw_aq_atl_utils_mbox_header { +__rte_packed_begin struct hw_aq_atl_utils_mbox_header { u32 version; u32 transaction_id; u32 error; -} __rte_packed; +} __rte_packed_end; -struct hw_aq_info { +__rte_packed_begin struct hw_aq_info { u8 reserved[6]; u16 phy_fault_code; u16 phy_temperature; @@ -244,13 +244,13 @@ struct hw_aq_info { u8 reserved2[32]; u32 caps_lo; u32 caps_hi; -} __rte_packed; +} __rte_packed_end; -struct hw_aq_atl_utils_mbox { +__rte_packed_begin struct hw_aq_atl_utils_mbox { struct hw_aq_atl_utils_mbox_header header; struct hw_atl_stats_s stats; struct hw_aq_info info; -} __rte_packed; +} __rte_packed_end; /* fw2x */ typedef u16 in_port_t; @@ -259,11 +259,11 @@ typedef int int32_t; typedef short int16_t; typedef u32 fw_offset_t; -struct ip6_addr { +__rte_packed_begin struct ip6_addr { u32 addr[4]; -} __rte_packed; +} __rte_packed_end; -struct offload_ka_v4 { +__rte_packed_begin struct offload_ka_v4 { u32 timeout; in_port_t local_port; in_port_t remote_port; @@ -273,9 +273,9 @@ struct offload_ka_v4 { u32 ack_num; ip4_addr_t local_ip; ip4_addr_t remote_ip; -} __rte_packed; +} __rte_packed_end; -struct offload_ka_v6 { +__rte_packed_begin struct offload_ka_v6 { u32 timeout; in_port_t local_port; in_port_t remote_port; @@ -285,9 +285,9 @@ struct offload_ka_v6 { u32 ack_num; struct ip6_addr local_ip; struct ip6_addr remote_ip; -} __rte_packed; +} __rte_packed_end; -struct offload_ip_info { +__rte_packed_begin struct offload_ip_info { u8 v4_local_addr_count; u8 v4_addr_count; u8 v6_local_addr_count; @@ -296,32 +296,32 @@ struct offload_ip_info { fw_offset_t v4_prefix; fw_offset_t v6_addr; fw_offset_t v6_prefix; -} __rte_packed; +} __rte_packed_end; -struct offload_port_info { +__rte_packed_begin struct offload_port_info { u16 udp_port_count; u16 tcp_port_count; fw_offset_t udp_port; fw_offset_t tcp_port; -} __rte_packed; +} __rte_packed_end; -struct offload_ka_info { +__rte_packed_begin struct offload_ka_info { u16 v4_ka_count; u16 v6_ka_count; u32 retry_count; u32 retry_interval; fw_offset_t v4_ka; fw_offset_t v6_ka; -} __rte_packed; +} __rte_packed_end; -struct offload_rr_info { +__rte_packed_begin struct offload_rr_info { u32 rr_count; u32 rr_buf_len; fw_offset_t rr_id_x; fw_offset_t rr_buf; -} __rte_packed; +} __rte_packed_end; -struct offload_info { +__rte_packed_begin struct offload_info { u32 version; // current version is 0x00000000 u32 len; // The whole structure length // including the variable-size buf @@ -335,14 +335,14 @@ struct offload_info { struct offload_ka_info kas; struct offload_rr_info rrs; u8 buf[]; -} __rte_packed; +} __rte_packed_end; -struct smbus_request { +__rte_packed_begin struct smbus_request { u32 msg_id; /* not used */ u32 device_id; u32 address; u32 length; -} __rte_packed; +} __rte_packed_end; enum macsec_msg_type { macsec_cfg_msg = 0, @@ -353,14 +353,14 @@ enum macsec_msg_type { macsec_get_stats_msg, }; -struct macsec_cfg { +__rte_packed_begin struct macsec_cfg { uint32_t enabled; uint32_t egress_threshold; uint32_t ingress_threshold; uint32_t interrupts_enabled; -} __rte_packed; +} __rte_packed_end; -struct add_rx_sc { +__rte_packed_begin struct add_rx_sc { uint32_t index; uint32_t pi; /* Port identifier */ uint32_t sci[2]; /* Secure Channel identifier */ @@ -376,9 +376,9 @@ struct add_rx_sc { uint32_t anti_replay_window; /* default 0 */ /* 1: auto_rollover enabled (when SA next_pn is saturated */ uint32_t an_rol; -} __rte_packed; +} __rte_packed_end; -struct add_tx_sc { +__rte_packed_begin struct add_tx_sc { uint32_t index; uint32_t pi; /* Port identifier */ uint32_t sci[2]; /* Secure Channel identifier */ @@ -391,28 +391,28 @@ struct add_tx_sc { uint32_t da_mask; /* 0: ignore mac_da */ uint32_t protect; uint32_t curr_an; /* SA index which currently used */ -} __rte_packed; +} __rte_packed_end; -struct add_rx_sa { +__rte_packed_begin struct add_rx_sa { uint32_t index; uint32_t next_pn; uint32_t key[4]; /* 128 bit key */ -} __rte_packed; +} __rte_packed_end; -struct add_tx_sa { +__rte_packed_begin struct add_tx_sa { uint32_t index; uint32_t next_pn; uint32_t key[4]; /* 128 bit key */ -} __rte_packed; +} __rte_packed_end; -struct get_stats { +__rte_packed_begin struct get_stats { uint32_t version_only; uint32_t ingress_sa_index; uint32_t egress_sa_index; uint32_t egress_sc_index; -} __rte_packed; +} __rte_packed_end; -struct macsec_stats { +__rte_packed_begin struct macsec_stats { uint32_t api_version; /* Ingress Common Counters */ uint64_t in_ctl_pkts; @@ -471,9 +471,9 @@ struct macsec_stats { uint32_t ingress_threshold_expired; uint32_t egress_expired; uint32_t ingress_expired; -} __rte_packed; +} __rte_packed_end; -struct macsec_msg_fw_request { +__rte_packed_begin struct macsec_msg_fw_request { uint32_t offset; /* not used */ uint32_t msg_type; @@ -485,12 +485,12 @@ struct macsec_msg_fw_request { struct add_tx_sa txsa; struct get_stats stats; }; -} __rte_packed; +} __rte_packed_end; -struct macsec_msg_fw_response { +__rte_packed_begin struct macsec_msg_fw_response { uint32_t result; struct macsec_stats stats; -} __rte_packed; +} __rte_packed_end; #define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U #define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U diff --git a/drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c b/drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c index 3a7faf405c..45c4b3549a 100644 --- a/drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c +++ b/drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c @@ -37,12 +37,12 @@ #define HW_ATL_FW_FEATURE_LED 0x03010026 -struct fw2x_msg_wol_pattern { +__rte_packed_begin struct fw2x_msg_wol_pattern { u8 mask[16]; u32 crc; -} __rte_packed; +} __rte_packed_end; -struct fw2x_msg_wol { +__rte_packed_begin struct fw2x_msg_wol { u32 msg_id; u8 hw_addr[6]; u8 magic_packet_enabled; @@ -53,7 +53,7 @@ struct fw2x_msg_wol { u16 reserved; u32 link_up_timeout; u32 link_down_timeout; -} __rte_packed; +} __rte_packed_end; static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed); static int aq_fw2x_set_state(struct aq_hw_s *self, diff --git a/drivers/net/avp/rte_avp_common.h b/drivers/net/avp/rte_avp_common.h index 5ad71ac088..10c1e798db 100644 --- a/drivers/net/avp/rte_avp_common.h +++ b/drivers/net/avp/rte_avp_common.h @@ -60,7 +60,7 @@ enum rte_avp_req_id { /* * Structure for AVP queue configuration query request/result */ -struct rte_avp_device_config { +__rte_packed_begin struct rte_avp_device_config { uint64_t device_id; /**< Unique system identifier */ uint32_t driver_type; /**< Device Driver type */ uint32_t driver_version; /**< Device Driver version */ @@ -68,12 +68,12 @@ struct rte_avp_device_config { uint16_t num_tx_queues; /**< Number of active transmit queues */ uint16_t num_rx_queues; /**< Number of active receive queues */ uint8_t if_up; /**< 1: interface up, 0: interface down */ -} __rte_packed; +} __rte_packed_end; /* * Structure for AVP request. */ -struct rte_avp_request { +__rte_packed_begin struct rte_avp_request { uint32_t req_id; /**< Request id */ union { uint32_t new_mtu; /**< New MTU */ @@ -81,7 +81,7 @@ struct rte_avp_request { struct rte_avp_device_config config; /**< Queue configuration */ }; int32_t result; /**< Result for processing request */ -} __rte_packed; +} __rte_packed_end; /* * FIFO struct mapped in a shared memory. It describes a circular buffer FIFO @@ -100,7 +100,7 @@ struct rte_avp_fifo { /* * AVP packet buffer header used to define the exchange of packet data. */ -struct __rte_cache_aligned rte_avp_desc { +__rte_packed_begin struct __rte_cache_aligned rte_avp_desc { uint64_t pad0; void *pkt_mbuf; /**< Reference to packet mbuf */ uint8_t pad1[14]; @@ -114,7 +114,7 @@ struct __rte_cache_aligned rte_avp_desc { uint32_t pad3; uint16_t vlan_tci; /**< VLAN Tag Control Identifier (CPU order). */ uint32_t pad4; -} __rte_packed; +} __rte_packed_end; /**{ AVP device features */ diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 0402de3eb9..b6ad6c0277 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -219,16 +219,16 @@ struct bnxt_led_cfg { #define BNXT_LED_DFLT_ENABLES(x) \ rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) -struct bnxt_vlan_table_entry { +__rte_packed_begin struct bnxt_vlan_table_entry { uint16_t tpid; uint16_t vid; -} __rte_packed; +} __rte_packed_end; -struct bnxt_vlan_antispoof_table_entry { +__rte_packed_begin struct bnxt_vlan_antispoof_table_entry { uint16_t tpid; uint16_t vid; uint16_t mask; -} __rte_packed; +} __rte_packed_end; struct bnxt_child_vf_info { void *req_buf; diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 737bf2693b..6c3c66a5e4 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -10,7 +10,7 @@ /* This is the HWRM command header. */ /* hwrm_cmd_hdr (size:128b/16B) */ -struct hwrm_cmd_hdr { +__rte_packed_begin struct hwrm_cmd_hdr { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39,11 +39,11 @@ struct hwrm_cmd_hdr { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* This is the HWRM response header. */ /* hwrm_resp_hdr (size:64b/8B) */ -struct hwrm_resp_hdr { +__rte_packed_begin struct hwrm_resp_hdr { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52,7 +52,7 @@ struct hwrm_resp_hdr { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; -} __rte_packed; +} __rte_packed_end; /* * TLV encapsulated message. Use the TLV type field of the @@ -99,7 +99,7 @@ struct hwrm_resp_hdr { /* tlv (size:64b/8B) */ -struct tlv { +__rte_packed_begin struct tlv { /* * The command discriminator is used to differentiate between various * types of HWRM messages. This includes legacy HWRM and RoCE slowpath @@ -151,11 +151,11 @@ struct tlv { * and it must be an integer multiple of 8B. */ uint16_t length; -} __rte_packed; +} __rte_packed_end; /* Input */ /* input (size:128b/16B) */ -struct input { +__rte_packed_begin struct input { /* * This value indicates what type of request this is. The format * for the rest of the command is determined by this field. @@ -184,11 +184,11 @@ struct input { * and must be cleared to zero before the request is made. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* Output */ /* output (size:64b/8B) */ -struct output { +__rte_packed_begin struct output { /* * Pass/Fail or error type * @@ -207,11 +207,11 @@ struct output { * memory. */ uint16_t resp_len; -} __rte_packed; +} __rte_packed_end; /* Short Command Structure */ /* hwrm_short_input (size:128b/16B) */ -struct hwrm_short_input { +__rte_packed_begin struct hwrm_short_input { /* * This field indicates the type of request in the request buffer. * The format for the rest of the command (request) is determined @@ -243,7 +243,7 @@ struct hwrm_short_input { * This area must be 16B aligned. */ uint64_t req_addr; -} __rte_packed; +} __rte_packed_end; /* * Command numbering @@ -251,7 +251,7 @@ struct hwrm_short_input { * # So only structure definition is provided here. */ /* cmd_nums (size:64b/8B) */ -struct cmd_nums { +__rte_packed_begin struct cmd_nums { /* * This version of the specification defines the commands listed in * the table below. The following are general implementation @@ -1046,11 +1046,11 @@ struct cmd_nums { #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff) #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK uint16_t unused_0[3]; -} __rte_packed; +} __rte_packed_end; /* Return Codes */ /* ret_codes (size:64b/8B) */ -struct ret_codes { +__rte_packed_begin struct ret_codes { uint16_t error_code; /* Request was successfully executed by the HWRM. */ #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0) @@ -1169,11 +1169,11 @@ struct ret_codes { #define HWRM_ERR_CODE_LAST \ HWRM_ERR_CODE_CMD_NOT_SUPPORTED uint16_t unused_0[3]; -} __rte_packed; +} __rte_packed_end; /* Output */ /* hwrm_err_output (size:128b/16B) */ -struct hwrm_err_output { +__rte_packed_begin struct hwrm_err_output { /* * Pass/Fail or error type * @@ -1209,7 +1209,7 @@ struct hwrm_err_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* * Following is the signature for HWRM message field that indicates not * applicable (All F's). Need to cast it the size of the field if needed. @@ -1255,7 +1255,7 @@ struct hwrm_err_output { /* hwrm_ver_get_input (size:192b/24B) */ -struct hwrm_ver_get_input { +__rte_packed_begin struct hwrm_ver_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -1312,10 +1312,10 @@ struct hwrm_ver_get_input { */ uint8_t hwrm_intf_upd; uint8_t unused_0[5]; -} __rte_packed; +} __rte_packed_end; /* hwrm_ver_get_output (size:1408b/176B) */ -struct hwrm_ver_get_output { +__rte_packed_begin struct hwrm_ver_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -1842,10 +1842,10 @@ struct hwrm_ver_get_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* cfa_bds_read_cmd_data_msg (size:128b/16B) */ -struct cfa_bds_read_cmd_data_msg { +__rte_packed_begin struct cfa_bds_read_cmd_data_msg { /* This value selects the format for the mid-path command for the CFA. */ uint8_t opcode; /* @@ -1888,10 +1888,10 @@ struct cfa_bds_read_cmd_data_msg { * zero. The size of the write is controlled by the data_size field. */ uint64_t host_address; -} __rte_packed; +} __rte_packed_end; /* cfa_bds_write_cmd_data_msg (size:1152b/144B) */ -struct cfa_bds_write_cmd_data_msg { +__rte_packed_begin struct cfa_bds_write_cmd_data_msg { /* This value selects the format for the mid-path command for the CFA. */ uint8_t opcode; /* @@ -1941,10 +1941,10 @@ struct cfa_bds_write_cmd_data_msg { * WRITE_CMD message is extracted from the BD. */ uint32_t dta[32]; -} __rte_packed; +} __rte_packed_end; /* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */ -struct cfa_bds_read_clr_cmd_data_msg { +__rte_packed_begin struct cfa_bds_read_clr_cmd_data_msg { /* This value selects the format for the mid-path command for the CFA. */ uint8_t opcode; /* @@ -1997,10 +1997,10 @@ struct cfa_bds_read_clr_cmd_data_msg { uint16_t clear_mask; uint16_t unused0[3]; uint16_t unused1[4]; -} __rte_packed; +} __rte_packed_end; /* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */ -struct cfa_bds_em_insert_cmd_data_msg { +__rte_packed_begin struct cfa_bds_em_insert_cmd_data_msg { /* This value selects the format for the mid-path command for the CFA. */ uint8_t opcode; /* @@ -2049,10 +2049,10 @@ struct cfa_bds_em_insert_cmd_data_msg { * the data_size field. The bd_cnt in the encapsulating BD must also be */ uint32_t dta[32]; -} __rte_packed; +} __rte_packed_end; /* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */ -struct cfa_bds_em_delete_cmd_data_msg { +__rte_packed_begin struct cfa_bds_em_delete_cmd_data_msg { /* This value selects the format for the mid-path command for the CFA. */ uint8_t opcode; /* An exact match table delete will be attempted. */ @@ -2094,10 +2094,10 @@ struct cfa_bds_em_delete_cmd_data_msg { */ uint64_t dta; uint32_t unused1[2]; -} __rte_packed; +} __rte_packed_end; /* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */ -struct cfa_bds_invalidate_cmd_data_msg { +__rte_packed_begin struct cfa_bds_invalidate_cmd_data_msg { /* This value selects the format for the mid-path command for the CFA. */ uint8_t opcode; /* @@ -2134,10 +2134,10 @@ struct cfa_bds_invalidate_cmd_data_msg { UINT32_C(0x3ffffff) #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0 uint32_t unused[2]; -} __rte_packed; +} __rte_packed_end; /* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */ -struct cfa_bds_event_collect_cmd_data_msg { +__rte_packed_begin struct cfa_bds_event_collect_cmd_data_msg { /* This value selects the format for the mid-path command for the CFA. */ uint8_t opcode; /* Reads notification messages from the Host Notification Queue. */ @@ -2164,10 +2164,10 @@ struct cfa_bds_event_collect_cmd_data_msg { * data will be written to the same function as the one that owns the SQ */ uint64_t host_address; -} __rte_packed; +} __rte_packed_end; /* ce_bds_add_data_msg (size:576b/72B) */ -struct ce_bds_add_data_msg { +__rte_packed_begin struct ce_bds_add_data_msg { uint32_t version_algorithm_kid_opcode; /* * This value selects the operation for the mid-path command for the @@ -2281,10 +2281,10 @@ struct ce_bds_add_data_msg { * the two end points. This field is used for TLS1.3 only. */ uint8_t addl_iv[8]; -} __rte_packed; +} __rte_packed_end; /* ce_bds_delete_data_msg (size:32b/4B) */ -struct ce_bds_delete_data_msg { +__rte_packed_begin struct ce_bds_delete_data_msg { uint32_t kid_opcode_ctx_kind; /* * This value selects the operation for the mid-path command for the @@ -2323,10 +2323,10 @@ struct ce_bds_delete_data_msg { #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24) #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_LAST \ CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX -} __rte_packed; +} __rte_packed_end; /* ce_bds_resync_resp_ack_msg (size:128b/16B) */ -struct ce_bds_resync_resp_ack_msg { +__rte_packed_begin struct ce_bds_resync_resp_ack_msg { uint32_t resync_status_kid_opcode; /* * This value selects the operation for the mid-path command for the @@ -2376,10 +2376,10 @@ struct ce_bds_resync_resp_ack_msg { * resume decrypting records. */ uint64_t resync_record_seq_num; -} __rte_packed; +} __rte_packed_end; /* ce_bds_resync_resp_nack_msg (size:64b/8B) */ -struct ce_bds_resync_resp_nack_msg { +__rte_packed_begin struct ce_bds_resync_resp_nack_msg { uint32_t resync_status_kid_opcode; /* * This value selects the operation for the mid-path command for the @@ -2423,10 +2423,10 @@ struct ce_bds_resync_resp_nack_msg { * response. */ uint32_t resync_record_tcp_seq_num; -} __rte_packed; +} __rte_packed_end; /* crypto_presync_bd_cmd (size:256b/32B) */ -struct crypto_presync_bd_cmd { +__rte_packed_begin struct crypto_presync_bd_cmd { uint8_t flags; /* * Typically, presync BDs are used for packet retransmissions. Source @@ -2519,10 +2519,10 @@ struct crypto_presync_bd_cmd { * field. */ uint64_t record_seq_num; -} __rte_packed; +} __rte_packed_end; /* ce_bds_quic_add_data_msg (size:832b/104B) */ -struct ce_bds_quic_add_data_msg { +__rte_packed_begin struct ce_bds_quic_add_data_msg { uint32_t ver_algo_kid_opcode; /* * This value selects the operation for the mid-path command for the @@ -2622,10 +2622,10 @@ struct ce_bds_quic_add_data_msg { uint8_t hp_key[32]; /* Packet number associated with the QUIC connection. */ uint64_t pkt_number; -} __rte_packed; +} __rte_packed_end; /* bd_base (size:64b/8B) */ -struct bd_base { +__rte_packed_begin struct bd_base { uint8_t type; /* This value identifies the type of buffer descriptor. */ #define BD_BASE_TYPE_MASK UINT32_C(0x3f) @@ -2684,10 +2684,10 @@ struct bd_base { #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11) #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE uint8_t unused_1[7]; -} __rte_packed; +} __rte_packed_end; /* tx_bd_short (size:128b/16B) */ -struct tx_bd_short { +__rte_packed_begin struct tx_bd_short { /* * All bits in this field must be valid on the first BD of a packet. * Only the packet_end bit must be valid for the remaining BDs @@ -2798,10 +2798,10 @@ struct tx_bd_short { * This value must be valid on all BDs of a packet. */ uint64_t address; -} __rte_packed; +} __rte_packed_end; /* tx_bd_long (size:128b/16B) */ -struct tx_bd_long { +__rte_packed_begin struct tx_bd_long { /* This value identifies the type of buffer descriptor. */ uint16_t flags_type; /* @@ -2910,11 +2910,11 @@ struct tx_bd_long { * This value must be valid on all BDs of a packet. */ uint64_t address; -} __rte_packed; +} __rte_packed_end; /* Last 16 bytes of tx_bd_long. */ /* tx_bd_long_hi (size:128b/16B) */ -struct tx_bd_long_hi { +__rte_packed_begin struct tx_bd_long_hi { /* * All bits in this field must be valid on the first BD of a packet. * Their value on other BDs of the packet will be ignored. @@ -3196,7 +3196,7 @@ struct tx_bd_long_hi { (UINT32_C(0x2) << 28) #define TX_BD_LONG_CFA_META_KEY_LAST \ TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER -} __rte_packed; +} __rte_packed_end; /* * This structure is used to inform the NIC of packet data that needs to @@ -3206,7 +3206,7 @@ struct tx_bd_long_hi { * the additional extended features supported by long BDs. */ /* tx_bd_long_inline (size:256b/32B) */ -struct tx_bd_long_inline { +__rte_packed_begin struct tx_bd_long_inline { uint16_t flags_type; /* This value identifies the type of buffer descriptor. */ #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f) @@ -3492,10 +3492,10 @@ struct tx_bd_long_inline { (UINT32_C(0x2) << 28) #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \ TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER -} __rte_packed; +} __rte_packed_end; /* tx_bd_empty (size:128b/16B) */ -struct tx_bd_empty { +__rte_packed_begin struct tx_bd_empty { /* This value identifies the type of buffer descriptor. */ uint8_t type; #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f) @@ -3510,10 +3510,10 @@ struct tx_bd_empty { uint8_t unused_2; uint8_t unused_3[3]; uint8_t unused_4[8]; -} __rte_packed; +} __rte_packed_end; /* tx_bd_mp_cmd (size:128b/16B) */ -struct tx_bd_mp_cmd { +__rte_packed_begin struct tx_bd_mp_cmd { /* Unless otherwise stated, sub-fields of this field are always valid. */ uint16_t flags_type; /* This value identifies the type of buffer descriptor. */ @@ -3549,10 +3549,10 @@ struct tx_bd_mp_cmd { */ uint32_t opaque; uint64_t unused1; -} __rte_packed; +} __rte_packed_end; /* tx_bd_presync_cmd (size:128b/16B) */ -struct tx_bd_presync_cmd { +__rte_packed_begin struct tx_bd_presync_cmd { /* Unless otherwise stated, sub-fields of this field are always valid. */ uint16_t flags_type; /* This value identifies the type of buffer descriptor. */ @@ -3601,7 +3601,7 @@ struct tx_bd_presync_cmd { #define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff) #define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0 uint32_t unused_1; -} __rte_packed; +} __rte_packed_end; /* * This structure is used to send additional information for transmitting @@ -3610,7 +3610,7 @@ struct tx_bd_presync_cmd { * BDs will follow the timed transmit BD. */ /* tx_bd_timedtx (size:128b/16B) */ -struct tx_bd_timedtx { +__rte_packed_begin struct tx_bd_timedtx { uint16_t flags_type; /* This value identifies the type of buffer descriptor. */ #define TX_BD_TIMEDTX_TYPE_MASK UINT32_C(0x3f) @@ -3686,10 +3686,10 @@ struct tx_bd_timedtx { * This field is applicable only if flags.kind is so_txtime. */ uint64_t tx_time; -} __rte_packed; +} __rte_packed_end; /* rx_prod_pkt_bd (size:128b/16B) */ -struct rx_prod_pkt_bd { +__rte_packed_begin struct rx_prod_pkt_bd { /* This value identifies the type of buffer descriptor. */ uint16_t flags_type; /* This value identifies the type of buffer descriptor. */ @@ -3746,10 +3746,10 @@ struct rx_prod_pkt_bd { * be placed in host memory. */ uint64_t address; -} __rte_packed; +} __rte_packed_end; /* rx_prod_bfr_bd (size:128b/16B) */ -struct rx_prod_bfr_bd { +__rte_packed_begin struct rx_prod_bfr_bd { /* This value identifies the type of buffer descriptor. */ uint16_t flags_type; /* This value identifies the type of buffer descriptor. */ @@ -3775,10 +3775,10 @@ struct rx_prod_bfr_bd { * be placed in host memory. */ uint64_t address; -} __rte_packed; +} __rte_packed_end; /* rx_prod_agg_bd (size:128b/16B) */ -struct rx_prod_agg_bd { +__rte_packed_begin struct rx_prod_agg_bd { /* This value identifies the type of buffer descriptor. */ uint16_t flags_type; /* This value identifies the type of buffer descriptor. */ @@ -3814,10 +3814,10 @@ struct rx_prod_agg_bd { * be placed in host memory. */ uint64_t address; -} __rte_packed; +} __rte_packed_end; /* cfa_cmpls_cmp_data_msg (size:128b/16B) */ -struct cfa_cmpls_cmp_data_msg { +__rte_packed_begin struct cfa_cmpls_cmp_data_msg { uint32_t mp_client_dma_length_opcode_status_type; /* * This field represents the Mid-Path client that generated the @@ -3996,38 +3996,38 @@ struct cfa_cmpls_cmp_data_msg { */ #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff) #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0 -} __rte_packed; +} __rte_packed_end; /* CFA Mid-Path 32B DMA Message */ /* cfa_dma32b_data_msg (size:256b/32B) */ -struct cfa_dma32b_data_msg { +__rte_packed_begin struct cfa_dma32b_data_msg { /* DMA data value. */ uint32_t dta[8]; -} __rte_packed; +} __rte_packed_end; /* CFA Mid-Path 64B DMA Message */ /* cfa_dma64b_data_msg (size:512b/64B) */ -struct cfa_dma64b_data_msg { +__rte_packed_begin struct cfa_dma64b_data_msg { /* DMA data value. */ uint32_t dta[16]; -} __rte_packed; +} __rte_packed_end; /* CFA Mid-Path 96B DMA Message */ /* cfa_dma96b_data_msg (size:768b/96B) */ -struct cfa_dma96b_data_msg { +__rte_packed_begin struct cfa_dma96b_data_msg { /* DMA data value. */ uint32_t dta[24]; -} __rte_packed; +} __rte_packed_end; /* CFA Mid-Path 128B DMA Message */ /* cfa_dma128b_data_msg (size:1024b/128B) */ -struct cfa_dma128b_data_msg { +__rte_packed_begin struct cfa_dma128b_data_msg { /* DMA data value. */ uint32_t dta[32]; -} __rte_packed; +} __rte_packed_end; /* ce_cmpls_cmp_data_msg (size:128b/16B) */ -struct ce_cmpls_cmp_data_msg { +__rte_packed_begin struct ce_cmpls_cmp_data_msg { uint16_t client_subtype_type; /* * This field indicates the exact type of the completion. By @@ -4117,10 +4117,10 @@ struct ce_cmpls_cmp_data_msg { #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 0 #define CE_CMPLS_CMP_DATA_MSG_UNUSED3_MASK UINT32_C(0xfff00000) #define CE_CMPLS_CMP_DATA_MSG_UNUSED3_SFT 20 -} __rte_packed; +} __rte_packed_end; /* cmpl_base (size:128b/16B) */ -struct cmpl_base { +__rte_packed_begin struct cmpl_base { uint16_t type; /* * This field indicates the exact type of the completion. @@ -4273,10 +4273,10 @@ struct cmpl_base { #define CMPL_BASE_INFO3_SFT 1 /* info4 is 32 b */ uint32_t info4; -} __rte_packed; +} __rte_packed_end; /* tx_cmpl (size:128b/16B) */ -struct tx_cmpl { +__rte_packed_begin struct tx_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -4392,10 +4392,10 @@ struct tx_cmpl { uint16_t unused_1; /* unused3 is 32 b */ uint32_t unused_2; -} __rte_packed; +} __rte_packed_end; /* tx_cmpl_coal (size:128b/16B) */ -struct tx_cmpl_coal { +__rte_packed_begin struct tx_cmpl_coal { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -4529,10 +4529,10 @@ struct tx_cmpl_coal { */ #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff) #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0 -} __rte_packed; +} __rte_packed_end; /* tx_cmpl_packet_timestamp (size:128b/16B) */ -struct tx_cmpl_packet_timestamp { +__rte_packed_begin struct tx_cmpl_packet_timestamp { uint16_t ts_sub_ns_flags_type; /* * This field indicates the exact type of the completion. By @@ -4709,10 +4709,10 @@ struct tx_cmpl_packet_timestamp { * PA for PA timestamps. This field is in units of ns. */ uint32_t ts_ns_lo; -} __rte_packed; +} __rte_packed_end; /* rx_pkt_cmpl (size:128b/16B) */ -struct rx_pkt_cmpl { +__rte_packed_begin struct rx_pkt_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -4926,11 +4926,11 @@ struct rx_pkt_cmpl { * based on the mode bits and key value in the VNIC. */ uint32_t rss_hash; -} __rte_packed; +} __rte_packed_end; /* Last 16 bytes of rx_pkt_cmpl. */ /* rx_pkt_cmpl_hi (size:128b/16B) */ -struct rx_pkt_cmpl_hi { +__rte_packed_begin struct rx_pkt_cmpl_hi { uint32_t flags2; /* * This indicates that the ip checksum was calculated for the @@ -5272,10 +5272,10 @@ struct rx_pkt_cmpl_hi { */ #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff) #define RX_PKT_CMPL_REORDER_SFT 0 -} __rte_packed; +} __rte_packed_end; /* rx_pkt_v2_cmpl (size:128b/16B) */ -struct rx_pkt_v2_cmpl { +__rte_packed_begin struct rx_pkt_v2_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -5534,11 +5534,11 @@ struct rx_pkt_v2_cmpl { * from the first BD used to place the packet. */ uint32_t rss_hash; -} __rte_packed; +} __rte_packed_end; /* Last 16 bytes of RX Packet V2 Completion Record */ /* rx_pkt_v2_cmpl_hi (size:128b/16B) */ -struct rx_pkt_v2_cmpl_hi { +__rte_packed_begin struct rx_pkt_v2_cmpl_hi { uint32_t flags2; /* * When this bit is '0', the cs_ok field has the following definition:- @@ -5937,10 +5937,10 @@ struct rx_pkt_v2_cmpl_hi { * the MAC. */ uint32_t timestamp; -} __rte_packed; +} __rte_packed_end; /* rx_pkt_v3_cmpl (size:128b/16B) */ -struct rx_pkt_v3_cmpl { +__rte_packed_begin struct rx_pkt_v3_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -6263,11 +6263,11 @@ struct rx_pkt_v3_cmpl { * from the first BD used to place the packet. */ uint32_t rss_hash; -} __rte_packed; +} __rte_packed_end; /* Last 16 bytes of RX Packet V3 Completion Record */ /* rx_pkt_v3_cmpl_hi (size:128b/16B) */ -struct rx_pkt_v3_cmpl_hi { +__rte_packed_begin struct rx_pkt_v3_cmpl_hi { uint32_t flags2; /* * This indicates that the ip checksum was calculated for the inner @@ -6623,10 +6623,10 @@ struct rx_pkt_v3_cmpl_hi { * host address from the first BD used to place the packet. */ uint32_t timestamp; -} __rte_packed; +} __rte_packed_end; /* rx_pkt_compress_cmpl (size:128b/16B) */ -struct rx_pkt_compress_cmpl { +__rte_packed_begin struct rx_pkt_compress_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -7031,14 +7031,14 @@ struct rx_pkt_compress_cmpl { UINT32_C(0xe0000000) #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_UNUSED1_SFT \ 29 -} __rte_packed; +} __rte_packed_end; /* * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ /* rx_tpa_start_cmpl (size:128b/16B) */ -struct rx_tpa_start_cmpl { +__rte_packed_begin struct rx_tpa_start_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -7196,7 +7196,7 @@ struct rx_tpa_start_cmpl { * based on the mode bits and key value in the VNIC. */ uint32_t rss_hash; -} __rte_packed; +} __rte_packed_end; /* * Last 16 bytes of rx_tpa_start_cmpl. @@ -7205,7 +7205,7 @@ struct rx_tpa_start_cmpl { * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ /* rx_tpa_start_cmpl_hi (size:128b/16B) */ -struct rx_tpa_start_cmpl_hi { +__rte_packed_begin struct rx_tpa_start_cmpl_hi { uint32_t flags2; /* * This indicates that the ip checksum was calculated for the @@ -7313,7 +7313,7 @@ struct rx_tpa_start_cmpl_hi { */ #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27 -} __rte_packed; +} __rte_packed_end; /* * This TPA completion structure is used on devices where the @@ -7322,7 +7322,7 @@ struct rx_tpa_start_cmpl_hi { * struct) */ /* rx_tpa_start_v2_cmpl (size:128b/16B) */ -struct rx_tpa_start_v2_cmpl { +__rte_packed_begin struct rx_tpa_start_v2_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -7549,7 +7549,7 @@ struct rx_tpa_start_v2_cmpl { * 32b of the host address from the first BD used to place the packet. */ uint32_t rss_hash; -} __rte_packed; +} __rte_packed_end; /* * Last 16 bytes of RX L2 TPA Start V2 Completion Record @@ -7558,7 +7558,7 @@ struct rx_tpa_start_v2_cmpl { * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ /* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */ -struct rx_tpa_start_v2_cmpl_hi { +__rte_packed_begin struct rx_tpa_start_v2_cmpl_hi { uint32_t flags2; /* This indicates that the aggregation was done using GRO rules. */ #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \ @@ -7760,7 +7760,7 @@ struct rx_tpa_start_v2_cmpl_hi { * hdr_offsets[31:27] contains the inner_l4_size. */ uint32_t hdr_offsets; -} __rte_packed; +} __rte_packed_end; /* * This TPA completion structure is used on devices where the @@ -7769,7 +7769,7 @@ struct rx_tpa_start_v2_cmpl_hi { * struct) */ /* rx_tpa_start_v3_cmpl (size:128b/16B) */ -struct rx_tpa_start_v3_cmpl { +__rte_packed_begin struct rx_tpa_start_v3_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -8016,7 +8016,7 @@ struct rx_tpa_start_v3_cmpl { * 32b of the host address from the first BD used to place the packet. */ uint32_t rss_hash; -} __rte_packed; +} __rte_packed_end; /* * Last 16 bytes of RX L2 TPA Start V3 Completion Record @@ -8025,7 +8025,7 @@ struct rx_tpa_start_v3_cmpl { * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ /* rx_tpa_start_v3_cmpl_hi (size:128b/16B) */ -struct rx_tpa_start_v3_cmpl_hi { +__rte_packed_begin struct rx_tpa_start_v3_cmpl_hi { uint32_t flags2; /* * This indicates that the ip checksum was calculated for the inner @@ -8241,14 +8241,14 @@ struct rx_tpa_start_v3_cmpl_hi { * hdr_offsets[31:27] contains the inner_l4_size. */ uint32_t hdr_offsets; -} __rte_packed; +} __rte_packed_end; /* * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ /* rx_tpa_end_cmpl (size:128b/16B) */ -struct rx_tpa_end_cmpl { +__rte_packed_begin struct rx_tpa_end_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -8425,7 +8425,7 @@ struct rx_tpa_end_cmpl { * option is present in the packet. */ uint32_t tsdelta; -} __rte_packed; +} __rte_packed_end; /* * Last 16 bytes of rx_tpa_end_cmpl. @@ -8434,7 +8434,7 @@ struct rx_tpa_end_cmpl { * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ /* rx_tpa_end_cmpl_hi (size:128b/16B) */ -struct rx_tpa_end_cmpl_hi { +__rte_packed_begin struct rx_tpa_end_cmpl_hi { uint32_t tpa_dup_acks; /* * This value is the number of duplicate ACKs that have been @@ -8507,14 +8507,14 @@ struct rx_tpa_end_cmpl_hi { * completion that corresponds to this TPA end completion. */ uint32_t start_opaque; -} __rte_packed; +} __rte_packed_end; /* * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. */ /* rx_tpa_v2_start_cmpl (size:128b/16B) */ -struct rx_tpa_v2_start_cmpl { +__rte_packed_begin struct rx_tpa_v2_start_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -8678,7 +8678,7 @@ struct rx_tpa_v2_start_cmpl { * based on the mode bits and key value in the VNIC. */ uint32_t rss_hash; -} __rte_packed; +} __rte_packed_end; /* * Last 16 bytes of rx_tpa_v2_start_cmpl. @@ -8687,7 +8687,7 @@ struct rx_tpa_v2_start_cmpl { * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. */ /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */ -struct rx_tpa_v2_start_cmpl_hi { +__rte_packed_begin struct rx_tpa_v2_start_cmpl_hi { uint32_t flags2; /* * This indicates that the ip checksum was calculated for the @@ -8893,14 +8893,14 @@ struct rx_tpa_v2_start_cmpl_hi { */ #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27 -} __rte_packed; +} __rte_packed_end; /* * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. */ /* rx_tpa_v2_end_cmpl (size:128b/16B) */ -struct rx_tpa_v2_end_cmpl { +__rte_packed_begin struct rx_tpa_v2_end_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -9049,7 +9049,7 @@ struct rx_tpa_v2_end_cmpl { * option is present in the packet. */ uint32_t tsdelta; -} __rte_packed; +} __rte_packed_end; /* * Last 16 bytes of rx_tpa_v2_end_cmpl. @@ -9058,7 +9058,7 @@ struct rx_tpa_v2_end_cmpl { * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. */ /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */ -struct rx_tpa_v2_end_cmpl_hi { +__rte_packed_begin struct rx_tpa_v2_end_cmpl_hi { /* * This value is the number of duplicate ACKs that have been * received as part of the TPA operation. @@ -9159,14 +9159,14 @@ struct rx_tpa_v2_end_cmpl_hi { * completion that corresponds to this TPA end completion. */ uint32_t start_opaque; -} __rte_packed; +} __rte_packed_end; /* * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. */ /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */ -struct rx_tpa_v2_abuf_cmpl { +__rte_packed_begin struct rx_tpa_v2_abuf_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -9213,10 +9213,10 @@ struct rx_tpa_v2_abuf_cmpl { */ uint16_t agg_id; uint32_t unused_1; -} __rte_packed; +} __rte_packed_end; /* rx_abuf_cmpl (size:128b/16B) */ -struct rx_abuf_cmpl { +__rte_packed_begin struct rx_abuf_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -9257,11 +9257,11 @@ struct rx_abuf_cmpl { #define RX_ABUF_CMPL_V UINT32_C(0x1) /* unused3 is 32 b */ uint32_t unused_2; -} __rte_packed; +} __rte_packed_end; /* VEE FLUSH Completion Record (16 bytes) */ /* vee_flush (size:128b/16B) */ -struct vee_flush { +__rte_packed_begin struct vee_flush { uint32_t downstream_path_type; /* * This field indicates the exact type of the completion. @@ -9303,10 +9303,10 @@ struct vee_flush { #define VEE_FLUSH_V UINT32_C(0x1) /* unused3 is 32 b */ uint32_t unused_3; -} __rte_packed; +} __rte_packed_end; /* eject_cmpl (size:128b/16B) */ -struct eject_cmpl { +__rte_packed_begin struct eject_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -9385,10 +9385,10 @@ struct eject_cmpl { uint16_t reserved16; /* unused3 is 32 b */ uint32_t unused_2; -} __rte_packed; +} __rte_packed_end; /* hwrm_cmpl (size:128b/16B) */ -struct hwrm_cmpl { +__rte_packed_begin struct hwrm_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -9418,10 +9418,10 @@ struct hwrm_cmpl { #define HWRM_CMPL_V UINT32_C(0x1) /* unused4 is 32 b */ uint32_t unused_3; -} __rte_packed; +} __rte_packed_end; /* hwrm_fwd_req_cmpl (size:128b/16B) */ -struct hwrm_fwd_req_cmpl { +__rte_packed_begin struct hwrm_fwd_req_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -9467,10 +9467,10 @@ struct hwrm_fwd_req_cmpl { /* Address of forwarded request. */ #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe) #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 -} __rte_packed; +} __rte_packed_end; /* hwrm_fwd_resp_cmpl (size:128b/16B) */ -struct hwrm_fwd_resp_cmpl { +__rte_packed_begin struct hwrm_fwd_resp_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -9508,10 +9508,10 @@ struct hwrm_fwd_resp_cmpl { /* Address of forwarded request. */ #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe) #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl (size:128b/16B) */ -struct hwrm_async_event_cmpl { +__rte_packed_begin struct hwrm_async_event_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -9784,10 +9784,10 @@ struct hwrm_async_event_cmpl { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_status_change { +__rte_packed_begin struct hwrm_async_event_cmpl_link_status_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -9863,10 +9863,10 @@ struct hwrm_async_event_cmpl_link_status_change { UINT32_C(0xff00000) #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \ 20 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_mtu_change { +__rte_packed_begin struct hwrm_async_event_cmpl_link_mtu_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -9913,10 +9913,10 @@ struct hwrm_async_event_cmpl_link_mtu_change { #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \ UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_speed_change { +__rte_packed_begin struct hwrm_async_event_cmpl_link_speed_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10008,10 +10008,10 @@ struct hwrm_async_event_cmpl_link_speed_change { UINT32_C(0xffff0000) #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \ 16 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_dcb_config_change { +__rte_packed_begin struct hwrm_async_event_cmpl_dcb_config_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10092,10 +10092,10 @@ struct hwrm_async_event_cmpl_dcb_config_change { (UINT32_C(0xff) << 24) #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \ HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ -struct hwrm_async_event_cmpl_port_conn_not_allowed { +__rte_packed_begin struct hwrm_async_event_cmpl_port_conn_not_allowed { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10168,10 +10168,10 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed { (UINT32_C(0x3) << 16) #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \ HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { +__rte_packed_begin struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10221,10 +10221,10 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_speed_cfg_change { +__rte_packed_begin struct hwrm_async_event_cmpl_link_speed_cfg_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10290,10 +10290,10 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \ UINT32_C(0x20000) -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_port_phy_cfg_change { +__rte_packed_begin struct hwrm_async_event_cmpl_port_phy_cfg_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10366,10 +10366,10 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \ UINT32_C(0x40000) -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ -struct hwrm_async_event_cmpl_reset_notify { +__rte_packed_begin struct hwrm_async_event_cmpl_reset_notify { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10488,10 +10488,10 @@ struct hwrm_async_event_cmpl_reset_notify { UINT32_C(0xffff0000) #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \ 16 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ -struct hwrm_async_event_cmpl_error_recovery { +__rte_packed_begin struct hwrm_async_event_cmpl_error_recovery { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10557,10 +10557,10 @@ struct hwrm_async_event_cmpl_error_recovery { */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \ UINT32_C(0x2) -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ -struct hwrm_async_event_cmpl_ring_monitor_msg { +__rte_packed_begin struct hwrm_async_event_cmpl_ring_monitor_msg { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10622,10 +10622,10 @@ struct hwrm_async_event_cmpl_ring_monitor_msg { * then this field will indicate the ring id. */ uint32_t event_data1; -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */ -struct hwrm_async_event_cmpl_func_drvr_unload { +__rte_packed_begin struct hwrm_async_event_cmpl_func_drvr_unload { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10673,10 +10673,10 @@ struct hwrm_async_event_cmpl_func_drvr_unload { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \ 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */ -struct hwrm_async_event_cmpl_func_drvr_load { +__rte_packed_begin struct hwrm_async_event_cmpl_func_drvr_load { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10722,10 +10722,10 @@ struct hwrm_async_event_cmpl_func_drvr_load { #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */ -struct hwrm_async_event_cmpl_func_flr_proc_cmplt { +__rte_packed_begin struct hwrm_async_event_cmpl_func_flr_proc_cmplt { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10775,10 +10775,10 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \ 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */ -struct hwrm_async_event_cmpl_pf_drvr_unload { +__rte_packed_begin struct hwrm_async_event_cmpl_pf_drvr_unload { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10828,10 +10828,10 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \ UINT32_C(0x70000) #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */ -struct hwrm_async_event_cmpl_pf_drvr_load { +__rte_packed_begin struct hwrm_async_event_cmpl_pf_drvr_load { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10881,10 +10881,10 @@ struct hwrm_async_event_cmpl_pf_drvr_load { #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \ UINT32_C(0x70000) #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */ -struct hwrm_async_event_cmpl_vf_flr { +__rte_packed_begin struct hwrm_async_event_cmpl_vf_flr { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10933,10 +10933,10 @@ struct hwrm_async_event_cmpl_vf_flr { #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \ UINT32_C(0xff0000) #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_vf_mac_addr_change { +__rte_packed_begin struct hwrm_async_event_cmpl_vf_mac_addr_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -10985,10 +10985,10 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \ 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_pf_vf_comm_status_change { +__rte_packed_begin struct hwrm_async_event_cmpl_pf_vf_comm_status_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11041,10 +11041,10 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { */ #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \ UINT32_C(0x1) -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_vf_cfg_change { +__rte_packed_begin struct hwrm_async_event_cmpl_vf_cfg_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11145,10 +11145,10 @@ struct hwrm_async_event_cmpl_vf_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE \ UINT32_C(0x20) -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_llfc_pfc_change { +__rte_packed_begin struct hwrm_async_event_cmpl_llfc_pfc_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11224,10 +11224,10 @@ struct hwrm_async_event_cmpl_llfc_pfc_change { UINT32_C(0x1fffe0) #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \ 5 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_default_vnic_change { +__rte_packed_begin struct hwrm_async_event_cmpl_default_vnic_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11306,10 +11306,10 @@ struct hwrm_async_event_cmpl_default_vnic_change { UINT32_C(0x3fffc00) #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \ 10 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ -struct hwrm_async_event_cmpl_hw_flow_aged { +__rte_packed_begin struct hwrm_async_event_cmpl_hw_flow_aged { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11373,10 +11373,10 @@ struct hwrm_async_event_cmpl_hw_flow_aged { (UINT32_C(0x1) << 31) #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_cache_flush_req { +__rte_packed_begin struct hwrm_async_event_cmpl_eem_cache_flush_req { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11421,10 +11421,10 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_cache_flush_done { +__rte_packed_begin struct hwrm_async_event_cmpl_eem_cache_flush_done { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11477,10 +11477,10 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \ 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_tcp_flag_action_change { +__rte_packed_begin struct hwrm_async_event_cmpl_tcp_flag_action_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11525,10 +11525,10 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_flow_active { +__rte_packed_begin struct hwrm_async_event_cmpl_eem_flow_active { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11625,10 +11625,10 @@ struct hwrm_async_event_cmpl_eem_flow_active { (UINT32_C(0x1) << 31) #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_cfg_change { +__rte_packed_begin struct hwrm_async_event_cmpl_eem_cfg_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11682,10 +11682,10 @@ struct hwrm_async_event_cmpl_eem_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \ UINT32_C(0x2) -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */ -struct hwrm_async_event_cmpl_quiesce_done { +__rte_packed_begin struct hwrm_async_event_cmpl_quiesce_done { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11785,10 +11785,10 @@ struct hwrm_async_event_cmpl_quiesce_done { /* Time stamp for error event */ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \ UINT32_C(0x1) -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ -struct hwrm_async_event_cmpl_deferred_response { +__rte_packed_begin struct hwrm_async_event_cmpl_deferred_response { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11846,10 +11846,10 @@ struct hwrm_async_event_cmpl_deferred_response { uint16_t timestamp_hi; /* Estimated remaining time of command execution in ms (if not zero) */ uint32_t event_data1; -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { +__rte_packed_begin struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11931,10 +11931,10 @@ struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { UINT32_C(0xffff00) #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ 8 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ -struct hwrm_async_event_cmpl_echo_request { +__rte_packed_begin struct hwrm_async_event_cmpl_echo_request { uint16_t type; /* * This field indicates the exact type of the completion. @@ -11979,10 +11979,10 @@ struct hwrm_async_event_cmpl_echo_request { uint16_t timestamp_hi; /* Event specific data that should be provided in the echo response */ uint32_t event_data1; -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ -struct hwrm_async_event_cmpl_phc_update { +__rte_packed_begin struct hwrm_async_event_cmpl_phc_update { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12078,10 +12078,10 @@ struct hwrm_async_event_cmpl_phc_update { UINT32_C(0xffff0) #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT \ 4 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ -struct hwrm_async_event_cmpl_pps_timestamp { +__rte_packed_begin struct hwrm_async_event_cmpl_pps_timestamp { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12162,10 +12162,10 @@ struct hwrm_async_event_cmpl_pps_timestamp { UINT32_C(0xffffffff) #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT \ 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ -struct hwrm_async_event_cmpl_error_report { +__rte_packed_begin struct hwrm_async_event_cmpl_error_report { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12218,10 +12218,10 @@ struct hwrm_async_event_cmpl_error_report { #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK \ UINT32_C(0xff) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_doorbell_pacing_threshold (size:128b/16B) */ -struct hwrm_async_event_cmpl_doorbell_pacing_threshold { +__rte_packed_begin struct hwrm_async_event_cmpl_doorbell_pacing_threshold { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12271,10 +12271,10 @@ struct hwrm_async_event_cmpl_doorbell_pacing_threshold { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_rss_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_rss_change { +__rte_packed_begin struct hwrm_async_event_cmpl_rss_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12320,10 +12320,10 @@ struct hwrm_async_event_cmpl_rss_change { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_doorbell_pacing_nq_update (size:128b/16B) */ -struct hwrm_async_event_cmpl_doorbell_pacing_nq_update { +__rte_packed_begin struct hwrm_async_event_cmpl_doorbell_pacing_nq_update { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12373,10 +12373,10 @@ struct hwrm_async_event_cmpl_doorbell_pacing_nq_update { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_hw_doorbell_recovery_read_error (size:128b/16B) */ -struct hwrm_async_event_cmpl_hw_doorbell_recovery_read_error { +__rte_packed_begin struct hwrm_async_event_cmpl_hw_doorbell_recovery_read_error { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12460,10 +12460,10 @@ struct hwrm_async_event_cmpl_hw_doorbell_recovery_read_error { */ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_CQ_ERR \ UINT32_C(0x8) -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_ctx_error (size:128b/16B) */ -struct hwrm_async_event_cmpl_ctx_error { +__rte_packed_begin struct hwrm_async_event_cmpl_ctx_error { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12534,10 +12534,10 @@ struct hwrm_async_event_cmpl_ctx_error { #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_MASK \ UINT32_C(0xffffffff) #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_SFT 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_udcc_session_change (size:128b/16B) */ -struct hwrm_async_event_udcc_session_change { +__rte_packed_begin struct hwrm_async_event_udcc_session_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12600,10 +12600,10 @@ struct hwrm_async_event_udcc_session_change { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_SFT \ 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_dbg_buf_producer (size:128b/16B) */ -struct hwrm_async_event_cmpl_dbg_buf_producer { +__rte_packed_begin struct hwrm_async_event_cmpl_dbg_buf_producer { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12690,10 +12690,10 @@ struct hwrm_async_event_cmpl_dbg_buf_producer { UINT32_C(0x6) #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST \ HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ -struct hwrm_async_event_cmpl_fw_trace_msg { +__rte_packed_begin struct hwrm_async_event_cmpl_fw_trace_msg { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12797,10 +12797,10 @@ struct hwrm_async_event_cmpl_fw_trace_msg { #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \ UINT32_C(0xff000000) #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ -struct hwrm_async_event_cmpl_hwrm_error { +__rte_packed_begin struct hwrm_async_event_cmpl_hwrm_error { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12860,10 +12860,10 @@ struct hwrm_async_event_cmpl_hwrm_error { /* Time stamp for error event */ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \ UINT32_C(0x1) -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ -struct hwrm_async_event_cmpl_error_report_base { +__rte_packed_begin struct hwrm_async_event_cmpl_error_report_base { uint16_t type; /* * This field indicates the exact type of the completion. @@ -12961,10 +12961,10 @@ struct hwrm_async_event_cmpl_error_report_base { UINT32_C(0x6) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ -struct hwrm_async_event_cmpl_error_report_pause_storm { +__rte_packed_begin struct hwrm_async_event_cmpl_error_report_pause_storm { uint16_t type; /* * This field indicates the exact type of the completion. @@ -13026,10 +13026,10 @@ struct hwrm_async_event_cmpl_error_report_pause_storm { UINT32_C(0x1) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ -struct hwrm_async_event_cmpl_error_report_invalid_signal { +__rte_packed_begin struct hwrm_async_event_cmpl_error_report_invalid_signal { uint16_t type; /* * This field indicates the exact type of the completion. @@ -13099,10 +13099,10 @@ struct hwrm_async_event_cmpl_error_report_invalid_signal { UINT32_C(0x2) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ -struct hwrm_async_event_cmpl_error_report_nvm { +__rte_packed_begin struct hwrm_async_event_cmpl_error_report_nvm { uint16_t type; /* * This field indicates the exact type of the completion. @@ -13188,10 +13188,10 @@ struct hwrm_async_event_cmpl_error_report_nvm { (UINT32_C(0x2) << 8) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ -struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { +__rte_packed_begin struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { uint16_t type; /* * This field indicates the exact type of the completion. @@ -13263,10 +13263,10 @@ struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { UINT32_C(0xffffff00) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT \ 8 -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */ -struct hwrm_async_event_cmpl_error_report_thermal { +__rte_packed_begin struct hwrm_async_event_cmpl_error_report_thermal { uint16_t type; /* * This field indicates the exact type of the completion. @@ -13382,10 +13382,10 @@ struct hwrm_async_event_cmpl_error_report_thermal { (UINT32_C(0x1) << 11) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING -} __rte_packed; +} __rte_packed_end; /* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */ -struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { +__rte_packed_begin struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { uint16_t type; /* * This field indicates the exact type of the completion. @@ -13448,10 +13448,10 @@ struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { UINT32_C(0x6) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED -} __rte_packed; +} __rte_packed_end; /* metadata_base_msg (size:64b/8B) */ -struct metadata_base_msg { +__rte_packed_begin struct metadata_base_msg { uint16_t md_type_link; /* This field classifies the data present in the meta-data. */ #define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f) @@ -13489,10 +13489,10 @@ struct metadata_base_msg { #define METADATA_BASE_MSG_LINK_SFT 5 uint16_t unused0; uint32_t unused1; -} __rte_packed; +} __rte_packed_end; /* tls_metadata_base_msg (size:64b/8B) */ -struct tls_metadata_base_msg { +__rte_packed_begin struct tls_metadata_base_msg { uint32_t md_type_link_flags_kid_lo; /* This field classifies the data present in the meta-data. */ #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \ @@ -13659,10 +13659,10 @@ struct tls_metadata_base_msg { #define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff) #define TLS_METADATA_BASE_MSG_KID_HI_SFT 0 uint16_t unused0; -} __rte_packed; +} __rte_packed_end; /* tls_metadata_insync_msg (size:192b/24B) */ -struct tls_metadata_insync_msg { +__rte_packed_begin struct tls_metadata_insync_msg { uint32_t md_type_link_flags_kid_lo; /* This field classifies the data present in the meta-data. */ #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \ @@ -13847,10 +13847,10 @@ struct tls_metadata_insync_msg { * only sent out with packet having the TAG field. */ uint8_t partial_ghash[8]; -} __rte_packed; +} __rte_packed_end; /* tls_metadata_resync_msg (size:256b/32B) */ -struct tls_metadata_resync_msg { +__rte_packed_begin struct tls_metadata_resync_msg { uint32_t md_type_link_flags_kid_lo; /* This field classifies the data present in the meta-data. */ #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \ @@ -13998,7 +13998,7 @@ struct tls_metadata_resync_msg { uint64_t metadata_2; /* This field is unused in this context. */ uint64_t metadata_3; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_func_reset * @@ -14006,7 +14006,7 @@ struct tls_metadata_resync_msg { /* hwrm_func_reset_input (size:192b/24B) */ -struct hwrm_func_reset_input { +__rte_packed_begin struct hwrm_func_reset_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -14081,10 +14081,10 @@ struct hwrm_func_reset_input { #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \ HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF uint8_t unused_0; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_reset_output (size:128b/16B) */ -struct hwrm_func_reset_output { +__rte_packed_begin struct hwrm_func_reset_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -14102,7 +14102,7 @@ struct hwrm_func_reset_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************** * hwrm_func_getfid * @@ -14110,7 +14110,7 @@ struct hwrm_func_reset_output { /* hwrm_func_getfid_input (size:192b/24B) */ -struct hwrm_func_getfid_input { +__rte_packed_begin struct hwrm_func_getfid_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -14153,10 +14153,10 @@ struct hwrm_func_getfid_input { */ uint16_t pci_id; uint8_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_getfid_output (size:128b/16B) */ -struct hwrm_func_getfid_output { +__rte_packed_begin struct hwrm_func_getfid_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -14179,7 +14179,7 @@ struct hwrm_func_getfid_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_func_vf_alloc * @@ -14187,7 +14187,7 @@ struct hwrm_func_getfid_output { /* hwrm_func_vf_alloc_input (size:192b/24B) */ -struct hwrm_func_vf_alloc_input { +__rte_packed_begin struct hwrm_func_vf_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -14229,10 +14229,10 @@ struct hwrm_func_vf_alloc_input { uint16_t first_vf_id; /* The number of virtual functions requested. */ uint16_t num_vfs; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_vf_alloc_output (size:128b/16B) */ -struct hwrm_func_vf_alloc_output { +__rte_packed_begin struct hwrm_func_vf_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -14252,7 +14252,7 @@ struct hwrm_func_vf_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_func_vf_free * @@ -14260,7 +14260,7 @@ struct hwrm_func_vf_alloc_output { /* hwrm_func_vf_free_input (size:192b/24B) */ -struct hwrm_func_vf_free_input { +__rte_packed_begin struct hwrm_func_vf_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -14305,10 +14305,10 @@ struct hwrm_func_vf_free_input { * 0xFFFF - Cleanup all children of this PF. */ uint16_t num_vfs; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_vf_free_output (size:128b/16B) */ -struct hwrm_func_vf_free_output { +__rte_packed_begin struct hwrm_func_vf_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -14326,7 +14326,7 @@ struct hwrm_func_vf_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************** * hwrm_func_vf_cfg * @@ -14334,7 +14334,7 @@ struct hwrm_func_vf_free_output { /* hwrm_func_vf_cfg_input (size:576b/72B) */ -struct hwrm_func_vf_cfg_input { +__rte_packed_begin struct hwrm_func_vf_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -14620,10 +14620,10 @@ struct hwrm_func_vf_cfg_input { uint32_t num_quic_tx_key_ctxs; /* Number of QUIC Rx Key Contexts requested. */ uint32_t num_quic_rx_key_ctxs; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_vf_cfg_output (size:128b/16B) */ -struct hwrm_func_vf_cfg_output { +__rte_packed_begin struct hwrm_func_vf_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -14641,7 +14641,7 @@ struct hwrm_func_vf_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_func_qcaps * @@ -14649,7 +14649,7 @@ struct hwrm_func_vf_cfg_output { /* hwrm_func_qcaps_input (size:192b/24B) */ -struct hwrm_func_qcaps_input { +__rte_packed_begin struct hwrm_func_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -14687,10 +14687,10 @@ struct hwrm_func_qcaps_input { */ uint16_t fid; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_qcaps_output (size:1088b/136B) */ -struct hwrm_func_qcaps_output { +__rte_packed_begin struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -15666,7 +15666,7 @@ struct hwrm_func_qcaps_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************** * hwrm_func_qcfg * @@ -15674,7 +15674,7 @@ struct hwrm_func_qcaps_output { /* hwrm_func_qcfg_input (size:192b/24B) */ -struct hwrm_func_qcfg_input { +__rte_packed_begin struct hwrm_func_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -15712,10 +15712,10 @@ struct hwrm_func_qcfg_input { */ uint16_t fid; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_qcfg_output (size:1280b/160B) */ -struct hwrm_func_qcfg_output { +__rte_packed_begin struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -16465,7 +16465,7 @@ struct hwrm_func_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************** * hwrm_func_cfg * @@ -16473,7 +16473,7 @@ struct hwrm_func_qcfg_output { /* hwrm_func_cfg_input (size:1280b/160B) */ -struct hwrm_func_cfg_input { +__rte_packed_begin struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17555,10 +17555,10 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_RX_CK UINT32_C(0x2) uint16_t unused_2; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_cfg_output (size:128b/16B) */ -struct hwrm_func_cfg_output { +__rte_packed_begin struct hwrm_func_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -17576,10 +17576,10 @@ struct hwrm_func_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_cfg_cmd_err (size:64b/8B) */ -struct hwrm_func_cfg_cmd_err { +__rte_packed_begin struct hwrm_func_cfg_cmd_err { /* command specific error codes for the cmd_err field in hwrm_err_output */ uint8_t code; /* Unknown error. */ @@ -17603,7 +17603,7 @@ struct hwrm_func_cfg_cmd_err { #define HWRM_FUNC_CFG_CMD_ERR_CODE_LAST \ HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /******************** * hwrm_func_qstats * @@ -17611,7 +17611,7 @@ struct hwrm_func_cfg_cmd_err { /* hwrm_func_qstats_input (size:192b/24B) */ -struct hwrm_func_qstats_input { +__rte_packed_begin struct hwrm_func_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17669,10 +17669,10 @@ struct hwrm_func_qstats_input { */ #define HWRM_FUNC_QSTATS_INPUT_FLAGS_L2_ONLY UINT32_C(0x4) uint8_t unused_0[5]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_qstats_output (size:1408b/176B) */ -struct hwrm_func_qstats_output { +__rte_packed_begin struct hwrm_func_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -17762,7 +17762,7 @@ struct hwrm_func_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_func_qstats_ext * @@ -17770,7 +17770,7 @@ struct hwrm_func_qstats_output { /* hwrm_func_qstats_ext_input (size:256b/32B) */ -struct hwrm_func_qstats_ext_input { +__rte_packed_begin struct hwrm_func_qstats_ext_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17836,10 +17836,10 @@ struct hwrm_func_qstats_ext_input { */ uint16_t traffic_class; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_qstats_ext_output (size:1536b/192B) */ -struct hwrm_func_qstats_ext_output { +__rte_packed_begin struct hwrm_func_qstats_ext_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -17901,7 +17901,7 @@ struct hwrm_func_qstats_ext_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_func_clr_stats * @@ -17909,7 +17909,7 @@ struct hwrm_func_qstats_ext_output { /* hwrm_func_clr_stats_input (size:192b/24B) */ -struct hwrm_func_clr_stats_input { +__rte_packed_begin struct hwrm_func_clr_stats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17945,10 +17945,10 @@ struct hwrm_func_clr_stats_input { */ uint16_t fid; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_clr_stats_output (size:128b/16B) */ -struct hwrm_func_clr_stats_output { +__rte_packed_begin struct hwrm_func_clr_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -17966,7 +17966,7 @@ struct hwrm_func_clr_stats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_func_vf_resc_free * @@ -17974,7 +17974,7 @@ struct hwrm_func_clr_stats_output { /* hwrm_func_vf_resc_free_input (size:192b/24B) */ -struct hwrm_func_vf_resc_free_input { +__rte_packed_begin struct hwrm_func_vf_resc_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18009,10 +18009,10 @@ struct hwrm_func_vf_resc_free_input { */ uint16_t vf_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_vf_resc_free_output (size:128b/16B) */ -struct hwrm_func_vf_resc_free_output { +__rte_packed_begin struct hwrm_func_vf_resc_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18030,7 +18030,7 @@ struct hwrm_func_vf_resc_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_func_drv_rgtr * @@ -18038,7 +18038,7 @@ struct hwrm_func_vf_resc_free_output { /* hwrm_func_drv_rgtr_input (size:896b/112B) */ -struct hwrm_func_drv_rgtr_input { +__rte_packed_begin struct hwrm_func_drv_rgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18305,10 +18305,10 @@ struct hwrm_func_drv_rgtr_input { uint16_t ver_upd; /* This is the 16bit patch version of the driver. */ uint16_t ver_patch; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_drv_rgtr_output (size:128b/16B) */ -struct hwrm_func_drv_rgtr_output { +__rte_packed_begin struct hwrm_func_drv_rgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18333,7 +18333,7 @@ struct hwrm_func_drv_rgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_func_drv_unrgtr * @@ -18341,7 +18341,7 @@ struct hwrm_func_drv_rgtr_output { /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ -struct hwrm_func_drv_unrgtr_input { +__rte_packed_begin struct hwrm_func_drv_unrgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18378,10 +18378,10 @@ struct hwrm_func_drv_unrgtr_input { #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \ UINT32_C(0x1) uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ -struct hwrm_func_drv_unrgtr_output { +__rte_packed_begin struct hwrm_func_drv_unrgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18399,7 +18399,7 @@ struct hwrm_func_drv_unrgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_func_buf_rgtr * @@ -18407,7 +18407,7 @@ struct hwrm_func_drv_unrgtr_output { /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ -struct hwrm_func_buf_rgtr_input { +__rte_packed_begin struct hwrm_func_buf_rgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18513,10 +18513,10 @@ struct hwrm_func_buf_rgtr_input { * HWRM. */ uint64_t resp_buf_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_buf_rgtr_output (size:128b/16B) */ -struct hwrm_func_buf_rgtr_output { +__rte_packed_begin struct hwrm_func_buf_rgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18534,7 +18534,7 @@ struct hwrm_func_buf_rgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_func_buf_unrgtr * @@ -18542,7 +18542,7 @@ struct hwrm_func_buf_rgtr_output { /* hwrm_func_buf_unrgtr_input (size:192b/24B) */ -struct hwrm_func_buf_unrgtr_input { +__rte_packed_begin struct hwrm_func_buf_unrgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18583,10 +18583,10 @@ struct hwrm_func_buf_unrgtr_input { */ uint16_t vf_id; uint8_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_buf_unrgtr_output (size:128b/16B) */ -struct hwrm_func_buf_unrgtr_output { +__rte_packed_begin struct hwrm_func_buf_unrgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18604,7 +18604,7 @@ struct hwrm_func_buf_unrgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_func_drv_qver * @@ -18612,7 +18612,7 @@ struct hwrm_func_buf_unrgtr_output { /* hwrm_func_drv_qver_input (size:192b/24B) */ -struct hwrm_func_drv_qver_input { +__rte_packed_begin struct hwrm_func_drv_qver_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18661,10 +18661,10 @@ struct hwrm_func_drv_qver_input { #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_LAST \ HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_ROCE uint8_t unused_0; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_drv_qver_output (size:256b/32B) */ -struct hwrm_func_drv_qver_output { +__rte_packed_begin struct hwrm_func_drv_qver_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18726,7 +18726,7 @@ struct hwrm_func_drv_qver_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_func_resource_qcaps * @@ -18734,7 +18734,7 @@ struct hwrm_func_drv_qver_output { /* hwrm_func_resource_qcaps_input (size:192b/24B) */ -struct hwrm_func_resource_qcaps_input { +__rte_packed_begin struct hwrm_func_resource_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18770,10 +18770,10 @@ struct hwrm_func_resource_qcaps_input { */ uint16_t fid; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_resource_qcaps_output (size:704b/88B) */ -struct hwrm_func_resource_qcaps_output { +__rte_packed_begin struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18884,7 +18884,7 @@ struct hwrm_func_resource_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_func_vf_resource_cfg * @@ -18892,7 +18892,7 @@ struct hwrm_func_resource_qcaps_output { /* hwrm_func_vf_resource_cfg_input (size:704b/88B) */ -struct hwrm_func_vf_resource_cfg_input { +__rte_packed_begin struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18983,10 +18983,10 @@ struct hwrm_func_vf_resource_cfg_input { uint32_t min_quic_rx_key_ctxs; /* Maximum non-guaranteed number of QUIC Rx Key Contexts */ uint32_t max_quic_rx_key_ctxs; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_vf_resource_cfg_output (size:384b/48B) */ -struct hwrm_func_vf_resource_cfg_output { +__rte_packed_begin struct hwrm_func_vf_resource_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -19028,7 +19028,7 @@ struct hwrm_func_vf_resource_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************* * hwrm_func_backing_store_qcaps * @@ -19036,7 +19036,7 @@ struct hwrm_func_vf_resource_cfg_output { /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ -struct hwrm_func_backing_store_qcaps_input { +__rte_packed_begin struct hwrm_func_backing_store_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19065,10 +19065,10 @@ struct hwrm_func_backing_store_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ -struct hwrm_func_backing_store_qcaps_output { +__rte_packed_begin struct hwrm_func_backing_store_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -19327,10 +19327,10 @@ struct hwrm_func_backing_store_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* tqm_fp_ring_cfg (size:128b/16B) */ -struct tqm_fp_ring_cfg { +__rte_packed_begin struct tqm_fp_ring_cfg { /* TQM ring page size and level. */ uint8_t tqm_ring_pg_size_tqm_ring_lvl; /* TQM ring PBL indirect levels. */ @@ -19380,7 +19380,7 @@ struct tqm_fp_ring_cfg { uint32_t tqm_ring_num_entries; /* TQM ring page directory. */ uint64_t tqm_ring_page_dir; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_func_backing_store_cfg * @@ -19388,7 +19388,7 @@ struct tqm_fp_ring_cfg { /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ -struct hwrm_func_backing_store_cfg_input { +__rte_packed_begin struct hwrm_func_backing_store_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -20736,10 +20736,10 @@ struct hwrm_func_backing_store_cfg_input { * function to support fast QP modify destroy feature. */ uint16_t qp_num_fast_qpmd_entries; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ -struct hwrm_func_backing_store_cfg_output { +__rte_packed_begin struct hwrm_func_backing_store_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -20757,7 +20757,7 @@ struct hwrm_func_backing_store_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************** * hwrm_func_backing_store_qcfg * @@ -20765,7 +20765,7 @@ struct hwrm_func_backing_store_cfg_output { /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */ -struct hwrm_func_backing_store_qcfg_input { +__rte_packed_begin struct hwrm_func_backing_store_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -20794,10 +20794,10 @@ struct hwrm_func_backing_store_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_backing_store_qcfg_output (size:2496b/312B) */ -struct hwrm_func_backing_store_qcfg_output { +__rte_packed_begin struct hwrm_func_backing_store_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22009,7 +22009,7 @@ struct hwrm_func_backing_store_qcfg_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_error_recovery_qcfg * @@ -22017,7 +22017,7 @@ struct hwrm_func_backing_store_qcfg_output { /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ -struct hwrm_error_recovery_qcfg_input { +__rte_packed_begin struct hwrm_error_recovery_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22047,10 +22047,10 @@ struct hwrm_error_recovery_qcfg_input { */ uint64_t resp_addr; uint8_t unused_0[8]; -} __rte_packed; +} __rte_packed_end; /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ -struct hwrm_error_recovery_qcfg_output { +__rte_packed_begin struct hwrm_error_recovery_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22423,7 +22423,7 @@ struct hwrm_error_recovery_qcfg_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_func_echo_response * @@ -22431,7 +22431,7 @@ struct hwrm_error_recovery_qcfg_output { /* hwrm_func_echo_response_input (size:192b/24B) */ -struct hwrm_func_echo_response_input { +__rte_packed_begin struct hwrm_func_echo_response_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22462,10 +22462,10 @@ struct hwrm_func_echo_response_input { uint64_t resp_addr; uint32_t event_data1; uint32_t event_data2; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_echo_response_output (size:128b/16B) */ -struct hwrm_func_echo_response_output { +__rte_packed_begin struct hwrm_func_echo_response_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22483,7 +22483,7 @@ struct hwrm_func_echo_response_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_func_ptp_pin_qcfg * @@ -22491,7 +22491,7 @@ struct hwrm_func_echo_response_output { /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ -struct hwrm_func_ptp_pin_qcfg_input { +__rte_packed_begin struct hwrm_func_ptp_pin_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22521,10 +22521,10 @@ struct hwrm_func_ptp_pin_qcfg_input { */ uint64_t resp_addr; uint8_t unused_0[8]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ -struct hwrm_func_ptp_pin_qcfg_output { +__rte_packed_begin struct hwrm_func_ptp_pin_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22651,7 +22651,7 @@ struct hwrm_func_ptp_pin_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_func_ptp_pin_cfg * @@ -22659,7 +22659,7 @@ struct hwrm_func_ptp_pin_qcfg_output { /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ -struct hwrm_func_ptp_pin_cfg_input { +__rte_packed_begin struct hwrm_func_ptp_pin_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22848,10 +22848,10 @@ struct hwrm_func_ptp_pin_cfg_input { #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ -struct hwrm_func_ptp_pin_cfg_output { +__rte_packed_begin struct hwrm_func_ptp_pin_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22869,7 +22869,7 @@ struct hwrm_func_ptp_pin_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_func_ptp_cfg * @@ -22877,7 +22877,7 @@ struct hwrm_func_ptp_pin_cfg_output { /* hwrm_func_ptp_cfg_input (size:384b/48B) */ -struct hwrm_func_ptp_cfg_input { +__rte_packed_begin struct hwrm_func_ptp_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23056,10 +23056,10 @@ struct hwrm_func_ptp_cfg_input { * to indicate the programmed upper 16 bits. */ uint64_t ptp_set_time; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_ptp_cfg_output (size:128b/16B) */ -struct hwrm_func_ptp_cfg_output { +__rte_packed_begin struct hwrm_func_ptp_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23077,7 +23077,7 @@ struct hwrm_func_ptp_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_func_ptp_ts_query * @@ -23085,7 +23085,7 @@ struct hwrm_func_ptp_cfg_output { /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ -struct hwrm_func_ptp_ts_query_input { +__rte_packed_begin struct hwrm_func_ptp_ts_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23120,10 +23120,10 @@ struct hwrm_func_ptp_ts_query_input { /* If set, the response includes PTM timestamps */ #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2) uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ -struct hwrm_func_ptp_ts_query_output { +__rte_packed_begin struct hwrm_func_ptp_ts_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23162,7 +23162,7 @@ struct hwrm_func_ptp_ts_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_func_ptp_ext_cfg * @@ -23170,7 +23170,7 @@ struct hwrm_func_ptp_ts_query_output { /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ -struct hwrm_func_ptp_ext_cfg_input { +__rte_packed_begin struct hwrm_func_ptp_ext_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23288,10 +23288,10 @@ struct hwrm_func_ptp_ext_cfg_input { */ uint32_t failover_timer; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ -struct hwrm_func_ptp_ext_cfg_output { +__rte_packed_begin struct hwrm_func_ptp_ext_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23309,7 +23309,7 @@ struct hwrm_func_ptp_ext_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_func_ptp_ext_qcfg * @@ -23317,7 +23317,7 @@ struct hwrm_func_ptp_ext_cfg_output { /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ -struct hwrm_func_ptp_ext_qcfg_input { +__rte_packed_begin struct hwrm_func_ptp_ext_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23347,10 +23347,10 @@ struct hwrm_func_ptp_ext_qcfg_input { */ uint64_t resp_addr; uint8_t unused_0[8]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ -struct hwrm_func_ptp_ext_qcfg_output { +__rte_packed_begin struct hwrm_func_ptp_ext_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23404,7 +23404,7 @@ struct hwrm_func_ptp_ext_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_func_key_ctx_alloc * @@ -23412,7 +23412,7 @@ struct hwrm_func_ptp_ext_qcfg_output { /* hwrm_func_key_ctx_alloc_input (size:384b/48B) */ -struct hwrm_func_key_ctx_alloc_input { +__rte_packed_begin struct hwrm_func_key_ctx_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23496,10 +23496,10 @@ struct hwrm_func_key_ctx_alloc_input { */ uint32_t partition_start_xid; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_key_ctx_alloc_output (size:192b/24B) */ -struct hwrm_func_key_ctx_alloc_output { +__rte_packed_begin struct hwrm_func_key_ctx_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23537,7 +23537,7 @@ struct hwrm_func_key_ctx_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_func_key_ctx_free * @@ -23545,7 +23545,7 @@ struct hwrm_func_key_ctx_alloc_output { /* hwrm_func_key_ctx_free_input (size:256b/32B) */ -struct hwrm_func_key_ctx_free_input { +__rte_packed_begin struct hwrm_func_key_ctx_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23602,10 +23602,10 @@ struct hwrm_func_key_ctx_free_input { */ uint16_t num_entries; uint8_t unused_1[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_key_ctx_free_output (size:128b/16B) */ -struct hwrm_func_key_ctx_free_output { +__rte_packed_begin struct hwrm_func_key_ctx_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23624,7 +23624,7 @@ struct hwrm_func_key_ctx_free_output { * that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************** * hwrm_func_backing_store_cfg_v2 * @@ -23632,7 +23632,7 @@ struct hwrm_func_key_ctx_free_output { /* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */ -struct hwrm_func_backing_store_cfg_v2_input { +__rte_packed_begin struct hwrm_func_backing_store_cfg_v2_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23877,10 +23877,10 @@ struct hwrm_func_backing_store_cfg_v2_input { uint32_t split_entry_2; /* Split entry #3. */ uint32_t split_entry_3; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ -struct hwrm_func_backing_store_cfg_v2_output { +__rte_packed_begin struct hwrm_func_backing_store_cfg_v2_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23899,7 +23899,7 @@ struct hwrm_func_backing_store_cfg_v2_output { * that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************************** * hwrm_func_backing_store_qcfg_v2 * @@ -23907,7 +23907,7 @@ struct hwrm_func_backing_store_cfg_v2_output { /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ -struct hwrm_func_backing_store_qcfg_v2_input { +__rte_packed_begin struct hwrm_func_backing_store_qcfg_v2_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24034,10 +24034,10 @@ struct hwrm_func_backing_store_qcfg_v2_input { */ uint16_t instance; uint8_t rsvd[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ -struct hwrm_func_backing_store_qcfg_v2_output { +__rte_packed_begin struct hwrm_func_backing_store_qcfg_v2_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24226,7 +24226,7 @@ struct hwrm_func_backing_store_qcfg_v2_output { * that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* Common structure to cast QPC split entries. This casting is required in the * following HWRM command inputs/outputs if the backing store type is QPC. @@ -24235,7 +24235,7 @@ struct hwrm_func_backing_store_qcfg_v2_output { * 3. hwrm_func_backing_store_qcaps_v2_output */ /* qpc_split_entries (size:128b/16B) */ -struct qpc_split_entries { +__rte_packed_begin struct qpc_split_entries { /* Number of L2 QP backing store entries. */ uint32_t qp_num_l2_entries; /* Number of QP1 entries. */ @@ -24246,7 +24246,7 @@ struct qpc_split_entries { */ uint32_t qp_num_fast_qpmd_entries; uint32_t rsvd; -} __rte_packed; +} __rte_packed_end; /* Common structure to cast SRQ split entries. This casting is required in the * following HWRM command inputs/outputs if the backing store type is SRQ. @@ -24255,12 +24255,12 @@ struct qpc_split_entries { * 3. hwrm_func_backing_store_qcaps_v2_output */ /* srq_split_entries (size:128b/16B) */ -struct srq_split_entries { +__rte_packed_begin struct srq_split_entries { /* Number of L2 SRQ backing store entries. */ uint32_t srq_num_l2_entries; uint32_t rsvd; uint32_t rsvd2[2]; -} __rte_packed; +} __rte_packed_end; /* Common structure to cast CQ split entries. This casting is required in the * following HWRM command inputs/outputs if the backing store type is CQ. @@ -24269,12 +24269,12 @@ struct srq_split_entries { * 3. hwrm_func_backing_store_qcaps_v2_output */ /* cq_split_entries (size:128b/16B) */ -struct cq_split_entries { +__rte_packed_begin struct cq_split_entries { /* Number of L2 CQ backing store entries. */ uint32_t cq_num_l2_entries; uint32_t rsvd; uint32_t rsvd2[2]; -} __rte_packed; +} __rte_packed_end; /* Common structure to cast VNIC split entries. This casting is required in the * following HWRM command inputs/outputs if the backing store type is VNIC. @@ -24283,12 +24283,12 @@ struct cq_split_entries { * 3. hwrm_func_backing_store_qcaps_v2_output */ /* vnic_split_entries (size:128b/16B) */ -struct vnic_split_entries { +__rte_packed_begin struct vnic_split_entries { /* Number of VNIC backing store entries. */ uint32_t vnic_num_vnic_entries; uint32_t rsvd; uint32_t rsvd2[2]; -} __rte_packed; +} __rte_packed_end; /* Common structure to cast MRAV split entries. This casting is required in the * following HWRM command inputs/outputs if the backing store type is MRAV. @@ -24297,12 +24297,12 @@ struct vnic_split_entries { * 3. hwrm_func_backing_store_qcaps_v2_output */ /* mrav_split_entries (size:128b/16B) */ -struct mrav_split_entries { +__rte_packed_begin struct mrav_split_entries { /* Number of AV backing store entries. */ uint32_t mrav_num_av_entries; uint32_t rsvd; uint32_t rsvd2[2]; -} __rte_packed; +} __rte_packed_end; /* Common structure to cast TBL_SCOPE split entries. This casting is required * in the following HWRM command inputs/outputs if the backing store type is @@ -24312,7 +24312,7 @@ struct mrav_split_entries { * 3. hwrm_func_backing_store_qcaps_v2_output */ /* ts_split_entries (size:128b/16B) */ -struct ts_split_entries { +__rte_packed_begin struct ts_split_entries { /* Max number of TBL_SCOPE region entries (QCAPS). */ uint32_t region_num_entries; /* tsid to configure (CFG). */ @@ -24324,7 +24324,7 @@ struct ts_split_entries { uint8_t lkup_static_bkt_cnt_exp[2]; uint8_t rsvd; uint32_t rsvd2[2]; -} __rte_packed; +} __rte_packed_end; /* Common structure to cast crypto key split entries. This casting is required * in the following HWRM command inputs/outputs if the backing store type is @@ -24334,7 +24334,7 @@ struct ts_split_entries { * 3. hwrm_func_backing_store_qcaps_v2_output */ /* ck_split_entries (size:128b/16B) */ -struct ck_split_entries { +__rte_packed_begin struct ck_split_entries { /* * Number of QUIC backing store entries. That means the number of KTLS * backing store entries is the difference between this number and the @@ -24343,7 +24343,7 @@ struct ck_split_entries { uint32_t num_quic_entries; uint32_t rsvd; uint32_t rsvd2[2]; -} __rte_packed; +} __rte_packed_end; /************************************ * hwrm_func_backing_store_qcaps_v2 * @@ -24351,7 +24351,7 @@ struct ck_split_entries { /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ -struct hwrm_func_backing_store_qcaps_v2_input { +__rte_packed_begin struct hwrm_func_backing_store_qcaps_v2_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24463,10 +24463,10 @@ struct hwrm_func_backing_store_qcaps_v2_input { #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_LAST \ HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID uint8_t rsvd[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ -struct hwrm_func_backing_store_qcaps_v2_output { +__rte_packed_begin struct hwrm_func_backing_store_qcaps_v2_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24721,7 +24721,7 @@ struct hwrm_func_backing_store_qcaps_v2_output { * that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_func_dbr_pacing_cfg * @@ -24729,7 +24729,7 @@ struct hwrm_func_backing_store_qcaps_v2_output { /* hwrm_func_dbr_pacing_cfg_input (size:320b/40B) */ -struct hwrm_func_dbr_pacing_cfg_input { +__rte_packed_begin struct hwrm_func_dbr_pacing_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24794,10 +24794,10 @@ struct hwrm_func_dbr_pacing_cfg_input { */ uint32_t pacing_threshold; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_dbr_pacing_cfg_output (size:128b/16B) */ -struct hwrm_func_dbr_pacing_cfg_output { +__rte_packed_begin struct hwrm_func_dbr_pacing_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24816,7 +24816,7 @@ struct hwrm_func_dbr_pacing_cfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_func_dbr_pacing_qcfg * @@ -24824,7 +24824,7 @@ struct hwrm_func_dbr_pacing_cfg_output { /* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */ -struct hwrm_func_dbr_pacing_qcfg_input { +__rte_packed_begin struct hwrm_func_dbr_pacing_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24853,10 +24853,10 @@ struct hwrm_func_dbr_pacing_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */ -struct hwrm_func_dbr_pacing_qcfg_output { +__rte_packed_begin struct hwrm_func_dbr_pacing_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25020,7 +25020,7 @@ struct hwrm_func_dbr_pacing_qcfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************************** * hwrm_func_dbr_pacing_broadcast_event * @@ -25028,7 +25028,7 @@ struct hwrm_func_dbr_pacing_qcfg_output { /* hwrm_func_dbr_pacing_broadcast_event_input (size:128b/16B) */ -struct hwrm_func_dbr_pacing_broadcast_event_input { +__rte_packed_begin struct hwrm_func_dbr_pacing_broadcast_event_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25057,10 +25057,10 @@ struct hwrm_func_dbr_pacing_broadcast_event_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_dbr_pacing_broadcast_event_output (size:128b/16B) */ -struct hwrm_func_dbr_pacing_broadcast_event_output { +__rte_packed_begin struct hwrm_func_dbr_pacing_broadcast_event_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25079,7 +25079,7 @@ struct hwrm_func_dbr_pacing_broadcast_event_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************************* * hwrm_func_dbr_pacing_nqlist_query * @@ -25087,7 +25087,7 @@ struct hwrm_func_dbr_pacing_broadcast_event_output { /* hwrm_func_dbr_pacing_nqlist_query_input (size:128b/16B) */ -struct hwrm_func_dbr_pacing_nqlist_query_input { +__rte_packed_begin struct hwrm_func_dbr_pacing_nqlist_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25116,10 +25116,10 @@ struct hwrm_func_dbr_pacing_nqlist_query_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_dbr_pacing_nqlist_query_output (size:384b/48B) */ -struct hwrm_func_dbr_pacing_nqlist_query_output { +__rte_packed_begin struct hwrm_func_dbr_pacing_nqlist_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25171,7 +25171,7 @@ struct hwrm_func_dbr_pacing_nqlist_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************************ * hwrm_func_dbr_recovery_completed * @@ -25179,7 +25179,7 @@ struct hwrm_func_dbr_pacing_nqlist_query_output { /* hwrm_func_dbr_recovery_completed_input (size:192b/24B) */ -struct hwrm_func_dbr_recovery_completed_input { +__rte_packed_begin struct hwrm_func_dbr_recovery_completed_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25219,10 +25219,10 @@ struct hwrm_func_dbr_recovery_completed_input { UINT32_C(0xffffff) #define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_SFT 0 uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_dbr_recovery_completed_output (size:128b/16B) */ -struct hwrm_func_dbr_recovery_completed_output { +__rte_packed_begin struct hwrm_func_dbr_recovery_completed_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25241,7 +25241,7 @@ struct hwrm_func_dbr_recovery_completed_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_func_synce_cfg * @@ -25249,7 +25249,7 @@ struct hwrm_func_dbr_recovery_completed_output { /* hwrm_func_synce_cfg_input (size:192b/24B) */ -struct hwrm_func_synce_cfg_input { +__rte_packed_begin struct hwrm_func_synce_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25332,10 +25332,10 @@ struct hwrm_func_synce_cfg_input { #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_LAST \ HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_synce_cfg_output (size:128b/16B) */ -struct hwrm_func_synce_cfg_output { +__rte_packed_begin struct hwrm_func_synce_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25353,7 +25353,7 @@ struct hwrm_func_synce_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_func_synce_qcfg * @@ -25361,7 +25361,7 @@ struct hwrm_func_synce_cfg_output { /* hwrm_func_synce_qcfg_input (size:192b/24B) */ -struct hwrm_func_synce_qcfg_input { +__rte_packed_begin struct hwrm_func_synce_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25391,10 +25391,10 @@ struct hwrm_func_synce_qcfg_input { */ uint64_t resp_addr; uint8_t unused_0[8]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_synce_qcfg_output (size:128b/16B) */ -struct hwrm_func_synce_qcfg_output { +__rte_packed_begin struct hwrm_func_synce_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25436,7 +25436,7 @@ struct hwrm_func_synce_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_func_lag_create * @@ -25444,7 +25444,7 @@ struct hwrm_func_synce_qcfg_output { /* hwrm_func_lag_create_input (size:192b/24B) */ -struct hwrm_func_lag_create_input { +__rte_packed_begin struct hwrm_func_lag_create_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25577,10 +25577,10 @@ struct hwrm_func_lag_create_input { #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_LAST \ HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_802_3_AD uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_lag_create_output (size:128b/16B) */ -struct hwrm_func_lag_create_output { +__rte_packed_begin struct hwrm_func_lag_create_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25603,7 +25603,7 @@ struct hwrm_func_lag_create_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_func_lag_update * @@ -25611,7 +25611,7 @@ struct hwrm_func_lag_create_output { /* hwrm_func_lag_update_input (size:192b/24B) */ -struct hwrm_func_lag_update_input { +__rte_packed_begin struct hwrm_func_lag_update_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25746,10 +25746,10 @@ struct hwrm_func_lag_update_input { #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_LAST \ HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_802_3_AD uint8_t unused_0[3]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_lag_update_output (size:128b/16B) */ -struct hwrm_func_lag_update_output { +__rte_packed_begin struct hwrm_func_lag_update_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25767,7 +25767,7 @@ struct hwrm_func_lag_update_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_func_lag_free * @@ -25775,7 +25775,7 @@ struct hwrm_func_lag_update_output { /* hwrm_func_lag_free_input (size:192b/24B) */ -struct hwrm_func_lag_free_input { +__rte_packed_begin struct hwrm_func_lag_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25807,10 +25807,10 @@ struct hwrm_func_lag_free_input { /* Link aggregation group ID of the LAG to be freed. */ uint8_t fw_lag_id; uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_lag_free_output (size:128b/16B) */ -struct hwrm_func_lag_free_output { +__rte_packed_begin struct hwrm_func_lag_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25828,7 +25828,7 @@ struct hwrm_func_lag_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_func_lag_qcfg * @@ -25836,7 +25836,7 @@ struct hwrm_func_lag_free_output { /* hwrm_func_lag_qcfg_input (size:192b/24B) */ -struct hwrm_func_lag_qcfg_input { +__rte_packed_begin struct hwrm_func_lag_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25868,10 +25868,10 @@ struct hwrm_func_lag_qcfg_input { /* Link aggregation group ID of the LAG to be queried. */ uint8_t fw_lag_id; uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_lag_qcfg_output (size:128b/16B) */ -struct hwrm_func_lag_qcfg_output { +__rte_packed_begin struct hwrm_func_lag_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25968,7 +25968,7 @@ struct hwrm_func_lag_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_func_lag_mode_cfg * @@ -25976,7 +25976,7 @@ struct hwrm_func_lag_qcfg_output { /* hwrm_func_lag_mode_cfg_input (size:192b/24B) */ -struct hwrm_func_lag_mode_cfg_input { +__rte_packed_begin struct hwrm_func_lag_mode_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26139,10 +26139,10 @@ struct hwrm_func_lag_mode_cfg_input { /* Link aggregation group idx being used. */ uint8_t lag_id; uint8_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_lag_mode_cfg_output (size:128b/16B) */ -struct hwrm_func_lag_mode_cfg_output { +__rte_packed_begin struct hwrm_func_lag_mode_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26162,7 +26162,7 @@ struct hwrm_func_lag_mode_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_func_lag_mode_qcfg * @@ -26170,7 +26170,7 @@ struct hwrm_func_lag_mode_cfg_output { /* hwrm_func_lag_mode_qcfg_input (size:192b/24B) */ -struct hwrm_func_lag_mode_qcfg_input { +__rte_packed_begin struct hwrm_func_lag_mode_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26200,10 +26200,10 @@ struct hwrm_func_lag_mode_qcfg_input { */ uint64_t resp_addr; uint8_t unused_0[8]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_lag_mode_qcfg_output (size:128b/16B) */ -struct hwrm_func_lag_mode_qcfg_output { +__rte_packed_begin struct hwrm_func_lag_mode_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26315,7 +26315,7 @@ struct hwrm_func_lag_mode_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_func_vlan_qcfg * @@ -26323,7 +26323,7 @@ struct hwrm_func_lag_mode_qcfg_output { /* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { +__rte_packed_begin struct hwrm_func_vlan_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26360,10 +26360,10 @@ struct hwrm_func_vlan_qcfg_input { */ uint16_t fid; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { +__rte_packed_begin struct hwrm_func_vlan_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26406,7 +26406,7 @@ struct hwrm_func_vlan_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_func_vlan_cfg * @@ -26414,7 +26414,7 @@ struct hwrm_func_vlan_qcfg_output { /* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { +__rte_packed_begin struct hwrm_func_vlan_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26507,10 +26507,10 @@ struct hwrm_func_vlan_cfg_input { /* Future use. */ uint32_t rsvd2; uint8_t unused_3[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_vlan_cfg_output (size:128b/16B) */ -struct hwrm_func_vlan_cfg_output { +__rte_packed_begin struct hwrm_func_vlan_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26528,7 +26528,7 @@ struct hwrm_func_vlan_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_func_vf_vnic_ids_query * @@ -26536,7 +26536,7 @@ struct hwrm_func_vlan_cfg_output { /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ -struct hwrm_func_vf_vnic_ids_query_input { +__rte_packed_begin struct hwrm_func_vf_vnic_ids_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26575,10 +26575,10 @@ struct hwrm_func_vf_vnic_ids_query_input { uint32_t max_vnic_id_cnt; /* This is the address for VF VNIC ID table */ uint64_t vnic_id_tbl_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ -struct hwrm_func_vf_vnic_ids_query_output { +__rte_packed_begin struct hwrm_func_vf_vnic_ids_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26602,7 +26602,7 @@ struct hwrm_func_vf_vnic_ids_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_func_vf_bw_cfg * @@ -26610,7 +26610,7 @@ struct hwrm_func_vf_vnic_ids_query_output { /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */ -struct hwrm_func_vf_bw_cfg_input { +__rte_packed_begin struct hwrm_func_vf_bw_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26706,10 +26706,10 @@ struct hwrm_func_vf_bw_cfg_input { (UINT32_C(0xf) << 12) #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \ HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 -} __rte_packed; +} __rte_packed_end; /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */ -struct hwrm_func_vf_bw_cfg_output { +__rte_packed_begin struct hwrm_func_vf_bw_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26727,7 +26727,7 @@ struct hwrm_func_vf_bw_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_func_vf_bw_qcfg * @@ -26735,7 +26735,7 @@ struct hwrm_func_vf_bw_cfg_output { /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */ -struct hwrm_func_vf_bw_qcfg_input { +__rte_packed_begin struct hwrm_func_vf_bw_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26776,10 +26776,10 @@ struct hwrm_func_vf_bw_qcfg_input { /* The physical VF id of interest */ #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff) #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0 -} __rte_packed; +} __rte_packed_end; /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */ -struct hwrm_func_vf_bw_qcfg_output { +__rte_packed_begin struct hwrm_func_vf_bw_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26865,7 +26865,7 @@ struct hwrm_func_vf_bw_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_func_drv_if_change * @@ -26873,7 +26873,7 @@ struct hwrm_func_vf_bw_qcfg_output { /* hwrm_func_drv_if_change_input (size:192b/24B) */ -struct hwrm_func_drv_if_change_input { +__rte_packed_begin struct hwrm_func_drv_if_change_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26918,10 +26918,10 @@ struct hwrm_func_drv_if_change_input { */ #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1) uint32_t unused; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_drv_if_change_output (size:128b/16B) */ -struct hwrm_func_drv_if_change_output { +__rte_packed_begin struct hwrm_func_drv_if_change_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26965,7 +26965,7 @@ struct hwrm_func_drv_if_change_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_func_host_pf_ids_query * @@ -26973,7 +26973,7 @@ struct hwrm_func_drv_if_change_output { /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */ -struct hwrm_func_host_pf_ids_query_input { +__rte_packed_begin struct hwrm_func_host_pf_ids_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27051,10 +27051,10 @@ struct hwrm_func_host_pf_ids_query_input { #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \ HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE uint8_t unused_1[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */ -struct hwrm_func_host_pf_ids_query_output { +__rte_packed_begin struct hwrm_func_host_pf_ids_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27171,7 +27171,7 @@ struct hwrm_func_host_pf_ids_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_func_spd_cfg * @@ -27179,7 +27179,7 @@ struct hwrm_func_host_pf_ids_query_output { /* hwrm_func_spd_cfg_input (size:384b/48B) */ -struct hwrm_func_spd_cfg_input { +__rte_packed_begin struct hwrm_func_spd_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27355,10 +27355,10 @@ struct hwrm_func_spd_cfg_input { uint64_t ring_grp_tbl_addr; /* This is the address for rss hash key table */ uint64_t hash_key_tbl_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_spd_cfg_output (size:128b/16B) */ -struct hwrm_func_spd_cfg_output { +__rte_packed_begin struct hwrm_func_spd_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27376,7 +27376,7 @@ struct hwrm_func_spd_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_func_spd_qcfg * @@ -27384,7 +27384,7 @@ struct hwrm_func_spd_cfg_output { /* hwrm_func_spd_qcfg_input (size:128b/16B) */ -struct hwrm_func_spd_qcfg_input { +__rte_packed_begin struct hwrm_func_spd_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27413,10 +27413,10 @@ struct hwrm_func_spd_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_func_spd_qcfg_output (size:512b/64B) */ -struct hwrm_func_spd_qcfg_output { +__rte_packed_begin struct hwrm_func_spd_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27539,7 +27539,7 @@ struct hwrm_func_spd_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_port_phy_cfg * @@ -27547,7 +27547,7 @@ struct hwrm_func_spd_qcfg_output { /* hwrm_port_phy_cfg_input (size:512b/64B) */ -struct hwrm_port_phy_cfg_input { +__rte_packed_begin struct hwrm_port_phy_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28360,10 +28360,10 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 \ UINT32_C(0x2000) uint8_t unused_2[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_phy_cfg_output (size:128b/16B) */ -struct hwrm_port_phy_cfg_output { +__rte_packed_begin struct hwrm_port_phy_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28381,10 +28381,10 @@ struct hwrm_port_phy_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ -struct hwrm_port_phy_cfg_cmd_err { +__rte_packed_begin struct hwrm_port_phy_cfg_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -28410,7 +28410,7 @@ struct hwrm_port_phy_cfg_cmd_err { #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \ HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_port_phy_qcfg * @@ -28418,7 +28418,7 @@ struct hwrm_port_phy_cfg_cmd_err { /* hwrm_port_phy_qcfg_input (size:192b/24B) */ -struct hwrm_port_phy_qcfg_input { +__rte_packed_begin struct hwrm_port_phy_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28450,10 +28450,10 @@ struct hwrm_port_phy_qcfg_input { /* Port ID of port that is to be queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_phy_qcfg_output (size:832b/104B) */ -struct hwrm_port_phy_qcfg_output { +__rte_packed_begin struct hwrm_port_phy_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29754,7 +29754,7 @@ struct hwrm_port_phy_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_port_mac_cfg * @@ -29762,7 +29762,7 @@ struct hwrm_port_phy_qcfg_output { /* hwrm_port_mac_cfg_input (size:448b/56B) */ -struct hwrm_port_mac_cfg_input { +__rte_packed_begin struct hwrm_port_mac_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30209,10 +30209,10 @@ struct hwrm_port_mac_cfg_input { * nanoseconds. */ int64_t ptp_adj_phase; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_mac_cfg_output (size:128b/16B) */ -struct hwrm_port_mac_cfg_output { +__rte_packed_begin struct hwrm_port_mac_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30263,7 +30263,7 @@ struct hwrm_port_mac_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_port_mac_qcfg * @@ -30271,7 +30271,7 @@ struct hwrm_port_mac_cfg_output { /* hwrm_port_mac_qcfg_input (size:192b/24B) */ -struct hwrm_port_mac_qcfg_input { +__rte_packed_begin struct hwrm_port_mac_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30303,10 +30303,10 @@ struct hwrm_port_mac_qcfg_input { /* Port ID of port that is to be configured. */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_mac_qcfg_output (size:256b/32B) */ -struct hwrm_port_mac_qcfg_output { +__rte_packed_begin struct hwrm_port_mac_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30586,7 +30586,7 @@ struct hwrm_port_mac_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_port_mac_ptp_qcfg * @@ -30594,7 +30594,7 @@ struct hwrm_port_mac_qcfg_output { /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ -struct hwrm_port_mac_ptp_qcfg_input { +__rte_packed_begin struct hwrm_port_mac_ptp_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30626,10 +30626,10 @@ struct hwrm_port_mac_ptp_qcfg_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ -struct hwrm_port_mac_ptp_qcfg_output { +__rte_packed_begin struct hwrm_port_mac_ptp_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30736,11 +30736,11 @@ struct hwrm_port_mac_ptp_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* Port Tx Statistics Format */ /* tx_port_stats (size:3264b/408B) */ -struct tx_port_stats { +__rte_packed_begin struct tx_port_stats { /* Total Number of 64 Bytes frames transmitted */ uint64_t tx_64b_frames; /* Total Number of 65-127 Bytes frames transmitted */ @@ -30877,11 +30877,11 @@ struct tx_port_stats { uint64_t tx_stat_discard; /* Total Tx Error Drops per Port reported by STATS block */ uint64_t tx_stat_error; -} __rte_packed; +} __rte_packed_end; /* Port Rx Statistics Format */ /* rx_port_stats (size:4224b/528B) */ -struct rx_port_stats { +__rte_packed_begin struct rx_port_stats { /* Total Number of 64 Bytes frames received */ uint64_t rx_64b_frames; /* Total Number of 65-127 Bytes frames received */ @@ -31092,7 +31092,7 @@ struct rx_port_stats { /* Total Rx Discards per Port reported by STATS block */ uint64_t rx_stat_discard; uint64_t rx_stat_err; -} __rte_packed; +} __rte_packed_end; /******************** * hwrm_port_qstats * @@ -31100,7 +31100,7 @@ struct rx_port_stats { /* hwrm_port_qstats_input (size:320b/40B) */ -struct hwrm_port_qstats_input { +__rte_packed_begin struct hwrm_port_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31149,10 +31149,10 @@ struct hwrm_port_qstats_input { * Rx port statistics will be stored */ uint64_t rx_stat_host_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_qstats_output (size:128b/16B) */ -struct hwrm_port_qstats_output { +__rte_packed_begin struct hwrm_port_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31174,11 +31174,11 @@ struct hwrm_port_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* Port Tx Statistics extended Format */ /* tx_port_stats_ext (size:2048b/256B) */ -struct tx_port_stats_ext { +__rte_packed_begin struct tx_port_stats_ext { /* Total number of tx bytes count on cos queue 0 */ uint64_t tx_bytes_cos0; /* Total number of tx bytes count on cos queue 1 */ @@ -31291,11 +31291,11 @@ struct tx_port_stats_ext { * priority 7 */ uint64_t pfc_pri7_tx_transitions; -} __rte_packed; +} __rte_packed_end; /* Port Rx Statistics extended Format */ /* rx_port_stats_ext (size:3904b/488B) */ -struct rx_port_stats_ext { +__rte_packed_begin struct rx_port_stats_ext { /* Number of times link state changed to down */ uint64_t link_down_events; /* Number of times the idle rings with pause bit are found */ @@ -31487,7 +31487,7 @@ struct rx_port_stats_ext { * codeword gets corrected. */ uint64_t rx_fec_symbol_err; -} __rte_packed; +} __rte_packed_end; /* * Port Rx Statistics extended PFC WatchDog Format. @@ -31504,7 +31504,7 @@ struct rx_port_stats_ext { * hwrm_queue_pfc_enable_cfg call. */ /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */ -struct rx_port_stats_ext_pfc_wd { +__rte_packed_begin struct rx_port_stats_ext_pfc_wd { /* * Total number of PFC WatchDog StormDetect events detected * for Pri 0 @@ -31905,7 +31905,7 @@ struct rx_port_stats_ext_pfc_wd { * for pri 7 */ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_port_qstats_ext * @@ -31913,7 +31913,7 @@ struct rx_port_stats_ext_pfc_wd { /* hwrm_port_qstats_ext_input (size:320b/40B) */ -struct hwrm_port_qstats_ext_input { +__rte_packed_begin struct hwrm_port_qstats_ext_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31972,10 +31972,10 @@ struct hwrm_port_qstats_ext_input { * Rx port statistics will be stored */ uint64_t rx_stat_host_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_qstats_ext_output (size:128b/16B) */ -struct hwrm_port_qstats_ext_output { +__rte_packed_begin struct hwrm_port_qstats_ext_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32005,7 +32005,7 @@ struct hwrm_port_qstats_ext_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_port_qstats_ext_pfc_wd * @@ -32013,7 +32013,7 @@ struct hwrm_port_qstats_ext_output { /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */ -struct hwrm_port_qstats_ext_pfc_wd_input { +__rte_packed_begin struct hwrm_port_qstats_ext_pfc_wd_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -32055,10 +32055,10 @@ struct hwrm_port_qstats_ext_pfc_wd_input { * rx_port_stats_ext_pfc_wd will be stored */ uint64_t pfc_wd_stat_host_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */ -struct hwrm_port_qstats_ext_pfc_wd_output { +__rte_packed_begin struct hwrm_port_qstats_ext_pfc_wd_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32081,7 +32081,7 @@ struct hwrm_port_qstats_ext_pfc_wd_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_port_lpbk_qstats * @@ -32089,7 +32089,7 @@ struct hwrm_port_qstats_ext_pfc_wd_output { /* hwrm_port_lpbk_qstats_input (size:256b/32B) */ -struct hwrm_port_lpbk_qstats_input { +__rte_packed_begin struct hwrm_port_lpbk_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -32140,10 +32140,10 @@ struct hwrm_port_lpbk_qstats_input { * loopback statistics will be stored */ uint64_t lpbk_stat_host_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_lpbk_qstats_output (size:128b/16B) */ -struct hwrm_port_lpbk_qstats_output { +__rte_packed_begin struct hwrm_port_lpbk_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32169,11 +32169,11 @@ struct hwrm_port_lpbk_qstats_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* Loopback Port Statistic Format */ /* port_lpbk_stats (size:640b/80B) */ -struct port_lpbk_stats { +__rte_packed_begin struct port_lpbk_stats { /* Number of transmitted unicast frames */ uint64_t lpbk_ucast_frames; /* Number of transmitted multicast frames */ @@ -32194,7 +32194,7 @@ struct port_lpbk_stats { uint64_t lpbk_rx_discards; /* Number of error dropped rx packets */ uint64_t lpbk_rx_errors; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_port_ecn_qstats * @@ -32202,7 +32202,7 @@ struct port_lpbk_stats { /* hwrm_port_ecn_qstats_input (size:256b/32B) */ -struct hwrm_port_ecn_qstats_input { +__rte_packed_begin struct hwrm_port_ecn_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -32254,10 +32254,10 @@ struct hwrm_port_ecn_qstats_input { * ECN port statistics will be stored */ uint64_t ecn_stat_host_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_ecn_qstats_output (size:128b/16B) */ -struct hwrm_port_ecn_qstats_output { +__rte_packed_begin struct hwrm_port_ecn_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32282,11 +32282,11 @@ struct hwrm_port_ecn_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* ECN mark statistics format */ /* port_stats_ecn (size:512b/64B) */ -struct port_stats_ecn { +__rte_packed_begin struct port_stats_ecn { /* * Number of packets marked in CoS queue 0. * Or, if the driver requested counter masks, a mask to indicate the size @@ -32335,7 +32335,7 @@ struct port_stats_ecn { * of the counter. */ uint64_t mark_cnt_cos7; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_port_clr_stats * @@ -32343,7 +32343,7 @@ struct port_stats_ecn { /* hwrm_port_clr_stats_input (size:192b/24B) */ -struct hwrm_port_clr_stats_input { +__rte_packed_begin struct hwrm_port_clr_stats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -32387,10 +32387,10 @@ struct hwrm_port_clr_stats_input { */ #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1) uint8_t unused_0[5]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_clr_stats_output (size:128b/16B) */ -struct hwrm_port_clr_stats_output { +__rte_packed_begin struct hwrm_port_clr_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32408,7 +32408,7 @@ struct hwrm_port_clr_stats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_port_lpbk_clr_stats * @@ -32416,7 +32416,7 @@ struct hwrm_port_clr_stats_output { /* hwrm_port_lpbk_clr_stats_input (size:192b/24B) */ -struct hwrm_port_lpbk_clr_stats_input { +__rte_packed_begin struct hwrm_port_lpbk_clr_stats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -32448,10 +32448,10 @@ struct hwrm_port_lpbk_clr_stats_input { /* Port ID of port that is to be queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ -struct hwrm_port_lpbk_clr_stats_output { +__rte_packed_begin struct hwrm_port_lpbk_clr_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32469,7 +32469,7 @@ struct hwrm_port_lpbk_clr_stats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_port_phy_qcaps * @@ -32477,7 +32477,7 @@ struct hwrm_port_lpbk_clr_stats_output { /* hwrm_port_phy_qcaps_input (size:192b/24B) */ -struct hwrm_port_phy_qcaps_input { +__rte_packed_begin struct hwrm_port_phy_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -32509,10 +32509,10 @@ struct hwrm_port_phy_qcaps_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_phy_qcaps_output (size:320b/40B) */ -struct hwrm_port_phy_qcaps_output { +__rte_packed_begin struct hwrm_port_phy_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32926,7 +32926,7 @@ struct hwrm_port_phy_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_port_phy_mdio_write * @@ -32934,7 +32934,7 @@ struct hwrm_port_phy_qcaps_output { /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ -struct hwrm_port_phy_mdio_write_input { +__rte_packed_begin struct hwrm_port_phy_mdio_write_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -32982,10 +32982,10 @@ struct hwrm_port_phy_mdio_write_input { uint8_t cl45_mdio; /* */ uint8_t unused_1[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ -struct hwrm_port_phy_mdio_write_output { +__rte_packed_begin struct hwrm_port_phy_mdio_write_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -33003,7 +33003,7 @@ struct hwrm_port_phy_mdio_write_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_port_phy_mdio_read * @@ -33011,7 +33011,7 @@ struct hwrm_port_phy_mdio_write_output { /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ -struct hwrm_port_phy_mdio_read_input { +__rte_packed_begin struct hwrm_port_phy_mdio_read_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -33057,10 +33057,10 @@ struct hwrm_port_phy_mdio_read_input { uint8_t cl45_mdio; /* */ uint8_t unused_1; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ -struct hwrm_port_phy_mdio_read_output { +__rte_packed_begin struct hwrm_port_phy_mdio_read_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -33080,7 +33080,7 @@ struct hwrm_port_phy_mdio_read_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_port_led_cfg * @@ -33088,7 +33088,7 @@ struct hwrm_port_phy_mdio_read_output { /* hwrm_port_led_cfg_input (size:512b/64B) */ -struct hwrm_port_led_cfg_input { +__rte_packed_begin struct hwrm_port_led_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -33483,10 +33483,10 @@ struct hwrm_port_led_cfg_input { uint8_t led3_group_id; /* Reserved field. */ uint8_t rsvd3; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_led_cfg_output (size:128b/16B) */ -struct hwrm_port_led_cfg_output { +__rte_packed_begin struct hwrm_port_led_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -33504,7 +33504,7 @@ struct hwrm_port_led_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_port_led_qcfg * @@ -33512,7 +33512,7 @@ struct hwrm_port_led_cfg_output { /* hwrm_port_led_qcfg_input (size:192b/24B) */ -struct hwrm_port_led_qcfg_input { +__rte_packed_begin struct hwrm_port_led_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -33544,10 +33544,10 @@ struct hwrm_port_led_qcfg_input { /* Port ID of port whose LED configuration is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_led_qcfg_output (size:448b/56B) */ -struct hwrm_port_led_qcfg_output { +__rte_packed_begin struct hwrm_port_led_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -33810,7 +33810,7 @@ struct hwrm_port_led_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_port_led_qcaps * @@ -33818,7 +33818,7 @@ struct hwrm_port_led_qcfg_output { /* hwrm_port_led_qcaps_input (size:192b/24B) */ -struct hwrm_port_led_qcaps_input { +__rte_packed_begin struct hwrm_port_led_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -33850,10 +33850,10 @@ struct hwrm_port_led_qcaps_input { /* Port ID of port whose LED configuration is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_led_qcaps_output (size:384b/48B) */ -struct hwrm_port_led_qcaps_output { +__rte_packed_begin struct hwrm_port_led_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34162,7 +34162,7 @@ struct hwrm_port_led_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_port_prbs_test * @@ -34170,7 +34170,7 @@ struct hwrm_port_led_qcaps_output { /* hwrm_port_prbs_test_input (size:384b/48B) */ -struct hwrm_port_prbs_test_input { +__rte_packed_begin struct hwrm_port_prbs_test_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -34293,10 +34293,10 @@ struct hwrm_port_prbs_test_input { * bit1 = lane1 ..bit31 = lane31 */ uint32_t rx_lane_map; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_prbs_test_output (size:128b/16B) */ -struct hwrm_port_prbs_test_output { +__rte_packed_begin struct hwrm_port_prbs_test_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34325,7 +34325,7 @@ struct hwrm_port_prbs_test_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_port_dsc_dump * @@ -34333,7 +34333,7 @@ struct hwrm_port_prbs_test_output { /* hwrm_port_dsc_dump_input (size:320b/40B) */ -struct hwrm_port_dsc_dump_input { +__rte_packed_begin struct hwrm_port_dsc_dump_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -34470,10 +34470,10 @@ struct hwrm_port_dsc_dump_input { */ #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_DEFER_CLOSE \ UINT32_C(0x4) -} __rte_packed; +} __rte_packed_end; /* hwrm_port_dsc_dump_output (size:128b/16B) */ -struct hwrm_port_dsc_dump_output { +__rte_packed_begin struct hwrm_port_dsc_dump_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34528,7 +34528,7 @@ struct hwrm_port_dsc_dump_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_port_sfp_sideband_cfg * @@ -34536,7 +34536,7 @@ struct hwrm_port_dsc_dump_output { /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */ -struct hwrm_port_sfp_sideband_cfg_input { +__rte_packed_begin struct hwrm_port_sfp_sideband_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -34648,10 +34648,10 @@ struct hwrm_port_sfp_sideband_cfg_input { /* When this bit is set to '1', the module will be powered down. */ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \ UINT32_C(0x40) -} __rte_packed; +} __rte_packed_end; /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */ -struct hwrm_port_sfp_sideband_cfg_output { +__rte_packed_begin struct hwrm_port_sfp_sideband_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34669,7 +34669,7 @@ struct hwrm_port_sfp_sideband_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_port_sfp_sideband_qcfg * @@ -34677,7 +34677,7 @@ struct hwrm_port_sfp_sideband_cfg_output { /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */ -struct hwrm_port_sfp_sideband_qcfg_input { +__rte_packed_begin struct hwrm_port_sfp_sideband_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -34709,10 +34709,10 @@ struct hwrm_port_sfp_sideband_qcfg_input { /* Port ID of port that is to be queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */ -struct hwrm_port_sfp_sideband_qcfg_output { +__rte_packed_begin struct hwrm_port_sfp_sideband_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34792,7 +34792,7 @@ struct hwrm_port_sfp_sideband_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************** * hwrm_port_phy_mdio_bus_acquire * @@ -34800,7 +34800,7 @@ struct hwrm_port_sfp_sideband_qcfg_output { /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */ -struct hwrm_port_phy_mdio_bus_acquire_input { +__rte_packed_begin struct hwrm_port_phy_mdio_bus_acquire_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -34847,10 +34847,10 @@ struct hwrm_port_phy_mdio_bus_acquire_input { */ uint16_t mdio_bus_timeout; uint8_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */ -struct hwrm_port_phy_mdio_bus_acquire_output { +__rte_packed_begin struct hwrm_port_phy_mdio_bus_acquire_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34874,7 +34874,7 @@ struct hwrm_port_phy_mdio_bus_acquire_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************** * hwrm_port_phy_mdio_bus_release * @@ -34882,7 +34882,7 @@ struct hwrm_port_phy_mdio_bus_acquire_output { /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */ -struct hwrm_port_phy_mdio_bus_release_input { +__rte_packed_begin struct hwrm_port_phy_mdio_bus_release_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -34919,10 +34919,10 @@ struct hwrm_port_phy_mdio_bus_release_input { */ uint16_t client_id; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */ -struct hwrm_port_phy_mdio_bus_release_output { +__rte_packed_begin struct hwrm_port_phy_mdio_bus_release_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34943,7 +34943,7 @@ struct hwrm_port_phy_mdio_bus_release_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_port_tx_fir_cfg * @@ -34951,7 +34951,7 @@ struct hwrm_port_phy_mdio_bus_release_output { /* hwrm_port_tx_fir_cfg_input (size:320b/40B) */ -struct hwrm_port_tx_fir_cfg_input { +__rte_packed_begin struct hwrm_port_tx_fir_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35010,10 +35010,10 @@ struct hwrm_port_tx_fir_cfg_input { /* Value4 of TX FIR, required for PAM4. */ uint32_t txfir_val_4; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_tx_fir_cfg_output (size:128b/16B) */ -struct hwrm_port_tx_fir_cfg_output { +__rte_packed_begin struct hwrm_port_tx_fir_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35031,7 +35031,7 @@ struct hwrm_port_tx_fir_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_port_tx_fir_qcfg * @@ -35039,7 +35039,7 @@ struct hwrm_port_tx_fir_cfg_output { /* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */ -struct hwrm_port_tx_fir_qcfg_input { +__rte_packed_begin struct hwrm_port_tx_fir_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35089,10 +35089,10 @@ struct hwrm_port_tx_fir_qcfg_input { /* The ID of the lane TX FIR will be queried. */ uint8_t lane_id; uint8_t unused[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */ -struct hwrm_port_tx_fir_qcfg_output { +__rte_packed_begin struct hwrm_port_tx_fir_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35118,7 +35118,7 @@ struct hwrm_port_tx_fir_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_port_ep_tx_cfg * @@ -35126,7 +35126,7 @@ struct hwrm_port_tx_fir_qcfg_output { /* hwrm_port_ep_tx_cfg_input (size:256b/32B) */ -struct hwrm_port_ep_tx_cfg_input { +__rte_packed_begin struct hwrm_port_ep_tx_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35240,10 +35240,10 @@ struct hwrm_port_ep_tx_cfg_input { */ uint8_t ep3_max_bw; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_ep_tx_cfg_output (size:128b/16B) */ -struct hwrm_port_ep_tx_cfg_output { +__rte_packed_begin struct hwrm_port_ep_tx_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35262,10 +35262,10 @@ struct hwrm_port_ep_tx_cfg_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */ -struct hwrm_port_ep_tx_cfg_cmd_err { +__rte_packed_begin struct hwrm_port_ep_tx_cfg_cmd_err { /* * command specific error codes for the cmd_err field in * hwrm_err_output @@ -35301,7 +35301,7 @@ struct hwrm_port_ep_tx_cfg_cmd_err { #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \ HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_port_ep_tx_qcfg * @@ -35309,7 +35309,7 @@ struct hwrm_port_ep_tx_cfg_cmd_err { /* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */ -struct hwrm_port_ep_tx_qcfg_input { +__rte_packed_begin struct hwrm_port_ep_tx_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35341,10 +35341,10 @@ struct hwrm_port_ep_tx_qcfg_input { /* The port whose endpoint rate limits are queried. */ uint8_t port_id; uint8_t unused[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */ -struct hwrm_port_ep_tx_qcfg_output { +__rte_packed_begin struct hwrm_port_ep_tx_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35427,7 +35427,7 @@ struct hwrm_port_ep_tx_qcfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************** * hwrm_port_cfg * @@ -35435,7 +35435,7 @@ struct hwrm_port_ep_tx_qcfg_output { /* hwrm_port_cfg_input (size:256b/32B) */ -struct hwrm_port_cfg_input { +__rte_packed_begin struct hwrm_port_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35481,10 +35481,10 @@ struct hwrm_port_cfg_input { * field is '1'. */ uint32_t tx_rate_limit; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_cfg_output (size:128b/16B) */ -struct hwrm_port_cfg_output { +__rte_packed_begin struct hwrm_port_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35502,7 +35502,7 @@ struct hwrm_port_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************** * hwrm_port_qcfg * @@ -35510,7 +35510,7 @@ struct hwrm_port_cfg_output { /* hwrm_port_qcfg_input (size:192b/24B) */ -struct hwrm_port_qcfg_input { +__rte_packed_begin struct hwrm_port_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35542,10 +35542,10 @@ struct hwrm_port_qcfg_input { /* Port ID of port that is to be queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_qcfg_output (size:192b/24B) */ -struct hwrm_port_qcfg_output { +__rte_packed_begin struct hwrm_port_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35581,7 +35581,7 @@ struct hwrm_port_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_port_mac_qcaps * @@ -35589,7 +35589,7 @@ struct hwrm_port_qcfg_output { /* hwrm_port_mac_qcaps_input (size:192b/24B) */ -struct hwrm_port_mac_qcaps_input { +__rte_packed_begin struct hwrm_port_mac_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35621,10 +35621,10 @@ struct hwrm_port_mac_qcaps_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_mac_qcaps_output (size:128b/16B) */ -struct hwrm_port_mac_qcaps_output { +__rte_packed_begin struct hwrm_port_mac_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35656,7 +35656,7 @@ struct hwrm_port_mac_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_queue_qportcfg * @@ -35664,7 +35664,7 @@ struct hwrm_port_mac_qcaps_output { /* hwrm_queue_qportcfg_input (size:192b/24B) */ -struct hwrm_queue_qportcfg_input { +__rte_packed_begin struct hwrm_queue_qportcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35723,10 +35723,10 @@ struct hwrm_queue_qportcfg_input { #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \ HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED uint8_t unused_0; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_qportcfg_output (size:1344b/168B) */ -struct hwrm_queue_qportcfg_output { +__rte_packed_begin struct hwrm_queue_qportcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36280,7 +36280,7 @@ struct hwrm_queue_qportcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_queue_qcfg * @@ -36288,7 +36288,7 @@ struct hwrm_queue_qportcfg_output { /* hwrm_queue_qcfg_input (size:192b/24B) */ -struct hwrm_queue_qcfg_input { +__rte_packed_begin struct hwrm_queue_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -36332,10 +36332,10 @@ struct hwrm_queue_qcfg_input { HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX /* Queue ID of the queue. */ uint32_t queue_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_qcfg_output (size:128b/16B) */ -struct hwrm_queue_qcfg_output { +__rte_packed_begin struct hwrm_queue_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36378,7 +36378,7 @@ struct hwrm_queue_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************** * hwrm_queue_cfg * @@ -36386,7 +36386,7 @@ struct hwrm_queue_qcfg_output { /* hwrm_queue_cfg_input (size:320b/40B) */ -struct hwrm_queue_cfg_input { +__rte_packed_begin struct hwrm_queue_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -36461,10 +36461,10 @@ struct hwrm_queue_cfg_input { #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \ HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_cfg_output (size:128b/16B) */ -struct hwrm_queue_cfg_output { +__rte_packed_begin struct hwrm_queue_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36482,7 +36482,7 @@ struct hwrm_queue_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_queue_pfcenable_qcfg * @@ -36490,7 +36490,7 @@ struct hwrm_queue_cfg_output { /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ -struct hwrm_queue_pfcenable_qcfg_input { +__rte_packed_begin struct hwrm_queue_pfcenable_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -36526,10 +36526,10 @@ struct hwrm_queue_pfcenable_qcfg_input { */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ -struct hwrm_queue_pfcenable_qcfg_output { +__rte_packed_begin struct hwrm_queue_pfcenable_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36596,7 +36596,7 @@ struct hwrm_queue_pfcenable_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_queue_pfcenable_cfg * @@ -36604,7 +36604,7 @@ struct hwrm_queue_pfcenable_qcfg_output { /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ -struct hwrm_queue_pfcenable_cfg_input { +__rte_packed_begin struct hwrm_queue_pfcenable_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -36689,10 +36689,10 @@ struct hwrm_queue_pfcenable_cfg_input { */ uint16_t port_id; uint8_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ -struct hwrm_queue_pfcenable_cfg_output { +__rte_packed_begin struct hwrm_queue_pfcenable_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36710,7 +36710,7 @@ struct hwrm_queue_pfcenable_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_queue_pri2cos_qcfg * @@ -36718,7 +36718,7 @@ struct hwrm_queue_pfcenable_cfg_output { /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ -struct hwrm_queue_pri2cos_qcfg_input { +__rte_packed_begin struct hwrm_queue_pri2cos_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -36774,10 +36774,10 @@ struct hwrm_queue_pri2cos_qcfg_input { */ uint8_t port_id; uint8_t unused_0[3]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ -struct hwrm_queue_pri2cos_qcfg_output { +__rte_packed_begin struct hwrm_queue_pri2cos_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36861,7 +36861,7 @@ struct hwrm_queue_pri2cos_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_queue_pri2cos_cfg * @@ -36869,7 +36869,7 @@ struct hwrm_queue_pri2cos_qcfg_output { /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ -struct hwrm_queue_pri2cos_cfg_input { +__rte_packed_begin struct hwrm_queue_pri2cos_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -37017,10 +37017,10 @@ struct hwrm_queue_pri2cos_cfg_input { */ uint8_t pri7_cos_queue_id; uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ -struct hwrm_queue_pri2cos_cfg_output { +__rte_packed_begin struct hwrm_queue_pri2cos_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -37038,7 +37038,7 @@ struct hwrm_queue_pri2cos_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_queue_cos2bw_qcfg * @@ -37046,7 +37046,7 @@ struct hwrm_queue_pri2cos_cfg_output { /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ -struct hwrm_queue_cos2bw_qcfg_input { +__rte_packed_begin struct hwrm_queue_cos2bw_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -37082,10 +37082,10 @@ struct hwrm_queue_cos2bw_qcfg_input { */ uint16_t port_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ -struct hwrm_queue_cos2bw_qcfg_output { +__rte_packed_begin struct hwrm_queue_cos2bw_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -38081,7 +38081,7 @@ struct hwrm_queue_cos2bw_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_queue_cos2bw_cfg * @@ -38089,7 +38089,7 @@ struct hwrm_queue_cos2bw_qcfg_output { /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ -struct hwrm_queue_cos2bw_cfg_input { +__rte_packed_begin struct hwrm_queue_cos2bw_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39152,10 +39152,10 @@ struct hwrm_queue_cos2bw_cfg_input { */ uint8_t queue_id7_bw_weight; uint8_t unused_1[5]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ -struct hwrm_queue_cos2bw_cfg_output { +__rte_packed_begin struct hwrm_queue_cos2bw_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39173,7 +39173,7 @@ struct hwrm_queue_cos2bw_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_queue_dscp_qcaps * @@ -39181,7 +39181,7 @@ struct hwrm_queue_cos2bw_cfg_output { /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ -struct hwrm_queue_dscp_qcaps_input { +__rte_packed_begin struct hwrm_queue_dscp_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39217,10 +39217,10 @@ struct hwrm_queue_dscp_qcaps_input { */ uint8_t port_id; uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ -struct hwrm_queue_dscp_qcaps_output { +__rte_packed_begin struct hwrm_queue_dscp_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39243,7 +39243,7 @@ struct hwrm_queue_dscp_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_queue_dscp2pri_qcfg * @@ -39251,7 +39251,7 @@ struct hwrm_queue_dscp_qcaps_output { /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ -struct hwrm_queue_dscp2pri_qcfg_input { +__rte_packed_begin struct hwrm_queue_dscp2pri_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39295,10 +39295,10 @@ struct hwrm_queue_dscp2pri_qcfg_input { /* Size of the buffer pointed to by dest_data_addr. */ uint16_t dest_data_buffer_size; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ -struct hwrm_queue_dscp2pri_qcfg_output { +__rte_packed_begin struct hwrm_queue_dscp2pri_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39326,7 +39326,7 @@ struct hwrm_queue_dscp2pri_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_queue_dscp2pri_cfg * @@ -39334,7 +39334,7 @@ struct hwrm_queue_dscp2pri_qcfg_output { /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ -struct hwrm_queue_dscp2pri_cfg_input { +__rte_packed_begin struct hwrm_queue_dscp2pri_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39400,10 +39400,10 @@ struct hwrm_queue_dscp2pri_cfg_input { */ uint16_t entry_cnt; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_dscp2pri_cfg_output { +__rte_packed_begin struct hwrm_queue_dscp2pri_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39421,7 +39421,7 @@ struct hwrm_queue_dscp2pri_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_queue_mpls_qcaps * @@ -39429,7 +39429,7 @@ struct hwrm_queue_dscp2pri_cfg_output { /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */ -struct hwrm_queue_mpls_qcaps_input { +__rte_packed_begin struct hwrm_queue_mpls_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39465,10 +39465,10 @@ struct hwrm_queue_mpls_qcaps_input { */ uint8_t port_id; uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */ -struct hwrm_queue_mpls_qcaps_output { +__rte_packed_begin struct hwrm_queue_mpls_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39504,7 +39504,7 @@ struct hwrm_queue_mpls_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_queue_mplstc2pri_qcfg * @@ -39512,7 +39512,7 @@ struct hwrm_queue_mpls_qcaps_output { /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */ -struct hwrm_queue_mplstc2pri_qcfg_input { +__rte_packed_begin struct hwrm_queue_mplstc2pri_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39548,10 +39548,10 @@ struct hwrm_queue_mplstc2pri_qcfg_input { */ uint8_t port_id; uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */ -struct hwrm_queue_mplstc2pri_qcfg_output { +__rte_packed_begin struct hwrm_queue_mplstc2pri_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39625,7 +39625,7 @@ struct hwrm_queue_mplstc2pri_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_queue_mplstc2pri_cfg * @@ -39633,7 +39633,7 @@ struct hwrm_queue_mplstc2pri_qcfg_output { /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */ -struct hwrm_queue_mplstc2pri_cfg_input { +__rte_packed_begin struct hwrm_queue_mplstc2pri_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39758,10 +39758,10 @@ struct hwrm_queue_mplstc2pri_cfg_input { * be changed before traffic has started. */ uint8_t tc7_pri_queue_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_mplstc2pri_cfg_output { +__rte_packed_begin struct hwrm_queue_mplstc2pri_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39779,7 +39779,7 @@ struct hwrm_queue_mplstc2pri_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_queue_vlanpri_qcaps * @@ -39787,7 +39787,7 @@ struct hwrm_queue_mplstc2pri_cfg_output { /* hwrm_queue_vlanpri_qcaps_input (size:192b/24B) */ -struct hwrm_queue_vlanpri_qcaps_input { +__rte_packed_begin struct hwrm_queue_vlanpri_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39823,10 +39823,10 @@ struct hwrm_queue_vlanpri_qcaps_input { */ uint8_t port_id; uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_vlanpri_qcaps_output (size:128b/16B) */ -struct hwrm_queue_vlanpri_qcaps_output { +__rte_packed_begin struct hwrm_queue_vlanpri_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39849,7 +39849,7 @@ struct hwrm_queue_vlanpri_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_queue_vlanpri2pri_qcfg * @@ -39857,7 +39857,7 @@ struct hwrm_queue_vlanpri_qcaps_output { /* hwrm_queue_vlanpri2pri_qcfg_input (size:192b/24B) */ -struct hwrm_queue_vlanpri2pri_qcfg_input { +__rte_packed_begin struct hwrm_queue_vlanpri2pri_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39893,10 +39893,10 @@ struct hwrm_queue_vlanpri2pri_qcfg_input { */ uint8_t port_id; uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ -struct hwrm_queue_vlanpri2pri_qcfg_output { +__rte_packed_begin struct hwrm_queue_vlanpri2pri_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39962,7 +39962,7 @@ struct hwrm_queue_vlanpri2pri_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_queue_vlanpri2pri_cfg * @@ -39970,7 +39970,7 @@ struct hwrm_queue_vlanpri2pri_qcfg_output { /* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ -struct hwrm_queue_vlanpri2pri_cfg_input { +__rte_packed_begin struct hwrm_queue_vlanpri2pri_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40095,10 +40095,10 @@ struct hwrm_queue_vlanpri2pri_cfg_input { * be changed before traffic has started. */ uint8_t vlanpri7_user_pri_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_vlanpri2pri_cfg_output { +__rte_packed_begin struct hwrm_queue_vlanpri2pri_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -40116,7 +40116,7 @@ struct hwrm_queue_vlanpri2pri_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_queue_global_cfg * @@ -40124,7 +40124,7 @@ struct hwrm_queue_vlanpri2pri_cfg_output { /* hwrm_queue_global_cfg_input (size:192b/24B) */ -struct hwrm_queue_global_cfg_input { +__rte_packed_begin struct hwrm_queue_global_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40227,10 +40227,10 @@ struct hwrm_queue_global_cfg_input { * indicates no rate limit. */ uint8_t g3_max_bw; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_global_cfg_output (size:128b/16B) */ -struct hwrm_queue_global_cfg_output { +__rte_packed_begin struct hwrm_queue_global_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -40248,7 +40248,7 @@ struct hwrm_queue_global_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_queue_global_qcfg * @@ -40256,7 +40256,7 @@ struct hwrm_queue_global_cfg_output { /* hwrm_queue_global_qcfg_input (size:128b/16B) */ -struct hwrm_queue_global_qcfg_input { +__rte_packed_begin struct hwrm_queue_global_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40285,10 +40285,10 @@ struct hwrm_queue_global_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_global_qcfg_output (size:320b/40B) */ -struct hwrm_queue_global_qcfg_output { +__rte_packed_begin struct hwrm_queue_global_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -40394,7 +40394,7 @@ struct hwrm_queue_global_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************************** * hwrm_queue_adptv_qos_rx_feature_qcfg * @@ -40402,7 +40402,7 @@ struct hwrm_queue_global_qcfg_output { /* hwrm_queue_adptv_qos_rx_feature_qcfg_input (size:128b/16B) */ -struct hwrm_queue_adptv_qos_rx_feature_qcfg_input { +__rte_packed_begin struct hwrm_queue_adptv_qos_rx_feature_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40431,10 +40431,10 @@ struct hwrm_queue_adptv_qos_rx_feature_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_adptv_qos_rx_feature_qcfg_output (size:128b/16B) */ -struct hwrm_queue_adptv_qos_rx_feature_qcfg_output { +__rte_packed_begin struct hwrm_queue_adptv_qos_rx_feature_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -40646,7 +40646,7 @@ struct hwrm_queue_adptv_qos_rx_feature_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************************** * hwrm_queue_adptv_qos_rx_feature_cfg * @@ -40654,7 +40654,7 @@ struct hwrm_queue_adptv_qos_rx_feature_qcfg_output { /* hwrm_queue_adptv_qos_rx_feature_cfg_input (size:192b/24B) */ -struct hwrm_queue_adptv_qos_rx_feature_cfg_input { +__rte_packed_begin struct hwrm_queue_adptv_qos_rx_feature_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40885,10 +40885,10 @@ struct hwrm_queue_adptv_qos_rx_feature_cfg_input { #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LAST \ HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSLESS uint8_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_adptv_qos_rx_feature_cfg_output (size:128b/16B) */ -struct hwrm_queue_adptv_qos_rx_feature_cfg_output { +__rte_packed_begin struct hwrm_queue_adptv_qos_rx_feature_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -40906,7 +40906,7 @@ struct hwrm_queue_adptv_qos_rx_feature_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************************** * hwrm_queue_adptv_qos_tx_feature_qcfg * @@ -40914,7 +40914,7 @@ struct hwrm_queue_adptv_qos_rx_feature_cfg_output { /* hwrm_queue_adptv_qos_tx_feature_qcfg_input (size:128b/16B) */ -struct hwrm_queue_adptv_qos_tx_feature_qcfg_input { +__rte_packed_begin struct hwrm_queue_adptv_qos_tx_feature_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40943,10 +40943,10 @@ struct hwrm_queue_adptv_qos_tx_feature_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_adptv_qos_tx_feature_qcfg_output (size:128b/16B) */ -struct hwrm_queue_adptv_qos_tx_feature_qcfg_output { +__rte_packed_begin struct hwrm_queue_adptv_qos_tx_feature_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41061,7 +41061,7 @@ struct hwrm_queue_adptv_qos_tx_feature_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************************** * hwrm_queue_adptv_qos_tx_feature_cfg * @@ -41069,7 +41069,7 @@ struct hwrm_queue_adptv_qos_tx_feature_qcfg_output { /* hwrm_queue_adptv_qos_tx_feature_cfg_input (size:192b/24B) */ -struct hwrm_queue_adptv_qos_tx_feature_cfg_input { +__rte_packed_begin struct hwrm_queue_adptv_qos_tx_feature_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -41200,10 +41200,10 @@ struct hwrm_queue_adptv_qos_tx_feature_cfg_input { #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_LAST \ HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED uint8_t unused_0[3]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_adptv_qos_tx_feature_cfg_output (size:128b/16B) */ -struct hwrm_queue_adptv_qos_tx_feature_cfg_output { +__rte_packed_begin struct hwrm_queue_adptv_qos_tx_feature_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41221,7 +41221,7 @@ struct hwrm_queue_adptv_qos_tx_feature_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************** * hwrm_queue_qcaps * @@ -41229,7 +41229,7 @@ struct hwrm_queue_adptv_qos_tx_feature_cfg_output { /* hwrm_queue_qcaps_input (size:128b/16B) */ -struct hwrm_queue_qcaps_input { +__rte_packed_begin struct hwrm_queue_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -41258,10 +41258,10 @@ struct hwrm_queue_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_qcaps_output (size:256b/32B) */ -struct hwrm_queue_qcaps_output { +__rte_packed_begin struct hwrm_queue_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41509,7 +41509,7 @@ struct hwrm_queue_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************************** * hwrm_queue_adptv_qos_rx_tuning_qcfg * @@ -41517,7 +41517,7 @@ struct hwrm_queue_qcaps_output { /* hwrm_queue_adptv_qos_rx_tuning_qcfg_input (size:128b/16B) */ -struct hwrm_queue_adptv_qos_rx_tuning_qcfg_input { +__rte_packed_begin struct hwrm_queue_adptv_qos_rx_tuning_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -41546,10 +41546,10 @@ struct hwrm_queue_adptv_qos_rx_tuning_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_adptv_qos_rx_tuning_qcfg_output (size:576b/72B) */ -struct hwrm_queue_adptv_qos_rx_tuning_qcfg_output { +__rte_packed_begin struct hwrm_queue_adptv_qos_rx_tuning_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41642,7 +41642,7 @@ struct hwrm_queue_adptv_qos_rx_tuning_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************************** * hwrm_queue_adptv_qos_rx_tuning_cfg * @@ -41650,7 +41650,7 @@ struct hwrm_queue_adptv_qos_rx_tuning_qcfg_output { /* hwrm_queue_adptv_qos_rx_tuning_cfg_input (size:640b/80B) */ -struct hwrm_queue_adptv_qos_rx_tuning_cfg_input { +__rte_packed_begin struct hwrm_queue_adptv_qos_rx_tuning_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -41798,10 +41798,10 @@ struct hwrm_queue_adptv_qos_rx_tuning_cfg_input { */ uint32_t shaper_refill_timer; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_adptv_qos_rx_tuning_cfg_output (size:128b/16B) */ -struct hwrm_queue_adptv_qos_rx_tuning_cfg_output { +__rte_packed_begin struct hwrm_queue_adptv_qos_rx_tuning_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41819,7 +41819,7 @@ struct hwrm_queue_adptv_qos_rx_tuning_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************************** * hwrm_queue_adptv_qos_tx_tuning_qcfg * @@ -41827,7 +41827,7 @@ struct hwrm_queue_adptv_qos_rx_tuning_cfg_output { /* hwrm_queue_adptv_qos_tx_tuning_qcfg_input (size:128b/16B) */ -struct hwrm_queue_adptv_qos_tx_tuning_qcfg_input { +__rte_packed_begin struct hwrm_queue_adptv_qos_tx_tuning_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -41856,10 +41856,10 @@ struct hwrm_queue_adptv_qos_tx_tuning_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_adptv_qos_tx_tuning_qcfg_output (size:448b/56B) */ -struct hwrm_queue_adptv_qos_tx_tuning_qcfg_output { +__rte_packed_begin struct hwrm_queue_adptv_qos_tx_tuning_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41928,7 +41928,7 @@ struct hwrm_queue_adptv_qos_tx_tuning_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************************** * hwrm_queue_adptv_qos_tx_tuning_cfg * @@ -41936,7 +41936,7 @@ struct hwrm_queue_adptv_qos_tx_tuning_qcfg_output { /* hwrm_queue_adptv_qos_tx_tuning_cfg_input (size:512b/64B) */ -struct hwrm_queue_adptv_qos_tx_tuning_cfg_input { +__rte_packed_begin struct hwrm_queue_adptv_qos_tx_tuning_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42048,10 +42048,10 @@ struct hwrm_queue_adptv_qos_tx_tuning_cfg_input { */ uint32_t shaper_refill_timer; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_adptv_qos_tx_tuning_cfg_output (size:128b/16B) */ -struct hwrm_queue_adptv_qos_tx_tuning_cfg_output { +__rte_packed_begin struct hwrm_queue_adptv_qos_tx_tuning_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42069,7 +42069,7 @@ struct hwrm_queue_adptv_qos_tx_tuning_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************** * hwrm_queue_pfcwd_timeout_qcaps * @@ -42077,7 +42077,7 @@ struct hwrm_queue_adptv_qos_tx_tuning_cfg_output { /* hwrm_queue_pfcwd_timeout_qcaps_input (size:128b/16B) */ -struct hwrm_queue_pfcwd_timeout_qcaps_input { +__rte_packed_begin struct hwrm_queue_pfcwd_timeout_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42106,10 +42106,10 @@ struct hwrm_queue_pfcwd_timeout_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_pfcwd_timeout_qcaps_output (size:128b/16B) */ -struct hwrm_queue_pfcwd_timeout_qcaps_output { +__rte_packed_begin struct hwrm_queue_pfcwd_timeout_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42129,7 +42129,7 @@ struct hwrm_queue_pfcwd_timeout_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************** * hwrm_queue_pfcwd_timeout_cfg * @@ -42137,7 +42137,7 @@ struct hwrm_queue_pfcwd_timeout_qcaps_output { /* hwrm_queue_pfcwd_timeout_cfg_input (size:192b/24B) */ -struct hwrm_queue_pfcwd_timeout_cfg_input { +__rte_packed_begin struct hwrm_queue_pfcwd_timeout_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42169,10 +42169,10 @@ struct hwrm_queue_pfcwd_timeout_cfg_input { /* pfc watchdog timeout value in msec. */ uint32_t pfcwd_timeout_value; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_pfcwd_timeout_cfg_output (size:128b/16B) */ -struct hwrm_queue_pfcwd_timeout_cfg_output { +__rte_packed_begin struct hwrm_queue_pfcwd_timeout_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42190,7 +42190,7 @@ struct hwrm_queue_pfcwd_timeout_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************* * hwrm_queue_pfcwd_timeout_qcfg * @@ -42198,7 +42198,7 @@ struct hwrm_queue_pfcwd_timeout_cfg_output { /* hwrm_queue_pfcwd_timeout_qcfg_input (size:128b/16B) */ -struct hwrm_queue_pfcwd_timeout_qcfg_input { +__rte_packed_begin struct hwrm_queue_pfcwd_timeout_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42227,10 +42227,10 @@ struct hwrm_queue_pfcwd_timeout_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_queue_pfcwd_timeout_qcfg_output (size:128b/16B) */ -struct hwrm_queue_pfcwd_timeout_qcfg_output { +__rte_packed_begin struct hwrm_queue_pfcwd_timeout_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42250,7 +42250,7 @@ struct hwrm_queue_pfcwd_timeout_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_vnic_alloc * @@ -42258,7 +42258,7 @@ struct hwrm_queue_pfcwd_timeout_qcfg_output { /* hwrm_vnic_alloc_input (size:192b/24B) */ -struct hwrm_vnic_alloc_input { +__rte_packed_begin struct hwrm_vnic_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42308,10 +42308,10 @@ struct hwrm_vnic_alloc_input { */ uint16_t virtio_net_fid; uint8_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_alloc_output (size:128b/16B) */ -struct hwrm_vnic_alloc_output { +__rte_packed_begin struct hwrm_vnic_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42331,7 +42331,7 @@ struct hwrm_vnic_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************** * hwrm_vnic_update * @@ -42339,7 +42339,7 @@ struct hwrm_vnic_alloc_output { /* hwrm_vnic_update_input (size:256b/32B) */ -struct hwrm_vnic_update_input { +__rte_packed_begin struct hwrm_vnic_update_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42425,10 +42425,10 @@ struct hwrm_vnic_update_input { */ uint16_t mru; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_update_output (size:128b/16B) */ -struct hwrm_vnic_update_output { +__rte_packed_begin struct hwrm_vnic_update_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42447,7 +42447,7 @@ struct hwrm_vnic_update_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************** * hwrm_vnic_free * @@ -42455,7 +42455,7 @@ struct hwrm_vnic_update_output { /* hwrm_vnic_free_input (size:192b/24B) */ -struct hwrm_vnic_free_input { +__rte_packed_begin struct hwrm_vnic_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42487,10 +42487,10 @@ struct hwrm_vnic_free_input { /* Logical vnic ID */ uint32_t vnic_id; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_free_output (size:128b/16B) */ -struct hwrm_vnic_free_output { +__rte_packed_begin struct hwrm_vnic_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42508,7 +42508,7 @@ struct hwrm_vnic_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************** * hwrm_vnic_cfg * @@ -42516,7 +42516,7 @@ struct hwrm_vnic_free_output { /* hwrm_vnic_cfg_input (size:384b/48B) */ -struct hwrm_vnic_cfg_input { +__rte_packed_begin struct hwrm_vnic_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42799,10 +42799,10 @@ struct hwrm_vnic_cfg_input { #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_LAST \ HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED uint8_t unused0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_cfg_output (size:128b/16B) */ -struct hwrm_vnic_cfg_output { +__rte_packed_begin struct hwrm_vnic_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42820,7 +42820,7 @@ struct hwrm_vnic_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************** * hwrm_vnic_qcfg * @@ -42828,7 +42828,7 @@ struct hwrm_vnic_cfg_output { /* hwrm_vnic_qcfg_input (size:256b/32B) */ -struct hwrm_vnic_qcfg_input { +__rte_packed_begin struct hwrm_vnic_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42868,10 +42868,10 @@ struct hwrm_vnic_qcfg_input { /* ID of Virtual Function whose VNIC resource is being queried. */ uint16_t vf_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_qcfg_output (size:256b/32B) */ -struct hwrm_vnic_qcfg_output { +__rte_packed_begin struct hwrm_vnic_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -43064,7 +43064,7 @@ struct hwrm_vnic_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_vnic_qcaps * @@ -43072,7 +43072,7 @@ struct hwrm_vnic_qcfg_output { /* hwrm_vnic_qcaps_input (size:192b/24B) */ -struct hwrm_vnic_qcaps_input { +__rte_packed_begin struct hwrm_vnic_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -43103,10 +43103,10 @@ struct hwrm_vnic_qcaps_input { uint64_t resp_addr; uint32_t enables; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_qcaps_output (size:192b/24B) */ -struct hwrm_vnic_qcaps_output { +__rte_packed_begin struct hwrm_vnic_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -43362,7 +43362,7 @@ struct hwrm_vnic_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_vnic_tpa_cfg * @@ -43370,7 +43370,7 @@ struct hwrm_vnic_qcaps_output { /* hwrm_vnic_tpa_cfg_input (size:384b/48B) */ -struct hwrm_vnic_tpa_cfg_input { +__rte_packed_begin struct hwrm_vnic_tpa_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -43664,10 +43664,10 @@ struct hwrm_vnic_tpa_cfg_input { #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR8 \ UINT32_C(0x10000) uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ -struct hwrm_vnic_tpa_cfg_output { +__rte_packed_begin struct hwrm_vnic_tpa_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -43685,7 +43685,7 @@ struct hwrm_vnic_tpa_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_vnic_tpa_qcfg * @@ -43693,7 +43693,7 @@ struct hwrm_vnic_tpa_cfg_output { /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ -struct hwrm_vnic_tpa_qcfg_input { +__rte_packed_begin struct hwrm_vnic_tpa_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -43725,10 +43725,10 @@ struct hwrm_vnic_tpa_qcfg_input { /* Logical vnic ID */ uint16_t vnic_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ -struct hwrm_vnic_tpa_qcfg_output { +__rte_packed_begin struct hwrm_vnic_tpa_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -43967,7 +43967,7 @@ struct hwrm_vnic_tpa_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_vnic_rss_cfg * @@ -43975,7 +43975,7 @@ struct hwrm_vnic_tpa_qcfg_output { /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ -struct hwrm_vnic_rss_cfg_input { +__rte_packed_begin struct hwrm_vnic_rss_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44225,10 +44225,10 @@ struct hwrm_vnic_rss_cfg_input { #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_LAST \ HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ -struct hwrm_vnic_rss_cfg_output { +__rte_packed_begin struct hwrm_vnic_rss_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -44246,10 +44246,10 @@ struct hwrm_vnic_rss_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ -struct hwrm_vnic_rss_cfg_cmd_err { +__rte_packed_begin struct hwrm_vnic_rss_cfg_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -44267,7 +44267,7 @@ struct hwrm_vnic_rss_cfg_cmd_err { #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \ HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_vnic_rss_qcfg * @@ -44275,7 +44275,7 @@ struct hwrm_vnic_rss_cfg_cmd_err { /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ -struct hwrm_vnic_rss_qcfg_input { +__rte_packed_begin struct hwrm_vnic_rss_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44315,10 +44315,10 @@ struct hwrm_vnic_rss_qcfg_input { */ uint16_t vnic_id; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ -struct hwrm_vnic_rss_qcfg_output { +__rte_packed_begin struct hwrm_vnic_rss_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -44509,7 +44509,7 @@ struct hwrm_vnic_rss_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_vnic_plcmodes_cfg * @@ -44517,7 +44517,7 @@ struct hwrm_vnic_rss_qcfg_output { /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ -struct hwrm_vnic_plcmodes_cfg_input { +__rte_packed_begin struct hwrm_vnic_plcmodes_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44679,10 +44679,10 @@ struct hwrm_vnic_plcmodes_cfg_input { */ uint16_t max_bds; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ -struct hwrm_vnic_plcmodes_cfg_output { +__rte_packed_begin struct hwrm_vnic_plcmodes_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -44701,7 +44701,7 @@ struct hwrm_vnic_plcmodes_cfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_vnic_plcmodes_qcfg * @@ -44709,7 +44709,7 @@ struct hwrm_vnic_plcmodes_cfg_output { /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */ -struct hwrm_vnic_plcmodes_qcfg_input { +__rte_packed_begin struct hwrm_vnic_plcmodes_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44741,10 +44741,10 @@ struct hwrm_vnic_plcmodes_qcfg_input { /* Logical vnic ID */ uint32_t vnic_id; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */ -struct hwrm_vnic_plcmodes_qcfg_output { +__rte_packed_begin struct hwrm_vnic_plcmodes_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -44852,7 +44852,7 @@ struct hwrm_vnic_plcmodes_qcfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************** * hwrm_vnic_rss_cos_lb_ctx_alloc * @@ -44860,7 +44860,7 @@ struct hwrm_vnic_plcmodes_qcfg_output { /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { +__rte_packed_begin struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44889,10 +44889,10 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { +__rte_packed_begin struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -44912,7 +44912,7 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************* * hwrm_vnic_rss_cos_lb_ctx_free * @@ -44920,7 +44920,7 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ -struct hwrm_vnic_rss_cos_lb_ctx_free_input { +__rte_packed_begin struct hwrm_vnic_rss_cos_lb_ctx_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44952,10 +44952,10 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_input { /* rss_cos_lb_ctx_id is 16 b */ uint16_t rss_cos_lb_ctx_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_free_output { +__rte_packed_begin struct hwrm_vnic_rss_cos_lb_ctx_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -44973,7 +44973,7 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_ring_alloc * @@ -44981,7 +44981,7 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_output { /* hwrm_ring_alloc_input (size:704b/88B) */ -struct hwrm_ring_alloc_input { +__rte_packed_begin struct hwrm_ring_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -45437,10 +45437,10 @@ struct hwrm_ring_alloc_input { * record. */ uint64_t cq_handle; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_alloc_output (size:128b/16B) */ -struct hwrm_ring_alloc_output { +__rte_packed_begin struct hwrm_ring_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -45478,7 +45478,7 @@ struct hwrm_ring_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************** * hwrm_ring_free * @@ -45486,7 +45486,7 @@ struct hwrm_ring_alloc_output { /* hwrm_ring_free_input (size:256b/32B) */ -struct hwrm_ring_free_input { +__rte_packed_begin struct hwrm_ring_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -45562,10 +45562,10 @@ struct hwrm_ring_free_input { */ uint32_t opaque; uint32_t unused_1; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_free_output (size:128b/16B) */ -struct hwrm_ring_free_output { +__rte_packed_begin struct hwrm_ring_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -45583,7 +45583,7 @@ struct hwrm_ring_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_ring_reset * @@ -45591,7 +45591,7 @@ struct hwrm_ring_free_output { /* hwrm_ring_reset_input (size:192b/24B) */ -struct hwrm_ring_reset_input { +__rte_packed_begin struct hwrm_ring_reset_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -45645,10 +45645,10 @@ struct hwrm_ring_reset_input { */ uint16_t ring_id; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_reset_output (size:128b/16B) */ -struct hwrm_ring_reset_output { +__rte_packed_begin struct hwrm_ring_reset_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -45681,7 +45681,7 @@ struct hwrm_ring_reset_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************** * hwrm_ring_cfg * @@ -45689,7 +45689,7 @@ struct hwrm_ring_reset_output { /* hwrm_ring_cfg_input (size:320b/40B) */ -struct hwrm_ring_cfg_input { +__rte_packed_begin struct hwrm_ring_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -45820,10 +45820,10 @@ struct hwrm_ring_cfg_input { */ uint32_t tx_metadata; uint8_t unused_2[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_cfg_output (size:128b/16B) */ -struct hwrm_ring_cfg_output { +__rte_packed_begin struct hwrm_ring_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -45842,7 +45842,7 @@ struct hwrm_ring_cfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************** * hwrm_ring_qcfg * @@ -45850,7 +45850,7 @@ struct hwrm_ring_cfg_output { /* hwrm_ring_qcfg_input (size:192b/24B) */ -struct hwrm_ring_qcfg_input { +__rte_packed_begin struct hwrm_ring_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -45890,10 +45890,10 @@ struct hwrm_ring_qcfg_input { uint8_t unused_0[5]; /* Physical number of the ring. */ uint16_t ring_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_qcfg_output (size:256b/32B) */ -struct hwrm_ring_qcfg_output { +__rte_packed_begin struct hwrm_ring_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -45984,7 +45984,7 @@ struct hwrm_ring_qcfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_ring_aggint_qcaps * @@ -45992,7 +45992,7 @@ struct hwrm_ring_qcfg_output { /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ -struct hwrm_ring_aggint_qcaps_input { +__rte_packed_begin struct hwrm_ring_aggint_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46021,10 +46021,10 @@ struct hwrm_ring_aggint_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ -struct hwrm_ring_aggint_qcaps_output { +__rte_packed_begin struct hwrm_ring_aggint_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46134,7 +46134,7 @@ struct hwrm_ring_aggint_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************************** * hwrm_ring_cmpl_ring_qaggint_params * @@ -46142,7 +46142,7 @@ struct hwrm_ring_aggint_qcaps_output { /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ -struct hwrm_ring_cmpl_ring_qaggint_params_input { +__rte_packed_begin struct hwrm_ring_cmpl_ring_qaggint_params_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46185,10 +46185,10 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input { #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \ UINT32_C(0x4) uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ -struct hwrm_ring_cmpl_ring_qaggint_params_output { +__rte_packed_begin struct hwrm_ring_cmpl_ring_qaggint_params_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46252,7 +46252,7 @@ struct hwrm_ring_cmpl_ring_qaggint_params_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************************** * hwrm_ring_cmpl_ring_cfg_aggint_params * @@ -46260,7 +46260,7 @@ struct hwrm_ring_cmpl_ring_qaggint_params_output { /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ -struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { +__rte_packed_begin struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46388,10 +46388,10 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \ UINT32_C(0x20) uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ -struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { +__rte_packed_begin struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46409,7 +46409,7 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_ring_grp_alloc * @@ -46417,7 +46417,7 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { /* hwrm_ring_grp_alloc_input (size:192b/24B) */ -struct hwrm_ring_grp_alloc_input { +__rte_packed_begin struct hwrm_ring_grp_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46467,10 +46467,10 @@ struct hwrm_ring_grp_alloc_input { * with the ring group. */ uint16_t sc; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_grp_alloc_output (size:128b/16B) */ -struct hwrm_ring_grp_alloc_output { +__rte_packed_begin struct hwrm_ring_grp_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46494,7 +46494,7 @@ struct hwrm_ring_grp_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_ring_grp_free * @@ -46502,7 +46502,7 @@ struct hwrm_ring_grp_alloc_output { /* hwrm_ring_grp_free_input (size:192b/24B) */ -struct hwrm_ring_grp_free_input { +__rte_packed_begin struct hwrm_ring_grp_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46534,10 +46534,10 @@ struct hwrm_ring_grp_free_input { /* This is the ring group ID value. */ uint32_t ring_group_id; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_grp_free_output (size:128b/16B) */ -struct hwrm_ring_grp_free_output { +__rte_packed_begin struct hwrm_ring_grp_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46555,7 +46555,7 @@ struct hwrm_ring_grp_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_ring_schq_alloc * @@ -46563,7 +46563,7 @@ struct hwrm_ring_grp_free_output { /* hwrm_ring_schq_alloc_input (size:1088b/136B) */ -struct hwrm_ring_schq_alloc_input { +__rte_packed_begin struct hwrm_ring_schq_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47102,10 +47102,10 @@ struct hwrm_ring_schq_alloc_input { /* Number of bytes that have been allocated for each context entry. */ uint16_t tqm_entry_size; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_schq_alloc_output (size:128b/16B) */ -struct hwrm_ring_schq_alloc_output { +__rte_packed_begin struct hwrm_ring_schq_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47129,7 +47129,7 @@ struct hwrm_ring_schq_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_ring_schq_cfg * @@ -47137,7 +47137,7 @@ struct hwrm_ring_schq_alloc_output { /* hwrm_ring_schq_cfg_input (size:768b/96B) */ -struct hwrm_ring_schq_cfg_input { +__rte_packed_begin struct hwrm_ring_schq_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47263,10 +47263,10 @@ struct hwrm_ring_schq_cfg_input { */ uint32_t max_bw; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_schq_cfg_output (size:128b/16B) */ -struct hwrm_ring_schq_cfg_output { +__rte_packed_begin struct hwrm_ring_schq_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47284,7 +47284,7 @@ struct hwrm_ring_schq_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_ring_schq_free * @@ -47292,7 +47292,7 @@ struct hwrm_ring_schq_cfg_output { /* hwrm_ring_schq_free_input (size:192b/24B) */ -struct hwrm_ring_schq_free_input { +__rte_packed_begin struct hwrm_ring_schq_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47324,10 +47324,10 @@ struct hwrm_ring_schq_free_input { /* Identifies the SCHQ being freed. */ uint16_t schq_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_ring_schq_free_output (size:128b/16B) */ -struct hwrm_ring_schq_free_output { +__rte_packed_begin struct hwrm_ring_schq_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47345,7 +47345,7 @@ struct hwrm_ring_schq_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* * special reserved flow ID to identify per function default * flows for vSwitch offload @@ -47373,7 +47373,7 @@ struct hwrm_ring_schq_free_output { /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ -struct hwrm_cfa_l2_filter_alloc_input { +__rte_packed_begin struct hwrm_cfa_l2_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47789,10 +47789,10 @@ struct hwrm_cfa_l2_filter_alloc_input { * 2 - Below the given filter */ uint64_t l2_filter_id_hint; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_l2_filter_alloc_output { +__rte_packed_begin struct hwrm_cfa_l2_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47856,7 +47856,7 @@ struct hwrm_cfa_l2_filter_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_cfa_l2_filter_free * @@ -47864,7 +47864,7 @@ struct hwrm_cfa_l2_filter_alloc_output { /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_l2_filter_free_input { +__rte_packed_begin struct hwrm_cfa_l2_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47898,10 +47898,10 @@ struct hwrm_cfa_l2_filter_free_input { * context. */ uint64_t l2_filter_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_l2_filter_free_output { +__rte_packed_begin struct hwrm_cfa_l2_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47920,7 +47920,7 @@ struct hwrm_cfa_l2_filter_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_cfa_l2_filter_cfg * @@ -47928,7 +47928,7 @@ struct hwrm_cfa_l2_filter_free_output { /* hwrm_cfa_l2_filter_cfg_input (size:384b/48B) */ -struct hwrm_cfa_l2_filter_cfg_input { +__rte_packed_begin struct hwrm_cfa_l2_filter_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48069,10 +48069,10 @@ struct hwrm_cfa_l2_filter_cfg_input { * Lookup entry for further classification. */ uint32_t l2_context_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ -struct hwrm_cfa_l2_filter_cfg_output { +__rte_packed_begin struct hwrm_cfa_l2_filter_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48091,7 +48091,7 @@ struct hwrm_cfa_l2_filter_cfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_cfa_l2_set_rx_mask * @@ -48099,7 +48099,7 @@ struct hwrm_cfa_l2_filter_cfg_output { /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ -struct hwrm_cfa_l2_set_rx_mask_input { +__rte_packed_begin struct hwrm_cfa_l2_set_rx_mask_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48252,10 +48252,10 @@ struct hwrm_cfa_l2_set_rx_mask_input { */ uint32_t num_vlan_tags; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ -struct hwrm_cfa_l2_set_rx_mask_output { +__rte_packed_begin struct hwrm_cfa_l2_set_rx_mask_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48274,10 +48274,10 @@ struct hwrm_cfa_l2_set_rx_mask_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ -struct hwrm_cfa_l2_set_rx_mask_cmd_err { +__rte_packed_begin struct hwrm_cfa_l2_set_rx_mask_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -48292,7 +48292,7 @@ struct hwrm_cfa_l2_set_rx_mask_cmd_err { #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \ HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_cfa_vlan_antispoof_cfg * @@ -48300,7 +48300,7 @@ struct hwrm_cfa_l2_set_rx_mask_cmd_err { /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */ -struct hwrm_cfa_vlan_antispoof_cfg_input { +__rte_packed_begin struct hwrm_cfa_vlan_antispoof_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48346,10 +48346,10 @@ struct hwrm_cfa_vlan_antispoof_cfg_input { * for the 12-bit VLAN ID. */ uint64_t vlan_tag_mask_tbl_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */ -struct hwrm_cfa_vlan_antispoof_cfg_output { +__rte_packed_begin struct hwrm_cfa_vlan_antispoof_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48368,7 +48368,7 @@ struct hwrm_cfa_vlan_antispoof_cfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************** * hwrm_cfa_vlan_antispoof_qcfg * @@ -48376,7 +48376,7 @@ struct hwrm_cfa_vlan_antispoof_cfg_output { /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */ -struct hwrm_cfa_vlan_antispoof_qcfg_input { +__rte_packed_begin struct hwrm_cfa_vlan_antispoof_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48425,10 +48425,10 @@ struct hwrm_cfa_vlan_antispoof_qcfg_input { * the mask value should be 0xfff for the 12-bit VLAN ID. */ uint64_t vlan_tag_mask_tbl_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */ -struct hwrm_cfa_vlan_antispoof_qcfg_output { +__rte_packed_begin struct hwrm_cfa_vlan_antispoof_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48449,7 +48449,7 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************** * hwrm_cfa_tunnel_filter_alloc * @@ -48457,7 +48457,7 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output { /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ -struct hwrm_cfa_tunnel_filter_alloc_input { +__rte_packed_begin struct hwrm_cfa_tunnel_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48708,10 +48708,10 @@ struct hwrm_cfa_tunnel_filter_alloc_input { * mirrored. */ uint32_t mirror_vnic_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_tunnel_filter_alloc_output { +__rte_packed_begin struct hwrm_cfa_tunnel_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48772,7 +48772,7 @@ struct hwrm_cfa_tunnel_filter_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_cfa_tunnel_filter_free * @@ -48780,7 +48780,7 @@ struct hwrm_cfa_tunnel_filter_alloc_output { /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_tunnel_filter_free_input { +__rte_packed_begin struct hwrm_cfa_tunnel_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48811,10 +48811,10 @@ struct hwrm_cfa_tunnel_filter_free_input { uint64_t resp_addr; /* This value is an opaque id into CFA data structures. */ uint64_t tunnel_filter_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_tunnel_filter_free_output { +__rte_packed_begin struct hwrm_cfa_tunnel_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48833,7 +48833,7 @@ struct hwrm_cfa_tunnel_filter_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************************** * hwrm_cfa_redirect_tunnel_type_alloc * @@ -48841,7 +48841,7 @@ struct hwrm_cfa_tunnel_filter_free_output { /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */ -struct hwrm_cfa_redirect_tunnel_type_alloc_input { +__rte_packed_begin struct hwrm_cfa_redirect_tunnel_type_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48936,10 +48936,10 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input { #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \ UINT32_C(0x1) uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */ -struct hwrm_cfa_redirect_tunnel_type_alloc_output { +__rte_packed_begin struct hwrm_cfa_redirect_tunnel_type_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48958,7 +48958,7 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************************** * hwrm_cfa_redirect_tunnel_type_free * @@ -48966,7 +48966,7 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_output { /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */ -struct hwrm_cfa_redirect_tunnel_type_free_input { +__rte_packed_begin struct hwrm_cfa_redirect_tunnel_type_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49053,10 +49053,10 @@ struct hwrm_cfa_redirect_tunnel_type_free_input { #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \ HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL uint8_t unused_0[5]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */ -struct hwrm_cfa_redirect_tunnel_type_free_output { +__rte_packed_begin struct hwrm_cfa_redirect_tunnel_type_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49075,7 +49075,7 @@ struct hwrm_cfa_redirect_tunnel_type_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************************** * hwrm_cfa_redirect_tunnel_type_info * @@ -49083,7 +49083,7 @@ struct hwrm_cfa_redirect_tunnel_type_free_output { /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */ -struct hwrm_cfa_redirect_tunnel_type_info_input { +__rte_packed_begin struct hwrm_cfa_redirect_tunnel_type_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49170,10 +49170,10 @@ struct hwrm_cfa_redirect_tunnel_type_info_input { #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \ HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL uint8_t unused_0[5]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */ -struct hwrm_cfa_redirect_tunnel_type_info_output { +__rte_packed_begin struct hwrm_cfa_redirect_tunnel_type_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49194,10 +49194,10 @@ struct hwrm_cfa_redirect_tunnel_type_info_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ -struct hwrm_vxlan_ipv4_hdr { +__rte_packed_begin struct hwrm_vxlan_ipv4_hdr { /* IPv4 version and header length. */ uint8_t ver_hlen; /* IPv4 header length */ @@ -49220,10 +49220,10 @@ struct hwrm_vxlan_ipv4_hdr { uint32_t src_ip_addr; /* IPv4 destination address. */ uint32_t dest_ip_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ -struct hwrm_vxlan_ipv6_hdr { +__rte_packed_begin struct hwrm_vxlan_ipv6_hdr { /* IPv6 version, traffic class and flow label. */ uint32_t ver_tc_flow_label; /* IPv6 version shift */ @@ -49256,10 +49256,10 @@ struct hwrm_vxlan_ipv6_hdr { uint32_t src_ip_addr[4]; /* IPv6 destination address. */ uint32_t dest_ip_addr[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ -struct hwrm_cfa_encap_data_vxlan { +__rte_packed_begin struct hwrm_cfa_encap_data_vxlan { /* Source MAC address. */ uint8_t src_mac_addr[6]; /* reserved. */ @@ -49304,7 +49304,7 @@ struct hwrm_cfa_encap_data_vxlan { /* VXLAN header flags field. */ uint8_t hdr_flags; uint8_t unused[3]; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_cfa_encap_record_alloc * @@ -49312,7 +49312,7 @@ struct hwrm_cfa_encap_data_vxlan { /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ -struct hwrm_cfa_encap_record_alloc_input { +__rte_packed_begin struct hwrm_cfa_encap_record_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49407,10 +49407,10 @@ struct hwrm_cfa_encap_record_alloc_input { uint8_t unused_0[3]; /* This value is encap data used for the given encap type. */ uint32_t encap_data[20]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ -struct hwrm_cfa_encap_record_alloc_output { +__rte_packed_begin struct hwrm_cfa_encap_record_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49431,7 +49431,7 @@ struct hwrm_cfa_encap_record_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_cfa_encap_record_free * @@ -49439,7 +49439,7 @@ struct hwrm_cfa_encap_record_alloc_output { /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ -struct hwrm_cfa_encap_record_free_input { +__rte_packed_begin struct hwrm_cfa_encap_record_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49471,10 +49471,10 @@ struct hwrm_cfa_encap_record_free_input { /* This value is an opaque id into CFA data structures. */ uint32_t encap_record_id; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ -struct hwrm_cfa_encap_record_free_output { +__rte_packed_begin struct hwrm_cfa_encap_record_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49493,7 +49493,7 @@ struct hwrm_cfa_encap_record_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************** * hwrm_cfa_ntuple_filter_alloc * @@ -49501,7 +49501,7 @@ struct hwrm_cfa_encap_record_free_output { /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ -struct hwrm_cfa_ntuple_filter_alloc_input { +__rte_packed_begin struct hwrm_cfa_ntuple_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49907,10 +49907,10 @@ struct hwrm_cfa_ntuple_filter_alloc_input { * the pri_hint. */ uint64_t ntuple_filter_id_hint; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_ntuple_filter_alloc_output { +__rte_packed_begin struct hwrm_cfa_ntuple_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49971,10 +49971,10 @@ struct hwrm_cfa_ntuple_filter_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ -struct hwrm_cfa_ntuple_filter_alloc_cmd_err { +__rte_packed_begin struct hwrm_cfa_ntuple_filter_alloc_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -49989,7 +49989,7 @@ struct hwrm_cfa_ntuple_filter_alloc_cmd_err { #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \ HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_cfa_ntuple_filter_free * @@ -49997,7 +49997,7 @@ struct hwrm_cfa_ntuple_filter_alloc_cmd_err { /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_ntuple_filter_free_input { +__rte_packed_begin struct hwrm_cfa_ntuple_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50028,10 +50028,10 @@ struct hwrm_cfa_ntuple_filter_free_input { uint64_t resp_addr; /* This value is an opaque id into CFA data structures. */ uint64_t ntuple_filter_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_ntuple_filter_free_output { +__rte_packed_begin struct hwrm_cfa_ntuple_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50050,7 +50050,7 @@ struct hwrm_cfa_ntuple_filter_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_cfa_ntuple_filter_cfg * @@ -50058,7 +50058,7 @@ struct hwrm_cfa_ntuple_filter_free_output { /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ -struct hwrm_cfa_ntuple_filter_cfg_input { +__rte_packed_begin struct hwrm_cfa_ntuple_filter_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50159,10 +50159,10 @@ struct hwrm_cfa_ntuple_filter_cfg_input { #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \ HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID uint8_t unused_1[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ -struct hwrm_cfa_ntuple_filter_cfg_output { +__rte_packed_begin struct hwrm_cfa_ntuple_filter_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50181,7 +50181,7 @@ struct hwrm_cfa_ntuple_filter_cfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_cfa_em_flow_alloc * @@ -50189,7 +50189,7 @@ struct hwrm_cfa_ntuple_filter_cfg_output { /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */ -struct hwrm_cfa_em_flow_alloc_input { +__rte_packed_begin struct hwrm_cfa_em_flow_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50539,10 +50539,10 @@ struct hwrm_cfa_em_flow_alloc_input { /* Logical ID of the encapsulation record. */ uint32_t encap_record_id; uint8_t unused_2[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */ -struct hwrm_cfa_em_flow_alloc_output { +__rte_packed_begin struct hwrm_cfa_em_flow_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50603,7 +50603,7 @@ struct hwrm_cfa_em_flow_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_cfa_em_flow_free * @@ -50611,7 +50611,7 @@ struct hwrm_cfa_em_flow_alloc_output { /* hwrm_cfa_em_flow_free_input (size:192b/24B) */ -struct hwrm_cfa_em_flow_free_input { +__rte_packed_begin struct hwrm_cfa_em_flow_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50642,10 +50642,10 @@ struct hwrm_cfa_em_flow_free_input { uint64_t resp_addr; /* This value is an opaque id into CFA data structures. */ uint64_t em_filter_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_em_flow_free_output (size:128b/16B) */ -struct hwrm_cfa_em_flow_free_output { +__rte_packed_begin struct hwrm_cfa_em_flow_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50664,7 +50664,7 @@ struct hwrm_cfa_em_flow_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_cfa_meter_qcaps * @@ -50672,7 +50672,7 @@ struct hwrm_cfa_em_flow_free_output { /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */ -struct hwrm_cfa_meter_qcaps_input { +__rte_packed_begin struct hwrm_cfa_meter_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50701,10 +50701,10 @@ struct hwrm_cfa_meter_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */ -struct hwrm_cfa_meter_qcaps_output { +__rte_packed_begin struct hwrm_cfa_meter_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50778,7 +50778,7 @@ struct hwrm_cfa_meter_qcaps_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************** * hwrm_cfa_meter_profile_alloc * @@ -50786,7 +50786,7 @@ struct hwrm_cfa_meter_qcaps_output { /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */ -struct hwrm_cfa_meter_profile_alloc_input { +__rte_packed_begin struct hwrm_cfa_meter_profile_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51025,10 +51025,10 @@ struct hwrm_cfa_meter_profile_alloc_input { (UINT32_C(0x7) << 29) #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_alloc_output { +__rte_packed_begin struct hwrm_cfa_meter_profile_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51057,7 +51057,7 @@ struct hwrm_cfa_meter_profile_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_cfa_meter_profile_free * @@ -51065,7 +51065,7 @@ struct hwrm_cfa_meter_profile_alloc_output { /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */ -struct hwrm_cfa_meter_profile_free_input { +__rte_packed_begin struct hwrm_cfa_meter_profile_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51121,10 +51121,10 @@ struct hwrm_cfa_meter_profile_free_input { #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \ HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_free_output { +__rte_packed_begin struct hwrm_cfa_meter_profile_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51143,7 +51143,7 @@ struct hwrm_cfa_meter_profile_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_cfa_meter_profile_cfg * @@ -51151,7 +51151,7 @@ struct hwrm_cfa_meter_profile_free_output { /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */ -struct hwrm_cfa_meter_profile_cfg_input { +__rte_packed_begin struct hwrm_cfa_meter_profile_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51393,10 +51393,10 @@ struct hwrm_cfa_meter_profile_cfg_input { (UINT32_C(0x7) << 29) #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_cfg_output { +__rte_packed_begin struct hwrm_cfa_meter_profile_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51415,7 +51415,7 @@ struct hwrm_cfa_meter_profile_cfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************* * hwrm_cfa_meter_instance_alloc * @@ -51423,7 +51423,7 @@ struct hwrm_cfa_meter_profile_cfg_output { /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */ -struct hwrm_cfa_meter_instance_alloc_input { +__rte_packed_begin struct hwrm_cfa_meter_instance_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51480,10 +51480,10 @@ struct hwrm_cfa_meter_instance_alloc_input { #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */ -struct hwrm_cfa_meter_instance_alloc_output { +__rte_packed_begin struct hwrm_cfa_meter_instance_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51512,7 +51512,7 @@ struct hwrm_cfa_meter_instance_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_cfa_meter_instance_cfg * @@ -51520,7 +51520,7 @@ struct hwrm_cfa_meter_instance_alloc_output { /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */ -struct hwrm_cfa_meter_instance_cfg_input { +__rte_packed_begin struct hwrm_cfa_meter_instance_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51584,10 +51584,10 @@ struct hwrm_cfa_meter_instance_cfg_input { */ uint16_t meter_instance_id; uint8_t unused_1[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */ -struct hwrm_cfa_meter_instance_cfg_output { +__rte_packed_begin struct hwrm_cfa_meter_instance_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51606,7 +51606,7 @@ struct hwrm_cfa_meter_instance_cfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************** * hwrm_cfa_meter_instance_free * @@ -51614,7 +51614,7 @@ struct hwrm_cfa_meter_instance_cfg_output { /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */ -struct hwrm_cfa_meter_instance_free_input { +__rte_packed_begin struct hwrm_cfa_meter_instance_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51670,10 +51670,10 @@ struct hwrm_cfa_meter_instance_free_input { #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */ -struct hwrm_cfa_meter_instance_free_output { +__rte_packed_begin struct hwrm_cfa_meter_instance_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51692,7 +51692,7 @@ struct hwrm_cfa_meter_instance_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_cfa_decap_filter_alloc * @@ -51700,7 +51700,7 @@ struct hwrm_cfa_meter_instance_free_output { /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ -struct hwrm_cfa_decap_filter_alloc_input { +__rte_packed_begin struct hwrm_cfa_decap_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52003,10 +52003,10 @@ struct hwrm_cfa_decap_filter_alloc_input { * L2 information of the decap filter. */ uint16_t l2_ctxt_ref_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ -struct hwrm_cfa_decap_filter_alloc_output { +__rte_packed_begin struct hwrm_cfa_decap_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52027,7 +52027,7 @@ struct hwrm_cfa_decap_filter_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_cfa_decap_filter_free * @@ -52035,7 +52035,7 @@ struct hwrm_cfa_decap_filter_alloc_output { /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_decap_filter_free_input { +__rte_packed_begin struct hwrm_cfa_decap_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52067,10 +52067,10 @@ struct hwrm_cfa_decap_filter_free_input { /* This value is an opaque id into CFA data structures. */ uint32_t decap_filter_id; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_decap_filter_free_output { +__rte_packed_begin struct hwrm_cfa_decap_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52089,7 +52089,7 @@ struct hwrm_cfa_decap_filter_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_cfa_flow_alloc * @@ -52097,7 +52097,7 @@ struct hwrm_cfa_decap_filter_free_output { /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ -struct hwrm_cfa_flow_alloc_input { +__rte_packed_begin struct hwrm_cfa_flow_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52387,10 +52387,10 @@ struct hwrm_cfa_flow_alloc_input { UINT32_C(0xff) #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ -struct hwrm_cfa_flow_alloc_output { +__rte_packed_begin struct hwrm_cfa_flow_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52455,10 +52455,10 @@ struct hwrm_cfa_flow_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ -struct hwrm_cfa_flow_alloc_cmd_err { +__rte_packed_begin struct hwrm_cfa_flow_alloc_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -52483,7 +52483,7 @@ struct hwrm_cfa_flow_alloc_cmd_err { #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \ HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_cfa_flow_free * @@ -52491,7 +52491,7 @@ struct hwrm_cfa_flow_alloc_cmd_err { /* hwrm_cfa_flow_free_input (size:256b/32B) */ -struct hwrm_cfa_flow_free_input { +__rte_packed_begin struct hwrm_cfa_flow_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52527,10 +52527,10 @@ struct hwrm_cfa_flow_free_input { uint32_t flow_counter_id; /* This value identifies a set of CFA data structures used for a flow. */ uint64_t ext_flow_handle; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_free_output (size:256b/32B) */ -struct hwrm_cfa_flow_free_output { +__rte_packed_begin struct hwrm_cfa_flow_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52553,10 +52553,10 @@ struct hwrm_cfa_flow_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_action_data (size:960b/120B) */ -struct hwrm_cfa_flow_action_data { +__rte_packed_begin struct hwrm_cfa_flow_action_data { uint16_t action_flags; /* Setting of this flag indicates accept action. */ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \ @@ -52643,10 +52643,10 @@ struct hwrm_cfa_flow_action_data { uint8_t unused[7]; /* This value is encap data for the associated encap type. */ uint32_t encap_data[20]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */ -struct hwrm_cfa_flow_tunnel_hdr_data { +__rte_packed_begin struct hwrm_cfa_flow_tunnel_hdr_data { /* Tunnel Type. */ uint8_t tunnel_type; /* Non-tunnel */ @@ -52708,19 +52708,19 @@ struct hwrm_cfa_flow_tunnel_hdr_data { * Virtual Network Identifier (VNI). */ uint32_t tunnel_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */ -struct hwrm_cfa_flow_l4_key_data { +__rte_packed_begin struct hwrm_cfa_flow_l4_key_data { /* The value of source port. */ uint16_t l4_src_port; /* The value of destination port. */ uint16_t l4_dst_port; uint32_t unused; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */ -struct hwrm_cfa_flow_l3_key_data { +__rte_packed_begin struct hwrm_cfa_flow_l3_key_data { /* The value of ip protocol. */ uint8_t ip_protocol; uint8_t unused_0[7]; @@ -52731,10 +52731,10 @@ struct hwrm_cfa_flow_l3_key_data { /* NAT IPv4/IPv6 address. */ uint32_t nat_ip_address[4]; uint32_t unused[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */ -struct hwrm_cfa_flow_l2_key_data { +__rte_packed_begin struct hwrm_cfa_flow_l2_key_data { /* Destination MAC address. */ uint16_t dmac[3]; uint16_t unused_0; @@ -52764,10 +52764,10 @@ struct hwrm_cfa_flow_l2_key_data { /* Inner VLAN TCI. */ uint16_t ivlan_tci; uint8_t unused[8]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_key_data (size:4160b/520B) */ -struct hwrm_cfa_flow_key_data { +__rte_packed_begin struct hwrm_cfa_flow_key_data { /* Flow associated tunnel L2 header key info. */ uint32_t t_l2_key_data[14]; /* Flow associated tunnel L2 header mask info. */ @@ -52794,7 +52794,7 @@ struct hwrm_cfa_flow_key_data { uint32_t l4_key_data[2]; /* Flow associated L4 header mask info. */ uint32_t l4_key_mask[2]; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_cfa_flow_info * @@ -52802,7 +52802,7 @@ struct hwrm_cfa_flow_key_data { /* hwrm_cfa_flow_info_input (size:256b/32B) */ -struct hwrm_cfa_flow_info_input { +__rte_packed_begin struct hwrm_cfa_flow_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52868,10 +52868,10 @@ struct hwrm_cfa_flow_info_input { uint8_t unused_0[6]; /* This value identifies a set of CFA data structures used for a flow. */ uint64_t ext_flow_handle; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_info_output (size:5632b/704B) */ -struct hwrm_cfa_flow_info_output { +__rte_packed_begin struct hwrm_cfa_flow_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52922,7 +52922,7 @@ struct hwrm_cfa_flow_info_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_cfa_flow_flush * @@ -52930,7 +52930,7 @@ struct hwrm_cfa_flow_info_output { /* hwrm_cfa_flow_flush_input (size:256b/32B) */ -struct hwrm_cfa_flow_flush_input { +__rte_packed_begin struct hwrm_cfa_flow_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53045,10 +53045,10 @@ struct hwrm_cfa_flow_flush_input { uint16_t num_flows; /* Pointer to the PBL, or PDL depending on number of levels */ uint64_t page_dir; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_flush_output (size:128b/16B) */ -struct hwrm_cfa_flow_flush_output { +__rte_packed_begin struct hwrm_cfa_flow_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53067,7 +53067,7 @@ struct hwrm_cfa_flow_flush_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_cfa_flow_stats * @@ -53075,7 +53075,7 @@ struct hwrm_cfa_flow_flush_output { /* hwrm_cfa_flow_stats_input (size:640b/80B) */ -struct hwrm_cfa_flow_stats_input { +__rte_packed_begin struct hwrm_cfa_flow_stats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53187,10 +53187,10 @@ struct hwrm_cfa_flow_stats_input { uint32_t flow_id_8; /* Flow ID of a flow. */ uint32_t flow_id_9; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ -struct hwrm_cfa_flow_stats_output { +__rte_packed_begin struct hwrm_cfa_flow_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53258,7 +53258,7 @@ struct hwrm_cfa_flow_stats_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************************** * hwrm_cfa_flow_aging_timer_reset * @@ -53266,7 +53266,7 @@ struct hwrm_cfa_flow_stats_output { /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */ -struct hwrm_cfa_flow_aging_timer_reset_input { +__rte_packed_begin struct hwrm_cfa_flow_aging_timer_reset_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53305,10 +53305,10 @@ struct hwrm_cfa_flow_aging_timer_reset_input { uint32_t flow_timer; /* This value identifies a set of CFA data structures used for a flow. */ uint64_t ext_flow_handle; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */ -struct hwrm_cfa_flow_aging_timer_reset_output { +__rte_packed_begin struct hwrm_cfa_flow_aging_timer_reset_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53327,7 +53327,7 @@ struct hwrm_cfa_flow_aging_timer_reset_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_cfa_flow_aging_cfg * @@ -53335,7 +53335,7 @@ struct hwrm_cfa_flow_aging_timer_reset_output { /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */ -struct hwrm_cfa_flow_aging_cfg_input { +__rte_packed_begin struct hwrm_cfa_flow_aging_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53476,10 +53476,10 @@ struct hwrm_cfa_flow_aging_cfg_input { #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \ HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */ -struct hwrm_cfa_flow_aging_cfg_output { +__rte_packed_begin struct hwrm_cfa_flow_aging_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53498,7 +53498,7 @@ struct hwrm_cfa_flow_aging_cfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_cfa_flow_aging_qcfg * @@ -53506,7 +53506,7 @@ struct hwrm_cfa_flow_aging_cfg_output { /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */ -struct hwrm_cfa_flow_aging_qcfg_input { +__rte_packed_begin struct hwrm_cfa_flow_aging_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53549,10 +53549,10 @@ struct hwrm_cfa_flow_aging_qcfg_input { #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */ -struct hwrm_cfa_flow_aging_qcfg_output { +__rte_packed_begin struct hwrm_cfa_flow_aging_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53602,7 +53602,7 @@ struct hwrm_cfa_flow_aging_qcfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_cfa_flow_aging_qcaps * @@ -53610,7 +53610,7 @@ struct hwrm_cfa_flow_aging_qcfg_output { /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */ -struct hwrm_cfa_flow_aging_qcaps_input { +__rte_packed_begin struct hwrm_cfa_flow_aging_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53653,10 +53653,10 @@ struct hwrm_cfa_flow_aging_qcaps_input { #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */ -struct hwrm_cfa_flow_aging_qcaps_output { +__rte_packed_begin struct hwrm_cfa_flow_aging_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53692,7 +53692,7 @@ struct hwrm_cfa_flow_aging_qcaps_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************** * hwrm_cfa_tcp_flag_process_qcfg * @@ -53700,7 +53700,7 @@ struct hwrm_cfa_flow_aging_qcaps_output { /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */ -struct hwrm_cfa_tcp_flag_process_qcfg_input { +__rte_packed_begin struct hwrm_cfa_tcp_flag_process_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53729,10 +53729,10 @@ struct hwrm_cfa_tcp_flag_process_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */ -struct hwrm_cfa_tcp_flag_process_qcfg_output { +__rte_packed_begin struct hwrm_cfa_tcp_flag_process_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53765,7 +53765,7 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_cfa_vf_pair_alloc * @@ -53773,7 +53773,7 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output { /* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */ -struct hwrm_cfa_vf_pair_alloc_input { +__rte_packed_begin struct hwrm_cfa_vf_pair_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53809,10 +53809,10 @@ struct hwrm_cfa_vf_pair_alloc_input { uint8_t unused_0[4]; /* VF Pair name (32 byte string). */ char pair_name[32]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */ -struct hwrm_cfa_vf_pair_alloc_output { +__rte_packed_begin struct hwrm_cfa_vf_pair_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53831,7 +53831,7 @@ struct hwrm_cfa_vf_pair_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_cfa_vf_pair_free * @@ -53839,7 +53839,7 @@ struct hwrm_cfa_vf_pair_alloc_output { /* hwrm_cfa_vf_pair_free_input (size:384b/48B) */ -struct hwrm_cfa_vf_pair_free_input { +__rte_packed_begin struct hwrm_cfa_vf_pair_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53870,10 +53870,10 @@ struct hwrm_cfa_vf_pair_free_input { uint64_t resp_addr; /* VF Pair name (32 byte string). */ char pair_name[32]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_vf_pair_free_output (size:128b/16B) */ -struct hwrm_cfa_vf_pair_free_output { +__rte_packed_begin struct hwrm_cfa_vf_pair_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53892,7 +53892,7 @@ struct hwrm_cfa_vf_pair_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_cfa_vf_pair_info * @@ -53900,7 +53900,7 @@ struct hwrm_cfa_vf_pair_free_output { /* hwrm_cfa_vf_pair_info_input (size:448b/56B) */ -struct hwrm_cfa_vf_pair_info_input { +__rte_packed_begin struct hwrm_cfa_vf_pair_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53937,10 +53937,10 @@ struct hwrm_cfa_vf_pair_info_input { uint8_t unused_0[2]; /* VF Pair name (32 byte string). */ char vf_pair_name[32]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_vf_pair_info_output (size:512b/64B) */ -struct hwrm_cfa_vf_pair_info_output { +__rte_packed_begin struct hwrm_cfa_vf_pair_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53980,7 +53980,7 @@ struct hwrm_cfa_vf_pair_info_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_cfa_pair_alloc * @@ -53988,7 +53988,7 @@ struct hwrm_cfa_vf_pair_info_output { /* hwrm_cfa_pair_alloc_input (size:576b/72B) */ -struct hwrm_cfa_pair_alloc_input { +__rte_packed_begin struct hwrm_cfa_pair_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54126,10 +54126,10 @@ struct hwrm_cfa_pair_alloc_input { */ uint8_t fc_ba; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_pair_alloc_output (size:192b/24B) */ -struct hwrm_cfa_pair_alloc_output { +__rte_packed_begin struct hwrm_cfa_pair_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54156,7 +54156,7 @@ struct hwrm_cfa_pair_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_cfa_pair_free * @@ -54164,7 +54164,7 @@ struct hwrm_cfa_pair_alloc_output { /* hwrm_cfa_pair_free_input (size:448b/56B) */ -struct hwrm_cfa_pair_free_input { +__rte_packed_begin struct hwrm_cfa_pair_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54238,10 +54238,10 @@ struct hwrm_cfa_pair_free_input { #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7) #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \ HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_pair_free_output (size:128b/16B) */ -struct hwrm_cfa_pair_free_output { +__rte_packed_begin struct hwrm_cfa_pair_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54260,7 +54260,7 @@ struct hwrm_cfa_pair_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_cfa_pair_info * @@ -54268,7 +54268,7 @@ struct hwrm_cfa_pair_free_output { /* hwrm_cfa_pair_info_input (size:448b/56B) */ -struct hwrm_cfa_pair_info_input { +__rte_packed_begin struct hwrm_cfa_pair_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54310,10 +54310,10 @@ struct hwrm_cfa_pair_info_input { uint8_t pair_vfid; /* Pair name (32 byte string). */ char pair_name[32]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_pair_info_output (size:576b/72B) */ -struct hwrm_cfa_pair_info_output { +__rte_packed_begin struct hwrm_cfa_pair_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54391,7 +54391,7 @@ struct hwrm_cfa_pair_info_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_cfa_vfr_alloc * @@ -54399,7 +54399,7 @@ struct hwrm_cfa_pair_info_output { /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ -struct hwrm_cfa_vfr_alloc_input { +__rte_packed_begin struct hwrm_cfa_vfr_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54438,10 +54438,10 @@ struct hwrm_cfa_vfr_alloc_input { uint8_t unused_0[4]; /* VF Representor name (32 byte string). */ char vfr_name[32]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ -struct hwrm_cfa_vfr_alloc_output { +__rte_packed_begin struct hwrm_cfa_vfr_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54464,7 +54464,7 @@ struct hwrm_cfa_vfr_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_cfa_vfr_free * @@ -54472,7 +54472,7 @@ struct hwrm_cfa_vfr_alloc_output { /* hwrm_cfa_vfr_free_input (size:448b/56B) */ -struct hwrm_cfa_vfr_free_input { +__rte_packed_begin struct hwrm_cfa_vfr_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54511,10 +54511,10 @@ struct hwrm_cfa_vfr_free_input { */ uint16_t reserved; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_vfr_free_output (size:128b/16B) */ -struct hwrm_cfa_vfr_free_output { +__rte_packed_begin struct hwrm_cfa_vfr_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54533,7 +54533,7 @@ struct hwrm_cfa_vfr_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************************** * hwrm_cfa_redirect_query_tunnel_type * @@ -54541,7 +54541,7 @@ struct hwrm_cfa_vfr_free_output { /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */ -struct hwrm_cfa_redirect_query_tunnel_type_input { +__rte_packed_begin struct hwrm_cfa_redirect_query_tunnel_type_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54573,10 +54573,10 @@ struct hwrm_cfa_redirect_query_tunnel_type_input { /* The source function id. */ uint16_t src_fid; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */ -struct hwrm_cfa_redirect_query_tunnel_type_output { +__rte_packed_begin struct hwrm_cfa_redirect_query_tunnel_type_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54648,7 +54648,7 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_cfa_ctx_mem_rgtr * @@ -54656,7 +54656,7 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */ -struct hwrm_cfa_ctx_mem_rgtr_input { +__rte_packed_begin struct hwrm_cfa_ctx_mem_rgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54722,10 +54722,10 @@ struct hwrm_cfa_ctx_mem_rgtr_input { uint32_t unused_0; /* Pointer to the PBL, or PDL depending on number of levels */ uint64_t page_dir; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_rgtr_output { +__rte_packed_begin struct hwrm_cfa_ctx_mem_rgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54749,7 +54749,7 @@ struct hwrm_cfa_ctx_mem_rgtr_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_cfa_ctx_mem_unrgtr * @@ -54757,7 +54757,7 @@ struct hwrm_cfa_ctx_mem_rgtr_output { /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */ -struct hwrm_cfa_ctx_mem_unrgtr_input { +__rte_packed_begin struct hwrm_cfa_ctx_mem_unrgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54792,10 +54792,10 @@ struct hwrm_cfa_ctx_mem_unrgtr_input { */ uint16_t ctx_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_unrgtr_output { +__rte_packed_begin struct hwrm_cfa_ctx_mem_unrgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54814,7 +54814,7 @@ struct hwrm_cfa_ctx_mem_unrgtr_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_cfa_ctx_mem_qctx * @@ -54822,7 +54822,7 @@ struct hwrm_cfa_ctx_mem_unrgtr_output { /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */ -struct hwrm_cfa_ctx_mem_qctx_input { +__rte_packed_begin struct hwrm_cfa_ctx_mem_qctx_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54857,10 +54857,10 @@ struct hwrm_cfa_ctx_mem_qctx_input { */ uint16_t ctx_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */ -struct hwrm_cfa_ctx_mem_qctx_output { +__rte_packed_begin struct hwrm_cfa_ctx_mem_qctx_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54916,7 +54916,7 @@ struct hwrm_cfa_ctx_mem_qctx_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_cfa_ctx_mem_qcaps * @@ -54924,7 +54924,7 @@ struct hwrm_cfa_ctx_mem_qctx_output { /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_qcaps_input { +__rte_packed_begin struct hwrm_cfa_ctx_mem_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54953,10 +54953,10 @@ struct hwrm_cfa_ctx_mem_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_qcaps_output { +__rte_packed_begin struct hwrm_cfa_ctx_mem_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54980,7 +54980,7 @@ struct hwrm_cfa_ctx_mem_qcaps_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_cfa_counter_qcaps * @@ -54988,7 +54988,7 @@ struct hwrm_cfa_ctx_mem_qcaps_output { /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */ -struct hwrm_cfa_counter_qcaps_input { +__rte_packed_begin struct hwrm_cfa_counter_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55017,10 +55017,10 @@ struct hwrm_cfa_counter_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */ -struct hwrm_cfa_counter_qcaps_output { +__rte_packed_begin struct hwrm_cfa_counter_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55117,7 +55117,7 @@ struct hwrm_cfa_counter_qcaps_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_cfa_counter_cfg * @@ -55125,7 +55125,7 @@ struct hwrm_cfa_counter_qcaps_output { /* hwrm_cfa_counter_cfg_input (size:256b/32B) */ -struct hwrm_cfa_counter_cfg_input { +__rte_packed_begin struct hwrm_cfa_counter_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55208,10 +55208,10 @@ struct hwrm_cfa_counter_cfg_input { /* Total number of entries. */ uint32_t num_entries; uint32_t unused_0; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_counter_cfg_output (size:128b/16B) */ -struct hwrm_cfa_counter_cfg_output { +__rte_packed_begin struct hwrm_cfa_counter_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55230,7 +55230,7 @@ struct hwrm_cfa_counter_cfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_cfa_counter_qstats * @@ -55238,7 +55238,7 @@ struct hwrm_cfa_counter_cfg_output { /* hwrm_cfa_counter_qstats_input (size:320b/40B) */ -struct hwrm_cfa_counter_qstats_input { +__rte_packed_begin struct hwrm_cfa_counter_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55284,10 +55284,10 @@ struct hwrm_cfa_counter_qstats_input { uint16_t mdc_ctx_id; uint8_t unused_0[2]; uint64_t expected_count; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_counter_qstats_output (size:128b/16B) */ -struct hwrm_cfa_counter_qstats_output { +__rte_packed_begin struct hwrm_cfa_counter_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55306,7 +55306,7 @@ struct hwrm_cfa_counter_qstats_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_cfa_eem_qcaps * @@ -55314,7 +55314,7 @@ struct hwrm_cfa_counter_qstats_output { /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ -struct hwrm_cfa_eem_qcaps_input { +__rte_packed_begin struct hwrm_cfa_eem_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55362,10 +55362,10 @@ struct hwrm_cfa_eem_qcaps_input { #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ UINT32_C(0x4) uint32_t unused_0; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ -struct hwrm_cfa_eem_qcaps_output { +__rte_packed_begin struct hwrm_cfa_eem_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55468,7 +55468,7 @@ struct hwrm_cfa_eem_qcaps_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************** * hwrm_cfa_eem_cfg * @@ -55476,7 +55476,7 @@ struct hwrm_cfa_eem_qcaps_output { /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ -struct hwrm_cfa_eem_cfg_input { +__rte_packed_begin struct hwrm_cfa_eem_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55552,10 +55552,10 @@ struct hwrm_cfa_eem_cfg_input { uint16_t fid_ctx_id; uint16_t unused_2; uint32_t unused_3; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ -struct hwrm_cfa_eem_cfg_output { +__rte_packed_begin struct hwrm_cfa_eem_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55574,7 +55574,7 @@ struct hwrm_cfa_eem_cfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_cfa_eem_qcfg * @@ -55582,7 +55582,7 @@ struct hwrm_cfa_eem_cfg_output { /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ -struct hwrm_cfa_eem_qcfg_input { +__rte_packed_begin struct hwrm_cfa_eem_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55617,10 +55617,10 @@ struct hwrm_cfa_eem_qcfg_input { /* When set to 1, indicates the configuration is the RX flow. */ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) uint32_t unused_0; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ -struct hwrm_cfa_eem_qcfg_output { +__rte_packed_begin struct hwrm_cfa_eem_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55661,7 +55661,7 @@ struct hwrm_cfa_eem_qcfg_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_cfa_eem_op * @@ -55669,7 +55669,7 @@ struct hwrm_cfa_eem_qcfg_output { /* hwrm_cfa_eem_op_input (size:192b/24B) */ -struct hwrm_cfa_eem_op_input { +__rte_packed_begin struct hwrm_cfa_eem_op_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55737,10 +55737,10 @@ struct hwrm_cfa_eem_op_input { #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3) #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \ HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_eem_op_output (size:128b/16B) */ -struct hwrm_cfa_eem_op_output { +__rte_packed_begin struct hwrm_cfa_eem_op_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55759,7 +55759,7 @@ struct hwrm_cfa_eem_op_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************** * hwrm_cfa_adv_flow_mgnt_qcaps * @@ -55767,7 +55767,7 @@ struct hwrm_cfa_eem_op_output { /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ -struct hwrm_cfa_adv_flow_mgnt_qcaps_input { +__rte_packed_begin struct hwrm_cfa_adv_flow_mgnt_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55797,10 +55797,10 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input { */ uint64_t resp_addr; uint32_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ -struct hwrm_cfa_adv_flow_mgnt_qcaps_output { +__rte_packed_begin struct hwrm_cfa_adv_flow_mgnt_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55977,7 +55977,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************** * hwrm_cfa_tflib * @@ -55985,7 +55985,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { /* hwrm_cfa_tflib_input (size:1024b/128B) */ -struct hwrm_cfa_tflib_input { +__rte_packed_begin struct hwrm_cfa_tflib_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56022,10 +56022,10 @@ struct hwrm_cfa_tflib_input { uint8_t unused0[4]; /* TFLIB request data. */ uint32_t tf_req[26]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_tflib_output (size:5632b/704B) */ -struct hwrm_cfa_tflib_output { +__rte_packed_begin struct hwrm_cfa_tflib_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56053,7 +56053,7 @@ struct hwrm_cfa_tflib_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************** * hwrm_cfa_lag_group_member_rgtr * @@ -56061,7 +56061,7 @@ struct hwrm_cfa_tflib_output { /* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */ -struct hwrm_cfa_lag_group_member_rgtr_input { +__rte_packed_begin struct hwrm_cfa_lag_group_member_rgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56122,10 +56122,10 @@ struct hwrm_cfa_lag_group_member_rgtr_input { /* Specify the active port when active-backup mode is specified */ uint8_t active_port; uint8_t unused_0[5]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */ -struct hwrm_cfa_lag_group_member_rgtr_output { +__rte_packed_begin struct hwrm_cfa_lag_group_member_rgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56146,7 +56146,7 @@ struct hwrm_cfa_lag_group_member_rgtr_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************************ * hwrm_cfa_lag_group_member_unrgtr * @@ -56154,7 +56154,7 @@ struct hwrm_cfa_lag_group_member_rgtr_output { /* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */ -struct hwrm_cfa_lag_group_member_unrgtr_input { +__rte_packed_begin struct hwrm_cfa_lag_group_member_unrgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56186,10 +56186,10 @@ struct hwrm_cfa_lag_group_member_unrgtr_input { /* lag group ID configured for the function */ uint16_t lag_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */ -struct hwrm_cfa_lag_group_member_unrgtr_output { +__rte_packed_begin struct hwrm_cfa_lag_group_member_unrgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56208,7 +56208,7 @@ struct hwrm_cfa_lag_group_member_unrgtr_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_cfa_tls_filter_alloc * @@ -56216,7 +56216,7 @@ struct hwrm_cfa_lag_group_member_unrgtr_output { /* hwrm_cfa_tls_filter_alloc_input (size:768b/96B) */ -struct hwrm_cfa_tls_filter_alloc_input { +__rte_packed_begin struct hwrm_cfa_tls_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56403,10 +56403,10 @@ struct hwrm_cfa_tls_filter_alloc_input { uint32_t kid; /* The Destination Connection ID of QUIC. */ uint64_t quic_dst_connect_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_tls_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_tls_filter_alloc_output { +__rte_packed_begin struct hwrm_cfa_tls_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56467,7 +56467,7 @@ struct hwrm_cfa_tls_filter_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_cfa_tls_filter_free * @@ -56475,7 +56475,7 @@ struct hwrm_cfa_tls_filter_alloc_output { /* hwrm_cfa_tls_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_tls_filter_free_input { +__rte_packed_begin struct hwrm_cfa_tls_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56506,10 +56506,10 @@ struct hwrm_cfa_tls_filter_free_input { uint64_t resp_addr; /* This value is an opaque id into CFA data structures. */ uint64_t tls_filter_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_tls_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_tls_filter_free_output { +__rte_packed_begin struct hwrm_cfa_tls_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56528,7 +56528,7 @@ struct hwrm_cfa_tls_filter_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_cfa_release_afm_func * @@ -56536,7 +56536,7 @@ struct hwrm_cfa_tls_filter_free_output { /* hwrm_cfa_release_afm_func_input (size:256b/32B) */ -struct hwrm_cfa_release_afm_func_input { +__rte_packed_begin struct hwrm_cfa_release_afm_func_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56595,10 +56595,10 @@ struct hwrm_cfa_release_afm_func_input { #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_PROMISC_REM \ UINT32_C(0x4) uint32_t unused_1; -} __rte_packed; +} __rte_packed_end; /* hwrm_cfa_release_afm_func_output (size:128b/16B) */ -struct hwrm_cfa_release_afm_func_output { +__rte_packed_begin struct hwrm_cfa_release_afm_func_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56617,7 +56617,7 @@ struct hwrm_cfa_release_afm_func_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********** * hwrm_tf * @@ -56625,7 +56625,7 @@ struct hwrm_cfa_release_afm_func_output { /* hwrm_tf_input (size:1024b/128B) */ -struct hwrm_tf_input { +__rte_packed_begin struct hwrm_tf_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56662,10 +56662,10 @@ struct hwrm_tf_input { uint8_t unused0[4]; /* TF request data. */ uint32_t req[26]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_output (size:5632b/704B) */ -struct hwrm_tf_output { +__rte_packed_begin struct hwrm_tf_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56693,7 +56693,7 @@ struct hwrm_tf_output { * to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_tf_version_get * @@ -56701,7 +56701,7 @@ struct hwrm_tf_output { /* hwrm_tf_version_get_input (size:128b/16B) */ -struct hwrm_tf_version_get_input { +__rte_packed_begin struct hwrm_tf_version_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56730,10 +56730,10 @@ struct hwrm_tf_version_get_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_version_get_output (size:256b/32B) */ -struct hwrm_tf_version_get_output { +__rte_packed_begin struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56766,7 +56766,7 @@ struct hwrm_tf_version_get_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_tf_session_open * @@ -56774,7 +56774,7 @@ struct hwrm_tf_version_get_output { /* hwrm_tf_session_open_input (size:640b/80B) */ -struct hwrm_tf_session_open_input { +__rte_packed_begin struct hwrm_tf_session_open_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56805,10 +56805,10 @@ struct hwrm_tf_session_open_input { uint64_t resp_addr; /* Name of the session. */ uint8_t session_name[64]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_session_open_output (size:192b/24B) */ -struct hwrm_tf_session_open_output { +__rte_packed_begin struct hwrm_tf_session_open_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56861,7 +56861,7 @@ struct hwrm_tf_session_open_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_tf_session_register * @@ -56869,7 +56869,7 @@ struct hwrm_tf_session_open_output { /* hwrm_tf_session_register_input (size:704b/88B) */ -struct hwrm_tf_session_register_input { +__rte_packed_begin struct hwrm_tf_session_register_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56911,10 +56911,10 @@ struct hwrm_tf_session_register_input { uint32_t unused0; /* Name of the session client. */ uint8_t session_client_name[64]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_session_register_output (size:128b/16B) */ -struct hwrm_tf_session_register_output { +__rte_packed_begin struct hwrm_tf_session_register_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56940,7 +56940,7 @@ struct hwrm_tf_session_register_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_tf_session_unregister * @@ -56948,7 +56948,7 @@ struct hwrm_tf_session_register_output { /* hwrm_tf_session_unregister_input (size:192b/24B) */ -struct hwrm_tf_session_unregister_input { +__rte_packed_begin struct hwrm_tf_session_unregister_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56987,10 +56987,10 @@ struct hwrm_tf_session_unregister_input { * unregister request want to close. */ uint32_t fw_session_client_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_session_unregister_output (size:128b/16B) */ -struct hwrm_tf_session_unregister_output { +__rte_packed_begin struct hwrm_tf_session_unregister_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57010,7 +57010,7 @@ struct hwrm_tf_session_unregister_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_tf_session_close * @@ -57018,7 +57018,7 @@ struct hwrm_tf_session_unregister_output { /* hwrm_tf_session_close_input (size:192b/24B) */ -struct hwrm_tf_session_close_input { +__rte_packed_begin struct hwrm_tf_session_close_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57051,10 +57051,10 @@ struct hwrm_tf_session_close_input { uint32_t fw_session_id; /* unused. */ uint8_t unused0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_session_close_output (size:128b/16B) */ -struct hwrm_tf_session_close_output { +__rte_packed_begin struct hwrm_tf_session_close_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57074,7 +57074,7 @@ struct hwrm_tf_session_close_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_tf_session_qcfg * @@ -57082,7 +57082,7 @@ struct hwrm_tf_session_close_output { /* hwrm_tf_session_qcfg_input (size:192b/24B) */ -struct hwrm_tf_session_qcfg_input { +__rte_packed_begin struct hwrm_tf_session_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57115,10 +57115,10 @@ struct hwrm_tf_session_qcfg_input { uint32_t fw_session_id; /* unused. */ uint8_t unused0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_session_qcfg_output (size:128b/16B) */ -struct hwrm_tf_session_qcfg_output { +__rte_packed_begin struct hwrm_tf_session_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57186,7 +57186,7 @@ struct hwrm_tf_session_qcfg_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_tf_session_resc_qcaps * @@ -57194,7 +57194,7 @@ struct hwrm_tf_session_qcfg_output { /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */ -struct hwrm_tf_session_resc_qcaps_input { +__rte_packed_begin struct hwrm_tf_session_resc_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57249,10 +57249,10 @@ struct hwrm_tf_session_resc_qcaps_input { * device specific. */ uint64_t qcaps_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */ -struct hwrm_tf_session_resc_qcaps_output { +__rte_packed_begin struct hwrm_tf_session_resc_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57306,7 +57306,7 @@ struct hwrm_tf_session_resc_qcaps_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_tf_session_resc_alloc * @@ -57314,7 +57314,7 @@ struct hwrm_tf_session_resc_qcaps_output { /* hwrm_tf_session_resc_alloc_input (size:320b/40B) */ -struct hwrm_tf_session_resc_alloc_input { +__rte_packed_begin struct hwrm_tf_session_resc_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57375,10 +57375,10 @@ struct hwrm_tf_session_resc_alloc_input { * message. */ uint64_t resc_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */ -struct hwrm_tf_session_resc_alloc_output { +__rte_packed_begin struct hwrm_tf_session_resc_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57405,7 +57405,7 @@ struct hwrm_tf_session_resc_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_tf_session_resc_flush * @@ -57413,7 +57413,7 @@ struct hwrm_tf_session_resc_alloc_output { /* hwrm_tf_session_resc_flush_input (size:256b/32B) */ -struct hwrm_tf_session_resc_flush_input { +__rte_packed_begin struct hwrm_tf_session_resc_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57466,10 +57466,10 @@ struct hwrm_tf_session_resc_flush_input { * message. */ uint64_t flush_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_session_resc_flush_output (size:128b/16B) */ -struct hwrm_tf_session_resc_flush_output { +__rte_packed_begin struct hwrm_tf_session_resc_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57489,7 +57489,7 @@ struct hwrm_tf_session_resc_flush_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_tf_session_resc_info * @@ -57497,7 +57497,7 @@ struct hwrm_tf_session_resc_flush_output { /* hwrm_tf_session_resc_info_input (size:320b/40B) */ -struct hwrm_tf_session_resc_info_input { +__rte_packed_begin struct hwrm_tf_session_resc_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57558,10 +57558,10 @@ struct hwrm_tf_session_resc_info_input { * message. */ uint64_t resc_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_session_resc_info_output (size:128b/16B) */ -struct hwrm_tf_session_resc_info_output { +__rte_packed_begin struct hwrm_tf_session_resc_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57588,29 +57588,29 @@ struct hwrm_tf_session_resc_info_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* TruFlow RM capability of a resource. */ /* tf_rm_resc_req_entry (size:64b/8B) */ -struct tf_rm_resc_req_entry { +__rte_packed_begin struct tf_rm_resc_req_entry { /* Type of the resource, defined globally in HCAPI RM. */ uint32_t type; /* Minimum value. */ uint16_t min; /* Maximum value. */ uint16_t max; -} __rte_packed; +} __rte_packed_end; /* TruFlow RM reservation information. */ /* tf_rm_resc_entry (size:64b/8B) */ -struct tf_rm_resc_entry { +__rte_packed_begin struct tf_rm_resc_entry { /* Type of the resource, defined globally in HCAPI RM. */ uint32_t type; /* Start offset. */ uint16_t start; /* Number of resources. */ uint16_t stride; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_tf_tbl_type_alloc * @@ -57618,7 +57618,7 @@ struct tf_rm_resc_entry { /* hwrm_tf_tbl_type_alloc_input (size:192b/24B) */ -struct hwrm_tf_tbl_type_alloc_input { +__rte_packed_begin struct hwrm_tf_tbl_type_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57681,10 +57681,10 @@ struct hwrm_tf_tbl_type_alloc_input { * tunnel-type of dynamic UPAR tunnel. */ uint8_t type; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_tbl_type_alloc_output (size:128b/16B) */ -struct hwrm_tf_tbl_type_alloc_output { +__rte_packed_begin struct hwrm_tf_tbl_type_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57711,7 +57711,7 @@ struct hwrm_tf_tbl_type_alloc_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_tf_tbl_type_get * @@ -57719,7 +57719,7 @@ struct hwrm_tf_tbl_type_alloc_output { /* hwrm_tf_tbl_type_get_input (size:256b/32B) */ -struct hwrm_tf_tbl_type_get_input { +__rte_packed_begin struct hwrm_tf_tbl_type_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57794,10 +57794,10 @@ struct hwrm_tf_tbl_type_get_input { uint32_t type; /* Index of the type to retrieve. */ uint32_t index; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_tbl_type_get_output (size:2240b/280B) */ -struct hwrm_tf_tbl_type_get_output { +__rte_packed_begin struct hwrm_tf_tbl_type_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57825,7 +57825,7 @@ struct hwrm_tf_tbl_type_get_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_tf_tbl_type_set * @@ -57833,7 +57833,7 @@ struct hwrm_tf_tbl_type_get_output { /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */ -struct hwrm_tf_tbl_type_set_input { +__rte_packed_begin struct hwrm_tf_tbl_type_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57907,10 +57907,10 @@ struct hwrm_tf_tbl_type_set_input { uint8_t unused1[6]; /* Data to be set. */ uint8_t data[88]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_tbl_type_set_output (size:128b/16B) */ -struct hwrm_tf_tbl_type_set_output { +__rte_packed_begin struct hwrm_tf_tbl_type_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57930,7 +57930,7 @@ struct hwrm_tf_tbl_type_set_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_tf_tbl_type_free * @@ -57938,7 +57938,7 @@ struct hwrm_tf_tbl_type_set_output { /* hwrm_tf_tbl_type_free_input (size:256b/32B) */ -struct hwrm_tf_tbl_type_free_input { +__rte_packed_begin struct hwrm_tf_tbl_type_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58004,10 +58004,10 @@ struct hwrm_tf_tbl_type_free_input { uint16_t idx_tbl_id; /* Unused */ uint8_t unused1[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_tbl_type_free_output (size:128b/16B) */ -struct hwrm_tf_tbl_type_free_output { +__rte_packed_begin struct hwrm_tf_tbl_type_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58029,7 +58029,7 @@ struct hwrm_tf_tbl_type_free_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_tf_em_insert * @@ -58037,7 +58037,7 @@ struct hwrm_tf_tbl_type_free_output { /* hwrm_tf_em_insert_input (size:832b/104B) */ -struct hwrm_tf_em_insert_input { +__rte_packed_begin struct hwrm_tf_em_insert_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58090,10 +58090,10 @@ struct hwrm_tf_em_insert_input { uint16_t em_key_bitlen; /* unused. */ uint16_t unused0[3]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_em_insert_output (size:128b/16B) */ -struct hwrm_tf_em_insert_output { +__rte_packed_begin struct hwrm_tf_em_insert_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58119,7 +58119,7 @@ struct hwrm_tf_em_insert_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_tf_em_hash_insert * @@ -58127,7 +58127,7 @@ struct hwrm_tf_em_insert_output { /* hwrm_tf_em_hash_insert_input (size:1024b/128B) */ -struct hwrm_tf_em_hash_insert_input { +__rte_packed_begin struct hwrm_tf_em_hash_insert_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58182,10 +58182,10 @@ struct hwrm_tf_em_hash_insert_input { uint32_t unused0; /* EM record. */ uint64_t em_record[11]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_em_hash_insert_output (size:128b/16B) */ -struct hwrm_tf_em_hash_insert_output { +__rte_packed_begin struct hwrm_tf_em_hash_insert_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58211,7 +58211,7 @@ struct hwrm_tf_em_hash_insert_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_tf_em_delete * @@ -58219,7 +58219,7 @@ struct hwrm_tf_em_hash_insert_output { /* hwrm_tf_em_delete_input (size:832b/104B) */ -struct hwrm_tf_em_delete_input { +__rte_packed_begin struct hwrm_tf_em_delete_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58270,10 +58270,10 @@ struct hwrm_tf_em_delete_input { uint16_t em_key_bitlen; /* unused. */ uint16_t unused1[3]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_em_delete_output (size:128b/16B) */ -struct hwrm_tf_em_delete_output { +__rte_packed_begin struct hwrm_tf_em_delete_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58295,7 +58295,7 @@ struct hwrm_tf_em_delete_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_tf_em_move * @@ -58303,7 +58303,7 @@ struct hwrm_tf_em_delete_output { /* hwrm_tf_em_move_input (size:320b/40B) */ -struct hwrm_tf_em_move_input { +__rte_packed_begin struct hwrm_tf_em_move_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58352,10 +58352,10 @@ struct hwrm_tf_em_move_input { uint32_t unused0; /* EM internal flow handle. */ uint64_t flow_handle; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_em_move_output (size:128b/16B) */ -struct hwrm_tf_em_move_output { +__rte_packed_begin struct hwrm_tf_em_move_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58377,7 +58377,7 @@ struct hwrm_tf_em_move_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************** * hwrm_tf_tcam_set * @@ -58385,7 +58385,7 @@ struct hwrm_tf_em_move_output { /* hwrm_tf_tcam_set_input (size:1024b/128B) */ -struct hwrm_tf_tcam_set_input { +__rte_packed_begin struct hwrm_tf_tcam_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58456,10 +58456,10 @@ struct hwrm_tf_tcam_set_input { * and result at result_offset for the device. */ uint8_t dev_data[88]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_tcam_set_output (size:128b/16B) */ -struct hwrm_tf_tcam_set_output { +__rte_packed_begin struct hwrm_tf_tcam_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58479,7 +58479,7 @@ struct hwrm_tf_tcam_set_output { * to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************** * hwrm_tf_tcam_get * @@ -58487,7 +58487,7 @@ struct hwrm_tf_tcam_set_output { /* hwrm_tf_tcam_get_input (size:256b/32B) */ -struct hwrm_tf_tcam_get_input { +__rte_packed_begin struct hwrm_tf_tcam_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58537,10 +58537,10 @@ struct hwrm_tf_tcam_get_input { uint16_t idx; /* unused. */ uint16_t unused0; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_tcam_get_output (size:2368b/296B) */ -struct hwrm_tf_tcam_get_output { +__rte_packed_begin struct hwrm_tf_tcam_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58575,7 +58575,7 @@ struct hwrm_tf_tcam_get_output { * to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_tf_tcam_move * @@ -58583,7 +58583,7 @@ struct hwrm_tf_tcam_get_output { /* hwrm_tf_tcam_move_input (size:1024b/128B) */ -struct hwrm_tf_tcam_move_input { +__rte_packed_begin struct hwrm_tf_tcam_move_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58635,10 +58635,10 @@ struct hwrm_tf_tcam_move_input { uint16_t unused0; /* TCAM index pairs to be swapped for the device. */ uint16_t idx_pairs[48]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_tcam_move_output (size:128b/16B) */ -struct hwrm_tf_tcam_move_output { +__rte_packed_begin struct hwrm_tf_tcam_move_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58658,7 +58658,7 @@ struct hwrm_tf_tcam_move_output { * to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_tf_tcam_free * @@ -58666,7 +58666,7 @@ struct hwrm_tf_tcam_move_output { /* hwrm_tf_tcam_free_input (size:1024b/128B) */ -struct hwrm_tf_tcam_free_input { +__rte_packed_begin struct hwrm_tf_tcam_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58718,10 +58718,10 @@ struct hwrm_tf_tcam_free_input { uint16_t unused0; /* TCAM index list to be deleted for the device. */ uint16_t idx_list[48]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_tcam_free_output (size:128b/16B) */ -struct hwrm_tf_tcam_free_output { +__rte_packed_begin struct hwrm_tf_tcam_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58741,7 +58741,7 @@ struct hwrm_tf_tcam_free_output { * to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_tf_global_cfg_set * @@ -58749,7 +58749,7 @@ struct hwrm_tf_tcam_free_output { /* hwrm_tf_global_cfg_set_input (size:448b/56B) */ -struct hwrm_tf_global_cfg_set_input { +__rte_packed_begin struct hwrm_tf_global_cfg_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58804,10 +58804,10 @@ struct hwrm_tf_global_cfg_set_input { uint8_t data[8]; /* Mask of data to set, 0 indicates no mask */ uint8_t mask[8]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_global_cfg_set_output (size:128b/16B) */ -struct hwrm_tf_global_cfg_set_output { +__rte_packed_begin struct hwrm_tf_global_cfg_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58827,7 +58827,7 @@ struct hwrm_tf_global_cfg_set_output { * to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_tf_global_cfg_get * @@ -58835,7 +58835,7 @@ struct hwrm_tf_global_cfg_set_output { /* hwrm_tf_global_cfg_get_input (size:320b/40B) */ -struct hwrm_tf_global_cfg_get_input { +__rte_packed_begin struct hwrm_tf_global_cfg_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58884,10 +58884,10 @@ struct hwrm_tf_global_cfg_get_input { uint16_t size; /* unused. */ uint8_t unused0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_global_cfg_get_output (size:2240b/280B) */ -struct hwrm_tf_global_cfg_get_output { +__rte_packed_begin struct hwrm_tf_global_cfg_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58913,7 +58913,7 @@ struct hwrm_tf_global_cfg_get_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_tf_if_tbl_get * @@ -58921,7 +58921,7 @@ struct hwrm_tf_global_cfg_get_output { /* hwrm_tf_if_tbl_get_input (size:256b/32B) */ -struct hwrm_tf_if_tbl_get_input { +__rte_packed_begin struct hwrm_tf_if_tbl_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58971,10 +58971,10 @@ struct hwrm_tf_if_tbl_get_input { uint32_t type; /* Index of the type to retrieve. */ uint32_t index; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_if_tbl_get_output (size:1216b/152B) */ -struct hwrm_tf_if_tbl_get_output { +__rte_packed_begin struct hwrm_tf_if_tbl_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59002,7 +59002,7 @@ struct hwrm_tf_if_tbl_get_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_tf_if_tbl_type_set * @@ -59010,7 +59010,7 @@ struct hwrm_tf_if_tbl_get_output { /* hwrm_tf_if_tbl_set_input (size:1024b/128B) */ -struct hwrm_tf_if_tbl_set_input { +__rte_packed_begin struct hwrm_tf_if_tbl_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59066,10 +59066,10 @@ struct hwrm_tf_if_tbl_set_input { uint8_t unused1[6]; /* Data to be set. */ uint8_t data[88]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_if_tbl_set_output (size:128b/16B) */ -struct hwrm_tf_if_tbl_set_output { +__rte_packed_begin struct hwrm_tf_if_tbl_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59089,7 +59089,7 @@ struct hwrm_tf_if_tbl_set_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_tf_tbl_type_bulk_get * @@ -59097,7 +59097,7 @@ struct hwrm_tf_if_tbl_set_output { /* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */ -struct hwrm_tf_tbl_type_bulk_get_input { +__rte_packed_begin struct hwrm_tf_tbl_type_bulk_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59162,10 +59162,10 @@ struct hwrm_tf_tbl_type_bulk_get_input { uint32_t unused1; /* Host memory where data will be stored. */ uint64_t host_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */ -struct hwrm_tf_tbl_type_bulk_get_output { +__rte_packed_begin struct hwrm_tf_tbl_type_bulk_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59189,7 +59189,7 @@ struct hwrm_tf_tbl_type_bulk_get_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************************** * hwrm_tf_session_hotup_state_set * @@ -59197,7 +59197,7 @@ struct hwrm_tf_tbl_type_bulk_get_output { /* hwrm_tf_session_hotup_state_set_input (size:192b/24B) */ -struct hwrm_tf_session_hotup_state_set_input { +__rte_packed_begin struct hwrm_tf_session_hotup_state_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59243,10 +59243,10 @@ struct hwrm_tf_session_hotup_state_set_input { UINT32_C(0x1) #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_session_hotup_state_set_output (size:128b/16B) */ -struct hwrm_tf_session_hotup_state_set_output { +__rte_packed_begin struct hwrm_tf_session_hotup_state_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59266,7 +59266,7 @@ struct hwrm_tf_session_hotup_state_set_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************************** * hwrm_tf_session_hotup_state_get * @@ -59274,7 +59274,7 @@ struct hwrm_tf_session_hotup_state_set_output { /* hwrm_tf_session_hotup_state_get_input (size:192b/24B) */ -struct hwrm_tf_session_hotup_state_get_input { +__rte_packed_begin struct hwrm_tf_session_hotup_state_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59320,10 +59320,10 @@ struct hwrm_tf_session_hotup_state_get_input { HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX /* unused. */ uint8_t unused0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_session_hotup_state_get_output (size:128b/16B) */ -struct hwrm_tf_session_hotup_state_get_output { +__rte_packed_begin struct hwrm_tf_session_hotup_state_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59347,7 +59347,7 @@ struct hwrm_tf_session_hotup_state_get_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_tf_resc_usage_set * @@ -59355,7 +59355,7 @@ struct hwrm_tf_session_hotup_state_get_output { /* hwrm_tf_resc_usage_set_input (size:1024b/128B) */ -struct hwrm_tf_resc_usage_set_input { +__rte_packed_begin struct hwrm_tf_resc_usage_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59430,10 +59430,10 @@ struct hwrm_tf_resc_usage_set_input { uint8_t unused1[6]; /* Data to be set. */ uint8_t data[96]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_resc_usage_set_output (size:128b/16B) */ -struct hwrm_tf_resc_usage_set_output { +__rte_packed_begin struct hwrm_tf_resc_usage_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59453,7 +59453,7 @@ struct hwrm_tf_resc_usage_set_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_tf_resc_usage_query * @@ -59461,7 +59461,7 @@ struct hwrm_tf_resc_usage_set_output { /* hwrm_tf_resc_usage_query_input (size:256b/32B) */ -struct hwrm_tf_resc_usage_query_input { +__rte_packed_begin struct hwrm_tf_resc_usage_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59532,10 +59532,10 @@ struct hwrm_tf_resc_usage_query_input { UINT32_C(0x80) /* unused */ uint8_t unused1[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tf_resc_usage_query_output (size:960b/120B) */ -struct hwrm_tf_resc_usage_query_output { +__rte_packed_begin struct hwrm_tf_resc_usage_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59563,7 +59563,7 @@ struct hwrm_tf_resc_usage_query_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_tfc_tbl_scope_qcaps * @@ -59575,7 +59575,7 @@ struct hwrm_tf_resc_usage_query_output { * supporting table scopes. */ /* hwrm_tfc_tbl_scope_qcaps_input (size:128b/16B) */ -struct hwrm_tfc_tbl_scope_qcaps_input { +__rte_packed_begin struct hwrm_tfc_tbl_scope_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59604,10 +59604,10 @@ struct hwrm_tfc_tbl_scope_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tbl_scope_qcaps_output (size:192b/24B) */ -struct hwrm_tfc_tbl_scope_qcaps_output { +__rte_packed_begin struct hwrm_tfc_tbl_scope_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59644,7 +59644,7 @@ struct hwrm_tfc_tbl_scope_qcaps_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_tfc_tbl_scope_id_alloc * @@ -59661,7 +59661,7 @@ struct hwrm_tfc_tbl_scope_qcaps_output { * been freed. */ /* hwrm_tfc_tbl_scope_id_alloc_input (size:256b/32B) */ -struct hwrm_tfc_tbl_scope_id_alloc_input { +__rte_packed_begin struct hwrm_tfc_tbl_scope_id_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59721,10 +59721,10 @@ struct hwrm_tfc_tbl_scope_id_alloc_input { uint8_t app_type; /* unused. */ uint8_t unused0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tbl_scope_id_alloc_output (size:128b/16B) */ -struct hwrm_tfc_tbl_scope_id_alloc_output { +__rte_packed_begin struct hwrm_tfc_tbl_scope_id_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59751,7 +59751,7 @@ struct hwrm_tfc_tbl_scope_id_alloc_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_tfc_tbl_scope_config * @@ -59760,7 +59760,7 @@ struct hwrm_tfc_tbl_scope_id_alloc_output { /* TruFlow command to configure the table scope memory. */ /* hwrm_tfc_tbl_scope_config_input (size:704b/88B) */ -struct hwrm_tfc_tbl_scope_config_input { +__rte_packed_begin struct hwrm_tfc_tbl_scope_config_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59837,10 +59837,10 @@ struct hwrm_tfc_tbl_scope_config_input { uint8_t tsid; /* unused. */ uint8_t unused0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tbl_scope_config_output (size:128b/16B) */ -struct hwrm_tfc_tbl_scope_config_output { +__rte_packed_begin struct hwrm_tfc_tbl_scope_config_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59860,7 +59860,7 @@ struct hwrm_tfc_tbl_scope_config_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_tfc_tbl_scope_deconfig * @@ -59869,7 +59869,7 @@ struct hwrm_tfc_tbl_scope_config_output { /* TruFlow command to deconfigure the table scope memory. */ /* hwrm_tfc_tbl_scope_deconfig_input (size:192b/24B) */ -struct hwrm_tfc_tbl_scope_deconfig_input { +__rte_packed_begin struct hwrm_tfc_tbl_scope_deconfig_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59902,10 +59902,10 @@ struct hwrm_tfc_tbl_scope_deconfig_input { uint8_t tsid; /* unused. */ uint8_t unused0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tbl_scope_deconfig_output (size:128b/16B) */ -struct hwrm_tfc_tbl_scope_deconfig_output { +__rte_packed_begin struct hwrm_tfc_tbl_scope_deconfig_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59925,7 +59925,7 @@ struct hwrm_tfc_tbl_scope_deconfig_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_tfc_tbl_scope_fid_add * @@ -59934,7 +59934,7 @@ struct hwrm_tfc_tbl_scope_deconfig_output { /* TruFlow command to add a FID to a table scope. */ /* hwrm_tfc_tbl_scope_fid_add_input (size:192b/24B) */ -struct hwrm_tfc_tbl_scope_fid_add_input { +__rte_packed_begin struct hwrm_tfc_tbl_scope_fid_add_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59976,10 +59976,10 @@ struct hwrm_tfc_tbl_scope_fid_add_input { uint8_t tsid; /* unused. */ uint8_t unused0[5]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tbl_scope_fid_add_output (size:128b/16B) */ -struct hwrm_tfc_tbl_scope_fid_add_output { +__rte_packed_begin struct hwrm_tfc_tbl_scope_fid_add_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60001,7 +60001,7 @@ struct hwrm_tfc_tbl_scope_fid_add_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_tfc_tbl_scope_fid_rem * @@ -60010,7 +60010,7 @@ struct hwrm_tfc_tbl_scope_fid_add_output { /* TruFlow command to remove a FID from a table scope. */ /* hwrm_tfc_tbl_scope_fid_rem_input (size:192b/24B) */ -struct hwrm_tfc_tbl_scope_fid_rem_input { +__rte_packed_begin struct hwrm_tfc_tbl_scope_fid_rem_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60052,10 +60052,10 @@ struct hwrm_tfc_tbl_scope_fid_rem_input { uint8_t tsid; /* unused. */ uint8_t unused0[5]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tbl_scope_fid_rem_output (size:128b/16B) */ -struct hwrm_tfc_tbl_scope_fid_rem_output { +__rte_packed_begin struct hwrm_tfc_tbl_scope_fid_rem_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60077,7 +60077,7 @@ struct hwrm_tfc_tbl_scope_fid_rem_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_tfc_session_id_alloc * @@ -60092,7 +60092,7 @@ struct hwrm_tfc_tbl_scope_fid_rem_output { * to 0), will result in this session id being freed automatically. */ /* hwrm_tfc_session_id_alloc_input (size:192b/24B) */ -struct hwrm_tfc_session_id_alloc_input { +__rte_packed_begin struct hwrm_tfc_session_id_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60132,10 +60132,10 @@ struct hwrm_tfc_session_id_alloc_input { uint16_t fid; /* Unused field */ uint8_t unused0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_session_id_alloc_output (size:128b/16B) */ -struct hwrm_tfc_session_id_alloc_output { +__rte_packed_begin struct hwrm_tfc_session_id_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60160,7 +60160,7 @@ struct hwrm_tfc_session_id_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_tfc_session_fid_add * @@ -60172,7 +60172,7 @@ struct hwrm_tfc_session_id_alloc_output { * will be associated with the passed in sid. */ /* hwrm_tfc_session_fid_add_input (size:192b/24B) */ -struct hwrm_tfc_session_fid_add_input { +__rte_packed_begin struct hwrm_tfc_session_fid_add_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60217,10 +60217,10 @@ struct hwrm_tfc_session_fid_add_input { uint16_t sid; /* Unused field */ uint8_t unused0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_session_fid_add_output (size:128b/16B) */ -struct hwrm_tfc_session_fid_add_output { +__rte_packed_begin struct hwrm_tfc_session_fid_add_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60242,7 +60242,7 @@ struct hwrm_tfc_session_fid_add_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_tfc_session_fid_rem * @@ -60257,7 +60257,7 @@ struct hwrm_tfc_session_fid_add_output { * automatically. */ /* hwrm_tfc_session_fid_rem_input (size:192b/24B) */ -struct hwrm_tfc_session_fid_rem_input { +__rte_packed_begin struct hwrm_tfc_session_fid_rem_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60302,10 +60302,10 @@ struct hwrm_tfc_session_fid_rem_input { uint16_t sid; /* Unused field */ uint8_t unused0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_session_fid_rem_output (size:128b/16B) */ -struct hwrm_tfc_session_fid_rem_output { +__rte_packed_begin struct hwrm_tfc_session_fid_rem_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60327,7 +60327,7 @@ struct hwrm_tfc_session_fid_rem_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_tfc_ident_alloc * @@ -60342,7 +60342,7 @@ struct hwrm_tfc_session_fid_rem_output { * to all these is allocated and returned in the HWRM response. */ /* hwrm_tfc_ident_alloc_input (size:192b/24B) */ -struct hwrm_tfc_ident_alloc_input { +__rte_packed_begin struct hwrm_tfc_ident_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60415,10 +60415,10 @@ struct hwrm_tfc_ident_alloc_input { HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID /* Unused field */ uint8_t unused0; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_ident_alloc_output (size:128b/16B) */ -struct hwrm_tfc_ident_alloc_output { +__rte_packed_begin struct hwrm_tfc_ident_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60443,7 +60443,7 @@ struct hwrm_tfc_ident_alloc_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_tfc_ident_free * @@ -60457,7 +60457,7 @@ struct hwrm_tfc_ident_alloc_output { * freed, only after various sanity checks are completed. */ /* hwrm_tfc_ident_free_input (size:192b/24B) */ -struct hwrm_tfc_ident_free_input { +__rte_packed_begin struct hwrm_tfc_ident_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60517,10 +60517,10 @@ struct hwrm_tfc_ident_free_input { HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX /* The resource identifier to be freed */ uint16_t ident_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_ident_free_output (size:128b/16B) */ -struct hwrm_tfc_ident_free_output { +__rte_packed_begin struct hwrm_tfc_ident_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60540,7 +60540,7 @@ struct hwrm_tfc_ident_free_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_tfc_idx_tbl_alloc * @@ -60548,7 +60548,7 @@ struct hwrm_tfc_ident_free_output { /* hwrm_tfc_idx_tbl_alloc_input (size:192b/24B) */ -struct hwrm_tfc_idx_tbl_alloc_input { +__rte_packed_begin struct hwrm_tfc_idx_tbl_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60641,10 +60641,10 @@ struct hwrm_tfc_idx_tbl_alloc_input { UINT32_C(0x3) #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_LAST \ HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_idx_tbl_alloc_output (size:128b/16B) */ -struct hwrm_tfc_idx_tbl_alloc_output { +__rte_packed_begin struct hwrm_tfc_idx_tbl_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60669,7 +60669,7 @@ struct hwrm_tfc_idx_tbl_alloc_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_tfc_idx_tbl_alloc_set * @@ -60677,7 +60677,7 @@ struct hwrm_tfc_idx_tbl_alloc_output { /* hwrm_tfc_idx_tbl_alloc_set_input (size:1088b/136B) */ -struct hwrm_tfc_idx_tbl_alloc_set_input { +__rte_packed_begin struct hwrm_tfc_idx_tbl_alloc_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60786,10 +60786,10 @@ struct hwrm_tfc_idx_tbl_alloc_set_input { * then this field contains the DMA buffer pointer. */ uint8_t dev_data[96]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_idx_tbl_alloc_set_output (size:128b/16B) */ -struct hwrm_tfc_idx_tbl_alloc_set_output { +__rte_packed_begin struct hwrm_tfc_idx_tbl_alloc_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60814,7 +60814,7 @@ struct hwrm_tfc_idx_tbl_alloc_set_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_tfc_idx_tbl_set * @@ -60822,7 +60822,7 @@ struct hwrm_tfc_idx_tbl_alloc_set_output { /* hwrm_tfc_idx_tbl_set_input (size:1088b/136B) */ -struct hwrm_tfc_idx_tbl_set_input { +__rte_packed_begin struct hwrm_tfc_idx_tbl_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60917,10 +60917,10 @@ struct hwrm_tfc_idx_tbl_set_input { * then this field contains the DMA buffer pointer. */ uint8_t dev_data[96]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_idx_tbl_set_output (size:128b/16B) */ -struct hwrm_tfc_idx_tbl_set_output { +__rte_packed_begin struct hwrm_tfc_idx_tbl_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60940,7 +60940,7 @@ struct hwrm_tfc_idx_tbl_set_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_tfc_idx_tbl_get * @@ -60948,7 +60948,7 @@ struct hwrm_tfc_idx_tbl_set_output { /* hwrm_tfc_idx_tbl_get_input (size:320b/40B) */ -struct hwrm_tfc_idx_tbl_get_input { +__rte_packed_begin struct hwrm_tfc_idx_tbl_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61042,10 +61042,10 @@ struct hwrm_tfc_idx_tbl_get_input { uint8_t unused0[5]; /* The location of the response dma buffer */ uint64_t dma_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_idx_tbl_get_output (size:128b/16B) */ -struct hwrm_tfc_idx_tbl_get_output { +__rte_packed_begin struct hwrm_tfc_idx_tbl_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61067,7 +61067,7 @@ struct hwrm_tfc_idx_tbl_get_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_tfc_idx_tbl_free * @@ -61075,7 +61075,7 @@ struct hwrm_tfc_idx_tbl_get_output { /* hwrm_tfc_idx_tbl_free_input (size:256b/32B) */ -struct hwrm_tfc_idx_tbl_free_input { +__rte_packed_begin struct hwrm_tfc_idx_tbl_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61153,10 +61153,10 @@ struct hwrm_tfc_idx_tbl_free_input { HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE /* unused. */ uint8_t unused0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_idx_tbl_free_output (size:128b/16B) */ -struct hwrm_tfc_idx_tbl_free_output { +__rte_packed_begin struct hwrm_tfc_idx_tbl_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61176,11 +61176,11 @@ struct hwrm_tfc_idx_tbl_free_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* TruFlow resources request for a global id. */ /* tfc_global_id_hwrm_req (size:64b/8B) */ -struct tfc_global_id_hwrm_req { +__rte_packed_begin struct tfc_global_id_hwrm_req { /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */ uint16_t rtype; /* Indicates the flow direction in type of cfa_dir. */ @@ -61189,11 +61189,11 @@ struct tfc_global_id_hwrm_req { uint16_t subtype; /* Number of the type of resources. */ uint16_t cnt; -} __rte_packed; +} __rte_packed_end; /* The reserved resources for the global id. */ /* tfc_global_id_hwrm_rsp (size:64b/8B) */ -struct tfc_global_id_hwrm_rsp { +__rte_packed_begin struct tfc_global_id_hwrm_rsp { /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */ uint16_t rtype; /* Indicates the flow direction in type of cfa_dir. */ @@ -61202,7 +61202,7 @@ struct tfc_global_id_hwrm_rsp { uint16_t subtype; /* The global id that the resources reserved for. */ uint16_t id; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_tfc_global_id_alloc * @@ -61210,7 +61210,7 @@ struct tfc_global_id_hwrm_rsp { /* hwrm_tfc_global_id_alloc_input (size:320b/40B) */ -struct hwrm_tfc_global_id_alloc_input { +__rte_packed_begin struct hwrm_tfc_global_id_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61272,10 +61272,10 @@ struct hwrm_tfc_global_id_alloc_input { * message. */ uint64_t resc_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_global_id_alloc_output (size:128b/16B) */ -struct hwrm_tfc_global_id_alloc_output { +__rte_packed_begin struct hwrm_tfc_global_id_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61304,7 +61304,7 @@ struct hwrm_tfc_global_id_alloc_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_tfc_tcam_set * @@ -61312,7 +61312,7 @@ struct hwrm_tfc_global_id_alloc_output { /* hwrm_tfc_tcam_set_input (size:1088b/136B) */ -struct hwrm_tfc_tcam_set_input { +__rte_packed_begin struct hwrm_tfc_tcam_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61387,10 +61387,10 @@ struct hwrm_tfc_tcam_set_input { * and result at result_offset for the device. */ uint8_t dev_data[96]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tcam_set_output (size:128b/16B) */ -struct hwrm_tfc_tcam_set_output { +__rte_packed_begin struct hwrm_tfc_tcam_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61410,7 +61410,7 @@ struct hwrm_tfc_tcam_set_output { * to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_tfc_tcam_get * @@ -61418,7 +61418,7 @@ struct hwrm_tfc_tcam_set_output { /* hwrm_tfc_tcam_get_input (size:192b/24B) */ -struct hwrm_tfc_tcam_get_input { +__rte_packed_begin struct hwrm_tfc_tcam_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61478,10 +61478,10 @@ struct hwrm_tfc_tcam_get_input { uint16_t sid; /* Logical TCAM ID. */ uint16_t tcam_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tcam_get_output (size:2368b/296B) */ -struct hwrm_tfc_tcam_get_output { +__rte_packed_begin struct hwrm_tfc_tcam_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61512,7 +61512,7 @@ struct hwrm_tfc_tcam_get_output { * to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_tfc_tcam_alloc * @@ -61520,7 +61520,7 @@ struct hwrm_tfc_tcam_get_output { /* hwrm_tfc_tcam_alloc_input (size:256b/32B) */ -struct hwrm_tfc_tcam_alloc_input { +__rte_packed_begin struct hwrm_tfc_tcam_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61598,10 +61598,10 @@ struct hwrm_tfc_tcam_alloc_input { HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID /* Unused. */ uint8_t unused0[5]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tcam_alloc_output (size:128b/16B) */ -struct hwrm_tfc_tcam_alloc_output { +__rte_packed_begin struct hwrm_tfc_tcam_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61626,7 +61626,7 @@ struct hwrm_tfc_tcam_alloc_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_tfc_tcam_alloc_set * @@ -61634,7 +61634,7 @@ struct hwrm_tfc_tcam_alloc_output { /* hwrm_tfc_tcam_alloc_set_input (size:1088b/136B) */ -struct hwrm_tfc_tcam_alloc_set_input { +__rte_packed_begin struct hwrm_tfc_tcam_alloc_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61723,10 +61723,10 @@ struct hwrm_tfc_tcam_alloc_set_input { * then this field contains the DMA buffer pointer. */ uint8_t dev_data[96]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tcam_alloc_set_output (size:128b/16B) */ -struct hwrm_tfc_tcam_alloc_set_output { +__rte_packed_begin struct hwrm_tfc_tcam_alloc_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61748,7 +61748,7 @@ struct hwrm_tfc_tcam_alloc_set_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_tfc_tcam_free * @@ -61756,7 +61756,7 @@ struct hwrm_tfc_tcam_alloc_set_output { /* hwrm_tfc_tcam_free_input (size:192b/24B) */ -struct hwrm_tfc_tcam_free_input { +__rte_packed_begin struct hwrm_tfc_tcam_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61816,10 +61816,10 @@ struct hwrm_tfc_tcam_free_input { uint16_t sid; /* Logical TCAM ID. */ uint16_t tcam_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tcam_free_output (size:128b/16B) */ -struct hwrm_tfc_tcam_free_output { +__rte_packed_begin struct hwrm_tfc_tcam_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61839,7 +61839,7 @@ struct hwrm_tfc_tcam_free_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_tfc_if_tbl_set * @@ -61847,7 +61847,7 @@ struct hwrm_tfc_tcam_free_output { /* hwrm_tfc_if_tbl_set_input (size:960b/120B) */ -struct hwrm_tfc_if_tbl_set_input { +__rte_packed_begin struct hwrm_tfc_if_tbl_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61903,10 +61903,10 @@ struct hwrm_tfc_if_tbl_set_input { uint8_t unused0[7]; /* Table data. */ uint8_t data[88]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_if_tbl_set_output (size:128b/16B) */ -struct hwrm_tfc_if_tbl_set_output { +__rte_packed_begin struct hwrm_tfc_if_tbl_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61926,7 +61926,7 @@ struct hwrm_tfc_if_tbl_set_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_tfc_if_tbl_get * @@ -61934,7 +61934,7 @@ struct hwrm_tfc_if_tbl_set_output { /* hwrm_tfc_if_tbl_get_input (size:256b/32B) */ -struct hwrm_tfc_if_tbl_get_input { +__rte_packed_begin struct hwrm_tfc_if_tbl_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61988,10 +61988,10 @@ struct hwrm_tfc_if_tbl_get_input { uint8_t data_size; /* Reserved */ uint8_t unused0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_if_tbl_get_output (size:960b/120B) */ -struct hwrm_tfc_if_tbl_get_output { +__rte_packed_begin struct hwrm_tfc_if_tbl_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62038,7 +62038,7 @@ struct hwrm_tfc_if_tbl_get_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************* * hwrm_tfc_tbl_scope_config_get * @@ -62047,7 +62047,7 @@ struct hwrm_tfc_if_tbl_get_output { /* TruFlow command to return whether the table scope is fully configured. */ /* hwrm_tfc_tbl_scope_config_get_input (size:192b/24B) */ -struct hwrm_tfc_tbl_scope_config_get_input { +__rte_packed_begin struct hwrm_tfc_tbl_scope_config_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62080,10 +62080,10 @@ struct hwrm_tfc_tbl_scope_config_get_input { uint8_t tsid; /* unused. */ uint8_t unused0[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_tbl_scope_config_get_output (size:128b/16B) */ -struct hwrm_tfc_tbl_scope_config_get_output { +__rte_packed_begin struct hwrm_tfc_tbl_scope_config_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62105,7 +62105,7 @@ struct hwrm_tfc_tbl_scope_config_get_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_tfc_resc_usage_query * @@ -62113,7 +62113,7 @@ struct hwrm_tfc_tbl_scope_config_get_output { /* hwrm_tfc_resc_usage_query_input (size:256b/32B) */ -struct hwrm_tfc_resc_usage_query_input { +__rte_packed_begin struct hwrm_tfc_resc_usage_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62173,10 +62173,10 @@ struct hwrm_tfc_resc_usage_query_input { uint16_t data_size; /* unused */ uint8_t unused1[8]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tfc_resc_usage_query_output (size:960b/120B) */ -struct hwrm_tfc_resc_usage_query_output { +__rte_packed_begin struct hwrm_tfc_resc_usage_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62204,7 +62204,7 @@ struct hwrm_tfc_resc_usage_query_output { * is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_tunnel_dst_port_query * @@ -62212,7 +62212,7 @@ struct hwrm_tfc_resc_usage_query_output { /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ -struct hwrm_tunnel_dst_port_query_input { +__rte_packed_begin struct hwrm_tunnel_dst_port_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62314,10 +62314,10 @@ struct hwrm_tunnel_dst_port_query_input { */ uint8_t tunnel_next_proto; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ -struct hwrm_tunnel_dst_port_query_output { +__rte_packed_begin struct hwrm_tunnel_dst_port_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62398,7 +62398,7 @@ struct hwrm_tunnel_dst_port_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_tunnel_dst_port_alloc * @@ -62406,7 +62406,7 @@ struct hwrm_tunnel_dst_port_query_output { /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ -struct hwrm_tunnel_dst_port_alloc_input { +__rte_packed_begin struct hwrm_tunnel_dst_port_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62522,10 +62522,10 @@ struct hwrm_tunnel_dst_port_alloc_input { */ uint16_t tunnel_dst_port_val; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ -struct hwrm_tunnel_dst_port_alloc_output { +__rte_packed_begin struct hwrm_tunnel_dst_port_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62595,7 +62595,7 @@ struct hwrm_tunnel_dst_port_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_tunnel_dst_port_free * @@ -62603,7 +62603,7 @@ struct hwrm_tunnel_dst_port_alloc_output { /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ -struct hwrm_tunnel_dst_port_free_input { +__rte_packed_begin struct hwrm_tunnel_dst_port_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62713,10 +62713,10 @@ struct hwrm_tunnel_dst_port_free_input { */ uint16_t tunnel_dst_port_id; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ -struct hwrm_tunnel_dst_port_free_output { +__rte_packed_begin struct hwrm_tunnel_dst_port_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62747,11 +62747,11 @@ struct hwrm_tunnel_dst_port_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* Periodic statistics context DMA to host. */ /* ctx_hw_stats (size:1280b/160B) */ -struct ctx_hw_stats { +__rte_packed_begin struct ctx_hw_stats { /* Number of received unicast packets */ uint64_t rx_ucast_pkts; /* Number of received multicast packets */ @@ -62792,7 +62792,7 @@ struct ctx_hw_stats { uint64_t tpa_events; /* Number of TPA aborts */ uint64_t tpa_aborts; -} __rte_packed; +} __rte_packed_end; /* * Extended periodic statistics context DMA to host. On cards that @@ -62800,7 +62800,7 @@ struct ctx_hw_stats { * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure. */ /* ctx_hw_stats_ext (size:1408b/176B) */ -struct ctx_hw_stats_ext { +__rte_packed_begin struct ctx_hw_stats_ext { /* Number of received unicast packets */ uint64_t rx_ucast_pkts; /* Number of received multicast packets */ @@ -62845,11 +62845,11 @@ struct ctx_hw_stats_ext { uint64_t rx_tpa_errors; /* Number of TPA events */ uint64_t rx_tpa_events; -} __rte_packed; +} __rte_packed_end; /* Periodic Engine statistics context DMA to host. */ /* ctx_eng_stats (size:512b/64B) */ -struct ctx_eng_stats { +__rte_packed_begin struct ctx_eng_stats { /* * Count of data bytes into the Engine. * This includes any user supplied prefix, @@ -62891,7 +62891,7 @@ struct ctx_eng_stats { * the unit is count of clock cycles */ uint64_t cdd_engine_usage; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_stat_ctx_alloc * @@ -62899,7 +62899,7 @@ struct ctx_eng_stats { /* hwrm_stat_ctx_alloc_input (size:320b/40B) */ -struct hwrm_stat_ctx_alloc_input { +__rte_packed_begin struct hwrm_stat_ctx_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62981,10 +62981,10 @@ struct hwrm_stat_ctx_alloc_input { */ uint16_t steering_tag; uint32_t unused_1; -} __rte_packed; +} __rte_packed_end; /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ -struct hwrm_stat_ctx_alloc_output { +__rte_packed_begin struct hwrm_stat_ctx_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63004,7 +63004,7 @@ struct hwrm_stat_ctx_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_stat_ctx_free * @@ -63012,7 +63012,7 @@ struct hwrm_stat_ctx_alloc_output { /* hwrm_stat_ctx_free_input (size:192b/24B) */ -struct hwrm_stat_ctx_free_input { +__rte_packed_begin struct hwrm_stat_ctx_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63044,10 +63044,10 @@ struct hwrm_stat_ctx_free_input { /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_stat_ctx_free_output (size:128b/16B) */ -struct hwrm_stat_ctx_free_output { +__rte_packed_begin struct hwrm_stat_ctx_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63067,7 +63067,7 @@ struct hwrm_stat_ctx_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_stat_ctx_query * @@ -63075,7 +63075,7 @@ struct hwrm_stat_ctx_free_output { /* hwrm_stat_ctx_query_input (size:192b/24B) */ -struct hwrm_stat_ctx_query_input { +__rte_packed_begin struct hwrm_stat_ctx_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63114,10 +63114,10 @@ struct hwrm_stat_ctx_query_input { */ #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) uint8_t unused_0[3]; -} __rte_packed; +} __rte_packed_end; /* hwrm_stat_ctx_query_output (size:1408b/176B) */ -struct hwrm_stat_ctx_query_output { +__rte_packed_begin struct hwrm_stat_ctx_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63175,7 +63175,7 @@ struct hwrm_stat_ctx_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_stat_ext_ctx_query * @@ -63183,7 +63183,7 @@ struct hwrm_stat_ctx_query_output { /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ -struct hwrm_stat_ext_ctx_query_input { +__rte_packed_begin struct hwrm_stat_ext_ctx_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63223,10 +63223,10 @@ struct hwrm_stat_ext_ctx_query_input { #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \ UINT32_C(0x1) uint8_t unused_0[3]; -} __rte_packed; +} __rte_packed_end; /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ -struct hwrm_stat_ext_ctx_query_output { +__rte_packed_begin struct hwrm_stat_ext_ctx_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63288,7 +63288,7 @@ struct hwrm_stat_ext_ctx_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_stat_ctx_eng_query * @@ -63296,7 +63296,7 @@ struct hwrm_stat_ext_ctx_query_output { /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */ -struct hwrm_stat_ctx_eng_query_input { +__rte_packed_begin struct hwrm_stat_ctx_eng_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63328,10 +63328,10 @@ struct hwrm_stat_ctx_eng_query_input { /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */ -struct hwrm_stat_ctx_eng_query_output { +__rte_packed_begin struct hwrm_stat_ctx_eng_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63390,7 +63390,7 @@ struct hwrm_stat_ctx_eng_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_stat_ctx_clr_stats * @@ -63398,7 +63398,7 @@ struct hwrm_stat_ctx_eng_query_output { /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ -struct hwrm_stat_ctx_clr_stats_input { +__rte_packed_begin struct hwrm_stat_ctx_clr_stats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63430,10 +63430,10 @@ struct hwrm_stat_ctx_clr_stats_input { /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ -struct hwrm_stat_ctx_clr_stats_output { +__rte_packed_begin struct hwrm_stat_ctx_clr_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63451,7 +63451,7 @@ struct hwrm_stat_ctx_clr_stats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************** * hwrm_pcie_qstats * @@ -63459,7 +63459,7 @@ struct hwrm_stat_ctx_clr_stats_output { /* hwrm_pcie_qstats_input (size:256b/32B) */ -struct hwrm_pcie_qstats_input { +__rte_packed_begin struct hwrm_pcie_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63500,10 +63500,10 @@ struct hwrm_pcie_qstats_input { * PCIe statistics will be stored */ uint64_t pcie_stat_host_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_pcie_qstats_output (size:128b/16B) */ -struct hwrm_pcie_qstats_output { +__rte_packed_begin struct hwrm_pcie_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63523,11 +63523,11 @@ struct hwrm_pcie_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* PCIe Statistics Formats */ /* pcie_ctx_hw_stats (size:768b/96B) */ -struct pcie_ctx_hw_stats { +__rte_packed_begin struct pcie_ctx_hw_stats { /* Number of physical layer receiver errors */ uint64_t pcie_pl_signal_integrity; /* Number of DLLP CRC errors detected by Data Link Layer */ @@ -63559,7 +63559,7 @@ struct pcie_ctx_hw_stats { * to Recovery */ uint64_t pcie_recovery_histogram; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_stat_generic_qstats * @@ -63567,7 +63567,7 @@ struct pcie_ctx_hw_stats { /* hwrm_stat_generic_qstats_input (size:256b/32B) */ -struct hwrm_stat_generic_qstats_input { +__rte_packed_begin struct hwrm_stat_generic_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63618,10 +63618,10 @@ struct hwrm_stat_generic_qstats_input { * generic statistics will be stored */ uint64_t generic_stat_host_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_stat_generic_qstats_output (size:128b/16B) */ -struct hwrm_stat_generic_qstats_output { +__rte_packed_begin struct hwrm_stat_generic_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63642,11 +63642,11 @@ struct hwrm_stat_generic_qstats_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* Generic Statistic Format */ /* generic_sw_hw_stats (size:1472b/184B) */ -struct generic_sw_hw_stats { +__rte_packed_begin struct generic_sw_hw_stats { /* * This is the number of TLP bytes that have been transmitted for * the caller PF. @@ -63744,7 +63744,7 @@ struct generic_sw_hw_stats { * the hardware based doorbell drop recovery feature. */ uint64_t hw_db_recov_oo_drop_count; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_stat_db_error_qstats * @@ -63752,7 +63752,7 @@ struct generic_sw_hw_stats { /* hwrm_stat_db_error_qstats_input (size:128b/16B) */ -struct hwrm_stat_db_error_qstats_input { +__rte_packed_begin struct hwrm_stat_db_error_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63781,10 +63781,10 @@ struct hwrm_stat_db_error_qstats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_stat_db_error_qstats_output (size:320b/40B) */ -struct hwrm_stat_db_error_qstats_output { +__rte_packed_begin struct hwrm_stat_db_error_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63835,7 +63835,7 @@ struct hwrm_stat_db_error_qstats_output { * written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_exec_fwd_resp * @@ -63843,7 +63843,7 @@ struct hwrm_stat_db_error_qstats_output { /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ -struct hwrm_exec_fwd_resp_input { +__rte_packed_begin struct hwrm_exec_fwd_resp_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63888,10 +63888,10 @@ struct hwrm_exec_fwd_resp_input { */ uint16_t encap_resp_target_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_exec_fwd_resp_output (size:128b/16B) */ -struct hwrm_exec_fwd_resp_output { +__rte_packed_begin struct hwrm_exec_fwd_resp_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63909,7 +63909,7 @@ struct hwrm_exec_fwd_resp_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_reject_fwd_resp * @@ -63917,7 +63917,7 @@ struct hwrm_exec_fwd_resp_output { /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ -struct hwrm_reject_fwd_resp_input { +__rte_packed_begin struct hwrm_reject_fwd_resp_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63962,10 +63962,10 @@ struct hwrm_reject_fwd_resp_input { */ uint16_t encap_resp_target_id; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_reject_fwd_resp_output (size:128b/16B) */ -struct hwrm_reject_fwd_resp_output { +__rte_packed_begin struct hwrm_reject_fwd_resp_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63983,7 +63983,7 @@ struct hwrm_reject_fwd_resp_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************** * hwrm_fwd_resp * @@ -63991,7 +63991,7 @@ struct hwrm_reject_fwd_resp_output { /* hwrm_fwd_resp_input (size:1024b/128B) */ -struct hwrm_fwd_resp_input { +__rte_packed_begin struct hwrm_fwd_resp_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64051,10 +64051,10 @@ struct hwrm_fwd_resp_input { uint64_t encap_resp_addr; /* This is an encapsulated response. */ uint32_t encap_resp[24]; -} __rte_packed; +} __rte_packed_end; /* hwrm_fwd_resp_output (size:128b/16B) */ -struct hwrm_fwd_resp_output { +__rte_packed_begin struct hwrm_fwd_resp_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -64072,7 +64072,7 @@ struct hwrm_fwd_resp_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_fwd_async_event_cmpl * @@ -64080,7 +64080,7 @@ struct hwrm_fwd_resp_output { /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ -struct hwrm_fwd_async_event_cmpl_input { +__rte_packed_begin struct hwrm_fwd_async_event_cmpl_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64121,10 +64121,10 @@ struct hwrm_fwd_async_event_cmpl_input { uint8_t unused_0[6]; /* This is an encapsulated asynchronous event completion. */ uint32_t encap_async_event_cmpl[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ -struct hwrm_fwd_async_event_cmpl_output { +__rte_packed_begin struct hwrm_fwd_async_event_cmpl_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -64142,7 +64142,7 @@ struct hwrm_fwd_async_event_cmpl_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_nvm_raw_write_blk * @@ -64150,7 +64150,7 @@ struct hwrm_fwd_async_event_cmpl_output { /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */ -struct hwrm_nvm_raw_write_blk_input { +__rte_packed_begin struct hwrm_nvm_raw_write_blk_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64192,10 +64192,10 @@ struct hwrm_nvm_raw_write_blk_input { uint32_t dest_addr; /* Length of data to be written, in bytes. */ uint32_t len; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */ -struct hwrm_nvm_raw_write_blk_output { +__rte_packed_begin struct hwrm_nvm_raw_write_blk_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -64213,7 +64213,7 @@ struct hwrm_nvm_raw_write_blk_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************** * hwrm_nvm_read * @@ -64221,7 +64221,7 @@ struct hwrm_nvm_raw_write_blk_output { /* hwrm_nvm_read_input (size:320b/40B) */ -struct hwrm_nvm_read_input { +__rte_packed_begin struct hwrm_nvm_read_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64263,10 +64263,10 @@ struct hwrm_nvm_read_input { /* The length of the data to be read, in bytes. */ uint32_t len; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_read_output (size:128b/16B) */ -struct hwrm_nvm_read_output { +__rte_packed_begin struct hwrm_nvm_read_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -64284,7 +64284,7 @@ struct hwrm_nvm_read_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_nvm_raw_dump * @@ -64292,7 +64292,7 @@ struct hwrm_nvm_read_output { /* hwrm_nvm_raw_dump_input (size:256b/32B) */ -struct hwrm_nvm_raw_dump_input { +__rte_packed_begin struct hwrm_nvm_raw_dump_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64330,10 +64330,10 @@ struct hwrm_nvm_raw_dump_input { uint32_t offset; /* Total length of NVRAM contents to be read, in bytes. */ uint32_t len; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_raw_dump_output (size:128b/16B) */ -struct hwrm_nvm_raw_dump_output { +__rte_packed_begin struct hwrm_nvm_raw_dump_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -64351,7 +64351,7 @@ struct hwrm_nvm_raw_dump_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_nvm_get_dir_entries * @@ -64359,7 +64359,7 @@ struct hwrm_nvm_raw_dump_output { /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ -struct hwrm_nvm_get_dir_entries_input { +__rte_packed_begin struct hwrm_nvm_get_dir_entries_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64393,10 +64393,10 @@ struct hwrm_nvm_get_dir_entries_input { * This is the host address where the directory will be written. */ uint64_t host_dest_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ -struct hwrm_nvm_get_dir_entries_output { +__rte_packed_begin struct hwrm_nvm_get_dir_entries_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -64414,7 +64414,7 @@ struct hwrm_nvm_get_dir_entries_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_nvm_get_dir_info * @@ -64422,7 +64422,7 @@ struct hwrm_nvm_get_dir_entries_output { /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ -struct hwrm_nvm_get_dir_info_input { +__rte_packed_begin struct hwrm_nvm_get_dir_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64451,10 +64451,10 @@ struct hwrm_nvm_get_dir_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ -struct hwrm_nvm_get_dir_info_output { +__rte_packed_begin struct hwrm_nvm_get_dir_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -64476,7 +64476,7 @@ struct hwrm_nvm_get_dir_info_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************** * hwrm_nvm_write * @@ -64484,7 +64484,7 @@ struct hwrm_nvm_get_dir_info_output { /* hwrm_nvm_write_input (size:448b/56B) */ -struct hwrm_nvm_write_input { +__rte_packed_begin struct hwrm_nvm_write_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64598,10 +64598,10 @@ struct hwrm_nvm_write_input { */ uint32_t len; uint32_t unused_0; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_write_output (size:128b/16B) */ -struct hwrm_nvm_write_output { +__rte_packed_begin struct hwrm_nvm_write_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -64629,10 +64629,10 @@ struct hwrm_nvm_write_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_write_cmd_err (size:64b/8B) */ -struct hwrm_nvm_write_cmd_err { +__rte_packed_begin struct hwrm_nvm_write_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -64647,7 +64647,7 @@ struct hwrm_nvm_write_cmd_err { #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \ HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_nvm_modify * @@ -64655,7 +64655,7 @@ struct hwrm_nvm_write_cmd_err { /* hwrm_nvm_modify_input (size:320b/40B) */ -struct hwrm_nvm_modify_input { +__rte_packed_begin struct hwrm_nvm_modify_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64716,10 +64716,10 @@ struct hwrm_nvm_modify_input { */ uint32_t len; uint8_t unused_1[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_modify_output (size:128b/16B) */ -struct hwrm_nvm_modify_output { +__rte_packed_begin struct hwrm_nvm_modify_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -64737,7 +64737,7 @@ struct hwrm_nvm_modify_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_nvm_find_dir_entry * @@ -64745,7 +64745,7 @@ struct hwrm_nvm_modify_output { /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ -struct hwrm_nvm_find_dir_entry_input { +__rte_packed_begin struct hwrm_nvm_find_dir_entry_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64806,10 +64806,10 @@ struct hwrm_nvm_find_dir_entry_input { #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \ HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT uint8_t unused_0[3]; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ -struct hwrm_nvm_find_dir_entry_output { +__rte_packed_begin struct hwrm_nvm_find_dir_entry_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -64841,7 +64841,7 @@ struct hwrm_nvm_find_dir_entry_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_nvm_erase_dir_entry * @@ -64849,7 +64849,7 @@ struct hwrm_nvm_find_dir_entry_output { /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ -struct hwrm_nvm_erase_dir_entry_input { +__rte_packed_begin struct hwrm_nvm_erase_dir_entry_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64881,10 +64881,10 @@ struct hwrm_nvm_erase_dir_entry_input { /* Directory Entry Index */ uint16_t dir_idx; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ -struct hwrm_nvm_erase_dir_entry_output { +__rte_packed_begin struct hwrm_nvm_erase_dir_entry_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -64902,7 +64902,7 @@ struct hwrm_nvm_erase_dir_entry_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_nvm_get_dev_info * @@ -64910,7 +64910,7 @@ struct hwrm_nvm_erase_dir_entry_output { /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ -struct hwrm_nvm_get_dev_info_input { +__rte_packed_begin struct hwrm_nvm_get_dev_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -64939,10 +64939,10 @@ struct hwrm_nvm_get_dev_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_get_dev_info_output (size:704b/88B) */ -struct hwrm_nvm_get_dev_info_output { +__rte_packed_begin struct hwrm_nvm_get_dev_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -65076,7 +65076,7 @@ struct hwrm_nvm_get_dev_info_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_nvm_mod_dir_entry * @@ -65084,7 +65084,7 @@ struct hwrm_nvm_get_dev_info_output { /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ -struct hwrm_nvm_mod_dir_entry_input { +__rte_packed_begin struct hwrm_nvm_mod_dir_entry_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -65141,10 +65141,10 @@ struct hwrm_nvm_mod_dir_entry_input { * value of the content in the directory entry. */ uint32_t checksum; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ -struct hwrm_nvm_mod_dir_entry_output { +__rte_packed_begin struct hwrm_nvm_mod_dir_entry_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -65162,7 +65162,7 @@ struct hwrm_nvm_mod_dir_entry_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_nvm_verify_update * @@ -65170,7 +65170,7 @@ struct hwrm_nvm_mod_dir_entry_output { /* hwrm_nvm_verify_update_input (size:192b/24B) */ -struct hwrm_nvm_verify_update_input { +__rte_packed_begin struct hwrm_nvm_verify_update_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -65217,10 +65217,10 @@ struct hwrm_nvm_verify_update_input { */ uint16_t dir_ext; uint8_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_verify_update_output (size:128b/16B) */ -struct hwrm_nvm_verify_update_output { +__rte_packed_begin struct hwrm_nvm_verify_update_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -65238,7 +65238,7 @@ struct hwrm_nvm_verify_update_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_nvm_install_update * @@ -65246,7 +65246,7 @@ struct hwrm_nvm_verify_update_output { /* hwrm_nvm_install_update_input (size:192b/24B) */ -struct hwrm_nvm_install_update_input { +__rte_packed_begin struct hwrm_nvm_install_update_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -65329,10 +65329,10 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \ UINT32_C(0x8) uint8_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_install_update_output (size:192b/24B) */ -struct hwrm_nvm_install_update_output { +__rte_packed_begin struct hwrm_nvm_install_update_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -65481,10 +65481,10 @@ struct hwrm_nvm_install_update_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ -struct hwrm_nvm_install_update_cmd_err { +__rte_packed_begin struct hwrm_nvm_install_update_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -65508,7 +65508,7 @@ struct hwrm_nvm_install_update_cmd_err { #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /****************** * hwrm_nvm_flush * @@ -65516,7 +65516,7 @@ struct hwrm_nvm_install_update_cmd_err { /* hwrm_nvm_flush_input (size:128b/16B) */ -struct hwrm_nvm_flush_input { +__rte_packed_begin struct hwrm_nvm_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -65545,10 +65545,10 @@ struct hwrm_nvm_flush_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_flush_output (size:128b/16B) */ -struct hwrm_nvm_flush_output { +__rte_packed_begin struct hwrm_nvm_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -65566,10 +65566,10 @@ struct hwrm_nvm_flush_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_flush_cmd_err (size:64b/8B) */ -struct hwrm_nvm_flush_cmd_err { +__rte_packed_begin struct hwrm_nvm_flush_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -65582,7 +65582,7 @@ struct hwrm_nvm_flush_cmd_err { #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \ HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_nvm_get_variable * @@ -65590,7 +65590,7 @@ struct hwrm_nvm_flush_cmd_err { /* hwrm_nvm_get_variable_input (size:320b/40B) */ -struct hwrm_nvm_get_variable_input { +__rte_packed_begin struct hwrm_nvm_get_variable_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -65659,10 +65659,10 @@ struct hwrm_nvm_get_variable_input { #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \ UINT32_C(0x1) uint8_t unused_0; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_get_variable_output (size:128b/16B) */ -struct hwrm_nvm_get_variable_output { +__rte_packed_begin struct hwrm_nvm_get_variable_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -65699,10 +65699,10 @@ struct hwrm_nvm_get_variable_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ -struct hwrm_nvm_get_variable_cmd_err { +__rte_packed_begin struct hwrm_nvm_get_variable_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -65719,7 +65719,7 @@ struct hwrm_nvm_get_variable_cmd_err { #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \ HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /************************* * hwrm_nvm_set_variable * @@ -65727,7 +65727,7 @@ struct hwrm_nvm_get_variable_cmd_err { /* hwrm_nvm_set_variable_input (size:320b/40B) */ -struct hwrm_nvm_set_variable_input { +__rte_packed_begin struct hwrm_nvm_set_variable_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -65820,10 +65820,10 @@ struct hwrm_nvm_set_variable_input { #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \ UINT32_C(0x80) uint8_t unused_0; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_set_variable_output (size:128b/16B) */ -struct hwrm_nvm_set_variable_output { +__rte_packed_begin struct hwrm_nvm_set_variable_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -65841,10 +65841,10 @@ struct hwrm_nvm_set_variable_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ -struct hwrm_nvm_set_variable_cmd_err { +__rte_packed_begin struct hwrm_nvm_set_variable_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -65859,7 +65859,7 @@ struct hwrm_nvm_set_variable_cmd_err { #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \ HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_nvm_validate_option * @@ -65867,7 +65867,7 @@ struct hwrm_nvm_set_variable_cmd_err { /* hwrm_nvm_validate_option_input (size:320b/40B) */ -struct hwrm_nvm_validate_option_input { +__rte_packed_begin struct hwrm_nvm_validate_option_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -65930,10 +65930,10 @@ struct hwrm_nvm_validate_option_input { /* index for the 4th dimensions */ uint16_t index_3; uint8_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_validate_option_output (size:128b/16B) */ -struct hwrm_nvm_validate_option_output { +__rte_packed_begin struct hwrm_nvm_validate_option_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -65964,10 +65964,10 @@ struct hwrm_nvm_validate_option_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */ -struct hwrm_nvm_validate_option_cmd_err { +__rte_packed_begin struct hwrm_nvm_validate_option_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -65978,7 +65978,7 @@ struct hwrm_nvm_validate_option_cmd_err { #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \ HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_nvm_defrag * @@ -65986,7 +65986,7 @@ struct hwrm_nvm_validate_option_cmd_err { /* hwrm_nvm_defrag_input (size:192b/24B) */ -struct hwrm_nvm_defrag_input { +__rte_packed_begin struct hwrm_nvm_defrag_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -66019,10 +66019,10 @@ struct hwrm_nvm_defrag_input { /* This bit must be '1' to perform NVM defragmentation. */ #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1) uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_defrag_output (size:128b/16B) */ -struct hwrm_nvm_defrag_output { +__rte_packed_begin struct hwrm_nvm_defrag_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -66040,10 +66040,10 @@ struct hwrm_nvm_defrag_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ -struct hwrm_nvm_defrag_cmd_err { +__rte_packed_begin struct hwrm_nvm_defrag_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. @@ -66056,7 +66056,7 @@ struct hwrm_nvm_defrag_cmd_err { #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \ HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL uint8_t unused_0[7]; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_nvm_get_vpd_field_info * @@ -66064,7 +66064,7 @@ struct hwrm_nvm_defrag_cmd_err { /* hwrm_nvm_get_vpd_field_info_input (size:192b/24B) */ -struct hwrm_nvm_get_vpd_field_info_input { +__rte_packed_begin struct hwrm_nvm_get_vpd_field_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -66102,10 +66102,10 @@ struct hwrm_nvm_get_vpd_field_info_input { */ uint8_t tag_id[2]; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_get_vpd_field_info_output (size:2176b/272B) */ -struct hwrm_nvm_get_vpd_field_info_output { +__rte_packed_begin struct hwrm_nvm_get_vpd_field_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -66127,7 +66127,7 @@ struct hwrm_nvm_get_vpd_field_info_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************************* * hwrm_nvm_set_vpd_field_info * @@ -66135,7 +66135,7 @@ struct hwrm_nvm_get_vpd_field_info_output { /* hwrm_nvm_set_vpd_field_info_input (size:256b/32B) */ -struct hwrm_nvm_set_vpd_field_info_input { +__rte_packed_begin struct hwrm_nvm_set_vpd_field_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -66180,10 +66180,10 @@ struct hwrm_nvm_set_vpd_field_info_input { /* size of data in bytes */ uint16_t data_len; uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_nvm_set_vpd_field_info_output (size:128b/16B) */ -struct hwrm_nvm_set_vpd_field_info_output { +__rte_packed_begin struct hwrm_nvm_set_vpd_field_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -66201,7 +66201,7 @@ struct hwrm_nvm_set_vpd_field_info_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************** * hwrm_oem_cmd * @@ -66209,7 +66209,7 @@ struct hwrm_nvm_set_vpd_field_info_output { /* hwrm_oem_cmd_input (size:1024b/128B) */ -struct hwrm_oem_cmd_input { +__rte_packed_begin struct hwrm_oem_cmd_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -66265,10 +66265,10 @@ struct hwrm_oem_cmd_input { uint16_t unused; /* This field contains the vendor specific command data. */ uint32_t oem_data[26]; -} __rte_packed; +} __rte_packed_end; /* hwrm_oem_cmd_output (size:768b/96B) */ -struct hwrm_oem_cmd_output { +__rte_packed_begin struct hwrm_oem_cmd_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -66295,7 +66295,7 @@ struct hwrm_oem_cmd_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_dbg_crashdump_header * @@ -66303,7 +66303,7 @@ struct hwrm_oem_cmd_output { /* hwrm_dbg_crashdump_header_input (size:192b/24B) */ -struct hwrm_dbg_crashdump_header_input { +__rte_packed_begin struct hwrm_dbg_crashdump_header_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -66333,10 +66333,10 @@ struct hwrm_dbg_crashdump_header_input { */ uint64_t resp_addr; uint32_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_crashdump_header_output (size:512b/64B) */ -struct hwrm_dbg_crashdump_header_output { +__rte_packed_begin struct hwrm_dbg_crashdump_header_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -66481,7 +66481,7 @@ struct hwrm_dbg_crashdump_header_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /**************************** * hwrm_dbg_crashdump_erase * @@ -66489,7 +66489,7 @@ struct hwrm_dbg_crashdump_header_output { /* hwrm_dbg_crashdump_erase_input (size:192b/24B) */ -struct hwrm_dbg_crashdump_erase_input { +__rte_packed_begin struct hwrm_dbg_crashdump_erase_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -66537,10 +66537,10 @@ struct hwrm_dbg_crashdump_erase_input { HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_REINIT uint8_t unused_0[3]; uint32_t unused_1; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_crashdump_erase_output (size:128b/16B) */ -struct hwrm_dbg_crashdump_erase_output { +__rte_packed_begin struct hwrm_dbg_crashdump_erase_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -66558,7 +66558,7 @@ struct hwrm_dbg_crashdump_erase_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************** * hwrm_dbg_qcaps * @@ -66566,7 +66566,7 @@ struct hwrm_dbg_crashdump_erase_output { /* hwrm_dbg_qcaps_input (size:192b/24B) */ -struct hwrm_dbg_qcaps_input { +__rte_packed_begin struct hwrm_dbg_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -66602,10 +66602,10 @@ struct hwrm_dbg_qcaps_input { */ uint16_t fid; uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_qcaps_output (size:192b/24B) */ -struct hwrm_dbg_qcaps_output { +__rte_packed_begin struct hwrm_dbg_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -66653,7 +66653,7 @@ struct hwrm_dbg_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************** * hwrm_dbg_qcfg * @@ -66661,7 +66661,7 @@ struct hwrm_dbg_qcaps_output { /* hwrm_dbg_qcfg_input (size:192b/24B) */ -struct hwrm_dbg_qcfg_input { +__rte_packed_begin struct hwrm_dbg_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -66727,10 +66727,10 @@ struct hwrm_dbg_qcfg_input { */ #define HWRM_DBG_QCFG_INPUT_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM \ UINT32_C(0x1) -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_qcfg_output (size:256b/32B) */ -struct hwrm_dbg_qcfg_output { +__rte_packed_begin struct hwrm_dbg_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -66807,7 +66807,7 @@ struct hwrm_dbg_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************************* * hwrm_dbg_crashdump_medium_cfg * @@ -66815,7 +66815,7 @@ struct hwrm_dbg_qcfg_output { /* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ -struct hwrm_dbg_crashdump_medium_cfg_input { +__rte_packed_begin struct hwrm_dbg_crashdump_medium_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -66908,10 +66908,10 @@ struct hwrm_dbg_crashdump_medium_cfg_input { uint32_t unused_0; /* Crashdump buffer PBL physical address. */ uint64_t pbl; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ -struct hwrm_dbg_crashdump_medium_cfg_output { +__rte_packed_begin struct hwrm_dbg_crashdump_medium_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -66929,10 +66929,10 @@ struct hwrm_dbg_crashdump_medium_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* coredump_segment_record (size:128b/16B) */ -struct coredump_segment_record { +__rte_packed_begin struct coredump_segment_record { /* Component id of the returned component. */ uint16_t component_id; /* Segment id of the returned component. */ @@ -66961,7 +66961,7 @@ struct coredump_segment_record { * the firmware does not support returning the segment data length. */ uint32_t segment_len; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_dbg_coredump_list * @@ -66969,7 +66969,7 @@ struct coredump_segment_record { /* hwrm_dbg_coredump_list_input (size:256b/32B) */ -struct hwrm_dbg_coredump_list_input { +__rte_packed_begin struct hwrm_dbg_coredump_list_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -67015,10 +67015,10 @@ struct hwrm_dbg_coredump_list_input { */ #define HWRM_DBG_COREDUMP_LIST_INPUT_FLAGS_CRASHDUMP UINT32_C(0x1) uint8_t unused_0[1]; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_coredump_list_output (size:128b/16B) */ -struct hwrm_dbg_coredump_list_output { +__rte_packed_begin struct hwrm_dbg_coredump_list_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -67047,7 +67047,7 @@ struct hwrm_dbg_coredump_list_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_dbg_coredump_initiate * @@ -67055,7 +67055,7 @@ struct hwrm_dbg_coredump_list_output { /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ -struct hwrm_dbg_coredump_initiate_input { +__rte_packed_begin struct hwrm_dbg_coredump_initiate_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -67099,10 +67099,10 @@ struct hwrm_dbg_coredump_initiate_input { uint8_t seg_flags; /* Not used. */ uint8_t unused_1[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ -struct hwrm_dbg_coredump_initiate_output { +__rte_packed_begin struct hwrm_dbg_coredump_initiate_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -67120,10 +67120,10 @@ struct hwrm_dbg_coredump_initiate_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* coredump_data_hdr (size:128b/16B) */ -struct coredump_data_hdr { +__rte_packed_begin struct coredump_data_hdr { /* Starting address of the register range. */ uint32_t address; /* @@ -67143,7 +67143,7 @@ struct coredump_data_hdr { uint32_t instance; /* Starting address of the next register after the current data range */ uint32_t next_offset; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_dbg_coredump_retrieve * @@ -67151,7 +67151,7 @@ struct coredump_data_hdr { /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ -struct hwrm_dbg_coredump_retrieve_input { +__rte_packed_begin struct hwrm_dbg_coredump_retrieve_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -67209,10 +67209,10 @@ struct hwrm_dbg_coredump_retrieve_input { /* Sequence number is used per segment request. Starts at 0. */ uint32_t seq_no; uint32_t unused_5; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ -struct hwrm_dbg_coredump_retrieve_output { +__rte_packed_begin struct hwrm_dbg_coredump_retrieve_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -67239,7 +67239,7 @@ struct hwrm_dbg_coredump_retrieve_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /******************* * hwrm_dbg_fw_cli * @@ -67247,7 +67247,7 @@ struct hwrm_dbg_coredump_retrieve_output { /* hwrm_dbg_fw_cli_input (size:1024b/128B) */ -struct hwrm_dbg_fw_cli_input { +__rte_packed_begin struct hwrm_dbg_fw_cli_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -67288,10 +67288,10 @@ struct hwrm_dbg_fw_cli_input { uint8_t unused_0[2]; /* CLI command string, a single ASCII encoded null terminated string. */ uint8_t cli_cmd[96]; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_fw_cli_output (size:128b/16B) */ -struct hwrm_dbg_fw_cli_output { +__rte_packed_begin struct hwrm_dbg_fw_cli_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -67311,7 +67311,7 @@ struct hwrm_dbg_fw_cli_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /************************** * hwrm_dbg_ring_info_get * @@ -67319,7 +67319,7 @@ struct hwrm_dbg_fw_cli_output { /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ -struct hwrm_dbg_ring_info_get_input { +__rte_packed_begin struct hwrm_dbg_ring_info_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -67363,10 +67363,10 @@ struct hwrm_dbg_ring_info_get_input { uint8_t unused_0[3]; /* Firmware ring ID associated with ring being queried. */ uint32_t fw_ring_id; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ -struct hwrm_dbg_ring_info_get_output { +__rte_packed_begin struct hwrm_dbg_ring_info_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -67399,7 +67399,7 @@ struct hwrm_dbg_ring_info_get_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_dbg_drv_trace * @@ -67407,7 +67407,7 @@ struct hwrm_dbg_ring_info_get_output { /* hwrm_dbg_drv_trace_input (size:1024b/128B) */ -struct hwrm_dbg_drv_trace_input { +__rte_packed_begin struct hwrm_dbg_drv_trace_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -67463,10 +67463,10 @@ struct hwrm_dbg_drv_trace_input { * ASCII chars, 'NULL' termination not required. */ char trace_data[104]; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_drv_trace_output (size:128b/16B) */ -struct hwrm_dbg_drv_trace_output { +__rte_packed_begin struct hwrm_dbg_drv_trace_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -67484,7 +67484,7 @@ struct hwrm_dbg_drv_trace_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_dbg_useq_alloc * @@ -67492,7 +67492,7 @@ struct hwrm_dbg_drv_trace_output { /* hwrm_dbg_useq_alloc_input (size:192b/24B) */ -struct hwrm_dbg_useq_alloc_input { +__rte_packed_begin struct hwrm_dbg_useq_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -67533,10 +67533,10 @@ struct hwrm_dbg_useq_alloc_input { uint16_t output_bytes; /* This field is reserved */ uint16_t unused_0; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_useq_alloc_output (size:256b/32B) */ -struct hwrm_dbg_useq_alloc_output { +__rte_packed_begin struct hwrm_dbg_useq_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -67577,7 +67577,7 @@ struct hwrm_dbg_useq_alloc_output { * the order of writes has to be such that this field is written last. */ uint32_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_dbg_useq_free * @@ -67585,7 +67585,7 @@ struct hwrm_dbg_useq_alloc_output { /* hwrm_dbg_useq_free_input (size:192b/24B) */ -struct hwrm_dbg_useq_free_input { +__rte_packed_begin struct hwrm_dbg_useq_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -67618,10 +67618,10 @@ struct hwrm_dbg_useq_free_input { uint16_t usid; /* This field is reserved */ uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_useq_free_output (size:256b/32B) */ -struct hwrm_dbg_useq_free_output { +__rte_packed_begin struct hwrm_dbg_useq_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -67660,7 +67660,7 @@ struct hwrm_dbg_useq_free_output { * the order of writes has to be such that this field is written last. */ uint32_t valid; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_dbg_useq_flush * @@ -67668,7 +67668,7 @@ struct hwrm_dbg_useq_free_output { /* hwrm_dbg_useq_flush_input (size:192b/24B) */ -struct hwrm_dbg_useq_flush_input { +__rte_packed_begin struct hwrm_dbg_useq_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -67707,10 +67707,10 @@ struct hwrm_dbg_useq_flush_input { HWRM_DBG_USEQ_FLUSH_INPUT_BUFFERS /* This field is reserved */ uint8_t unused_0[6]; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_useq_flush_output (size:256b/32B) */ -struct hwrm_dbg_useq_flush_output { +__rte_packed_begin struct hwrm_dbg_useq_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -67749,7 +67749,7 @@ struct hwrm_dbg_useq_flush_output { * the order of writes has to be such that this field is written last. */ uint32_t valid; -} __rte_packed; +} __rte_packed_end; /************************ * hwrm_dbg_useq_cw_cfg * @@ -67757,7 +67757,7 @@ struct hwrm_dbg_useq_flush_output { /* hwrm_dbg_useq_cw_cfg_input (size:960b/120B) */ -struct hwrm_dbg_useq_cw_cfg_input { +__rte_packed_begin struct hwrm_dbg_useq_cw_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -67832,10 +67832,10 @@ struct hwrm_dbg_useq_cw_cfg_input { HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_END /* command dependent data (e.g. function id for host dma command) */ uint32_t opaque[24]; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_useq_cw_cfg_output (size:192b/24B) */ -struct hwrm_dbg_useq_cw_cfg_output { +__rte_packed_begin struct hwrm_dbg_useq_cw_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -67864,7 +67864,7 @@ struct hwrm_dbg_useq_cw_cfg_output { uint8_t full_cnt; /* Reserved */ uint8_t useq_resp_unused_0[3]; -} __rte_packed; +} __rte_packed_end; /*********************** * hwrm_dbg_useq_qcaps * @@ -67872,7 +67872,7 @@ struct hwrm_dbg_useq_cw_cfg_output { /* hwrm_dbg_useq_qcaps_input (size:128b/16B) */ -struct hwrm_dbg_useq_qcaps_input { +__rte_packed_begin struct hwrm_dbg_useq_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -67901,10 +67901,10 @@ struct hwrm_dbg_useq_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_useq_qcaps_output (size:384b/48B) */ -struct hwrm_dbg_useq_qcaps_output { +__rte_packed_begin struct hwrm_dbg_useq_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -67951,7 +67951,7 @@ struct hwrm_dbg_useq_qcaps_output { * the order of writes has to be such that this field is written last. */ uint32_t valid; -} __rte_packed; +} __rte_packed_end; /*************************** * hwrm_dbg_useq_sched_cfg * @@ -67959,7 +67959,7 @@ struct hwrm_dbg_useq_qcaps_output { /* hwrm_dbg_useq_sched_cfg_input (size:192b/24B) */ -struct hwrm_dbg_useq_sched_cfg_input { +__rte_packed_begin struct hwrm_dbg_useq_sched_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -68013,10 +68013,10 @@ struct hwrm_dbg_useq_sched_cfg_input { uint16_t usid; /* This value represents microseconds between runs of the USEQ */ uint32_t polling_interval; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_useq_sched_cfg_output (size:256b/32B) */ -struct hwrm_dbg_useq_sched_cfg_output { +__rte_packed_begin struct hwrm_dbg_useq_sched_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -68055,7 +68055,7 @@ struct hwrm_dbg_useq_sched_cfg_output { * the order of writes has to be such that this field is written last. */ uint32_t valid; -} __rte_packed; +} __rte_packed_end; /********************* * hwrm_dbg_useq_run * @@ -68063,7 +68063,7 @@ struct hwrm_dbg_useq_sched_cfg_output { /* hwrm_dbg_useq_run_input (size:320b/40B) */ -struct hwrm_dbg_useq_run_input { +__rte_packed_begin struct hwrm_dbg_useq_run_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -68138,10 +68138,10 @@ struct hwrm_dbg_useq_run_input { uint32_t host_dest_len; /* This field is reserved */ uint32_t unused_0; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_useq_run_output (size:256b/32B) */ -struct hwrm_dbg_useq_run_output { +__rte_packed_begin struct hwrm_dbg_useq_run_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -68184,7 +68184,7 @@ struct hwrm_dbg_useq_run_output { * the order of writes has to be such that this field is written last. */ uint32_t valid; -} __rte_packed; +} __rte_packed_end; /****************************** * hwrm_dbg_useq_delivery_req * @@ -68192,7 +68192,7 @@ struct hwrm_dbg_useq_run_output { /* hwrm_dbg_useq_delivery_req_input (size:896b/112B) */ -struct hwrm_dbg_useq_delivery_req_input { +__rte_packed_begin struct hwrm_dbg_useq_delivery_req_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -68233,10 +68233,10 @@ struct hwrm_dbg_useq_delivery_req_input { * 4096 bytes. */ uint32_t host_dest_len[8]; -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_useq_delivery_req_output (size:512b/64B) */ -struct hwrm_dbg_useq_delivery_req_output { +__rte_packed_begin struct hwrm_dbg_useq_delivery_req_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -68281,7 +68281,7 @@ struct hwrm_dbg_useq_delivery_req_output { * the order of writes has to be such that this field is written last. */ uint32_t valid; -} __rte_packed; +} __rte_packed_end; /***************************** * hwrm_dbg_log_buffer_flush * @@ -68289,7 +68289,7 @@ struct hwrm_dbg_useq_delivery_req_output { /* hwrm_dbg_log_buffer_flush_input (size:192b/24B) */ -struct hwrm_dbg_log_buffer_flush_input { +__rte_packed_begin struct hwrm_dbg_log_buffer_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -68352,10 +68352,10 @@ struct hwrm_dbg_log_buffer_flush_input { */ #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_FLAGS_FLUSH_ALL_BUFFERS \ UINT32_C(0x1) -} __rte_packed; +} __rte_packed_end; /* hwrm_dbg_log_buffer_flush_output (size:128b/16B) */ -struct hwrm_dbg_log_buffer_flush_output { +__rte_packed_begin struct hwrm_dbg_log_buffer_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -68381,7 +68381,7 @@ struct hwrm_dbg_log_buffer_flush_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /***************** * hwrm_fw_reset * @@ -68389,7 +68389,7 @@ struct hwrm_dbg_log_buffer_flush_output { /* hwrm_fw_reset_input (size:192b/24B) */ -struct hwrm_fw_reset_input { +__rte_packed_begin struct hwrm_fw_reset_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -68484,10 +68484,10 @@ struct hwrm_fw_reset_input { */ #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1) uint8_t unused_0[4]; -} __rte_packed; +} __rte_packed_end; /* hwrm_fw_reset_output (size:128b/16B) */ -struct hwrm_fw_reset_output { +__rte_packed_begin struct hwrm_fw_reset_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -68521,7 +68521,7 @@ struct hwrm_fw_reset_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /********************** * hwrm_port_ts_query * @@ -68529,7 +68529,7 @@ struct hwrm_fw_reset_output { /* hwrm_port_ts_query_input (size:192b/24B) */ -struct hwrm_port_ts_query_input { +__rte_packed_begin struct hwrm_port_ts_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -68579,10 +68579,10 @@ struct hwrm_port_ts_query_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t unused_0[2]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_ts_query_output (size:192b/24B) */ -struct hwrm_port_ts_query_output { +__rte_packed_begin struct hwrm_port_ts_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -68607,7 +68607,7 @@ struct hwrm_port_ts_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; /* * This structure is fixed at the beginning of the ChiMP SRAM (GRC @@ -68617,7 +68617,7 @@ struct hwrm_port_ts_query_output { * FW_STATUS location in the next field. */ /* hcomm_status (size:64b/8B) */ -struct hcomm_status { +__rte_packed_begin struct hcomm_status { uint32_t sig_ver; /* * This field defines the version of the structure. The latest @@ -68654,7 +68654,7 @@ struct hcomm_status { */ #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc) #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 -} __rte_packed; +} __rte_packed_end; /* This is the GRC offset where the hcomm_status struct resides. */ #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL @@ -68664,7 +68664,7 @@ struct hcomm_status { /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ -struct hwrm_port_phy_i2c_read_input { +__rte_packed_begin struct hwrm_port_phy_i2c_read_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -68716,10 +68716,10 @@ struct hwrm_port_phy_i2c_read_input { */ uint8_t data_length; uint8_t unused_1[7]; -} __rte_packed; +} __rte_packed_end; /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ -struct hwrm_port_phy_i2c_read_output { +__rte_packed_begin struct hwrm_port_phy_i2c_read_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -68739,5 +68739,5 @@ struct hwrm_port_phy_i2c_read_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __rte_packed; +} __rte_packed_end; #endif /* _HSI_STRUCT_DEF_DPDK_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_resources.h b/drivers/net/bnxt/tf_core/tf_resources.h index e77e882b70..a0adb9ff56 100644 --- a/drivers/net/bnxt/tf_core/tf_resources.h +++ b/drivers/net/bnxt/tf_core/tf_resources.h @@ -22,7 +22,7 @@ enum tf_resc_opt { * WC TCAM includes a set of rows, and each row have 4-slices; * each slice has 160bit */ -typedef struct tf_resc_wc_tcam_usage { +typedef __rte_packed_begin struct tf_resc_wc_tcam_usage { uint16_t max_row_number; /* Max number of rows (excluding AFM), 160bit row */ uint16_t slice_row_1_p_used; /* 1-slice rows partially used */ uint16_t slice_row_1_f_used; /* 1-slice rows fully used */ @@ -31,47 +31,47 @@ typedef struct tf_resc_wc_tcam_usage { uint16_t slice_row_4_used; /* 4-slice rows fully used */ uint16_t unused_row_number; /* number of unused rows */ uint8_t reserved[2]; -} __rte_packed tf_resc_wc_tcam_usage_t; +} __rte_packed_end tf_resc_wc_tcam_usage_t; /* Resource Internal EM memory pool; vary size records */ -typedef struct tf_resc_em_usage { +typedef __rte_packed_begin struct tf_resc_em_usage { uint16_t max_entries; /* Max 16-Bytes entries */ uint16_t used_entries; /* each record takes up to 7 entries by design */ -} __rte_packed tf_resc_em_usage_t; +} __rte_packed_end tf_resc_em_usage_t; /* Resource Meter */ -typedef struct tf_resc_meter_usage { +typedef __rte_packed_begin struct tf_resc_meter_usage { uint16_t max_meter_instance; /* 1023 for Thor, app can reserve some entries */ uint16_t max_meter_profile; /* 256 for Thor, app can reserve some profiles */ uint16_t used_meter_instance; /* meter instance: fixed size record */ uint16_t used_meter_profile; /* meter profile: fixed size record */ -} __rte_packed tf_resc_meter_usage_t; +} __rte_packed_end tf_resc_meter_usage_t; /* Resource Counter */ -typedef struct tf_resc_cnt_usage { +typedef __rte_packed_begin struct tf_resc_cnt_usage { uint16_t max_entries; /* each counter take 64-Bytes */ uint16_t used_entries; /* each record uses one entry */ -} __rte_packed tf_resc_cnt_usage_t; +} __rte_packed_end tf_resc_cnt_usage_t; /* Resource Action */ -typedef struct tf_resc_act_usage { +typedef __rte_packed_begin struct tf_resc_act_usage { uint16_t max_entries; /* Max 8-Bytes entries */ uint16_t num_compact_act_records; /* 8-Bytes records */ uint16_t num_full_act_records; /* 16-Bytes records */ uint16_t free_entries; /* unused entries */ -} __rte_packed tf_resc_act_usage_t; +} __rte_packed_end tf_resc_act_usage_t; /* Resource SP SMAC */ -typedef struct tf_resc_act_sp_smac_usage { +typedef __rte_packed_begin struct tf_resc_act_sp_smac_usage { uint16_t max_entries; /* Max 8-Bytes entries */ uint16_t num_sp_smac_records; /* 8-Bytes records */ uint16_t num_sp_smac_ipv4_records; /* 8-Bytes records */ uint16_t num_sp_smac_ipv6_records; /* 16-Bytes records */ uint16_t free_entries; /* unused entries */ -} __rte_packed tf_resc_act_sp_smac_usage_t; +} __rte_packed_end tf_resc_act_sp_smac_usage_t; /* Resource ACT MODIFY and ACT ENCAP */ -typedef struct tf_resc_act_mod_enc_usage { +typedef __rte_packed_begin struct tf_resc_act_mod_enc_usage { uint16_t max_entries; /* Max 8-Bytes entries */ struct { uint16_t num_8b_records; /* 8-bytes records */ @@ -81,10 +81,10 @@ typedef struct tf_resc_act_mod_enc_usage { uint16_t num_128b_records; /* 128-bytes records */ } data; int16_t free_entries; /* unused entries */ -} __rte_packed tf_resc_act_mod_enc_usage_t; +} __rte_packed_end tf_resc_act_mod_enc_usage_t; /* All types of resource usage on both direction */ -typedef struct cfa_tf_resc_usage { +typedef __rte_packed_begin struct cfa_tf_resc_usage { tf_resc_em_usage_t em_int_usage; tf_resc_wc_tcam_usage_t wc_tcam_usage; tf_resc_cnt_usage_t cnt_usage; @@ -92,7 +92,7 @@ typedef struct cfa_tf_resc_usage { tf_resc_meter_usage_t meter_usage; tf_resc_act_mod_enc_usage_t mod_encap_usage; tf_resc_act_sp_smac_usage_t sp_smac_usage; -} __rte_packed cfa_tf_resc_usage_t; +} __rte_packed_end cfa_tf_resc_usage_t; /* global data stored in firmware memory and TruFlow driver */ extern cfa_tf_resc_usage_t tf_resc_usage[TF_DIR_MAX]; diff --git a/drivers/net/bnxt/tf_core/v3/tfc_mpc_table.c b/drivers/net/bnxt/tf_core/v3/tfc_mpc_table.c index 9b85ede417..abdc9b6517 100644 --- a/drivers/net/bnxt/tf_core/v3/tfc_mpc_table.c +++ b/drivers/net/bnxt/tf_core/v3/tfc_mpc_table.c @@ -540,20 +540,20 @@ struct stat_fields_s { uint64_t pkt_cnt; uint64_t byte_cnt; union { - struct { - uint32_t timestamp __rte_packed; - uint16_t tcp_flags __rte_packed; - } c_24b; + __rte_packed_begin struct { + uint32_t timestamp; + uint16_t tcp_flags; + } c_24b __rte_packed_end; struct { uint64_t meter_pkt_cnt; uint64_t meter_byte_cnt; } c_32b; - struct { - uint64_t timestamp:32 __rte_packed; - uint64_t tcp_flags:16 __rte_packed; - uint64_t meter_pkt_cnt:38 __rte_packed; - uint64_t meter_byte_cnt:42 __rte_packed; - } c_32b_all; + __rte_packed_begin struct { + uint64_t timestamp:32; + uint64_t tcp_flags:16; + uint64_t meter_pkt_cnt:38; + uint64_t meter_byte_cnt:42; + } c_32b_all __rte_packed_end; } t; }; diff --git a/drivers/net/bonding/rte_eth_bond_8023ad.h b/drivers/net/bonding/rte_eth_bond_8023ad.h index 5432eafcfe..eb1326de8c 100644 --- a/drivers/net/bonding/rte_eth_bond_8023ad.h +++ b/drivers/net/bonding/rte_eth_bond_8023ad.h @@ -51,18 +51,18 @@ enum rte_bond_8023ad_agg_selection { }; /** Generic slow protocol structure */ -struct slow_protocol { +__rte_packed_begin struct slow_protocol { uint8_t subtype; uint8_t reserved_119[119]; -} __rte_packed; +} __rte_packed_end; /** Generic slow protocol frame type structure */ -struct __rte_aligned(2) slow_protocol_frame { +__rte_packed_begin struct __rte_aligned(2) slow_protocol_frame { struct rte_ether_hdr eth_hdr; struct slow_protocol slow_protocol; -} __rte_packed; +} __rte_packed_end; -struct __rte_aligned(2) port_params { +__rte_packed_begin struct __rte_aligned(2) port_params { uint16_t system_priority; /**< System priority (unused in current implementation) */ struct rte_ether_addr system; @@ -73,18 +73,18 @@ struct __rte_aligned(2) port_params { /**< Priority of this (unused in current implementation) */ uint16_t port_number; /**< Port number. It corresponds to member port id. */ -} __rte_packed; +} __rte_packed_end; -struct __rte_aligned(2) lacpdu_actor_partner_params { +__rte_packed_begin struct __rte_aligned(2) lacpdu_actor_partner_params { uint8_t tlv_type_info; uint8_t info_length; struct port_params port_params; uint8_t state; uint8_t reserved_3[3]; -} __rte_packed; +} __rte_packed_end; /** LACPDU structure (5.4.2 in 802.1AX documentation). */ -struct __rte_aligned(2) lacpdu { +__rte_packed_begin struct __rte_aligned(2) lacpdu { uint8_t subtype; uint8_t version_number; @@ -99,15 +99,15 @@ struct __rte_aligned(2) lacpdu { uint8_t tlv_type_terminator; uint8_t terminator_length; uint8_t reserved_50[50]; -} __rte_packed; +} __rte_packed_end; /** LACPDU frame: Contains ethernet header and LACPDU. */ -struct __rte_aligned(2) lacpdu_header { +__rte_packed_begin struct __rte_aligned(2) lacpdu_header { struct rte_ether_hdr eth_hdr; struct lacpdu lacpdu; -} __rte_packed; +} __rte_packed_end; -struct __rte_aligned(2) marker { +__rte_packed_begin struct __rte_aligned(2) marker { uint8_t subtype; uint8_t version_number; @@ -121,12 +121,12 @@ struct __rte_aligned(2) marker { uint8_t tlv_type_terminator; uint8_t terminator_length; uint8_t reserved_90[90]; -} __rte_packed; +} __rte_packed_end; -struct __rte_aligned(2) marker_header { +__rte_packed_begin struct __rte_aligned(2) marker_header { struct rte_ether_hdr eth_hdr; struct marker marker; -} __rte_packed; +} __rte_packed_end; struct rte_eth_bond_8023ad_conf { uint32_t fast_periodic_ms; diff --git a/drivers/net/cnxk/cn10k_rxtx.h b/drivers/net/cnxk/cn10k_rxtx.h index ed54e5f920..462957ac90 100644 --- a/drivers/net/cnxk/cn10k_rxtx.h +++ b/drivers/net/cnxk/cn10k_rxtx.h @@ -92,7 +92,7 @@ struct cn10k_inb_priv_data { struct cnxk_eth_sec_sess *eth_sec; }; -struct cn10k_sec_sess_priv { +__rte_packed_begin struct cn10k_sec_sess_priv { union { struct { uint32_t sa_idx; @@ -110,7 +110,7 @@ struct cn10k_sec_sess_priv { uint64_t u64; }; -} __rte_packed; +} __rte_packed_end; #define LMT_OFF(lmt_addr, lmt_num, offset) \ (void *)((uintptr_t)(lmt_addr) + \ diff --git a/drivers/net/cnxk/cn20k_rxtx.h b/drivers/net/cnxk/cn20k_rxtx.h index 03eaf34d64..1dccf8209f 100644 --- a/drivers/net/cnxk/cn20k_rxtx.h +++ b/drivers/net/cnxk/cn20k_rxtx.h @@ -91,7 +91,7 @@ struct cn20k_inb_priv_data { struct cnxk_eth_sec_sess *eth_sec; }; -struct cn20k_sec_sess_priv { +__rte_packed_begin struct cn20k_sec_sess_priv { union { struct { uint32_t sa_idx; @@ -109,7 +109,7 @@ struct cn20k_sec_sess_priv { uint64_t u64; }; -} __rte_packed; +} __rte_packed_end; #define LMT_OFF(lmt_addr, lmt_num, offset) \ (void *)((uintptr_t)(lmt_addr) + ((uint64_t)(lmt_num) << ROC_LMT_LINE_SIZE_LOG2) + (offset)) diff --git a/drivers/net/cnxk/cn9k_ethdev.h b/drivers/net/cnxk/cn9k_ethdev.h index 4933954c33..47bc0591e6 100644 --- a/drivers/net/cnxk/cn9k_ethdev.h +++ b/drivers/net/cnxk/cn9k_ethdev.h @@ -86,7 +86,7 @@ struct cn9k_outb_priv_data { uint8_t iv_dbg[ROC_IE_ON_MAX_IV_LEN]; }; -struct cn9k_sec_sess_priv { +__rte_packed_begin struct cn9k_sec_sess_priv { union { struct { uint32_t sa_idx; @@ -99,7 +99,7 @@ struct cn9k_sec_sess_priv { uint64_t u64; }; -} __rte_packed; +} __rte_packed_end; /* Rx and Tx routines */ void cn9k_eth_set_rx_function(struct rte_eth_dev *eth_dev); diff --git a/drivers/net/cnxk/cnxk_rep_msg.h b/drivers/net/cnxk/cnxk_rep_msg.h index f5cb636c6c..885ffdb380 100644 --- a/drivers/net/cnxk/cnxk_rep_msg.h +++ b/drivers/net/cnxk/cnxk_rep_msg.h @@ -45,27 +45,27 @@ typedef enum CNXK_NACK_CODE { } cnxk_nack_code_t; /* Types */ -typedef struct cnxk_type_data { +typedef __rte_packed_begin struct cnxk_type_data { cnxk_type_t type; uint32_t length; uint64_t data[]; -} __rte_packed cnxk_type_data_t; +} __rte_packed_end cnxk_type_data_t; /* Header */ -typedef struct cnxk_header { +typedef __rte_packed_begin struct cnxk_header { uint64_t signature; uint16_t nb_hops; -} __rte_packed cnxk_header_t; +} __rte_packed_end cnxk_header_t; /* Message meta */ -typedef struct cnxk_rep_msg_data { +typedef __rte_packed_begin struct cnxk_rep_msg_data { cnxk_rep_msg_t type; uint32_t length; uint64_t data[]; -} __rte_packed cnxk_rep_msg_data_t; +} __rte_packed_end cnxk_rep_msg_data_t; /* Ack msg */ -typedef struct cnxk_rep_msg_ack_data { +typedef __rte_packed_begin struct cnxk_rep_msg_ack_data { cnxk_rep_msg_t type; uint32_t size; union { @@ -73,87 +73,87 @@ typedef struct cnxk_rep_msg_ack_data { uint64_t val; int64_t sval; } u; -} __rte_packed cnxk_rep_msg_ack_data_t; +} __rte_packed_end cnxk_rep_msg_ack_data_t; /* Ack msg */ -typedef struct cnxk_rep_msg_ack_data1 { +typedef __rte_packed_begin struct cnxk_rep_msg_ack_data1 { cnxk_rep_msg_t type; uint32_t size; uint64_t data[]; -} __rte_packed cnxk_rep_msg_ack_data1_t; +} __rte_packed_end cnxk_rep_msg_ack_data1_t; /* Ready msg */ -typedef struct cnxk_rep_msg_ready_data { +typedef __rte_packed_begin struct cnxk_rep_msg_ready_data { uint8_t val; uint16_t nb_ports; uint32_t data[]; -} __rte_packed cnxk_rep_msg_ready_data_t; +} __rte_packed_end cnxk_rep_msg_ready_data_t; /* Exit msg */ -typedef struct cnxk_rep_msg_exit_data { +typedef __rte_packed_begin struct cnxk_rep_msg_exit_data { uint8_t val; uint16_t nb_ports; uint16_t data[]; -} __rte_packed cnxk_rep_msg_exit_data_t; +} __rte_packed_end cnxk_rep_msg_exit_data_t; /* Ethernet op - set mac */ -typedef struct cnxk_rep_msg_eth_mac_set_meta { +typedef __rte_packed_begin struct cnxk_rep_msg_eth_mac_set_meta { uint16_t portid; uint8_t addr_bytes[RTE_ETHER_ADDR_LEN]; -} __rte_packed cnxk_rep_msg_eth_set_mac_meta_t; +} __rte_packed_end cnxk_rep_msg_eth_set_mac_meta_t; /* Ethernet op - get/clear stats */ -typedef struct cnxk_rep_msg_eth_stats_meta { +typedef __rte_packed_begin struct cnxk_rep_msg_eth_stats_meta { uint16_t portid; -} __rte_packed cnxk_rep_msg_eth_stats_meta_t; +} __rte_packed_end cnxk_rep_msg_eth_stats_meta_t; /* Flow create msg meta */ -typedef struct cnxk_rep_msg_flow_create_meta { +typedef __rte_packed_begin struct cnxk_rep_msg_flow_create_meta { uint16_t portid; uint16_t nb_pattern; uint16_t nb_action; -} __rte_packed cnxk_rep_msg_flow_create_meta_t; +} __rte_packed_end cnxk_rep_msg_flow_create_meta_t; /* Flow destroy msg meta */ -typedef struct cnxk_rep_msg_flow_destroy_meta { +typedef __rte_packed_begin struct cnxk_rep_msg_flow_destroy_meta { uint64_t flow; uint16_t portid; -} __rte_packed cnxk_rep_msg_flow_destroy_meta_t; +} __rte_packed_end cnxk_rep_msg_flow_destroy_meta_t; /* Flow flush msg meta */ -typedef struct cnxk_rep_msg_flow_flush_meta { +typedef __rte_packed_begin struct cnxk_rep_msg_flow_flush_meta { uint16_t portid; -} __rte_packed cnxk_rep_msg_flow_flush_meta_t; +} __rte_packed_end cnxk_rep_msg_flow_flush_meta_t; /* Flow dump msg meta */ -typedef struct cnxk_rep_msg_flow_dump_meta { +typedef __rte_packed_begin struct cnxk_rep_msg_flow_dump_meta { uint64_t flow; uint16_t portid; uint8_t is_stdout; -} __rte_packed cnxk_rep_msg_flow_dump_meta_t; +} __rte_packed_end cnxk_rep_msg_flow_dump_meta_t; /* Flow query msg meta */ -typedef struct cnxk_rep_msg_flow_query_meta { +typedef __rte_packed_begin struct cnxk_rep_msg_flow_query_meta { uint64_t flow; uint16_t portid; uint8_t reset; uint32_t action_data_sz; uint8_t action_data[]; -} __rte_packed cnxk_rep_msg_flow_query_meta_t; +} __rte_packed_end cnxk_rep_msg_flow_query_meta_t; /* Type pattern meta */ -typedef struct cnxk_pattern_hdr { +typedef __rte_packed_begin struct cnxk_pattern_hdr { uint16_t type; uint16_t spec_sz; uint16_t last_sz; uint16_t mask_sz; -} __rte_packed cnxk_pattern_hdr_t; +} __rte_packed_end cnxk_pattern_hdr_t; /* Type action meta */ -typedef struct cnxk_action_hdr { +typedef __rte_packed_begin struct cnxk_action_hdr { uint16_t type; uint16_t conf_sz; -} __rte_packed cnxk_action_hdr_t; +} __rte_packed_end cnxk_action_hdr_t; void cnxk_rep_msg_populate_command(void *buffer, uint32_t *length, cnxk_rep_msg_t type, uint32_t size); diff --git a/drivers/net/dpaa/dpaa_rxtx.h b/drivers/net/dpaa/dpaa_rxtx.h index 392926e286..ad9f315a61 100644 --- a/drivers/net/dpaa/dpaa_rxtx.h +++ b/drivers/net/dpaa/dpaa_rxtx.h @@ -173,12 +173,12 @@ enum dpaa_parse_result_l4_type { /** * FMan parse result array */ -struct dpaa_eth_parse_results_t { +__rte_packed_begin struct dpaa_eth_parse_results_t { uint8_t lpid; /**< Logical port id */ uint8_t shimr; /**< Shim header result */ - union { + __rte_packed_begin union { uint16_t l2r; /**< Layer 2 result */ - struct { + __rte_packed_begin struct { uint16_t unused_1:3; uint16_t ppoe_ppp:1; uint16_t mpls:1; @@ -190,11 +190,11 @@ struct dpaa_eth_parse_results_t { uint16_t eth_frame_type:2; /*00-unicast, 01-multicast, 11-broadcast*/ uint16_t unknown_eth_proto:1; - } __rte_packed; - } __rte_packed; - union { + } __rte_packed_end; + } __rte_packed_end; + __rte_packed_begin union { uint16_t l3r; /**< Layer 3 result */ - struct { + __rte_packed_begin struct { uint16_t unused_2:1; uint16_t l3_err:1; uint16_t last_ipv6:1; @@ -205,19 +205,19 @@ struct dpaa_eth_parse_results_t { uint16_t first_ipv4:1; uint16_t unused_3:8; - } __rte_packed; - } __rte_packed; - union { + } __rte_packed_end; + } __rte_packed_end; + __rte_packed_begin union { uint8_t l4r; /**< Layer 4 result */ - struct{ + __rte_packed_begin struct{ uint8_t l4cv:1; uint8_t unused_4:1; uint8_t ah:1; uint8_t esp_sum:1; uint8_t l4_info_err:1; uint8_t l4_type:3; - } __rte_packed; - } __rte_packed; + } __rte_packed_end; + } __rte_packed_end; uint8_t cplan; /**< Classification plan id */ uint16_t nxthdr; /**< Next Header */ uint16_t cksum; /**< Checksum */ @@ -233,7 +233,7 @@ struct dpaa_eth_parse_results_t { uint8_t gre_off; /**< GRE offset */ uint8_t l4_off; /**< Layer 4 offset */ uint8_t nxthdr_off; /**< Parser end point */ -} __rte_packed; +} __rte_packed_end; /* The structure is the Prepended Data to the Frame which is used by FMAN */ struct annotations_t { diff --git a/drivers/net/dpaa/fmlib/fm_ext.h b/drivers/net/dpaa/fmlib/fm_ext.h index 9a3193674e..e3fb38e7e9 100644 --- a/drivers/net/dpaa/fmlib/fm_ext.h +++ b/drivers/net/dpaa/fmlib/fm_ext.h @@ -76,7 +76,7 @@ typedef enum e_fm_port_type { /* * @Description Parse results memory layout */ -typedef struct t_fm_prs_result { +typedef __rte_packed_begin struct t_fm_prs_result { volatile uint8_t lpid; /**< Logical port id */ volatile uint8_t shimr; /**< Shim header result */ volatile uint16_t l2r; /**< Layer 2 result */ @@ -109,7 +109,7 @@ typedef struct t_fm_prs_result { volatile uint8_t gre_off; /**< GRE offset */ volatile uint8_t l4_off; /**< Layer 4 offset */ volatile uint8_t nxthdr_off; /**< Parser end point */ -} __rte_packed t_fm_prs_result; +} __rte_packed_end t_fm_prs_result; /* * @Collection FM Parser results diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h b/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h index 7e5e499b6a..e807060294 100644 --- a/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h +++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h @@ -32,12 +32,12 @@ extern "C" { #define DPAA2_FD_CTRL_PTV1 0x00400000 /* Frame annotation status */ -struct dpaa2_fas { +__rte_packed_begin struct dpaa2_fas { uint8_t reserved; uint8_t ppid; __le16 ifpid; __le32 status; -} __rte_packed; +} __rte_packed_end; /** * HW Packet Annotation Register structures diff --git a/drivers/net/dpaa2/dpaa2_recycle.c b/drivers/net/dpaa2/dpaa2_recycle.c index 4fde9b95a0..eec99c3475 100644 --- a/drivers/net/dpaa2/dpaa2_recycle.c +++ b/drivers/net/dpaa2/dpaa2_recycle.c @@ -67,18 +67,18 @@ #define FSL_LS_SRDS1_PRTCL_MASK 0xFFFF0000 #define FSL_LS_SRDS2_PRTCL_MASK 0x0000FFFF -struct ccsr_lx_serdes_lan { +__rte_packed_begin struct ccsr_lx_serdes_lan { uint8_t unused1[0xa0]; uint32_t lnatcsr0; uint8_t unused2[0x100 - 0xa4]; -} __rte_packed; +} __rte_packed_end; -struct ccsr_lx_serdes { +__rte_packed_begin struct ccsr_lx_serdes { uint8_t unused0[0x800]; struct ccsr_lx_serdes_lan lane[LSX_SERDES_LAN_NB]; -} __rte_packed; +} __rte_packed_end; -struct ccsr_ls_serdes { +__rte_packed_begin struct ccsr_ls_serdes { uint8_t unused[0x800]; struct serdes_lane { uint32_t gcr0; /* General Control Register 0 */ @@ -94,9 +94,9 @@ struct ccsr_ls_serdes { uint32_t tsc3; } lane[LSX_SERDES_LAN_NB]; uint8_t res5[0x19fc - 0xa00]; -} __rte_packed; +} __rte_packed_end; -struct ccsr_gur { +__rte_packed_begin struct ccsr_gur { uint32_t porsr1; /* POR status 1 */ uint32_t porsr2; /* POR status 2 */ uint8_t res_008[0x20 - 0x8]; @@ -170,7 +170,7 @@ struct ccsr_gur { uint32_t ipbrr1; uint32_t ipbrr2; uint8_t res_858[0x1000 - 0xc00]; -} __rte_packed; +} __rte_packed_end; static void *lsx_ccsr_map_region(uint64_t addr, size_t len) { diff --git a/drivers/net/enic/base/vnic_devcmd.h b/drivers/net/enic/base/vnic_devcmd.h index 2b3be855f9..f784978595 100644 --- a/drivers/net/enic/base/vnic_devcmd.h +++ b/drivers/net/enic/base/vnic_devcmd.h @@ -798,13 +798,13 @@ struct vnic_devcmd_provinfo { FILTER_FIELD_USNIC_PROTO | \ FILTER_FIELD_USNIC_ID) -struct filter_usnic_id { +__rte_packed_begin struct filter_usnic_id { uint32_t flags; uint16_t vlan; uint16_t ethtype; uint8_t proto_version; uint32_t usnic_id; -} __rte_packed; +} __rte_packed_end; #define FILTER_FIELD_5TUP_PROTO FILTER_FIELD_VALID(1) #define FILTER_FIELD_5TUP_SRC_AD FILTER_FIELD_VALID(2) @@ -826,14 +826,14 @@ enum protocol_e { PROTO_IPV6 = 3 }; -struct filter_ipv4_5tuple { +__rte_packed_begin struct filter_ipv4_5tuple { uint32_t flags; uint32_t protocol; uint32_t src_addr; uint32_t dst_addr; uint16_t src_port; uint16_t dst_port; -} __rte_packed; +} __rte_packed_end; #define FILTER_FIELD_VMQ_VLAN FILTER_FIELD_VALID(1) #define FILTER_FIELD_VMQ_MAC FILTER_FIELD_VALID(2) @@ -843,11 +843,11 @@ struct filter_ipv4_5tuple { #define FILTER_FIELDS_NVGRE FILTER_FIELD_VMQ_MAC -struct filter_mac_vlan { +__rte_packed_begin struct filter_mac_vlan { uint32_t flags; uint16_t vlan; uint8_t mac_addr[6]; -} __rte_packed; +} __rte_packed_end; #define FILTER_FIELD_VLAN_IP_3TUP_VLAN FILTER_FIELD_VALID(1) #define FILTER_FIELD_VLAN_IP_3TUP_L3_PROTO FILTER_FIELD_VALID(2) @@ -861,7 +861,7 @@ struct filter_mac_vlan { FILTER_FIELD_VLAN_IP_3TUP_L4_PROTO | \ FILTER_FIELD_VLAN_IP_3TUP_DST_PT) -struct filter_vlan_ip_3tuple { +__rte_packed_begin struct filter_vlan_ip_3tuple { uint32_t flags; uint16_t vlan; uint16_t l3_protocol; @@ -871,7 +871,7 @@ struct filter_vlan_ip_3tuple { } u; uint32_t l4_protocol; uint16_t dst_port; -} __rte_packed; +} __rte_packed_end; #define FILTER_GENERIC_1_BYTES 64 @@ -898,19 +898,19 @@ enum filter_generic_1_layer { * Version 1 of generic filter specification * position is only 16 bits, reserving positions > 64k to be used by firmware */ -struct filter_generic_1 { +__rte_packed_begin struct filter_generic_1 { uint16_t position; /* lower position comes first */ uint32_t mask_flags; uint32_t val_flags; uint16_t mask_vlan; uint16_t val_vlan; - struct { + __rte_packed_begin struct { uint8_t mask[FILTER_GENERIC_1_KEY_LEN]; /* 0 bit means * " don't care" */ uint8_t val[FILTER_GENERIC_1_KEY_LEN]; - } __rte_packed layer[FILTER_GENERIC_1_NUM_LAYERS]; -} __rte_packed; + } __rte_packed_end layer[FILTER_GENERIC_1_NUM_LAYERS]; +} __rte_packed_end; /* Specifies the filter_action type. */ enum { @@ -919,12 +919,12 @@ enum { FILTER_ACTION_MAX }; -struct filter_action { +__rte_packed_begin struct filter_action { uint32_t type; union { uint32_t rq_idx; } u; -} __rte_packed; +} __rte_packed_end; #define FILTER_ACTION_RQ_STEERING_FLAG (1 << 0) #define FILTER_ACTION_FILTER_ID_FLAG (1 << 1) @@ -937,13 +937,13 @@ struct filter_action { /* Version 2 of filter action must be a strict extension of struct * filter_action where the first fields exactly match in size and meaning. */ -struct filter_action_v2 { +__rte_packed_begin struct filter_action_v2 { uint32_t type; uint32_t rq_idx; uint32_t flags; /* use FILTER_ACTION_XXX_FLAG defines */ uint16_t filter_id; uint8_t reserved[32]; /* for future expansion */ -} __rte_packed; +} __rte_packed_end; /* Specifies the filter type. */ enum filter_type { @@ -973,7 +973,7 @@ enum filter_type { FILTER_USNIC_IP_FLAG | \ FILTER_DPDK_1_FLAG) -struct filter { +__rte_packed_begin struct filter { uint32_t type; union { struct filter_usnic_id usnic; @@ -981,7 +981,7 @@ struct filter { struct filter_mac_vlan mac_vlan; struct filter_vlan_ip_3tuple vlan_3tuple; } u; -} __rte_packed; +} __rte_packed_end; /* * This is a strict superset of "struct filter" and exists only @@ -992,7 +992,7 @@ struct filter { * the TLV size instead of sizeof (struct fiter_v2) to guard against future * growth. */ -struct filter_v2 { +__rte_packed_begin struct filter_v2 { uint32_t type; union { struct filter_usnic_id usnic; @@ -1001,7 +1001,7 @@ struct filter_v2 { struct filter_vlan_ip_3tuple vlan_3tuple; struct filter_generic_1 generic_1; } u; -} __rte_packed; +} __rte_packed_end; enum { CLSF_TLV_FILTER = 0, diff --git a/drivers/net/enic/base/vnic_flowman.h b/drivers/net/enic/base/vnic_flowman.h index 81e2cff1b0..cfe0cbadea 100644 --- a/drivers/net/enic/base/vnic_flowman.h +++ b/drivers/net/enic/base/vnic_flowman.h @@ -100,23 +100,23 @@ enum { #define FM_LAYER_SIZE 64 /* Header match pattern */ -struct fm_header_set { +__rte_packed_begin struct fm_header_set { uint32_t fk_metadata; /* FKM flags */ uint32_t fk_header_select; /* FKH flags */ uint16_t fk_vlan; /* L2: Ethernet Header (valid if FKH_ETHER) */ - union { - struct { + __rte_packed_begin union { + __rte_packed_begin struct { uint8_t fk_dstmac[FM_ETH_ALEN]; uint8_t fk_srcmac[FM_ETH_ALEN]; uint16_t fk_ethtype; - } __rte_packed eth; + } __rte_packed_end eth; uint8_t rawdata[FM_LAYER_SIZE]; - } __rte_packed l2; + } __rte_packed_end l2; /* L3: IPv4 or IPv6 (valid if FKH_IPV4,6) */ - union { + __rte_packed_begin union { /* Valid if FKH_IPV4 */ - struct { + __rte_packed_begin struct { uint8_t fk_ihl_vers; uint8_t fk_tos; uint16_t fk_tot_len; @@ -127,9 +127,9 @@ struct fm_header_set { uint16_t fk_check; uint32_t fk_saddr; uint32_t fk_daddr; - } __rte_packed ip4; + } __rte_packed_end ip4; /* Valid if FKH_IPV6 */ - struct { + __rte_packed_begin struct { union { struct { uint32_t fk_un1_flow; @@ -141,18 +141,18 @@ struct fm_header_set { } ctl; uint8_t fk_srcip[16]; uint8_t fk_dstip[16]; - } __rte_packed ip6; + } __rte_packed_end ip6; uint8_t rawdata[FM_LAYER_SIZE]; - } __rte_packed l3; + } __rte_packed_end l3; /* L4: UDP, TCP, or ICMP (valid if FKH_UDP,TCP,ICMP) */ - union { - struct { + __rte_packed_begin union { + __rte_packed_begin struct { uint16_t fk_source; uint16_t fk_dest; uint16_t fk_len; uint16_t fk_check; - } __rte_packed udp; - struct { + } __rte_packed_end udp; + __rte_packed_begin struct { uint16_t fk_source; uint16_t fk_dest; uint32_t fk_seq; @@ -161,23 +161,23 @@ struct fm_header_set { uint16_t fk_window; uint16_t fk_check; uint16_t fk_urg_ptr; - } __rte_packed tcp; - struct { + } __rte_packed_end tcp; + __rte_packed_begin struct { uint8_t fk_code; uint8_t fk_type; - } __rte_packed icmp; + } __rte_packed_end icmp; uint8_t rawdata[FM_LAYER_SIZE]; - } __rte_packed l4; + } __rte_packed_end l4; /* VXLAN (valid if FKH_VXLAN) */ - struct { + __rte_packed_begin struct { uint8_t fkvx_flags; uint8_t fkvx_res0[3]; uint8_t fkvx_vni[3]; uint8_t fkvx_res1; - } __rte_packed vxlan; + } __rte_packed_end vxlan; /* Payload or unknown inner-most protocol */ uint8_t fk_l5_data[64]; -} __rte_packed; +} __rte_packed_end; /* * FK (flow key) template. @@ -186,7 +186,7 @@ struct fm_header_set { */ #define FM_HDRSET_MAX 2 -struct fm_key_template { +__rte_packed_begin struct fm_key_template { struct fm_header_set fk_hdrset[FM_HDRSET_MAX]; uint32_t fk_flags; uint16_t fk_packet_tag; @@ -194,7 +194,7 @@ struct fm_key_template { uint16_t fk_port_id; uint32_t fk_wq_id; /* WQ index */ uint64_t fk_wq_vnic; /* VNIC handle for WQ index */ -} __rte_packed; +} __rte_packed_end; /* Action operation types */ enum { @@ -260,11 +260,11 @@ enum { * encap" and also simple ops like insert this data, add PACKET_LEN to * this address, etc. */ -struct fm_action_op { +__rte_packed_begin struct fm_action_op { uint32_t fa_op; /* FMOP flags */ - union { - struct { + __rte_packed_begin union { + __rte_packed_begin struct { uint8_t len1_offset; uint8_t len1_delta; uint8_t len2_offset; @@ -272,35 +272,35 @@ struct fm_action_op { uint16_t outer_vlan; uint8_t template_offset; uint8_t template_len; - } __rte_packed encap; - struct { + } __rte_packed_end encap; + __rte_packed_begin struct { uint16_t rq_index; uint16_t rq_count; uint64_t vnic_handle; - } __rte_packed rq_steer; - struct { + } __rte_packed_end rq_steer; + __rte_packed_begin struct { uint16_t vlan; - } __rte_packed ovlan; - struct { + } __rte_packed_end ovlan; + __rte_packed_begin struct { uint16_t vlan; - } __rte_packed set_encap_vlan; - struct { + } __rte_packed_end set_encap_vlan; + __rte_packed_begin struct { uint16_t mark; - } __rte_packed mark; - struct { + } __rte_packed_end mark; + __rte_packed_begin struct { uint32_t ext_mark; - } __rte_packed ext_mark; - struct { + } __rte_packed_end ext_mark; + __rte_packed_begin struct { uint8_t tag; - } __rte_packed tag; - struct { + } __rte_packed_end tag; + __rte_packed_begin struct { uint64_t handle; - } __rte_packed exact; - struct { + } __rte_packed_end exact; + __rte_packed_begin struct { uint32_t egport; - } __rte_packed set_egport; - } __rte_packed; -} __rte_packed; + } __rte_packed_end set_egport; + } __rte_packed_end; +} __rte_packed_end; #define FM_ACTION_OP_MAX 64 #define FM_ACTION_DATA_MAX 96 @@ -309,31 +309,31 @@ struct fm_action_op { * Action is a series of action operations applied to matched * packet. FMA (flowman action). */ -struct fm_action { +__rte_packed_begin struct fm_action { struct fm_action_op fma_action_ops[FM_ACTION_OP_MAX]; uint8_t fma_data[FM_ACTION_DATA_MAX]; -} __rte_packed; +} __rte_packed_end; /* Match entry flags. FMEF (flow match entry flag) */ #define FMEF_COUNTER 0x0001 /* counter index is valid */ /* FEM (flow exact match) entry */ -struct fm_exact_match_entry { +__rte_packed_begin struct fm_exact_match_entry { struct fm_key_template fem_data; /* Match data. Mask is per table */ uint32_t fem_flags; /* FMEF_xxx */ uint64_t fem_action; /* Action handle */ uint32_t fem_counter; /* Counter index */ -} __rte_packed; +} __rte_packed_end; /* FTM (flow TCAM match) entry */ -struct fm_tcam_match_entry { +__rte_packed_begin struct fm_tcam_match_entry { struct fm_key_template ftm_mask; /* Key mask */ struct fm_key_template ftm_data; /* Match data */ uint32_t ftm_flags; /* FMEF_xxx */ uint32_t ftm_position; /* Entry position */ uint64_t ftm_action; /* Action handle */ uint32_t ftm_counter; /* Counter index */ -} __rte_packed; +} __rte_packed_end; /* Match directions */ enum { @@ -346,34 +346,34 @@ enum { #define FM_STAGE_LAST 0xff /* Hash based exact match table. FET (flow exact match table) */ -struct fm_exact_match_table { +__rte_packed_begin struct fm_exact_match_table { uint8_t fet_direction; /* FM_INGRESS or EGRESS*/ uint8_t fet_stage; uint8_t pad[2]; uint32_t fet_max_entries; uint64_t fet_dflt_action; struct fm_key_template fet_key; -} __rte_packed; +} __rte_packed_end; /* TCAM based match table. FTT (flow TCAM match table) */ -struct fm_tcam_match_table { +__rte_packed_begin struct fm_tcam_match_table { uint8_t ftt_direction; uint8_t ftt_stage; uint8_t pad[2]; uint32_t ftt_max_entries; -} __rte_packed; +} __rte_packed_end; -struct fm_counter_counts { +__rte_packed_begin struct fm_counter_counts { uint64_t fcc_packets; uint64_t fcc_bytes; -} __rte_packed; +} __rte_packed_end; /* * Return structure for FM_INFO_QUERY devcmd */ #define FM_VERSION 1 /* This header file is for version 1 */ -struct fm_info { +__rte_packed_begin struct fm_info { uint64_t fm_op_mask; /* Bitmask of action supported ops */ uint64_t fm_current_ts; /* Current VIC timestamp */ uint64_t fm_clock_freq; /* Timestamp clock frequency */ @@ -381,6 +381,6 @@ struct fm_info { uint8_t fm_stages; /* Number of match-action stages */ uint8_t pad[5]; uint32_t fm_counter_count; /* Number of allocated counters */ -} __rte_packed; +} __rte_packed_end; #endif /* _VNIC_FLOWMAN_H_ */ diff --git a/drivers/net/gve/base/gve_desc.h b/drivers/net/gve/base/gve_desc.h index 006b36442f..a54767093a 100644 --- a/drivers/net/gve/base/gve_desc.h +++ b/drivers/net/gve/base/gve_desc.h @@ -22,7 +22,7 @@ * rings. */ -struct gve_tx_pkt_desc { +__rte_packed_begin struct gve_tx_pkt_desc { u8 type_flags; /* desc type is lower 4 bits, flags upper */ u8 l4_csum_offset; /* relative offset of L4 csum word */ u8 l4_hdr_offset; /* Offset of start of L4 headers in packet */ @@ -30,24 +30,24 @@ struct gve_tx_pkt_desc { __be16 len; /* Total length of this packet (in bytes) */ __be16 seg_len; /* Length of this descriptor's segment */ __be64 seg_addr; /* Base address (see note) of this segment */ -} __packed; +} __rte_packed_end; -struct gve_tx_mtd_desc { +__rte_packed_begin struct gve_tx_mtd_desc { u8 type_flags; /* type is lower 4 bits, subtype upper */ u8 path_state; /* state is lower 4 bits, hash type upper */ __be16 reserved0; __be32 path_hash; __be64 reserved1; -} __packed; +} __rte_packed_end; -struct gve_tx_seg_desc { +__rte_packed_begin struct gve_tx_seg_desc { u8 type_flags; /* type is lower 4 bits, flags upper */ u8 l3_offset; /* TSO: 2 byte units to start of IPH */ __be16 reserved; __be16 mss; /* TSO MSS */ __be16 seg_len; __be64 seg_addr; -} __packed; +} __rte_packed_end; /* GVE Transmit Descriptor Types */ #define GVE_TXD_STD (0x0 << 4) /* Std with Host Address */ @@ -80,7 +80,7 @@ struct gve_tx_seg_desc { */ #define GVE_RX_PAD 2 -struct gve_rx_desc { +__rte_packed_begin struct gve_rx_desc { u8 padding[48]; __be32 rss_hash; /* Receive-side scaling hash (Toeplitz for gVNIC) */ __be16 mss; @@ -90,7 +90,7 @@ struct gve_rx_desc { __sum16 csum; /* 1's-complement partial checksum of L3+ bytes */ __be16 len; /* Length of the received packet */ __be16 flags_seq; /* Flags [15:3] and sequence number [2:0] (1-7) */ -} __packed; +} __rte_packed_end; GVE_CHECK_STRUCT_LEN(64, gve_rx_desc); /* If the device supports raw dma addressing then the addr in data slot is diff --git a/drivers/net/gve/base/gve_desc_dqo.h b/drivers/net/gve/base/gve_desc_dqo.h index bb4a18d4d1..e950bc3601 100644 --- a/drivers/net/gve/base/gve_desc_dqo.h +++ b/drivers/net/gve/base/gve_desc_dqo.h @@ -14,7 +14,7 @@ #define GVE_TX_MIN_TSO_MSS_DQO 88 /* Basic TX descriptor (DTYPE 0x0C) */ -struct gve_tx_pkt_desc_dqo { +__rte_packed_begin struct gve_tx_pkt_desc_dqo { __le64 buf_addr; /* Must be GVE_TX_PKT_DESC_DTYPE_DQO (0xc) */ @@ -34,7 +34,7 @@ struct gve_tx_pkt_desc_dqo { __le16 compl_tag; u16 buf_size: 14; u16 reserved2: 2; -} __packed; +} __rte_packed_end; GVE_CHECK_STRUCT_LEN(16, gve_tx_pkt_desc_dqo); #define GVE_TX_PKT_DESC_DTYPE_DQO 0xc @@ -66,7 +66,7 @@ GVE_CHECK_STRUCT_LEN(2, gve_tx_context_cmd_dtype); * * "flex" fields allow the driver to send additional packet context to HW. */ -struct gve_tx_tso_context_desc_dqo { +__rte_packed_begin struct gve_tx_tso_context_desc_dqo { /* The L4 payload bytes that should be segmented. */ u32 tso_total_len: 24; u32 flex10: 8; @@ -84,13 +84,13 @@ struct gve_tx_tso_context_desc_dqo { u8 flex7; u8 flex8; u8 flex9; -} __packed; +} __rte_packed_end; GVE_CHECK_STRUCT_LEN(16, gve_tx_tso_context_desc_dqo); #define GVE_TX_TSO_CTX_DESC_DTYPE_DQO 0x5 /* General context descriptor for sending metadata. */ -struct gve_tx_general_context_desc_dqo { +__rte_packed_begin struct gve_tx_general_context_desc_dqo { u8 flex4; u8 flex5; u8 flex6; @@ -105,7 +105,7 @@ struct gve_tx_general_context_desc_dqo { u8 flex1; u8 flex2; u8 flex3; -} __packed; +} __rte_packed_end; GVE_CHECK_STRUCT_LEN(16, gve_tx_general_context_desc_dqo); #define GVE_TX_GENERAL_CTX_DESC_DTYPE_DQO 0x4 @@ -113,9 +113,9 @@ GVE_CHECK_STRUCT_LEN(16, gve_tx_general_context_desc_dqo); /* Logical structure of metadata which is packed into context descriptor flex * fields. */ -struct gve_tx_metadata_dqo { +__rte_packed_begin struct gve_tx_metadata_dqo { union { - struct { + __rte_packed_begin struct { u8 version; /* If `skb->l4_hash` is set, this value should be @@ -130,16 +130,16 @@ struct gve_tx_metadata_dqo { * skb had a rehash from the TCP stack. */ u16 rehash_event: 1; - } __packed; + } __rte_packed_end; u8 bytes[12]; }; -} __packed; +} __rte_packed_end; GVE_CHECK_STRUCT_LEN(12, gve_tx_metadata_dqo); #define GVE_TX_METADATA_VERSION_DQO 0 /* TX completion descriptor */ -struct gve_tx_compl_desc { +__rte_packed_begin struct gve_tx_compl_desc { /* For types 0-4 this is the TX queue ID associated with this * completion. */ @@ -163,7 +163,7 @@ struct gve_tx_compl_desc { __le16 completion_tag; }; __le32 reserved1; -} __packed; +} __rte_packed_end; GVE_CHECK_STRUCT_LEN(8, gve_tx_compl_desc); #define GVE_COMPL_TYPE_DQO_PKT 0x2 /* Packet completion */ @@ -172,18 +172,18 @@ GVE_CHECK_STRUCT_LEN(8, gve_tx_compl_desc); #define GVE_COMPL_TYPE_DQO_REINJECTION 0x3 /* Re-injection completion */ /* Descriptor to post buffers to HW on buffer queue. */ -struct gve_rx_desc_dqo { +__rte_packed_begin struct gve_rx_desc_dqo { __le16 buf_id; /* ID returned in Rx completion descriptor */ __le16 reserved0; __le32 reserved1; __le64 buf_addr; /* DMA address of the buffer */ __le64 header_buf_addr; __le64 reserved2; -} __packed; +} __rte_packed_end; GVE_CHECK_STRUCT_LEN(32, gve_rx_desc_dqo); /* Descriptor for HW to notify SW of new packets received on RX queue. */ -struct gve_rx_compl_desc_dqo { +__rte_packed_begin struct gve_rx_compl_desc_dqo { /* Must be 1 */ u8 rxdid: 4; u8 reserved0: 4; @@ -238,7 +238,7 @@ struct gve_rx_compl_desc_dqo { __le32 hash; __le32 reserved6; __le64 reserved7; -} __packed; +} __rte_packed_end; GVE_CHECK_STRUCT_LEN(32, gve_rx_compl_desc_dqo); diff --git a/drivers/net/gve/base/gve_osdep.h b/drivers/net/gve/base/gve_osdep.h index 64181cebd6..cb3936c150 100644 --- a/drivers/net/gve/base/gve_osdep.h +++ b/drivers/net/gve/base/gve_osdep.h @@ -95,9 +95,6 @@ #ifndef ____cacheline_aligned #define ____cacheline_aligned __rte_cache_aligned #endif -#ifndef __packed -#define __packed __rte_packed -#endif #define __iomem #define msleep(ms) rte_delay_ms(ms) diff --git a/drivers/net/hns3/hns3_mbx.h b/drivers/net/hns3/hns3_mbx.h index 2b6cb8f513..3f923f128a 100644 --- a/drivers/net/hns3/hns3_mbx.h +++ b/drivers/net/hns3/hns3_mbx.h @@ -112,18 +112,18 @@ struct hns3_ring_chain_param { uint8_t int_gl_index; }; -struct hns3_mbx_vlan_filter { +__rte_packed_begin struct hns3_mbx_vlan_filter { uint8_t is_kill; uint16_t vlan_id; uint16_t proto; -} __rte_packed; +} __rte_packed_end; -struct hns3_mbx_link_status { +__rte_packed_begin struct hns3_mbx_link_status { uint16_t link_status; uint32_t speed; uint16_t duplex; uint8_t flag; -} __rte_packed; +} __rte_packed_end; #define HNS3_MBX_MSG_MAX_DATA_SIZE 14 #define HNS3_MBX_MAX_RING_CHAIN_PARAM_NUM 4 diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index e975cd151a..da8056f2cf 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -214,7 +214,7 @@ enum hns3_pkt_tun_type { }; /* hardware spec ring buffer format */ -struct hns3_desc { +__rte_packed_begin struct hns3_desc { union { uint64_t addr; uint64_t timestamp; @@ -282,7 +282,7 @@ struct hns3_desc { }; } rx; }; -} __rte_packed; +} __rte_packed_end; struct hns3_entry { struct rte_mbuf *mbuf; diff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40e/base/i40e_osdep.h index 8960206d8b..fde763ef6f 100644 --- a/drivers/net/i40e/base/i40e_osdep.h +++ b/drivers/net/i40e/base/i40e_osdep.h @@ -177,21 +177,23 @@ static inline uint64_t i40e_read64_addr(volatile void *addr) #define ARRAY_SIZE(arr) RTE_DIM(arr) /* memory allocation tracking */ +__rte_packed_begin struct i40e_dma_mem { void *va; u64 pa; u32 size; const void *zone; -} __rte_packed; +} __rte_packed_end; #define i40e_allocate_dma_mem(h, m, unused, s, a) \ i40e_allocate_dma_mem_d(h, m, s, a) #define i40e_free_dma_mem(h, m) i40e_free_dma_mem_d(h, m) +__rte_packed_begin struct i40e_virt_mem { void *va; u32 size; -} __rte_packed; +} __rte_packed_end; #define i40e_allocate_virt_mem(h, m, s) i40e_allocate_virt_mem_d(h, m, s) #define i40e_free_virt_mem(h, m) i40e_free_virt_mem_d(h, m) diff --git a/drivers/net/iavf/iavf_ipsec_crypto.h b/drivers/net/iavf/iavf_ipsec_crypto.h index 49f9202aca..58ca7bc648 100644 --- a/drivers/net/iavf/iavf_ipsec_crypto.h +++ b/drivers/net/iavf/iavf_ipsec_crypto.h @@ -11,12 +11,14 @@ +__rte_packed_begin struct iavf_tx_ipsec_desc { union { struct { __le64 qw0; __le64 qw1; }; + __rte_packed_begin struct { __le16 l4payload_length; __le32 esn; @@ -28,9 +30,9 @@ struct iavf_tx_ipsec_desc { u8 next_header; __le16 ipv6_ext_hdr_length; __le32 said; - } __rte_packed; + } __rte_packed_end; }; -} __rte_packed; +} __rte_packed_end; #define IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_SHIFT 0 #define IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_MASK (0x3FFFULL << \ @@ -97,7 +99,7 @@ struct iavf_ipsec_crypto_pkt_metadata { uint8_t next_proto; /* Next Protocol (8b/1B) */ uint32_t esn; /* Extended Sequence Number (32b/4B) */ -} __rte_packed; +}; /** * Inline IPsec Crypto offload is supported diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c index 6a093c6746..f7df5f21f2 100644 --- a/drivers/net/iavf/iavf_rxtx.c +++ b/drivers/net/iavf/iavf_rxtx.c @@ -53,7 +53,7 @@ static uint16_t geneve_udp_port = RTE_GENEVE_DEFAULT_PORT; struct simple_gre_hdr { uint16_t flags; uint16_t proto; -} __rte_packed; +}; /* structure that caches offload info for the current packet */ struct offload_info { diff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h index 5f7347023f..327e9a90e9 100644 --- a/drivers/net/ice/base/ice_osdep.h +++ b/drivers/net/ice/base/ice_osdep.h @@ -136,9 +136,6 @@ writeq(uint64_t value, volatile void *addr) #ifndef __maybe_unused #define __maybe_unused __rte_unused #endif -#ifndef __packed -#define __packed __rte_packed -#endif #ifndef BIT_ULL #define BIT_ULL(a) (1ULL << (a)) @@ -187,17 +184,19 @@ do { \ #define BITS_PER_BYTE 8 /* memory allocation tracking */ +__rte_packed_begin struct ice_dma_mem { void *va; u64 pa; u32 size; const void *zone; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct ice_virt_mem { void *va; u32 size; -} __rte_packed; +} __rte_packed_end; #define ice_malloc(h, s) rte_zmalloc(NULL, s, 0) #define ice_calloc(h, c, s) rte_calloc(NULL, c, s, 0) diff --git a/drivers/net/ionic/ionic_if.h b/drivers/net/ionic/ionic_if.h index e4ac79ac21..de15bde2f7 100644 --- a/drivers/net/ionic/ionic_if.h +++ b/drivers/net/ionic/ionic_if.h @@ -379,7 +379,7 @@ enum ionic_lif_state { * @queue_count: Queue counts per queue-type */ union ionic_lif_config { - struct { + __rte_packed_begin struct { u8 state; u8 rsvd[3]; char name[IONIC_IFNAMSIZ]; @@ -388,7 +388,7 @@ union ionic_lif_config { __le16 vlan; __le64 features; __le32 queue_count[IONIC_QTYPE_MAX]; - } __rte_packed; + } __rte_packed_end; __le32 words[64]; }; @@ -425,10 +425,10 @@ union ionic_lif_config { * @eq_qtype: RDMA Event Qtype */ union ionic_lif_identity { - struct { + __rte_packed_begin struct { __le64 capabilities; - struct { + __rte_packed_begin struct { u8 version; u8 rsvd[3]; __le32 max_ucast_filters; @@ -438,9 +438,9 @@ union ionic_lif_identity { __le32 max_mtu; u8 rsvd2[106]; union ionic_lif_config config; - } __rte_packed eth; + } __rte_packed_end eth; - struct { + __rte_packed_begin struct { u8 version; u8 qp_opcodes; u8 admin_opcodes; @@ -460,8 +460,8 @@ union ionic_lif_identity { struct ionic_lif_logical_qtype rq_qtype; struct ionic_lif_logical_qtype cq_qtype; struct ionic_lif_logical_qtype eq_qtype; - } __rte_packed rdma; - } __rte_packed; + } __rte_packed_end rdma; + } __rte_packed_end; __le32 words[478]; }; @@ -584,7 +584,7 @@ union ionic_q_identity { * @cq_ring_base: Completion queue ring base address * @sg_ring_base: Scatter/Gather ring base address */ -struct ionic_q_init_cmd { +__rte_packed_begin struct ionic_q_init_cmd { u8 opcode; u8 rsvd; __le16 lif_index; @@ -607,7 +607,7 @@ struct ionic_q_init_cmd { __le64 cq_ring_base; __le64 sg_ring_base; u8 rsvd2[20]; -} __rte_packed; +} __rte_packed_end; /** * struct ionic_q_init_comp - Queue init command completion @@ -1236,7 +1236,7 @@ union ionic_port_config { * @fec_type: fec type (enum ionic_port_fec_type) * @xcvr: transceiver status */ -struct ionic_port_status { +__rte_packed_begin struct ionic_port_status { __le32 id; __le32 speed; u8 status; @@ -1244,7 +1244,7 @@ struct ionic_port_status { u8 fec_type; u8 rsvd[48]; struct ionic_xcvr_status xcvr; -} __rte_packed; +} __rte_packed_end; /** * struct ionic_port_identify_cmd - Port identify command @@ -1414,7 +1414,7 @@ struct ionic_port_getattr_cmd { struct ionic_port_getattr_comp { u8 status; u8 rsvd[3]; - union { + __rte_packed_begin union { u8 state; __le32 speed; __le32 mtu; @@ -1423,7 +1423,7 @@ struct ionic_port_getattr_comp { u8 pause_type; u8 loopback_mode; u8 rsvd2[11]; - } __rte_packed; + } __rte_packed_end; u8 color; }; @@ -1489,12 +1489,12 @@ struct ionic_dev_setattr_cmd { u8 opcode; u8 attr; __le16 rsvd; - union { + __rte_packed_begin union { u8 state; char name[IONIC_IFNAMSIZ]; __le64 features; u8 rsvd2[60]; - } __rte_packed; + } __rte_packed_end; }; /** @@ -1506,10 +1506,10 @@ struct ionic_dev_setattr_cmd { struct ionic_dev_setattr_comp { u8 status; u8 rsvd[3]; - union { + __rte_packed_begin union { __le64 features; u8 rsvd2[11]; - } __rte_packed; + } __rte_packed_end; u8 color; }; @@ -1533,10 +1533,10 @@ struct ionic_dev_getattr_cmd { struct ionic_dev_getattr_comp { u8 status; u8 rsvd[3]; - union { + __rte_packed_begin union { __le64 features; u8 rsvd2[11]; - } __rte_packed; + } __rte_packed_end; u8 color; }; @@ -1594,7 +1594,7 @@ struct ionic_lif_setattr_cmd { u8 opcode; u8 attr; __le16 index; - union { + __rte_packed_begin union { u8 state; char name[IONIC_IFNAMSIZ]; __le32 mtu; @@ -1608,7 +1608,7 @@ struct ionic_lif_setattr_cmd { } rss; u8 stats_ctl; u8 rsvd[60]; - } __rte_packed; + } __rte_packed_end; }; /** @@ -1622,10 +1622,10 @@ struct ionic_lif_setattr_comp { u8 status; u8 rsvd; __le16 comp_index; - union { + __rte_packed_begin union { __le64 features; u8 rsvd2[11]; - } __rte_packed; + } __rte_packed_end; u8 color; }; @@ -1657,13 +1657,13 @@ struct ionic_lif_getattr_comp { u8 status; u8 rsvd; __le16 comp_index; - union { + __rte_packed_begin union { u8 state; __le32 mtu; u8 mac[6]; __le64 features; u8 rsvd2[11]; - } __rte_packed; + } __rte_packed_end; u8 color; }; @@ -1811,7 +1811,7 @@ struct ionic_vf_setattr_cmd { u8 opcode; u8 attr; __le16 vf_index; - union { + __rte_packed_begin union { u8 macaddr[6]; __le16 vlanid; __le32 maxrate; @@ -1820,7 +1820,7 @@ struct ionic_vf_setattr_cmd { u8 linkstate; __le64 stats_pa; u8 pad[60]; - } __rte_packed; + } __rte_packed_end; }; struct ionic_vf_setattr_comp { @@ -1849,7 +1849,7 @@ struct ionic_vf_getattr_comp { u8 status; u8 attr; __le16 vf_index; - union { + __rte_packed_begin union { u8 macaddr[6]; __le16 vlanid; __le32 maxrate; @@ -1858,7 +1858,7 @@ struct ionic_vf_getattr_comp { u8 linkstate; __le64 stats_pa; u8 pad[11]; - } __rte_packed; + } __rte_packed_end; u8 color; }; @@ -1953,7 +1953,7 @@ enum ionic_qos_sched_type { * @ip_dscp: IP dscp values */ union ionic_qos_config { - struct { + __rte_packed_begin struct { #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) /* Used to rewrite PCP or DSCP value. */ @@ -1988,7 +1988,7 @@ union ionic_qos_config { u8 ip_dscp[IONIC_QOS_DSCP_MAX]; }; }; - } __rte_packed; + } __rte_packed_end; __le32 words[64]; }; @@ -2785,14 +2785,14 @@ union ionic_dev_info_regs { * @data: Opcode-specific side-data */ union ionic_dev_cmd_regs { - struct { + __rte_packed_begin struct { u32 doorbell; u32 done; union ionic_dev_cmd cmd; union ionic_dev_cmd_comp comp; u8 rsvd[48]; u32 data[478]; - } __rte_packed; + } __rte_packed_end; u32 words[512]; }; @@ -2802,10 +2802,10 @@ union ionic_dev_cmd_regs { * @devcmd: Device command registers */ union ionic_dev_regs { - struct { + __rte_packed_begin struct { union ionic_dev_info_regs info; union ionic_dev_cmd_regs devcmd; - } __rte_packed; + } __rte_packed_end; __le32 words[1024]; }; diff --git a/drivers/net/memif/memif.h b/drivers/net/memif/memif.h index 3f5b407a48..c21c434e3e 100644 --- a/drivers/net/memif/memif.h +++ b/drivers/net/memif/memif.h @@ -59,7 +59,7 @@ typedef uint8_t memif_log2_ring_size_t; * S2C * Contains server interfaces configuration. */ -typedef struct __rte_packed { +typedef __rte_packed_begin struct { uint8_t name[MEMIF_NAME_SZ]; /**< Client app name. In this case DPDK version */ memif_version_t min_version; /**< lowest supported memif version */ memif_version_t max_version; /**< highest supported memif version */ @@ -67,36 +67,36 @@ typedef struct __rte_packed { memif_ring_index_t max_s2c_ring; /**< maximum num of S2C ring */ memif_ring_index_t max_c2s_ring; /**< maximum num of C2S rings */ memif_log2_ring_size_t max_log2_ring_size; /**< maximum ring size (as log2) */ -} memif_msg_hello_t; +} __rte_packed_end memif_msg_hello_t; /** * C2S * Contains information required to identify interface * to which the client wants to connect. */ -typedef struct __rte_packed { +typedef __rte_packed_begin struct { memif_version_t version; /**< memif version */ memif_interface_id_t id; /**< interface id */ memif_interface_mode_t mode:8; /**< interface mode */ uint8_t secret[24]; /**< optional security parameter */ uint8_t name[MEMIF_NAME_SZ]; /**< Client app name. In this case DPDK version */ -} memif_msg_init_t; +} __rte_packed_end memif_msg_init_t; /** * C2S * Request server to add new shared memory region to server interface. * Shared files file descriptor is passed in cmsghdr. */ -typedef struct __rte_packed { +typedef __rte_packed_begin struct { memif_region_index_t index; /**< shm regions index */ memif_region_size_t size; /**< shm region size */ -} memif_msg_add_region_t; +} __rte_packed_end memif_msg_add_region_t; /** * C2S * Request server to add new ring to server interface. */ -typedef struct __rte_packed { +typedef __rte_packed_begin struct { uint16_t flags; /**< flags */ #define MEMIF_MSG_ADD_RING_FLAG_C2S 1 /**< ring is in C2S direction */ memif_ring_index_t index; /**< ring index */ @@ -104,34 +104,34 @@ typedef struct __rte_packed { memif_region_offset_t offset; /**< buffer start offset */ memif_log2_ring_size_t log2_ring_size; /**< ring size (log2) */ uint16_t private_hdr_size; /**< used for private metadata */ -} memif_msg_add_ring_t; +} __rte_packed_end memif_msg_add_ring_t; /** * C2S * Finalize connection establishment. */ -typedef struct __rte_packed { +typedef __rte_packed_begin struct { uint8_t if_name[MEMIF_NAME_SZ]; /**< client interface name */ -} memif_msg_connect_t; +} __rte_packed_end memif_msg_connect_t; /** * S2C * Finalize connection establishment. */ -typedef struct __rte_packed { +typedef __rte_packed_begin struct { uint8_t if_name[MEMIF_NAME_SZ]; /**< server interface name */ -} memif_msg_connected_t; +} __rte_packed_end memif_msg_connected_t; /** * C2S & S2C * Disconnect interfaces. */ -typedef struct __rte_packed { +typedef __rte_packed_begin struct { uint32_t code; /**< error code */ uint8_t string[96]; /**< disconnect reason */ -} memif_msg_disconnect_t; +} __rte_packed_end memif_msg_disconnect_t; -typedef struct __rte_packed __rte_aligned(128) +typedef __rte_packed_begin struct __rte_aligned(128) { memif_msg_type_t type:16; union { @@ -143,7 +143,7 @@ typedef struct __rte_packed __rte_aligned(128) memif_msg_connected_t connected; memif_msg_disconnect_t disconnect; }; -} memif_msg_t; +} __rte_packed_end memif_msg_t; /* * Ring and Descriptor Layout @@ -152,14 +152,14 @@ typedef struct __rte_packed __rte_aligned(128) /** * Buffer descriptor. */ -typedef struct __rte_packed { +typedef __rte_packed_begin struct { uint16_t flags; /**< flags */ #define MEMIF_DESC_FLAG_NEXT 1 /**< is chained buffer */ memif_region_index_t region; /**< region index on which the buffer is located */ uint32_t length; /**< buffer length */ memif_region_offset_t offset; /**< buffer offset */ uint32_t metadata; -} memif_desc_t; +} __rte_packed_end memif_desc_t; #define MEMIF_CACHELINE_ALIGN_MARK(mark) \ alignas(RTE_CACHE_LINE_SIZE) RTE_MARKER mark; diff --git a/drivers/net/mlx4/mlx4_mr.h b/drivers/net/mlx4/mlx4_mr.h index af5251a960..626fcf39e3 100644 --- a/drivers/net/mlx4/mlx4_mr.h +++ b/drivers/net/mlx4/mlx4_mr.h @@ -41,29 +41,29 @@ struct mlx4_mr { }; /* Cache entry for Memory Region. */ -struct mlx4_mr_cache { +__rte_packed_begin struct mlx4_mr_cache { uintptr_t start; /* Start address of MR. */ uintptr_t end; /* End address of MR. */ uint32_t lkey; /* rte_cpu_to_be_32(ibv_mr->lkey). */ -} __rte_packed; +} __rte_packed_end; /* MR Cache table for Binary search. */ -struct mlx4_mr_btree { +__rte_packed_begin struct mlx4_mr_btree { uint16_t len; /* Number of entries. */ uint16_t size; /* Total number of entries. */ int overflow; /* Mark failure of table expansion. */ struct mlx4_mr_cache (*table)[]; -} __rte_packed; +} __rte_packed_end; /* Per-queue MR control descriptor. */ -struct mlx4_mr_ctrl { +__rte_packed_begin struct mlx4_mr_ctrl { uint32_t *dev_gen_ptr; /* Generation number of device to poll. */ uint32_t cur_gen; /* Generation number saved to flush caches. */ uint16_t mru; /* Index of last hit entry in top-half cache. */ uint16_t head; /* Index of the oldest entry in top-half cache. */ struct mlx4_mr_cache cache[MLX4_MR_CACHE_N]; /* Cache for top-half. */ struct mlx4_mr_btree cache_bh; /* Cache for bottom-half. */ -} __rte_packed; +} __rte_packed_end; extern struct mlx4_dev_list mlx4_mem_event_cb_list; extern rte_rwlock_t mlx4_mem_event_rwlock; diff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h index 3668ab9fcf..de1357e099 100644 --- a/drivers/net/mlx5/hws/mlx5dr.h +++ b/drivers/net/mlx5/hws/mlx5dr.h @@ -328,13 +328,14 @@ union mlx5dr_crc_encap_entropy_hash_ip_field { }; }; +__rte_packed_begin struct mlx5dr_crc_encap_entropy_hash_fields { union mlx5dr_crc_encap_entropy_hash_ip_field dst; union mlx5dr_crc_encap_entropy_hash_ip_field src; uint8_t next_protocol; rte_be16_t dst_port; rte_be16_t src_port; -} __rte_packed; +} __rte_packed_end; enum mlx5dr_crc_encap_entropy_hash_size { MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_8, diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 89d277b523..5fd356e00f 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -235,10 +235,11 @@ mlx5_is_probed_port_on_mpesw_device(struct mlx5_dev_spawn_data *spawn) } /** Data associated with socket messages. */ +__rte_packed_begin struct mlx5_flow_dump_req { uint32_t port_id; /**< There are plans in DPDK to extend port_id. */ uint64_t flow_id; -} __rte_packed; +} __rte_packed_end; struct mlx5_flow_dump_ack { int rc; /**< Return code. */ diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index bcc2782460..9aad71239e 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -673,6 +673,7 @@ struct mlx5_flow_dv_tag_resource { }; /* Modify resource structure */ +__rte_packed_begin struct mlx5_flow_dv_modify_hdr_resource { struct mlx5_list_entry entry; void *action; /**< Modify header action object. */ @@ -684,7 +685,7 @@ struct mlx5_flow_dv_modify_hdr_resource { bool root; /**< Whether action is in root table. */ struct mlx5_modification_cmd actions[]; /**< Modification actions. */ -} __rte_packed; +} __rte_packed_end; /* Modify resource key of the hash organization. */ union mlx5_flow_modify_hdr_key { @@ -831,6 +832,7 @@ struct mlx5_flow_dv_dest_array_resource { /** Device flow handle structure for DV mode only. */ +__rte_packed_begin struct mlx5_flow_handle_dv { /* Flow DV api: */ struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ @@ -846,9 +848,10 @@ struct mlx5_flow_handle_dv { /**< Index to sample action resource in cache. */ uint32_t rix_dest_array; /**< Index to destination array resource in cache. */ -} __rte_packed; +} __rte_packed_end; /** Device flow handle structure: used both for creating & destroying. */ +__rte_packed_begin struct mlx5_flow_handle { SILIST_ENTRY(uint32_t)next; struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ @@ -875,7 +878,7 @@ struct mlx5_flow_handle { struct mlx5_flow_handle_dv dvh; #endif uint8_t flex_item; /**< referenced Flex Item bitmask. */ -} __rte_packed; +} __rte_packed_end; /* * Size for Verbs device flow handle structure only. Do not use the DV only @@ -1250,6 +1253,7 @@ struct mlx5_flow_attr { }; /* Flow structure. */ +__rte_packed_begin struct rte_flow { uint32_t dev_handles; /**< Device flow handles that are part of the flow. */ @@ -1268,7 +1272,7 @@ struct rte_flow { uint32_t ct; /**< Holds ASO CT index. */ }; uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */ -} __rte_packed; +} __rte_packed_end; /* * HWS COUNTER ID's layout diff --git a/drivers/net/mlx5/mlx5_hws_cnt.h b/drivers/net/mlx5/mlx5_hws_cnt.h index d8da9dfcdd..28438d6319 100644 --- a/drivers/net/mlx5/mlx5_hws_cnt.h +++ b/drivers/net/mlx5/mlx5_hws_cnt.h @@ -133,6 +133,7 @@ enum { }; /* HWS counter age parameter. */ +__rte_packed_begin struct __rte_cache_aligned mlx5_hws_age_param { RTE_ATOMIC(uint32_t) timeout; /* Aging timeout in seconds (atomically accessed). */ RTE_ATOMIC(uint32_t) sec_since_last_hit; @@ -149,7 +150,7 @@ struct __rte_cache_aligned mlx5_hws_age_param { cnt_id_t own_cnt_index; /* Counter action created specifically for this AGE action. */ void *context; /* Flow AGE context. */ -} __rte_packed; +} __rte_packed_end; /** diff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h index f933daf03c..a1df3ed8f7 100644 --- a/drivers/net/mlx5/mlx5_utils.h +++ b/drivers/net/mlx5/mlx5_utils.h @@ -115,6 +115,7 @@ struct mlx5_l3t_level_tbl { }; /* L3 word entry table data structure. */ +__rte_packed_begin struct mlx5_l3t_entry_word { uint32_t idx; /* Table index. */ uint64_t ref_cnt; /* Table ref_cnt. */ @@ -122,9 +123,10 @@ struct mlx5_l3t_entry_word { uint16_t data; uint32_t ref_cnt; } entry[MLX5_L3T_ET_SIZE]; /* Entry array */ -} __rte_packed; +} __rte_packed_end; /* L3 double word entry table data structure. */ +__rte_packed_begin struct mlx5_l3t_entry_dword { uint32_t idx; /* Table index. */ uint64_t ref_cnt; /* Table ref_cnt. */ @@ -132,9 +134,10 @@ struct mlx5_l3t_entry_dword { uint32_t data; int32_t ref_cnt; } entry[MLX5_L3T_ET_SIZE]; /* Entry array */ -} __rte_packed; +} __rte_packed_end; /* L3 quad word entry table data structure. */ +__rte_packed_begin struct mlx5_l3t_entry_qword { uint32_t idx; /* Table index. */ uint64_t ref_cnt; /* Table ref_cnt. */ @@ -142,9 +145,10 @@ struct mlx5_l3t_entry_qword { uint64_t data; uint32_t ref_cnt; } entry[MLX5_L3T_ET_SIZE]; /* Entry array */ -} __rte_packed; +} __rte_packed_end; /* L3 pointer entry table data structure. */ +__rte_packed_begin struct mlx5_l3t_entry_ptr { uint32_t idx; /* Table index. */ uint64_t ref_cnt; /* Table ref_cnt. */ @@ -152,7 +156,7 @@ struct mlx5_l3t_entry_ptr { void *data; uint32_t ref_cnt; } entry[MLX5_L3T_ET_SIZE]; /* Entry array */ -} __rte_packed; +} __rte_packed_end; /* L3 table data structure. */ struct mlx5_l3t_tbl { diff --git a/drivers/net/netvsc/hn_nvs.h b/drivers/net/netvsc/hn_nvs.h index 3766d2ee34..1a76f8d93f 100644 --- a/drivers/net/netvsc/hn_nvs.h +++ b/drivers/net/netvsc/hn_nvs.h @@ -67,125 +67,125 @@ /* NVS message common header */ -struct hn_nvs_hdr { +__rte_packed_begin struct hn_nvs_hdr { uint32_t type; -} __rte_packed; +} __rte_packed_end; -struct hn_nvs_init { +__rte_packed_begin struct hn_nvs_init { uint32_t type; /* NVS_TYPE_INIT */ uint32_t ver_min; uint32_t ver_max; uint8_t rsvd[28]; -} __rte_packed; +} __rte_packed_end; -struct hn_nvs_init_resp { +__rte_packed_begin struct hn_nvs_init_resp { uint32_t type; /* NVS_TYPE_INIT_RESP */ uint32_t ver; /* deprecated */ uint32_t rsvd; uint32_t status; /* NVS_STATUS_ */ -} __rte_packed; +} __rte_packed_end; /* No response */ -struct hn_nvs_ndis_conf { +__rte_packed_begin struct hn_nvs_ndis_conf { uint32_t type; /* NVS_TYPE_NDIS_CONF */ uint32_t mtu; uint32_t rsvd; uint64_t caps; /* NVS_NDIS_CONF_ */ uint8_t rsvd1[20]; -} __rte_packed; +} __rte_packed_end; #define NVS_NDIS_CONF_SRIOV 0x0004 #define NVS_NDIS_CONF_VLAN 0x0008 /* No response */ -struct hn_nvs_ndis_init { +__rte_packed_begin struct hn_nvs_ndis_init { uint32_t type; /* NVS_TYPE_NDIS_INIT */ uint32_t ndis_major; /* NDIS_VERSION_MAJOR_ */ uint32_t ndis_minor; /* NDIS_VERSION_MINOR_ */ uint8_t rsvd[28]; -} __rte_packed; +} __rte_packed_end; -struct hn_nvs_vf_association { +__rte_packed_begin struct hn_nvs_vf_association { uint32_t type; /* NVS_TYPE_VFASSOC_NOTE */ uint32_t allocated; uint32_t serial; -} __rte_packed; +} __rte_packed_end; #define NVS_DATAPATH_SYNTHETIC 0 #define NVS_DATAPATH_VF 1 /* No response */ -struct hn_nvs_datapath { +__rte_packed_begin struct hn_nvs_datapath { uint32_t type; /* NVS_TYPE_SET_DATAPATH */ uint32_t active_path;/* NVS_DATAPATH_* */ uint8_t rsvd[32]; -} __rte_packed; +} __rte_packed_end; -struct hn_nvs_rxbuf_conn { +__rte_packed_begin struct hn_nvs_rxbuf_conn { uint32_t type; /* NVS_TYPE_RXBUF_CONN */ uint32_t gpadl; /* RXBUF vmbus GPADL */ uint16_t sig; /* NVS_RXBUF_SIG */ uint8_t rsvd[30]; -} __rte_packed; +} __rte_packed_end; -struct hn_nvs_rxbuf_sect { +__rte_packed_begin struct hn_nvs_rxbuf_sect { uint32_t start; uint32_t slotsz; uint32_t slotcnt; uint32_t end; -} __rte_packed; +} __rte_packed_end; -struct hn_nvs_rxbuf_connresp { +__rte_packed_begin struct hn_nvs_rxbuf_connresp { uint32_t type; /* NVS_TYPE_RXBUF_CONNRESP */ uint32_t status; /* NVS_STATUS_ */ uint32_t nsect; /* # of elem in nvs_sect */ struct hn_nvs_rxbuf_sect nvs_sect[1]; -} __rte_packed; +} __rte_packed_end; /* No response */ -struct hn_nvs_rxbuf_disconn { +__rte_packed_begin struct hn_nvs_rxbuf_disconn { uint32_t type; /* NVS_TYPE_RXBUF_DISCONN */ uint16_t sig; /* NVS_RXBUF_SIG */ uint8_t rsvd[34]; -} __rte_packed; +} __rte_packed_end; -struct hn_nvs_chim_conn { +__rte_packed_begin struct hn_nvs_chim_conn { uint32_t type; /* NVS_TYPE_CHIM_CONN */ uint32_t gpadl; /* chimney buf vmbus GPADL */ uint16_t sig; /* NDIS_NVS_CHIM_SIG */ uint8_t rsvd[30]; -} __rte_packed; +} __rte_packed_end; -struct hn_nvs_chim_connresp { +__rte_packed_begin struct hn_nvs_chim_connresp { uint32_t type; /* NVS_TYPE_CHIM_CONNRESP */ uint32_t status; /* NVS_STATUS_ */ uint32_t sectsz; /* section size */ -} __rte_packed; +} __rte_packed_end; /* No response */ -struct hn_nvs_chim_disconn { +__rte_packed_begin struct hn_nvs_chim_disconn { uint32_t type; /* NVS_TYPE_CHIM_DISCONN */ uint16_t sig; /* NVS_CHIM_SIG */ uint8_t rsvd[34]; -} __rte_packed; +} __rte_packed_end; #define NVS_SUBCH_OP_ALLOC 1 -struct hn_nvs_subch_req { +__rte_packed_begin struct hn_nvs_subch_req { uint32_t type; /* NVS_TYPE_SUBCH_REQ */ uint32_t op; /* NVS_SUBCH_OP_ */ uint32_t nsubch; uint8_t rsvd[28]; -} __rte_packed; +} __rte_packed_end; -struct hn_nvs_subch_resp { +__rte_packed_begin struct hn_nvs_subch_resp { uint32_t type; /* NVS_TYPE_SUBCH_RESP */ uint32_t status; /* NVS_STATUS_ */ uint32_t nsubch; uint8_t rsvd[28]; -} __rte_packed; +} __rte_packed_end; -struct hn_nvs_rndis { +__rte_packed_begin struct hn_nvs_rndis { uint32_t type; /* NVS_TYPE_RNDIS */ uint32_t rndis_mtype;/* NVS_RNDIS_MTYPE_ */ /* @@ -199,13 +199,13 @@ struct hn_nvs_rndis { uint32_t chim_idx; uint32_t chim_sz; uint8_t rsvd[24]; -} __rte_packed; +} __rte_packed_end; -struct hn_nvs_rndis_ack { +__rte_packed_begin struct hn_nvs_rndis_ack { uint32_t type; /* NVS_TYPE_RNDIS_ACK */ uint32_t status; /* NVS_STATUS_ */ uint8_t rsvd[32]; -} __rte_packed; +} __rte_packed_end; int hn_nvs_attach(struct hn_data *hv, unsigned int mtu); diff --git a/drivers/net/netvsc/ndis.h b/drivers/net/netvsc/ndis.h index d97a397a86..cf323b8266 100644 --- a/drivers/net/netvsc/ndis.h +++ b/drivers/net/netvsc/ndis.h @@ -42,11 +42,11 @@ #define NDIS_OBJTYPE_RSS_PARAMS 0x89 #define NDIS_OBJTYPE_OFFLOAD 0xa7 -struct ndis_object_hdr { +__rte_packed_begin struct ndis_object_hdr { uint8_t ndis_type; /* NDIS_OBJTYPE_ */ uint8_t ndis_rev; /* type specific */ uint16_t ndis_size; /* incl. this hdr */ -} __rte_packed; +} __rte_packed_end; /* * OID_TCP_OFFLOAD_PARAMETERS @@ -117,7 +117,7 @@ struct ndis_offload_params { * OID_GEN_RECEIVE_SCALE_CAPABILITIES * ndis_type: NDIS_OBJTYPE_RSS_CAPS */ -struct ndis_rss_caps { +__rte_packed_begin struct ndis_rss_caps { struct ndis_object_hdr ndis_hdr; uint32_t ndis_caps; /* NDIS_RSS_CAP_ */ uint32_t ndis_nmsi; /* # of MSIs */ @@ -125,7 +125,7 @@ struct ndis_rss_caps { /* NDIS >= 6.30 */ uint16_t ndis_nind; /* # of indtbl ent. */ uint16_t ndis_pad; -} __rte_packed; +} __rte_packed_end; #define NDIS_RSS_CAPS_SIZE \ offsetof(struct ndis_rss_caps, ndis_pad) diff --git a/drivers/net/nfp/flower/nfp_flower_cmsg.h b/drivers/net/nfp/flower/nfp_flower_cmsg.h index a7866e8382..3d73c0de0c 100644 --- a/drivers/net/nfp/flower/nfp_flower_cmsg.h +++ b/drivers/net/nfp/flower/nfp_flower_cmsg.h @@ -943,7 +943,7 @@ struct nfp_fl_act_pre_tun { * | var_flags | var_np | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -struct nfp_fl_act_set_tun { +__rte_packed_begin struct nfp_fl_act_set_tun { struct nfp_fl_act_head head; rte_be16_t reserved; rte_be64_t tun_id; @@ -956,7 +956,7 @@ struct nfp_fl_act_set_tun { uint8_t tun_len; /**< Only valid for NFP_FL_TUNNEL_GENEVE */ uint8_t reserved2; rte_be16_t tun_proto; /**< Only valid for NFP_FL_TUNNEL_GENEVE */ -} __rte_packed; +} __rte_packed_end; /* * Meter diff --git a/drivers/net/nfp/flower/nfp_flower_flow.h b/drivers/net/nfp/flower/nfp_flower_flow.h index f54ad6cf55..a5cb440bd5 100644 --- a/drivers/net/nfp/flower/nfp_flower_flow.h +++ b/drivers/net/nfp/flower/nfp_flower_flow.h @@ -53,8 +53,8 @@ struct nfp_fl_rule_metadata { uint8_t act_len; uint8_t flags; rte_be32_t host_ctx_id; - rte_be64_t host_cookie __rte_packed; - rte_be64_t flow_version __rte_packed; + rte_be64_t host_cookie; + rte_be64_t flow_version; rte_be32_t shortcut; }; diff --git a/drivers/net/nfp/nfd3/nfp_nfd3.h b/drivers/net/nfp/nfd3/nfp_nfd3.h index 3ba562cc3f..f0104d3f03 100644 --- a/drivers/net/nfp/nfd3/nfp_nfd3.h +++ b/drivers/net/nfp/nfd3/nfp_nfd3.h @@ -16,7 +16,7 @@ struct nfp_net_nfd3_tx_desc { union { - struct { + __rte_packed_begin struct { uint8_t dma_addr_hi; /**< High bits of host buf address */ uint16_t dma_len; /**< Length to DMA for this desc */ /** Offset in buf where pkt starts + highest bit is eop flag */ @@ -35,7 +35,7 @@ struct nfp_net_nfd3_tx_desc { uint16_t vlan; /**< VLAN tag to add if indicated */ }; uint16_t data_len; /**< Length of frame + meta data */ - } __rte_packed; + } __rte_packed_end; uint32_t vals[4]; }; }; diff --git a/drivers/net/nfp/nfp_rxtx.h b/drivers/net/nfp/nfp_rxtx.h index c717d97003..b595eeae52 100644 --- a/drivers/net/nfp/nfp_rxtx.h +++ b/drivers/net/nfp/nfp_rxtx.h @@ -117,22 +117,22 @@ struct __rte_aligned(64) nfp_net_txq { struct nfp_net_rx_desc { union { /** Freelist descriptor. */ - struct { + __rte_packed_begin struct { uint16_t dma_addr_hi; /**< High bits of buffer address. */ uint8_t spare; /**< Reserved, must be zero. */ uint8_t dd; /**< Whether descriptor available. */ uint32_t dma_addr_lo; /**< Low bits of buffer address. */ - } __rte_packed fld; + } __rte_packed_end fld; /** RX descriptor. */ - struct { + __rte_packed_begin struct { uint16_t data_len; /**< Length of frame + metadata. */ uint8_t reserved; /**< Reserved, must be zero. */ uint8_t meta_len_dd; /**< Length of metadata + done flag. */ uint16_t flags; /**< RX flags. */ uint16_t offload_info; /**< Offloading info. */ - } __rte_packed rxd; + } __rte_packed_end rxd; /** Reserved. */ uint32_t vals[2]; diff --git a/drivers/net/nfp/nfpcore/nfp_nsp.c b/drivers/net/nfp/nfpcore/nfp_nsp.c index 9837b3354b..94617f766d 100644 --- a/drivers/net/nfp/nfpcore/nfp_nsp.c +++ b/drivers/net/nfp/nfpcore/nfp_nsp.c @@ -837,14 +837,14 @@ nfp_nsp_read_module_eeprom(struct nfp_nsp *state, { int ret; int bufsz; - struct eeprom_buf { + __rte_packed_begin struct eeprom_buf { uint8_t metalen; rte_le16_t length; rte_le16_t offset; rte_le16_t readlen; uint8_t eth_index; uint8_t data[]; - } __rte_packed * buf; + } __rte_packed_end * buf; /* Buffer must be large enough and rounded to the next block size. */ bufsz = sizeof(*(buf)) + sizeof((buf)->data[0]) * diff --git a/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c index e46a3bef28..1b22ceaf79 100644 --- a/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c +++ b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c @@ -68,24 +68,24 @@ } \ } while (0) -struct __rte_packed virtq_avail { +__rte_packed_begin struct virtq_avail { uint16_t flags; uint16_t idx; uint16_t ring[]; /* Queue Size */ -}; +} __rte_packed_end; -struct __rte_packed virtq_used_elem { +__rte_packed_begin struct virtq_used_elem { /* Index of start of used descriptor chain. */ uint32_t id; /* Total length of the descriptor chain which was used (written to) */ uint32_t len; -}; +} __rte_packed_end; -struct __rte_packed virtq_used { +__rte_packed_begin struct virtq_used { uint16_t flags; uint16_t idx; struct virtq_used_elem ring[]; /* Queue Size */ -}; +} __rte_packed_end; struct virtq_struct_layout_s { size_t used_offset; diff --git a/drivers/net/octeon_ep/otx_ep_mbox.h b/drivers/net/octeon_ep/otx_ep_mbox.h index ec96e4edc5..a5aa940707 100644 --- a/drivers/net/octeon_ep/otx_ep_mbox.h +++ b/drivers/net/octeon_ep/otx_ep_mbox.h @@ -76,6 +76,7 @@ enum otx_ep_link_autoneg { #define OTX_EP_MBOX_MORE_FRAG_FLAG 1 #define OTX_EP_MBOX_WRITE_WAIT_TIME msecs_to_jiffies(1) +__rte_packed_begin union otx_ep_mbox_word { uint64_t u64; struct { @@ -127,7 +128,7 @@ union otx_ep_mbox_word { uint64_t status:1; uint64_t rsvd:53; } s_link_status; -} __rte_packed; +} __rte_packed_end; /* Hardware interface link state information. */ struct otx_ep_iface_link_info { diff --git a/drivers/net/octeontx/base/octeontx_pki_var.h b/drivers/net/octeontx/base/octeontx_pki_var.h index 4445369ce7..7e84b92bb2 100644 --- a/drivers/net/octeontx/base/octeontx_pki_var.h +++ b/drivers/net/octeontx/base/octeontx_pki_var.h @@ -21,7 +21,7 @@ #define OCTTX_PACKET_LATER_SKIP 128 /* WQE descriptor */ -typedef union octtx_wqe_s { +typedef __rte_packed_begin union octtx_wqe_s { uint64_t w[6]; struct { @@ -160,7 +160,7 @@ typedef union octtx_wqe_s { #endif } s; -} __rte_packed octtx_wqe_t; +} __rte_packed_end octtx_wqe_t; enum occtx_pki_ltype_e { OCCTX_PKI_LTYPE_NONE = 0, diff --git a/drivers/net/pfe/pfe_hif.h b/drivers/net/pfe/pfe_hif.h index e8d5ba10e1..aab2228955 100644 --- a/drivers/net/pfe/pfe_hif.h +++ b/drivers/net/pfe/pfe_hif.h @@ -83,9 +83,9 @@ struct __hif_hdr { }; }; -struct hif_ipsec_hdr { +__rte_packed_begin struct hif_ipsec_hdr { u16 sa_handle[2]; -} __packed; +} __rte_packed_end; struct pfe_parse { unsigned int packet_type; diff --git a/drivers/net/virtio/virtio.h b/drivers/net/virtio/virtio.h index 04a897bf51..2e8a243984 100644 --- a/drivers/net/virtio/virtio.h +++ b/drivers/net/virtio/virtio.h @@ -157,7 +157,7 @@ * config space; it is just a shadow structure. * */ -struct virtio_net_config { +__rte_packed_begin struct virtio_net_config { /* The config defining mac address (if VIRTIO_NET_F_MAC) */ uint8_t mac[RTE_ETHER_ADDR_LEN]; /* See VIRTIO_NET_F_STATUS and VIRTIO_NET_S_* above */ @@ -178,7 +178,7 @@ struct virtio_net_config { uint8_t rss_max_key_size; uint16_t rss_max_indirection_table_length; uint32_t supported_hash_types; -} __rte_packed; +} __rte_packed_end; struct virtio_hw { struct virtqueue **vqs; diff --git a/drivers/net/virtio/virtio_cvq.h b/drivers/net/virtio/virtio_cvq.h index 70739ae04b..7e35f079ab 100644 --- a/drivers/net/virtio/virtio_cvq.h +++ b/drivers/net/virtio/virtio_cvq.h @@ -43,10 +43,10 @@ struct virtqueue; * 6 bytes MAC address. This functionality is present if the * VIRTIO_NET_F_CTRL_MAC_ADDR feature is available. */ -struct virtio_net_ctrl_mac { +__rte_packed_begin struct virtio_net_ctrl_mac { uint32_t entries; uint8_t macs[][RTE_ETHER_ADDR_LEN]; -} __rte_packed; +} __rte_packed_end; #define VIRTIO_NET_CTRL_MAC 1 #define VIRTIO_NET_CTRL_MAC_TABLE_SET 0 @@ -98,10 +98,10 @@ struct virtio_net_ctrl_rss { #define VIRTIO_NET_CTRL_ANNOUNCE 3 #define VIRTIO_NET_CTRL_ANNOUNCE_ACK 0 -struct virtio_net_ctrl_hdr { +__rte_packed_begin struct virtio_net_ctrl_hdr { uint8_t class; uint8_t cmd; -} __rte_packed; +} __rte_packed_end; typedef uint8_t virtio_net_ctrl_ack; diff --git a/drivers/net/virtio/virtio_user/vhost_user.c b/drivers/net/virtio/virtio_user/vhost_user.c index c10252506b..69cdf14bae 100644 --- a/drivers/net/virtio/virtio_user/vhost_user.c +++ b/drivers/net/virtio/virtio_user/vhost_user.c @@ -81,7 +81,7 @@ enum vhost_user_request { VHOST_USER_GET_STATUS = 40, }; -struct vhost_user_msg { +__rte_packed_begin struct vhost_user_msg { enum vhost_user_request request; #define VHOST_USER_VERSION_MASK 0x3 @@ -97,7 +97,7 @@ struct vhost_user_msg { struct vhost_vring_addr addr; struct vhost_memory memory; } payload; -} __rte_packed; +} __rte_packed_end; #define VHOST_USER_HDR_SIZE offsetof(struct vhost_user_msg, payload.u64) #define VHOST_USER_PAYLOAD_SIZE \ diff --git a/drivers/net/zxdh/zxdh_common.c b/drivers/net/zxdh/zxdh_common.c index 4f18c97ed7..2e8796785b 100644 --- a/drivers/net/zxdh/zxdh_common.c +++ b/drivers/net/zxdh/zxdh_common.c @@ -27,22 +27,22 @@ #define ZXDH_REPS_HEADER_OFFSET 4 #define ZXDH_TBL_MSG_PRO_SUCCESS 0xaa -struct zxdh_common_msg { +__rte_packed_begin struct zxdh_common_msg { uint8_t type; /* 0:read table 1:write table */ uint8_t field; uint16_t pcie_id; uint16_t slen; /* Data length for write table */ uint16_t reserved; -} __rte_packed; +} __rte_packed_end; -struct zxdh_common_rsp_hdr { +__rte_packed_begin struct zxdh_common_rsp_hdr { uint8_t rsp_status; uint16_t rsp_len; uint8_t reserved; uint8_t payload_status; uint8_t rsv; uint16_t payload_len; -} __rte_packed; +} __rte_packed_end; struct zxdh_tbl_msg_header { uint8_t type; diff --git a/drivers/net/zxdh/zxdh_msg.h b/drivers/net/zxdh/zxdh_msg.h index 530ee406b1..fe30dbe649 100644 --- a/drivers/net/zxdh/zxdh_msg.h +++ b/drivers/net/zxdh/zxdh_msg.h @@ -160,29 +160,29 @@ struct zxdh_pci_bar_msg { uint16_t usr; }; -struct zxdh_bar_msix_reps { +__rte_packed_begin struct zxdh_bar_msix_reps { uint16_t pcie_id; uint16_t check; uint16_t vport; uint16_t rsv; -} __rte_packed; +} __rte_packed_end; -struct zxdh_bar_offset_reps { +__rte_packed_begin struct zxdh_bar_offset_reps { uint16_t check; uint16_t rsv; uint32_t offset; uint32_t length; -} __rte_packed; +} __rte_packed_end; -struct zxdh_bar_recv_msg { +__rte_packed_begin struct zxdh_bar_recv_msg { uint8_t reps_ok; uint16_t reps_len; uint8_t rsv; - union { + __rte_packed_begin union { struct zxdh_bar_msix_reps msix_reps; struct zxdh_bar_offset_reps offset_reps; - } __rte_packed; -} __rte_packed; + } __rte_packed_end; +} __rte_packed_end; struct zxdh_msg_recviver_mem { void *recv_buffer; /* first 4B is head, followed by payload */ diff --git a/drivers/net/zxdh/zxdh_pci.h b/drivers/net/zxdh/zxdh_pci.h index ed6fd89742..b8aa451cc7 100644 --- a/drivers/net/zxdh/zxdh_pci.h +++ b/drivers/net/zxdh/zxdh_pci.h @@ -64,7 +64,7 @@ enum zxdh_msix_status { #define ZXDH_CONFIG_STATUS_FAILED 0x80 #define ZXDH_PCI_QUEUE_ADDR_SHIFT 12 -struct zxdh_net_config { +__rte_packed_begin struct zxdh_net_config { /* The config defining mac address (if ZXDH_NET_F_MAC) */ uint8_t mac[RTE_ETHER_ADDR_LEN]; /* See ZXDH_NET_F_STATUS and ZXDH_NET_S_* above */ @@ -73,7 +73,7 @@ struct zxdh_net_config { uint16_t mtu; uint32_t speed; uint8_t duplex; -} __rte_packed; +} __rte_packed_end; /* This is the PCI capability header: */ struct zxdh_pci_cap { diff --git a/drivers/net/zxdh/zxdh_queue.h b/drivers/net/zxdh/zxdh_queue.h index 1088bf08fc..095c8f938d 100644 --- a/drivers/net/zxdh/zxdh_queue.h +++ b/drivers/net/zxdh/zxdh_queue.h @@ -35,12 +35,12 @@ enum { ZXDH_VTNET_RQ = 0, ZXDH_VTNET_TQ = 1 }; * ring descriptors: 16 bytes. * These can chain together via "next". */ -struct zxdh_vring_desc { +__rte_packed_begin struct zxdh_vring_desc { uint64_t addr; /* Address (guest-physical). */ uint32_t len; /* Length. */ uint16_t flags; /* The flags as indicated above. */ uint16_t next; /* We chain unused descriptors via this. */ -} __rte_packed; +} __rte_packed_end; struct zxdh_vring_used_elem { /* Index of start of used descriptor chain. */ @@ -49,46 +49,46 @@ struct zxdh_vring_used_elem { uint32_t len; }; -struct zxdh_vring_used { +__rte_packed_begin struct zxdh_vring_used { uint16_t flags; uint16_t idx; struct zxdh_vring_used_elem ring[]; -} __rte_packed; +} __rte_packed_end; -struct zxdh_vring_avail { +__rte_packed_begin struct zxdh_vring_avail { uint16_t flags; uint16_t idx; uint16_t ring[]; -} __rte_packed; +} __rte_packed_end; -struct zxdh_vring_packed_desc { +__rte_packed_begin struct zxdh_vring_packed_desc { uint64_t addr; uint32_t len; uint16_t id; uint16_t flags; -} __rte_packed; +} __rte_packed_end; -struct zxdh_vring_packed_desc_event { +__rte_packed_begin struct zxdh_vring_packed_desc_event { uint16_t desc_event_off_wrap; uint16_t desc_event_flags; -} __rte_packed; +} __rte_packed_end; -struct zxdh_vring_packed { +__rte_packed_begin struct zxdh_vring_packed { uint32_t num; struct zxdh_vring_packed_desc *desc; struct zxdh_vring_packed_desc_event *driver; struct zxdh_vring_packed_desc_event *device; -} __rte_packed; +} __rte_packed_end; -struct zxdh_vq_desc_extra { +__rte_packed_begin struct zxdh_vq_desc_extra { void *cookie; uint16_t ndescs; uint16_t next; -} __rte_packed; +} __rte_packed_end; -struct zxdh_virtqueue { +__rte_packed_begin struct zxdh_virtqueue { struct zxdh_hw *hw; /* < zxdh_hw structure pointer. */ - struct { + __rte_packed_begin struct { /* vring keeping descs and events */ struct zxdh_vring_packed ring; uint8_t used_wrap_counter; @@ -96,7 +96,7 @@ struct zxdh_virtqueue { uint16_t cached_flags; /* < cached flags for descs */ uint16_t event_flags_shadow; uint16_t rsv1; - } __rte_packed vq_packed; + } __rte_packed_end vq_packed; uint16_t vq_used_cons_idx; /* < last consumed descriptor */ uint16_t vq_nentries; /* < vring desc numbers */ uint16_t vq_free_cnt; /* < num of desc available */ @@ -129,16 +129,16 @@ struct zxdh_virtqueue { uint16_t *notify_addr; struct rte_mbuf **sw_ring; /* < RX software ring. */ struct zxdh_vq_desc_extra vq_descx[]; -} __rte_packed; +} __rte_packed_end; -struct zxdh_type_hdr { +__rte_packed_begin struct zxdh_type_hdr { uint8_t port; /* bit[0:1] 00-np 01-DRS 10-DTP */ uint8_t pd_len; uint8_t num_buffers; uint8_t reserved; -} __rte_packed; /* 4B */ +} __rte_packed_end; /* 4B */ -struct zxdh_pi_hdr { +__rte_packed_begin struct zxdh_pi_hdr { uint8_t pi_len; uint8_t pkt_type; uint16_t vlan_id; @@ -162,24 +162,24 @@ struct zxdh_pi_hdr { uint8_t reserved[2]; } ul; }; -} __rte_packed; /* 32B */ +} __rte_packed_end; /* 32B */ -struct zxdh_pd_hdr_dl { +__rte_packed_begin struct zxdh_pd_hdr_dl { uint32_t ol_flag; uint8_t tag_idx; uint8_t tag_data; uint16_t dst_vfid; uint32_t svlan_insert; uint32_t cvlan_insert; -} __rte_packed; /* 16B */ +} __rte_packed_end; /* 16B */ -struct zxdh_net_hdr_dl { +__rte_packed_begin struct zxdh_net_hdr_dl { struct zxdh_type_hdr type_hdr; /* 4B */ struct zxdh_pi_hdr pi_hdr; /* 32B */ struct zxdh_pd_hdr_dl pd_hdr; /* 16B */ -} __rte_packed; +} __rte_packed_end; -struct zxdh_pd_hdr_ul { +__rte_packed_begin struct zxdh_pd_hdr_ul { uint32_t pkt_flag; uint32_t rss_hash; uint32_t fd; @@ -189,20 +189,20 @@ struct zxdh_pd_hdr_ul { uint16_t src_vfid; uint16_t pkt_type_out; uint16_t pkt_type_in; -} __rte_packed; /* 24B */ +} __rte_packed_end; /* 24B */ -struct zxdh_net_hdr_ul { +__rte_packed_begin struct zxdh_net_hdr_ul { struct zxdh_type_hdr type_hdr; /* 4B */ struct zxdh_pi_hdr pi_hdr; /* 32B */ struct zxdh_pd_hdr_ul pd_hdr; /* 24B */ -} __rte_packed; /* 60B */ +} __rte_packed_end; /* 60B */ struct zxdh_tx_region { struct zxdh_net_hdr_dl tx_hdr; - union { + __rte_packed_begin union { struct zxdh_vring_desc tx_indir[ZXDH_MAX_TX_INDIRECT]; struct zxdh_vring_packed_desc tx_packed_indir[ZXDH_MAX_TX_INDIRECT]; - } __rte_packed; + } __rte_packed_end; }; static inline size_t diff --git a/drivers/net/zxdh/zxdh_rxtx.h b/drivers/net/zxdh/zxdh_rxtx.h index de9353b223..b6f795d84f 100644 --- a/drivers/net/zxdh/zxdh_rxtx.h +++ b/drivers/net/zxdh/zxdh_rxtx.h @@ -20,7 +20,7 @@ struct zxdh_virtnet_stats { uint64_t size_bins[8]; }; -struct zxdh_virtnet_rx { +__rte_packed_begin struct zxdh_virtnet_rx { struct zxdh_virtqueue *vq; /* dummy mbuf, for wraparound when processing RX ring. */ @@ -32,9 +32,9 @@ struct zxdh_virtnet_rx { uint16_t port_id; /* Device port identifier. */ struct zxdh_virtnet_stats stats; const struct rte_memzone *mz; /* mem zone to populate RX ring. */ -} __rte_packed; +} __rte_packed_end; -struct zxdh_virtnet_tx { +__rte_packed_begin struct zxdh_virtnet_tx { struct zxdh_virtqueue *vq; const struct rte_memzone *zxdh_net_hdr_mz; /* memzone to populate hdr. */ rte_iova_t zxdh_net_hdr_mem; /* hdr for each xmit packet */ @@ -42,6 +42,6 @@ struct zxdh_virtnet_tx { uint16_t port_id; /* Device port identifier. */ struct zxdh_virtnet_stats stats; const struct rte_memzone *mz; /* mem zone to populate TX ring. */ -} __rte_packed; +} __rte_packed_end; #endif /* ZXDH_RXTX_H */ From patchwork Wed Nov 27 00:52:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148883 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EF5AA45D31; Wed, 27 Nov 2024 01:54:46 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C7BF342DA6; Wed, 27 Nov 2024 01:53:25 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 57CF5402E0 for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 3FDA92057220; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 3FDA92057220 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=Nb7LVScUlg8etU769Fjg7eQZPfceqjyrqLkPjWDaUnY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BTOewsRGHeU1sCg+6Y/9+zDXSsul4+9MH1+HP/svS6WzVvSHuib+BzbAF4M/Fq8Ig P5WW9gy97/Klli58lQYrPoxuEhZhdShARSVNn4k/stVjlrCZ6uJZTO/FjXr1BLMjwx iMG0aUQVkolRny8EO9lC3Hy2AolyNpnFt5BslxkU= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 15/30] drivers/raw: replace packed attributes Date: Tue, 26 Nov 2024 16:52:26 -0800 Message-Id: <1732668761-5556-16-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retzlaff --- drivers/raw/ifpga/afu_pmd_n3000.h | 8 ++++---- drivers/raw/ifpga/base/opae_hw_api.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/raw/ifpga/afu_pmd_n3000.h b/drivers/raw/ifpga/afu_pmd_n3000.h index f6b6e07c6b..a74025cb3c 100644 --- a/drivers/raw/ifpga/afu_pmd_n3000.h +++ b/drivers/raw/ifpga/afu_pmd_n3000.h @@ -211,7 +211,7 @@ typedef union { }; } msgdma_desc_ctrl; -typedef struct __rte_packed { +typedef __rte_packed_begin struct { uint32_t rd_address; uint32_t wr_address; uint32_t len; @@ -223,7 +223,7 @@ typedef struct __rte_packed { uint32_t rd_address_ext; uint32_t wr_address_ext; msgdma_desc_ctrl control; -} msgdma_ext_desc; +} __rte_packed_end msgdma_ext_desc; typedef union { uint32_t csr; @@ -279,13 +279,13 @@ typedef union { }; } msgdma_seq_num; -typedef struct __rte_packed { +typedef __rte_packed_begin struct { msgdma_status status; msgdma_ctrl ctrl; msgdma_fill_level fill_level; msgdma_rsp_level rsp; msgdma_seq_num seq_num; -} msgdma_csr; +} __rte_packed_end msgdma_csr; #define CSR_STATUS(csr) (&(((msgdma_csr *)(csr))->status)) #define CSR_CONTROL(csr) (&(((msgdma_csr *)(csr))->ctrl)) diff --git a/drivers/raw/ifpga/base/opae_hw_api.h b/drivers/raw/ifpga/base/opae_hw_api.h index 613563a0b4..5957f67417 100644 --- a/drivers/raw/ifpga/base/opae_hw_api.h +++ b/drivers/raw/ifpga/base/opae_hw_api.h @@ -343,9 +343,9 @@ static inline void opae_adapter_remove_acc(struct opae_adapter *adapter, /* OPAE vBNG network datastruct */ #define OPAE_ETHER_ADDR_LEN 6 -struct opae_ether_addr { +__rte_packed_begin struct opae_ether_addr { unsigned char addr_bytes[OPAE_ETHER_ADDR_LEN]; -} __rte_packed; +} __rte_packed_end; /* OPAE vBNG network API*/ int opae_manager_read_mac_rom(struct opae_manager *mgr, int port, From patchwork Wed Nov 27 00:52:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148890 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 188C745D31; Wed, 27 Nov 2024 01:55:20 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7BDC5427CD; Wed, 27 Nov 2024 01:53:36 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id AFC09427C2 for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 4EAAD2057221; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 4EAAD2057221 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=hlOdXBQcu/hoTQMUSAPhKQmjG0TghtbClEoUYjcAlIM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lPrSmeFwP71qzL66kflFwmMSXHDSFGsyzh0Umll+UWflTV/BhAeg6C35sqnGpxAqM RRA/D9+9dIJu7pxgh0Bg79BkutqBfb7RmC3aiLuAPVcHyEI/J1hVbBTwGgVIlL5rna Df9S5B5t1wUzFIt4SkppklJXkZ7h5L1RPoCKKb9I= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 16/30] drivers/regex: replace packed attributes Date: Tue, 26 Nov 2024 16:52:27 -0800 Message-Id: <1732668761-5556-17-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retzlaff --- drivers/regex/cn9k/cn9k_regexdev.c | 4 ++-- drivers/regex/mlx5/mlx5_rxp.h | 16 ++++++++-------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/regex/cn9k/cn9k_regexdev.c b/drivers/regex/cn9k/cn9k_regexdev.c index aa809ab5bf..33de38e7f9 100644 --- a/drivers/regex/cn9k/cn9k_regexdev.c +++ b/drivers/regex/cn9k/cn9k_regexdev.c @@ -40,12 +40,12 @@ struct ree_rule_db_entry { uint64_t value; }; -struct ree_rule_db { +__rte_packed_begin struct ree_rule_db { uint32_t version; uint32_t revision; uint32_t number_of_entries; struct ree_rule_db_entry entries[]; -} __rte_packed; +} __rte_packed_end; static void qp_memzone_name_get(char *name, int size, int dev_id, int qp_id) diff --git a/drivers/regex/mlx5/mlx5_rxp.h b/drivers/regex/mlx5/mlx5_rxp.h index b38b53cc14..6deb25e13d 100644 --- a/drivers/regex/mlx5/mlx5_rxp.h +++ b/drivers/regex/mlx5/mlx5_rxp.h @@ -42,14 +42,14 @@ #define MLX5_RXP_RESP_STATUS_PMI_EOJ (1 << 14) /* This describes the header the RXP expects for any search data. */ -struct mlx5_rxp_job_desc { +__rte_packed_begin struct mlx5_rxp_job_desc { uint32_t job_id; uint16_t ctrl; uint16_t len; uint16_t subset[4]; -} __rte_packed; +} __rte_packed_end; -struct mlx5_rxp_response_desc { +__rte_packed_begin struct mlx5_rxp_response_desc { uint32_t job_id; uint16_t status; uint8_t detected_match_count; @@ -58,13 +58,13 @@ struct mlx5_rxp_response_desc { uint16_t instruction_count; uint16_t latency_count; uint16_t pmi_min_byte_ptr; -} __rte_packed; +} __rte_packed_end; -struct mlx5_rxp_match_tuple { +__rte_packed_begin struct mlx5_rxp_match_tuple { uint32_t rule_id; uint16_t start_ptr; uint16_t length; -} __rte_packed; +} __rte_packed_end; struct mlx5_rxp_response { struct mlx5_rxp_response_desc header; @@ -115,11 +115,11 @@ struct mlx5_rxp_rof { struct mlx5_rxp_rof_entry *rof_entries; }; -struct mlx5_rxp_ctl_rules_pgm { +__rte_packed_begin struct mlx5_rxp_ctl_rules_pgm { struct mlx5_rxp_ctl_hdr hdr; uint32_t count; struct mlx5_rxp_rof_entry rules[]; -} __rte_packed; +} __rte_packed_end; /* RXP programming mode setting. */ enum mlx5_rxp_program_mode { From patchwork Wed Nov 27 00:52:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148881 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5F4B845D31; Wed, 27 Nov 2024 01:54:34 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 542B542D8C; Wed, 27 Nov 2024 01:53:23 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 60496402A7 for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 5D10F2057222; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 5D10F2057222 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=5c+owxpQu0qHk95YuiJWUjqepHJEA0WudvwjA4hLeQ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KuzoBHS0G5OlaXTErHwkSHclw1A8OHURj4fJ3ObOPGBi7fRYnHk9xUhvWuwZW81s5 xCiTR/mzOOlv+MJ8WYMB4Pf47/1++Aydwtiye+pD5v5d0lFHbwoKKbflEXMKCBa1Dr WRR6ip8VJDW4zZt3KVtc9FJ9nuNAw2CpVf9w1E9Q= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 17/30] drivers/vdpa: replace packed attributes Date: Tue, 26 Nov 2024 16:52:28 -0800 Message-Id: <1732668761-5556-18-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie Reviewed-by: Tyler Retzlaff --- drivers/vdpa/ifc/base/ifcvf.h | 4 ++-- drivers/vdpa/mlx5/mlx5_vdpa.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/vdpa/ifc/base/ifcvf.h b/drivers/vdpa/ifc/base/ifcvf.h index 04c81c8196..7be1596556 100644 --- a/drivers/vdpa/ifc/base/ifcvf.h +++ b/drivers/vdpa/ifc/base/ifcvf.h @@ -115,11 +115,11 @@ struct ifcvf_pci_common_cfg { u32 queue_used_hi; }; -struct ifcvf_net_config { +__rte_packed_begin struct ifcvf_net_config { u8 mac[6]; u16 status; u16 max_virtqueue_pairs; -} __rte_packed; +} __rte_packed_end; struct ifcvf_pci_mem_resource { u64 phys_addr; /**< Physical address, 0 if not resource. */ diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index e156520172..6f25eea641 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -90,13 +90,13 @@ enum mlx5_vdpa_task_type { }; /* Generic task information and size must be multiple of 4B. */ -struct __rte_aligned(4) mlx5_vdpa_task { +__rte_packed_begin struct __rte_aligned(4) mlx5_vdpa_task { struct mlx5_vdpa_priv *priv; enum mlx5_vdpa_task_type type; RTE_ATOMIC(uint32_t) *remaining_cnt; RTE_ATOMIC(uint32_t) *err_cnt; uint32_t idx; -} __rte_packed; +} __rte_packed_end; /* Generic mlx5_vdpa_c_thread information. */ struct mlx5_vdpa_c_thread { From patchwork Wed Nov 27 00:52:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148887 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6147745D31; Wed, 27 Nov 2024 01:55:05 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8B4BF42DD1; Wed, 27 Nov 2024 01:53:31 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id B8C74427C4 for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 6B75F2057223; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 6B75F2057223 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=YHFcHbUhhtrOrgpYLOjy/2NfvslpNJZZ+DLrBREF2VI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NVrahZeOt1TRs+MjumRzRjME0bIXjzGJBzmB915+L/PnhN5AaOMo7+TLXkybkSezx bKdGLnTBV64Ii3PmxGM9l8uaMeYFfWXVG5c3Uk1pAlFxq1tK6IMGJyCn919/VThpGX tpcZeXzbKxEp1+WnmyqE9jDo8LPxw2dp6Kb+BBXY= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 18/30] examples/common: replace packed attributes Date: Tue, 26 Nov 2024 16:52:29 -0800 Message-Id: <1732668761-5556-19-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Added parenthesis around *pnum in line __ rte_packed_end (*pnum) = (void *)pn; to avoid patch check error below: ERROR:SPACING: need consistent spacing around '*' (ctx:WxV) 34: FILE: examples/common/neon/port_group.h:27: + } __ rte_packed_end *pnum = (void *)pn; With the parenthesis it becomes a warning, still not ideal, but better Running checkpatch.pl: WARNING:SPACING: space prohibited between function name and open parenthesis '(' 34: FILE: examples/common/neon/port_group.h:27: + } __ rte_packed_end (*pnum) = (void *)pn; Signed-off-by: Andre Muezerie --- examples/common/neon/port_group.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/common/neon/port_group.h b/examples/common/neon/port_group.h index 421e2e8613..0c8ea4c085 100644 --- a/examples/common/neon/port_group.h +++ b/examples/common/neon/port_group.h @@ -21,10 +21,10 @@ static inline uint16_t * port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp, uint16x8_t dp1, uint16x8_t dp2) { - union { + __rte_packed_begin union { uint16_t u16[FWDSTEP + 1]; uint64_t u64; - } __rte_packed *pnum = (void *)pn; + } __rte_packed_end (*pnum) = (void *)pn; uint16x8_t mask = {1, 2, 4, 8, 0, 0, 0, 0}; int32_t v; From patchwork Wed Nov 27 00:52:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148882 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B705445D31; Wed, 27 Nov 2024 01:54:39 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 89ED842D99; Wed, 27 Nov 2024 01:53:24 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 64C61427BF for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 7A4EE2057224; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 7A4EE2057224 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=sWQeXlXV0Bqc9hUBanIbWrsFAGpCOJF1vFQN7me95sU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X7Hn4Gh//uSE5D+W6MkiheaVCPVTIG9rY3HtVl/D3/Zikz67fTk3CiJLPTLWJg1MS vxwKk7LAJHcYZ0a0yaRm2v5FXTS/GHteO6FlMElQOZPu0APzWnX3S7SNeK2i8u0wpx ylBR0k7vCQu6F1ZNMIztRBMkNr49MGZ1jn/ZgPtw= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 19/30] examples/ip-pipeline: remove packed attributes Date: Tue, 26 Nov 2024 16:52:30 -0800 Message-Id: <1732668761-5556-20-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Removed packed attributes from structs that are naturally packed already, or don't require packing. Signed-off-by: Andre Muezerie --- examples/ip_pipeline/cli.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/examples/ip_pipeline/cli.c b/examples/ip_pipeline/cli.c index 92dfacdeb0..766fc8e46e 100644 --- a/examples/ip_pipeline/cli.c +++ b/examples/ip_pipeline/cli.c @@ -2571,7 +2571,7 @@ struct pkt_key_qinq { uint16_t svlan; uint16_t ethertype_cvlan; uint16_t cvlan; -} __rte_packed; +}; struct pkt_key_ipv4_5tuple { uint8_t time_to_live; @@ -2581,7 +2581,7 @@ struct pkt_key_ipv4_5tuple { uint32_t da; uint16_t sp; uint16_t dp; -} __rte_packed; +}; struct pkt_key_ipv6_5tuple { uint16_t payload_length; @@ -2591,15 +2591,15 @@ struct pkt_key_ipv6_5tuple { struct rte_ipv6_addr da; uint16_t sp; uint16_t dp; -} __rte_packed; +}; struct pkt_key_ipv4_addr { uint32_t addr; -} __rte_packed; +}; struct pkt_key_ipv6_addr { struct rte_ipv6_addr addr; -} __rte_packed; +}; static uint32_t parse_match(char **tokens, From patchwork Wed Nov 27 00:52:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148889 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8B99645D31; Wed, 27 Nov 2024 01:55:15 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 10B4742DDC; Wed, 27 Nov 2024 01:53:35 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id BBC91427D1 for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 893DB205A776; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 893DB205A776 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=kw5lY+Ogh+jwWuF13qixz2hyJ8kn3B3TbO+hy+dEduc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cEXISGYgMJCSs/E0DR0U4kkXiMw5LxHfQRkcg28ZxaNw7Tk4L7ZURY9LslM+lGZve my65i+g+Pi5okxh3AO71p9Zz31hbbgykDUWvyTGXya53hU7XINgDlNytdauZiO5ykH sP33nT0LDO5MPfkAAOPTXc32gsjEOYMMzP4nA+G4= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 20/30] examples/ipsec_secgw: replace packed attributes Date: Tue, 26 Nov 2024 16:52:31 -0800 Message-Id: <1732668761-5556-21-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie --- examples/ipsec-secgw/ipsec.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/examples/ipsec-secgw/ipsec.h b/examples/ipsec-secgw/ipsec.h index f12f57e2d5..afa0f28cc5 100644 --- a/examples/ipsec-secgw/ipsec.h +++ b/examples/ipsec-secgw/ipsec.h @@ -274,11 +274,12 @@ struct socket_ctx { struct rte_mempool *session_pool; }; +__rte_packed_begin struct cnt_blk { uint32_t salt; uint64_t iv; uint32_t cnt; -} __rte_packed; +} __rte_packed_end; struct __rte_cache_aligned lcore_rx_queue { uint16_t port_id; From patchwork Wed Nov 27 00:52:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148896 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9948645D31; Wed, 27 Nov 2024 01:55:53 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9E62642E4A; Wed, 27 Nov 2024 01:53:43 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 3C710427D2 for ; Wed, 27 Nov 2024 01:53:05 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 9756C23718AC; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 9756C23718AC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=bpbcV2PZxLQGpfzkfM527oAYvmgYNIGhUQhULtN9Ekc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Mntb/pIM1fXwNDDcRAxvcocr6IUNzDFaVZv4n75AMxWojgTye1Ee8eBMJPCav4Wyj VzYuLV5afOhFNIuXuXRA6gAQ4YKQ+J43VbZFtCOkgofxgMnYvew4Q0aPTsHdg3mioc Itf11ChMPWAcid2a0QktURTB4gx5oJbd29JUElZU= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 21/30] examples/l3fwd-power: replace packed attributes Date: Tue, 26 Nov 2024 16:52:32 -0800 Message-Id: <1732668761-5556-22-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie --- examples/l3fwd-power/main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c index ae8b55924e..65b6bd3756 100644 --- a/examples/l3fwd-power/main.c +++ b/examples/l3fwd-power/main.c @@ -282,21 +282,23 @@ static struct rte_mempool * pktmbuf_pool[NB_SOCKETS]; #define DEFAULT_HASH_FUNC rte_jhash #endif +__rte_packed_begin struct ipv4_5tuple { uint32_t ip_dst; uint32_t ip_src; uint16_t port_dst; uint16_t port_src; uint8_t proto; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct ipv6_5tuple { uint8_t ip_dst[IPV6_ADDR_LEN]; uint8_t ip_src[IPV6_ADDR_LEN]; uint16_t port_dst; uint16_t port_src; uint8_t proto; -} __rte_packed; +} __rte_packed_end; struct ipv4_l3fwd_route { struct ipv4_5tuple key; From patchwork Wed Nov 27 00:52:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148884 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3FC7E45D31; Wed, 27 Nov 2024 01:54:51 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 384CF42DBE; Wed, 27 Nov 2024 01:53:27 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 9381B427CB for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id A6056238AF4D; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com A6056238AF4D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=6gE3V/e3uzpFETNBlh3H8mYgXW5KKU6j39VTSCmgf7k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UQSN4yCENzxiK5cXVNImUswQ0XnY08Ggtuf/SzkAPvJ2UrxIS79bshgi+CtpXEp5q jw7lJN2XhiZ2hOqFrguaqtVvg811lbbx8RusppYo4JCKxgFBrVRJC/kZqrR0QicniK o8tN/LN0nAoTXimXN9XvhSeyvmwSHpF4Pzko73fM= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 22/30] examples/l3fwd: replace packed attributes Date: Tue, 26 Nov 2024 16:52:33 -0800 Message-Id: <1732668761-5556-23-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie --- examples/l3fwd/l3fwd_route.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/examples/l3fwd/l3fwd_route.h b/examples/l3fwd/l3fwd_route.h index 62263c3540..5303e7ce6f 100644 --- a/examples/l3fwd/l3fwd_route.h +++ b/examples/l3fwd/l3fwd_route.h @@ -36,21 +36,23 @@ struct ipv6_l3fwd_route { uint8_t if_out; }; +__rte_packed_begin struct ipv4_5tuple { uint32_t ip_dst; uint32_t ip_src; uint16_t port_dst; uint16_t port_src; uint8_t proto; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct ipv6_5tuple { uint8_t ip_dst[IPV6_ADDR_LEN]; uint8_t ip_src[IPV6_ADDR_LEN]; uint16_t port_dst; uint16_t port_src; uint8_t proto; -} __rte_packed; +} __rte_packed_end; struct lpm_route_rule { union { From patchwork Wed Nov 27 00:52:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148894 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7288D45D31; Wed, 27 Nov 2024 01:55:42 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8A7AC42DCB; Wed, 27 Nov 2024 01:53:41 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 93859427CC for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id B47DF2050D80; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com B47DF2050D80 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=PhTAAZFPuyInEyrL8ior8n8+h40vIPkBilMn2Ju0E/A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nI3fglnDMCY8y+bNtN1WaAzPF8NKTiB3CkTVvNsstKz58iGo0Hg3zLuxQT2knba9K wlpZax/VcqsG3qc4BavfyoPayMYuMWqbsiyCiEI4bEeOekPn04N6+Hyp6lVQ5sfDAv ToplTRzy/G0WxzJB4QNa195ws/H1eWYtw3fho5gg= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 23/30] examples/ptpclient: replace packed attributes Date: Tue, 26 Nov 2024 16:52:34 -0800 Message-Id: <1732668761-5556-24-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie --- examples/ptpclient/ptpclient.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/examples/ptpclient/ptpclient.c b/examples/ptpclient/ptpclient.c index 23fa487081..5486a87119 100644 --- a/examples/ptpclient/ptpclient.c +++ b/examples/ptpclient/ptpclient.c @@ -85,21 +85,24 @@ static const struct rte_ether_addr ether_multicast = { }; /* Structs used for PTP handling. */ +__rte_packed_begin struct tstamp { uint16_t sec_msb; uint32_t sec_lsb; uint32_t ns; -} __rte_packed; +} __rte_packed_end; struct clock_id { uint8_t id[8]; }; +__rte_packed_begin struct port_id { struct clock_id clock_id; uint16_t port_number; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct ptp_header { uint8_t msg_type; uint8_t ver; @@ -113,39 +116,44 @@ struct ptp_header { uint16_t seq_id; uint8_t control; int8_t log_message_interval; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct sync_msg { struct ptp_header hdr; struct tstamp origin_tstamp; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct follow_up_msg { struct ptp_header hdr; struct tstamp precise_origin_tstamp; uint8_t suffix[]; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct delay_req_msg { struct ptp_header hdr; struct tstamp origin_tstamp; -} __rte_packed; +} __rte_packed_end; +__rte_packed_begin struct delay_resp_msg { struct ptp_header hdr; struct tstamp rx_tstamp; struct port_id req_port_id; uint8_t suffix[]; -} __rte_packed; +} __rte_packed_end; struct ptp_message { + __rte_packed_begin union { struct ptp_header header; struct sync_msg sync; struct delay_req_msg delay_req; struct follow_up_msg follow_up; struct delay_resp_msg delay_resp; - } __rte_packed; + } __rte_packed_end; }; struct ptpv2_time_receiver_ordinary { From patchwork Wed Nov 27 00:52:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148885 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CD85345D31; Wed, 27 Nov 2024 01:54:55 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 93D8242DC9; Wed, 27 Nov 2024 01:53:28 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 98459427CF for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id C47152050D81; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com C47152050D81 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=GkuPPy52LVfHFeVdyfYOGLpb+6yucWeYjyJDaSLHCwQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IcmtJTdMTo2rSwJlPMULUq5o84PC0f2KGZybmucL3U8n6nFMOgErUmBI9rRevanbp qYEBKRS5SDyDXQfzRQYW7SeVF4eVA6gS5ebOYk5Fy6cgsKBQKT0wY5rUe1jmbqIbcD axQtR8wmPgLRwq1ntw1bBBf6mFMRperN/8Rz9uGw= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 24/30] examples/vhost_blk: replace packed attributes Date: Tue, 26 Nov 2024 16:52:35 -0800 Message-Id: <1732668761-5556-25-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie --- examples/vhost_blk/blk_spec.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/examples/vhost_blk/blk_spec.h b/examples/vhost_blk/blk_spec.h index 3c54f70eaf..6c6a36d471 100644 --- a/examples/vhost_blk/blk_spec.h +++ b/examples/vhost_blk/blk_spec.h @@ -73,6 +73,7 @@ struct vhost_memory_padded { struct vhost_memory_region regions[VHOST_USER_MEMORY_MAX_NREGIONS]; }; +__rte_packed_begin struct vhost_user_msg { enum vhost_user_request request; @@ -89,6 +90,6 @@ struct vhost_user_msg { struct vhost_memory_padded memory; struct vhost_user_config cfg; } payload; -} __rte_packed; +} __rte_packed_end; #endif From patchwork Wed Nov 27 00:52:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148888 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E8D7B45D31; Wed, 27 Nov 2024 01:55:10 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1BCDD42DB4; Wed, 27 Nov 2024 01:53:33 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 215AA427C6 for ; Wed, 27 Nov 2024 01:53:05 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id D30E12050D82; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com D30E12050D82 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=r1GObn/6n/J65v/M/U/+BJHcz2VosOtsJICZ4BprEAc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WdxM2WR8paxJC2tP4xzsYWrHrs6nlWzn7YwOzqeSAVuF9rwfVuF00rsiw+pKCe3uO EWbg40vkSgx/cdCiyWBkfV9LBSxJNrwLT/cPWackQtuPMPnx4vWcCDThs7eFuf1giO ixtM+p8LHChqbg4ill44hcfbN19i7OOkJdlvX+88= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 25/30] lib/eal: replace packed attributes Date: Tue, 26 Nov 2024 16:52:36 -0800 Message-Id: <1732668761-5556-26-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Removed the packed attributes from some structures that don't need them. Signed-off-by: Andre Muezerie --- lib/eal/common/eal_private.h | 2 +- lib/eal/include/rte_memory.h | 3 ++- lib/eal/include/rte_memzone.h | 3 ++- lib/eal/include/rte_trace_point.h | 2 +- lib/eal/x86/include/rte_memcpy.h | 9 ++++++--- 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/lib/eal/common/eal_private.h b/lib/eal/common/eal_private.h index bb315dab04..3b94e01b5b 100644 --- a/lib/eal/common/eal_private.h +++ b/lib/eal/common/eal_private.h @@ -62,7 +62,7 @@ struct rte_config { * DPDK instances */ struct rte_mem_config *mem_config; -} __rte_packed; +}; /** * Get the global configuration structure. diff --git a/lib/eal/include/rte_memory.h b/lib/eal/include/rte_memory.h index dbd0a6bedc..25fd7e0a6b 100644 --- a/lib/eal/include/rte_memory.h +++ b/lib/eal/include/rte_memory.h @@ -46,6 +46,7 @@ extern "C" { /** * Physical memory segment descriptor. */ +__rte_packed_begin struct rte_memseg { rte_iova_t iova; /**< Start IO address. */ union { @@ -58,7 +59,7 @@ struct rte_memseg { uint32_t nchannel; /**< Number of channels. */ uint32_t nrank; /**< Number of ranks. */ uint32_t flags; /**< Memseg-specific flags */ -} __rte_packed; +} __rte_packed_end; /** * memseg list is a special case as we need to store a bunch of other data diff --git a/lib/eal/include/rte_memzone.h b/lib/eal/include/rte_memzone.h index e1563994d5..28c2262e12 100644 --- a/lib/eal/include/rte_memzone.h +++ b/lib/eal/include/rte_memzone.h @@ -45,6 +45,7 @@ extern "C" { * A structure describing a memzone, which is a contiguous portion of * physical memory identified by a name. */ +__rte_packed_begin struct rte_memzone { #define RTE_MEMZONE_NAMESIZE 32 /**< Maximum length of memory zone name.*/ @@ -62,7 +63,7 @@ struct rte_memzone { int32_t socket_id; /**< NUMA socket ID. */ uint32_t flags; /**< Characteristics of this memzone. */ -} __rte_packed; +} __rte_packed_end; /** * Set the maximum number of memzones. diff --git a/lib/eal/include/rte_trace_point.h b/lib/eal/include/rte_trace_point.h index 87b5f43c3c..b24db3b6da 100644 --- a/lib/eal/include/rte_trace_point.h +++ b/lib/eal/include/rte_trace_point.h @@ -298,7 +298,7 @@ struct __rte_trace_stream_header { rte_uuid_t uuid; uint32_t lcore_id; char thread_name[__RTE_TRACE_EMIT_STRING_LEN_MAX]; -} __rte_packed; +}; struct __rte_trace_header { uint32_t offset; diff --git a/lib/eal/x86/include/rte_memcpy.h b/lib/eal/x86/include/rte_memcpy.h index 42058e4a3f..58368145c4 100644 --- a/lib/eal/x86/include/rte_memcpy.h +++ b/lib/eal/x86/include/rte_memcpy.h @@ -67,15 +67,18 @@ rte_mov15_or_less(void *dst, const void *src, size_t n) * Use the following structs to avoid violating C standard * alignment requirements and to avoid strict aliasing bugs */ + __rte_packed_begin struct rte_uint64_alias { uint64_t val; - } __rte_packed __rte_may_alias; + } __rte_packed_end __rte_may_alias; + __rte_packed_begin struct rte_uint32_alias { uint32_t val; - } __rte_packed __rte_may_alias; + } __rte_packed_end __rte_may_alias; + __rte_packed_begin struct rte_uint16_alias { uint16_t val; - } __rte_packed __rte_may_alias; + } __rte_packed_end __rte_may_alias; void *ret = dst; if (n & 8) { From patchwork Wed Nov 27 00:52:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148891 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9F42945D31; Wed, 27 Nov 2024 01:55:24 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BD16E42DE4; Wed, 27 Nov 2024 01:53:37 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id A08AE427D0 for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id E25412050D83; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com E25412050D83 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=lUztOxy6cRprErI6VhYNXkPGw6fvOmfeNumfRv9XIFs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Jtf9wNpARhUJY3jeVpFdeurgvf+osKzPCO8r3kAWxIWayDKMwr+oNDl/VA35UDaY5 oimlSPRioufNKllSo9WL6WVcqyJlebxPzo8EdhHSsFcoXJHDsAjibcHaHHe/x1Tn+t N+T31blYXlAcUysEuZhv9eD3/q99dDZaatmCLRkU= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 26/30] lib/ipsec: replace packed attributes Date: Tue, 26 Nov 2024 16:52:37 -0800 Message-Id: <1732668761-5556-27-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie --- lib/ipsec/crypto.h | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/lib/ipsec/crypto.h b/lib/ipsec/crypto.h index 93d20aaaa0..bbadd38257 100644 --- a/lib/ipsec/crypto.h +++ b/lib/ipsec/crypto.h @@ -15,11 +15,11 @@ * AES-CTR counter block format. */ -struct aesctr_cnt_blk { +__rte_packed_begin struct aesctr_cnt_blk { uint32_t nonce; uint64_t iv; uint32_t cnt; -} __rte_packed; +} __rte_packed_end; /* * CHACHA20-POLY1305 devices have some specific requirements @@ -27,13 +27,13 @@ struct aesctr_cnt_blk { * Ideally that to be done by the driver itself. */ -struct aead_chacha20_poly1305_iv { +__rte_packed_begin struct aead_chacha20_poly1305_iv { uint32_t salt; uint64_t iv; uint32_t cnt; -} __rte_packed; +} __rte_packed_end; -struct aead_chacha20_poly1305_aad { +__rte_packed_begin struct aead_chacha20_poly1305_aad { uint32_t spi; /* * RFC 4106, section 5: @@ -45,25 +45,25 @@ struct aead_chacha20_poly1305_aad { uint64_t u64; } sqn; uint32_t align0; /* align to 16B boundary */ -} __rte_packed; +} __rte_packed_end; -struct chacha20_poly1305_esph_iv { +__rte_packed_begin struct chacha20_poly1305_esph_iv { struct rte_esp_hdr esph; uint64_t iv; -} __rte_packed; +} __rte_packed_end; /* * AES-GCM devices have some specific requirements for IV and AAD formats. * Ideally that to be done by the driver itself. */ -struct aead_gcm_iv { +__rte_packed_begin struct aead_gcm_iv { uint32_t salt; uint64_t iv; uint32_t cnt; -} __rte_packed; +} __rte_packed_end; -struct aead_gcm_aad { +__rte_packed_begin struct aead_gcm_aad { uint32_t spi; /* * RFC 4106, section 5: @@ -75,34 +75,34 @@ struct aead_gcm_aad { uint64_t u64; } sqn; uint32_t align0; /* align to 16B boundary */ -} __rte_packed; +} __rte_packed_end; -struct gcm_esph_iv { +__rte_packed_begin struct gcm_esph_iv { struct rte_esp_hdr esph; uint64_t iv; -} __rte_packed; +} __rte_packed_end; /* * AES-CCM devices have some specific requirements for IV and AAD formats. * Ideally that to be done by the driver itself. */ -union aead_ccm_salt { +__rte_packed_begin union aead_ccm_salt { uint32_t salt; struct inner { uint8_t salt8[3]; uint8_t ccm_flags; } inner; -} __rte_packed; +} __rte_packed_end; -struct aead_ccm_iv { +__rte_packed_begin struct aead_ccm_iv { uint8_t ccm_flags; uint8_t salt[3]; uint64_t iv; uint32_t cnt; -} __rte_packed; +} __rte_packed_end; -struct aead_ccm_aad { +__rte_packed_begin struct aead_ccm_aad { uint8_t padding[18]; uint32_t spi; /* @@ -115,12 +115,12 @@ struct aead_ccm_aad { uint64_t u64; } sqn; uint32_t align0; /* align to 16B boundary */ -} __rte_packed; +} __rte_packed_end; -struct ccm_esph_iv { +__rte_packed_begin struct ccm_esph_iv { struct rte_esp_hdr esph; uint64_t iv; -} __rte_packed; +} __rte_packed_end; static inline void From patchwork Wed Nov 27 00:52:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148897 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 89AEE45D31; Wed, 27 Nov 2024 01:55:58 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AB6CC42E4C; Wed, 27 Nov 2024 01:53:44 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 93870427CD for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id F0DD92050D84; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com F0DD92050D84 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668783; bh=81AhoXfu8ZVuh0eKvL7t5iQ5UVr2jBtWtZly323EyP8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pVcUqouQ42lGNho1mSN3DPBxygHXK1r3J54yrVdh60XmtRAcuSA3UI+2zASJvUmGp EIeO2tpRHkCIqfnlIVhIub0DMDTQ3nmriEZBAz009teVz8+xoguTEuxEMJ4Wm/YGLO osyaKuu4JfC3iZIB7rEytrWU4oFidAFQseU7BmyQ= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 27/30] lib/net: replace packed attributes Date: Tue, 26 Nov 2024 16:52:38 -0800 Message-Id: <1732668761-5556-28-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie --- lib/net/rte_arp.h | 6 ++++-- lib/net/rte_dtls.h | 3 ++- lib/net/rte_esp.h | 6 ++++-- lib/net/rte_geneve.h | 3 ++- lib/net/rte_gre.h | 12 ++++++++---- lib/net/rte_gtp.h | 15 ++++++++++----- lib/net/rte_ib.h | 3 ++- lib/net/rte_icmp.h | 9 ++++++--- lib/net/rte_ip4.h | 3 ++- lib/net/rte_ip6.h | 12 ++++++++---- lib/net/rte_l2tpv2.h | 12 ++++++++---- lib/net/rte_macsec.h | 6 ++++-- lib/net/rte_mpls.h | 3 ++- lib/net/rte_pdcp_hdr.h | 12 ++++++++---- lib/net/rte_ppp.h | 3 ++- lib/net/rte_sctp.h | 3 ++- lib/net/rte_tcp.h | 3 ++- lib/net/rte_tls.h | 3 ++- lib/net/rte_udp.h | 3 ++- lib/net/rte_vxlan.h | 21 ++++++++++++++------- 20 files changed, 94 insertions(+), 47 deletions(-) diff --git a/lib/net/rte_arp.h b/lib/net/rte_arp.h index 668cea1704..4032dd72a5 100644 --- a/lib/net/rte_arp.h +++ b/lib/net/rte_arp.h @@ -21,16 +21,18 @@ extern "C" { /** * ARP header IPv4 payload. */ +__rte_packed_begin struct __rte_aligned(2) rte_arp_ipv4 { struct rte_ether_addr arp_sha; /**< sender hardware address */ rte_be32_t arp_sip; /**< sender IP address */ struct rte_ether_addr arp_tha; /**< target hardware address */ rte_be32_t arp_tip; /**< target IP address */ -} __rte_packed; +} __rte_packed_end; /** * ARP header. */ +__rte_packed_begin struct __rte_aligned(2) rte_arp_hdr { rte_be16_t arp_hardware; /**< format of hardware address */ #define RTE_ARP_HRD_ETHER 1 /**< ARP Ethernet address format */ @@ -47,7 +49,7 @@ struct __rte_aligned(2) rte_arp_hdr { #define RTE_ARP_OP_INVREPLY 9 /**< response identifying peer */ struct rte_arp_ipv4 arp_data; -} __rte_packed; +} __rte_packed_end; /** * Make a RARP packet based on MAC addr. diff --git a/lib/net/rte_dtls.h b/lib/net/rte_dtls.h index 246cd8a72d..a341b2155e 100644 --- a/lib/net/rte_dtls.h +++ b/lib/net/rte_dtls.h @@ -30,6 +30,7 @@ * DTLS Header */ __extension__ +__rte_packed_begin struct rte_dtls_hdr { /** Content type of DTLS packet. Defined as RTE_DTLS_TYPE_*. */ uint8_t type; @@ -48,6 +49,6 @@ struct rte_dtls_hdr { #endif /** The length (in bytes) of the following DTLS packet. */ rte_be16_t length; -} __rte_packed; +} __rte_packed_end; #endif /* RTE_DTLS_H */ diff --git a/lib/net/rte_esp.h b/lib/net/rte_esp.h index 745a9847fe..156e26ec0a 100644 --- a/lib/net/rte_esp.h +++ b/lib/net/rte_esp.h @@ -16,17 +16,19 @@ /** * ESP Header */ +__rte_packed_begin struct rte_esp_hdr { rte_be32_t spi; /**< Security Parameters Index */ rte_be32_t seq; /**< packet sequence number */ -} __rte_packed; +} __rte_packed_end; /** * ESP Trailer */ +__rte_packed_begin struct rte_esp_tail { uint8_t pad_len; /**< number of pad bytes (0-255) */ uint8_t next_proto; /**< IPv4 or IPv6 or next layer header */ -} __rte_packed; +} __rte_packed_end; #endif /* RTE_ESP_H_ */ diff --git a/lib/net/rte_geneve.h b/lib/net/rte_geneve.h index eb2c85f1e9..66489c524e 100644 --- a/lib/net/rte_geneve.h +++ b/lib/net/rte_geneve.h @@ -34,6 +34,7 @@ * More-bits (optional) variable length options. */ __extension__ +__rte_packed_begin struct rte_geneve_hdr { #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN uint8_t ver:2; /**< Version. */ @@ -52,7 +53,7 @@ struct rte_geneve_hdr { uint8_t vni[3]; /**< Virtual network identifier. */ uint8_t reserved2; /**< Reserved. */ uint32_t opts[]; /**< Variable length options. */ -} __rte_packed; +} __rte_packed_end; /* GENEVE ETH next protocol types */ #define RTE_GENEVE_TYPE_ETH 0x6558 /**< Ethernet Protocol. */ diff --git a/lib/net/rte_gre.h b/lib/net/rte_gre.h index 1483e1b42d..d9e70c43c6 100644 --- a/lib/net/rte_gre.h +++ b/lib/net/rte_gre.h @@ -23,6 +23,7 @@ * GRE Header */ __extension__ +__rte_packed_begin struct rte_gre_hdr { #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN uint16_t res2:4; /**< Reserved */ @@ -42,28 +43,31 @@ struct rte_gre_hdr { uint16_t ver:3; /**< Version Number */ #endif rte_be16_t proto; /**< Protocol Type */ -} __rte_packed; +} __rte_packed_end; /** * Optional field checksum in GRE header */ +__rte_packed_begin struct rte_gre_hdr_opt_checksum_rsvd { rte_be16_t checksum; rte_be16_t reserved1; -} __rte_packed; +} __rte_packed_end; /** * Optional field key in GRE header */ +__rte_packed_begin struct rte_gre_hdr_opt_key { rte_be32_t key; -} __rte_packed; +} __rte_packed_end; /** * Optional field sequence in GRE header */ +__rte_packed_begin struct rte_gre_hdr_opt_sequence { rte_be32_t sequence; -} __rte_packed; +} __rte_packed_end; #endif /* RTE_GRE_H_ */ diff --git a/lib/net/rte_gtp.h b/lib/net/rte_gtp.h index ab06e23a6e..e2d3711304 100644 --- a/lib/net/rte_gtp.h +++ b/lib/net/rte_gtp.h @@ -24,6 +24,7 @@ * No optional fields and next extension header. */ __extension__ +__rte_packed_begin struct rte_gtp_hdr { union { uint8_t gtp_hdr_info; /**< GTP header info */ @@ -48,20 +49,22 @@ struct rte_gtp_hdr { uint8_t msg_type; /**< GTP message type */ rte_be16_t plen; /**< Total payload length */ rte_be32_t teid; /**< Tunnel endpoint ID */ -} __rte_packed; +} __rte_packed_end; /* Optional word of GTP header, present if any of E, S, PN is set. */ +__rte_packed_begin struct rte_gtp_hdr_ext_word { rte_be16_t sqn; /**< Sequence Number. */ uint8_t npdu; /**< N-PDU number. */ uint8_t next_ext; /**< Next Extension Header Type. */ -} __rte_packed; +} __rte_packed_end; /** * Optional extension for GTP with next_ext set to 0x85 * defined based on RFC 38415-g30. */ __extension__ +__rte_packed_begin struct rte_gtp_psc_generic_hdr { uint8_t ext_hdr_len; /**< PDU ext hdr len in multiples of 4 bytes */ #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN @@ -78,13 +81,14 @@ struct rte_gtp_psc_generic_hdr { uint8_t spare:2; /**< type specific spare bits */ #endif uint8_t data[0]; /**< variable length data fields */ -} __rte_packed; +} __rte_packed_end; /** * Optional extension for GTP with next_ext set to 0x85 * type0 defined based on RFC 38415-g30 */ __extension__ +__rte_packed_begin struct rte_gtp_psc_type0_hdr { uint8_t ext_hdr_len; /**< PDU ext hdr len in multiples of 4 bytes */ #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN @@ -105,13 +109,14 @@ struct rte_gtp_psc_type0_hdr { uint8_t ppp:1; /**< Paging policy presence */ #endif uint8_t data[0]; /**< variable length data fields */ -} __rte_packed; +} __rte_packed_end; /** * Optional extension for GTP with next_ext set to 0x85 * type1 defined based on RFC 38415-g30 */ __extension__ +__rte_packed_begin struct rte_gtp_psc_type1_hdr { uint8_t ext_hdr_len; /**< PDU ext hdr len in multiples of 4 bytes */ #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN @@ -134,7 +139,7 @@ struct rte_gtp_psc_type1_hdr { uint8_t n_delay_ind:1; /**< N3/N9 delay result presence */ #endif uint8_t data[0]; /**< variable length data fields */ -} __rte_packed; +} __rte_packed_end; /** GTP header length */ #define RTE_ETHER_GTP_HLEN \ diff --git a/lib/net/rte_ib.h b/lib/net/rte_ib.h index a551f3753f..989d9d53b3 100644 --- a/lib/net/rte_ib.h +++ b/lib/net/rte_ib.h @@ -22,6 +22,7 @@ * IB Specification Vol 1-Release-1.4. */ __extension__ +__rte_packed_begin struct rte_ib_bth { uint8_t opcode; /**< Opcode. */ #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN @@ -54,7 +55,7 @@ struct rte_ib_bth { uint8_t rsvd1:7; /**< Reserved. */ #endif uint8_t psn[3]; /**< Packet Sequence Number */ -} __rte_packed; +} __rte_packed_end; /** RoCEv2 default port. */ #define RTE_ROCEV2_DEFAULT_PORT 4791 diff --git a/lib/net/rte_icmp.h b/lib/net/rte_icmp.h index e69d68ab6e..912d79a1cf 100644 --- a/lib/net/rte_icmp.h +++ b/lib/net/rte_icmp.h @@ -21,33 +21,36 @@ /** * ICMP base header */ +__rte_packed_begin struct rte_icmp_base_hdr { uint8_t type; uint8_t code; rte_be16_t checksum; -} __rte_packed; +} __rte_packed_end; /** * ICMP echo header */ +__rte_packed_begin struct rte_icmp_echo_hdr { struct rte_icmp_base_hdr base; rte_be16_t identifier; rte_be16_t sequence; -} __rte_packed; +} __rte_packed_end; /** * ICMP Header * * @see rte_icmp_echo_hdr which is similar. */ +__rte_packed_begin struct rte_icmp_hdr { uint8_t icmp_type; /* ICMP packet type. */ uint8_t icmp_code; /* ICMP packet code. */ rte_be16_t icmp_cksum; /* ICMP packet checksum. */ rte_be16_t icmp_ident; /* ICMP packet identifier. */ rte_be16_t icmp_seq_nb; /* ICMP packet sequence number. */ -} __rte_packed; +} __rte_packed_end; /* ICMP packet types */ #define RTE_ICMP_TYPE_ECHO_REPLY 0 diff --git a/lib/net/rte_ip4.h b/lib/net/rte_ip4.h index f9b8333332..30bbe1541d 100644 --- a/lib/net/rte_ip4.h +++ b/lib/net/rte_ip4.h @@ -39,6 +39,7 @@ extern "C" { /** * IPv4 Header */ +__rte_packed_begin struct __rte_aligned(2) rte_ipv4_hdr { __extension__ union { @@ -62,7 +63,7 @@ struct __rte_aligned(2) rte_ipv4_hdr { rte_be16_t hdr_checksum; /**< header checksum */ rte_be32_t src_addr; /**< source address */ rte_be32_t dst_addr; /**< destination address */ -} __rte_packed; +} __rte_packed_end; /** Create IPv4 address */ #define RTE_IPV4(a, b, c, d) ((uint32_t)(((a) & 0xff) << 24) | \ diff --git a/lib/net/rte_ip6.h b/lib/net/rte_ip6.h index 992ab5ee1f..c92753b3f2 100644 --- a/lib/net/rte_ip6.h +++ b/lib/net/rte_ip6.h @@ -345,6 +345,7 @@ rte_ipv6_addr_is_mcast(const struct rte_ipv6_addr *ip) /** * IPv6 multicast scope values as defined in RFC 4291, section 2.7. */ +__rte_packed_begin enum rte_ipv6_mc_scope { /** Invalid multicast scope. */ RTE_IPV6_MC_SCOPE_NONE = 0x00, @@ -358,7 +359,7 @@ enum rte_ipv6_mc_scope { RTE_IPV6_MC_SCOPE_ORGLOCAL = 0x08, /** Global multicast scope. */ RTE_IPV6_MC_SCOPE_GLOBAL = 0x0e, -} __rte_packed; +} __rte_packed_end; /** * Extract the IPv6 multicast scope value as defined in RFC 4291, section 2.7. @@ -461,6 +462,7 @@ rte_ether_mcast_from_ipv6(struct rte_ether_addr *mac, const struct rte_ipv6_addr /** * IPv6 Header */ +__rte_packed_begin struct __rte_aligned(2) rte_ipv6_hdr { union { rte_be32_t vtc_flow; /**< IP version, traffic class & flow label. */ @@ -484,7 +486,7 @@ struct __rte_aligned(2) rte_ipv6_hdr { uint8_t hop_limits; /**< Hop limits. */ struct rte_ipv6_addr src_addr; /**< IP address of source host. */ struct rte_ipv6_addr dst_addr; /**< IP address of destination host(s). */ -} __rte_packed; +} __rte_packed_end; /** * Check that the IPv6 header version field is valid according to RFC 8200 section 3. @@ -508,6 +510,7 @@ static inline int rte_ipv6_check_version(const struct rte_ipv6_hdr *ip) /** * IPv6 Routing Extension Header */ +__rte_packed_begin struct __rte_aligned(2) rte_ipv6_routing_ext { uint8_t next_hdr; /**< Protocol, next header. */ uint8_t hdr_len; /**< Header length. */ @@ -523,7 +526,7 @@ struct __rte_aligned(2) rte_ipv6_routing_ext { }; }; /* Next are 128-bit IPv6 address fields to describe segments. */ -} __rte_packed; +} __rte_packed_end; /* IPv6 vtc_flow: IPv / TC / flow_label */ #define RTE_IPV6_HDR_FL_SHIFT 0 @@ -752,12 +755,13 @@ rte_ipv6_udptcp_cksum_mbuf_verify(const struct rte_mbuf *m, #define RTE_IPV6_SET_FRAG_DATA(fo, mf) \ (((fo) & RTE_IPV6_EHDR_FO_MASK) | ((mf) & RTE_IPV6_EHDR_MF_MASK)) +__rte_packed_begin struct __rte_aligned(2) rte_ipv6_fragment_ext { uint8_t next_header; /**< Next header type */ uint8_t reserved; /**< Reserved */ rte_be16_t frag_data; /**< All fragmentation data */ rte_be32_t id; /**< Packet ID */ -} __rte_packed; +} __rte_packed_end; /* IPv6 fragment extension header size */ #define RTE_IPV6_FRAG_HDR_SIZE sizeof(struct rte_ipv6_fragment_ext) diff --git a/lib/net/rte_l2tpv2.h b/lib/net/rte_l2tpv2.h index ac16657856..f035a0d5b3 100644 --- a/lib/net/rte_l2tpv2.h +++ b/lib/net/rte_l2tpv2.h @@ -125,6 +125,7 @@ struct rte_l2tpv2_common_hdr { * L2TPv2 message Header contains all options(length, ns, nr, * offset size, offset padding). */ +__rte_packed_begin struct rte_l2tpv2_msg_with_all_options { rte_be16_t length; /**< length(16) */ rte_be16_t tunnel_id; /**< tunnel ID(16) */ @@ -133,12 +134,13 @@ struct rte_l2tpv2_msg_with_all_options { rte_be16_t nr; /**< Nr(16) */ rte_be16_t offset_size; /**< offset size(16) */ uint8_t *offset_padding; /**< offset padding(variable length) */ -} __rte_packed; +} __rte_packed_end; /** * L2TPv2 message Header contains all options except length(ns, nr, * offset size, offset padding). */ +__rte_packed_begin struct rte_l2tpv2_msg_without_length { rte_be16_t tunnel_id; /**< tunnel ID(16) */ rte_be16_t session_id; /**< session ID(16) */ @@ -146,7 +148,7 @@ struct rte_l2tpv2_msg_without_length { rte_be16_t nr; /**< Nr(16) */ rte_be16_t offset_size; /**< offset size(16) */ uint8_t *offset_padding; /**< offset padding(variable length) */ -} __rte_packed; +} __rte_packed_end; /** * L2TPv2 message Header contains all options except ns_nr(length, @@ -176,12 +178,13 @@ struct rte_l2tpv2_msg_without_offset { /** * L2TPv2 message Header contains options offset size and offset padding. */ +__rte_packed_begin struct rte_l2tpv2_msg_with_offset { rte_be16_t tunnel_id; /**< tunnel ID(16) */ rte_be16_t session_id; /**< session ID(16) */ rte_be16_t offset_size; /**< offset size(16) */ uint8_t *offset_padding; /**< offset padding(variable length) */ -} __rte_packed; +} __rte_packed_end; /** * L2TPv2 message Header contains options ns and nr. @@ -213,6 +216,7 @@ struct rte_l2tpv2_msg_without_all_options { /** * L2TPv2 Combined Message Header Format: Common Header + Options */ +__rte_packed_begin struct rte_l2tpv2_combined_msg_hdr { struct rte_l2tpv2_common_hdr common; /**< common header */ union { @@ -233,6 +237,6 @@ struct rte_l2tpv2_combined_msg_hdr { /** header without all options */ struct rte_l2tpv2_msg_without_all_options type7; }; -} __rte_packed; +} __rte_packed_end; #endif /* _RTE_L2TPV2_H_ */ diff --git a/lib/net/rte_macsec.h b/lib/net/rte_macsec.h index beeeb8effe..088f60417e 100644 --- a/lib/net/rte_macsec.h +++ b/lib/net/rte_macsec.h @@ -25,6 +25,7 @@ * MACsec Header (SecTAG) */ __extension__ +__rte_packed_begin struct rte_macsec_hdr { /** * Tag control information and Association number of secure channel. @@ -39,7 +40,7 @@ struct rte_macsec_hdr { uint8_t short_length:6; /**< Short Length. */ #endif rte_be32_t packet_number; /**< Packet number to support replay protection. */ -} __rte_packed; +} __rte_packed_end; /** SCI length in MACsec header if present. */ #define RTE_MACSEC_SCI_LEN 8 @@ -48,8 +49,9 @@ struct rte_macsec_hdr { * MACsec SCI header (8 bytes) after the MACsec header * which is present if SC bit is set in tci_an. */ +__rte_packed_begin struct rte_macsec_sci_hdr { uint8_t sci[RTE_MACSEC_SCI_LEN]; /**< Optional secure channel ID. */ -} __rte_packed; +} __rte_packed_end; #endif /* RTE_MACSEC_H */ diff --git a/lib/net/rte_mpls.h b/lib/net/rte_mpls.h index 35a356efd3..a5dda16db7 100644 --- a/lib/net/rte_mpls.h +++ b/lib/net/rte_mpls.h @@ -18,6 +18,7 @@ * MPLS header. */ __extension__ +__rte_packed_begin struct rte_mpls_hdr { rte_be16_t tag_msb; /**< Label(msb). */ #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN @@ -30,6 +31,6 @@ struct rte_mpls_hdr { uint8_t tag_lsb:4; /**< label(lsb) */ #endif uint8_t ttl; /**< Time to live. */ -} __rte_packed; +} __rte_packed_end; #endif /* RTE_MPLS_H_ */ diff --git a/lib/net/rte_pdcp_hdr.h b/lib/net/rte_pdcp_hdr.h index c22b66bf93..e05fcf83f2 100644 --- a/lib/net/rte_pdcp_hdr.h +++ b/lib/net/rte_pdcp_hdr.h @@ -56,6 +56,7 @@ enum rte_pdcp_pdu_type { * 6.2.2.1 Data PDU for SRBs */ __extension__ +__rte_packed_begin struct rte_pdcp_cp_data_pdu_sn_12_hdr { #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN uint8_t sn_11_8 : 4; /**< Sequence number bits 8-11 */ @@ -65,12 +66,13 @@ struct rte_pdcp_cp_data_pdu_sn_12_hdr { uint8_t sn_11_8 : 4; /**< Sequence number bits 8-11 */ #endif uint8_t sn_7_0; /**< Sequence number bits 0-7 */ -} __rte_packed; +} __rte_packed_end; /** * 6.2.2.2 Data PDU for DRBs and MRBs with 12 bits PDCP SN */ __extension__ +__rte_packed_begin struct rte_pdcp_up_data_pdu_sn_12_hdr { #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN uint8_t sn_11_8 : 4; /**< Sequence number bits 8-11 */ @@ -82,12 +84,13 @@ struct rte_pdcp_up_data_pdu_sn_12_hdr { uint8_t sn_11_8 : 4; /**< Sequence number bits 8-11 */ #endif uint8_t sn_7_0; /**< Sequence number bits 0-7 */ -} __rte_packed; +} __rte_packed_end; /** * 6.2.2.3 Data PDU for DRBs and MRBs with 18 bits PDCP SN */ __extension__ +__rte_packed_begin struct rte_pdcp_up_data_pdu_sn_18_hdr { #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN uint8_t sn_17_16 : 2; /**< Sequence number bits 16-17 */ @@ -100,12 +103,13 @@ struct rte_pdcp_up_data_pdu_sn_18_hdr { #endif uint8_t sn_15_8; /**< Sequence number bits 8-15 */ uint8_t sn_7_0; /**< Sequence number bits 0-7 */ -} __rte_packed; +} __rte_packed_end; /** * 6.2.3.1 Control PDU for PDCP status report */ __extension__ +__rte_packed_begin struct rte_pdcp_up_ctrl_pdu_hdr { #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN uint8_t r : 4; /**< Reserved */ @@ -134,6 +138,6 @@ struct rte_pdcp_up_ctrl_pdu_hdr { * in the Bitmap is 1. */ uint8_t bitmap[]; -} __rte_packed; +} __rte_packed_end; #endif /* RTE_PDCP_HDR_H */ diff --git a/lib/net/rte_ppp.h b/lib/net/rte_ppp.h index 63c72a9392..bda693a1e7 100644 --- a/lib/net/rte_ppp.h +++ b/lib/net/rte_ppp.h @@ -17,10 +17,11 @@ /** * PPP Header */ +__rte_packed_begin struct rte_ppp_hdr { uint8_t addr; /**< PPP address(8) */ uint8_t ctrl; /**< PPP control(8) */ rte_be16_t proto_id; /**< PPP protocol identifier(16) */ -} __rte_packed; +} __rte_packed_end; #endif /* _RTE_PPP_H_ */ diff --git a/lib/net/rte_sctp.h b/lib/net/rte_sctp.h index e757c57db3..f9dfac2ba7 100644 --- a/lib/net/rte_sctp.h +++ b/lib/net/rte_sctp.h @@ -21,11 +21,12 @@ /** * SCTP Header */ +__rte_packed_begin struct rte_sctp_hdr { rte_be16_t src_port; /**< Source port. */ rte_be16_t dst_port; /**< Destin port. */ rte_be32_t tag; /**< Validation tag. */ rte_be32_t cksum; /**< Checksum. */ -} __rte_packed; +} __rte_packed_end; #endif /* RTE_SCTP_H_ */ diff --git a/lib/net/rte_tcp.h b/lib/net/rte_tcp.h index 1bcacbf038..218599f790 100644 --- a/lib/net/rte_tcp.h +++ b/lib/net/rte_tcp.h @@ -21,6 +21,7 @@ /** * TCP Header */ +__rte_packed_begin struct rte_tcp_hdr { rte_be16_t src_port; /**< TCP source port. */ rte_be16_t dst_port; /**< TCP destination port. */ @@ -31,7 +32,7 @@ struct rte_tcp_hdr { rte_be16_t rx_win; /**< RX flow control window. */ rte_be16_t cksum; /**< TCP checksum. */ rte_be16_t tcp_urp; /**< TCP urgent pointer, if any. */ -} __rte_packed; +} __rte_packed_end; /** * TCP Flags diff --git a/lib/net/rte_tls.h b/lib/net/rte_tls.h index 595567e3e9..33411f83f2 100644 --- a/lib/net/rte_tls.h +++ b/lib/net/rte_tls.h @@ -28,6 +28,7 @@ * TLS Header */ __extension__ +__rte_packed_begin struct rte_tls_hdr { /** Content type of TLS packet. Defined as RTE_TLS_TYPE_*. */ uint8_t type; @@ -35,6 +36,6 @@ struct rte_tls_hdr { rte_be16_t version; /** The length (in bytes) of the following TLS packet. */ rte_be16_t length; -} __rte_packed; +} __rte_packed_end; #endif /* RTE_TLS_H */ diff --git a/lib/net/rte_udp.h b/lib/net/rte_udp.h index c01dad9c9b..548a063dab 100644 --- a/lib/net/rte_udp.h +++ b/lib/net/rte_udp.h @@ -21,11 +21,12 @@ /** * UDP Header */ +__rte_packed_begin struct rte_udp_hdr { rte_be16_t src_port; /**< UDP source port. */ rte_be16_t dst_port; /**< UDP destination port. */ rte_be16_t dgram_len; /**< UDP datagram length */ rte_be16_t dgram_cksum; /**< UDP datagram checksum */ -} __rte_packed; +} __rte_packed_end; #endif /* RTE_UDP_H_ */ diff --git a/lib/net/rte_vxlan.h b/lib/net/rte_vxlan.h index bd1c89835e..f54e4206b6 100644 --- a/lib/net/rte_vxlan.h +++ b/lib/net/rte_vxlan.h @@ -27,12 +27,15 @@ * Reserved fields (24 bits and 8 bits) */ __extension__ /* no named member in struct */ +__rte_packed_begin struct rte_vxlan_hdr { union { rte_be32_t vx_flags; /**< flags (8 bits) + extensions (24 bits). */ + __rte_packed_begin struct { union { uint8_t flags; /**< Default is I bit, others are extensions. */ + __rte_packed_begin struct { #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN uint8_t flag_g:1, /**< GBP bit. */ @@ -51,10 +54,11 @@ struct rte_vxlan_hdr { flag_rsvd:1, flag_g:1; #endif - } __rte_packed; + } __rte_packed_end; }; /* end of 1st byte */ union { uint8_t rsvd0[3]; /* Reserved for extensions. */ + __rte_packed_begin struct { #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN uint8_t rsvd0_gbp1:1, /* Reserved. */ @@ -71,6 +75,7 @@ struct rte_vxlan_hdr { #endif union { uint16_t policy_id; /**< GBP Identifier. */ + __rte_packed_begin struct { uint8_t rsvd0_gpe; /* Reserved. */ uint8_t proto; /**< GPE Next protocol. */ @@ -79,23 +84,24 @@ struct rte_vxlan_hdr { * 0x03 : Ethernet * 0x04 : Network Service Header */ - } __rte_packed; + } __rte_packed_end; }; - } __rte_packed; + } __rte_packed_end; }; - } __rte_packed; + } __rte_packed_end; }; /* end of 1st 32-bit word */ union { rte_be32_t vx_vni; /**< VNI (24 bits) + reserved (8 bits). */ + __rte_packed_begin struct { uint8_t vni[3]; /**< VXLAN Identifier. */ union { uint8_t rsvd1; /**< Reserved. */ uint8_t last_rsvd; /**< Reserved. */ }; - } __rte_packed; + } __rte_packed_end; }; /* end of 2nd 32-bit word */ -} __rte_packed; +} __rte_packed_end; /** VXLAN tunnel header length. */ #define RTE_ETHER_VXLAN_HLEN \ @@ -111,6 +117,7 @@ struct rte_vxlan_hdr { * Identifier and Reserved fields (16 bits and 8 bits). */ __extension__ /* no named member in struct */ +__rte_packed_begin struct rte_vxlan_gpe_hdr { union { struct { @@ -127,7 +134,7 @@ struct rte_vxlan_gpe_hdr { uint8_t rsvd1; /**< Reserved. */ }; }; -} __rte_packed; +} __rte_packed_end; /** * @deprecated From patchwork Wed Nov 27 00:52:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148892 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 95B9F45D31; Wed, 27 Nov 2024 01:55:29 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D7D7942E1C; Wed, 27 Nov 2024 01:53:38 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 3592B427C8 for ; Wed, 27 Nov 2024 01:53:05 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 0AEDD2050D85; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 0AEDD2050D85 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668784; bh=nmnBHU6kqyeqUSlTMI9r34+V7hWKydKKasOTH1+0oJs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WKtBBNHlnzJBMXKyQ7F240iFVknPIKIrd3DdQNvef6P1UcMCDfKObl0GBBcvR2GLW Jmo4Fv4LjWayJHz/9YJVnX3Mtx02XBuxtjAi8En5eAifVm0cY84/oH0SejpGYAVFj9 pI/ren/sQ5IT71lilIYClnsFC1Agwr3o+WnCgA9E= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 28/30] lib/pipeline: replace packed attributes Date: Tue, 26 Nov 2024 16:52:39 -0800 Message-Id: <1732668761-5556-29-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie --- lib/pipeline/rte_table_action.c | 64 ++++++++++++++++----------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/lib/pipeline/rte_table_action.c b/lib/pipeline/rte_table_action.c index a431f8f128..60cc9ae659 100644 --- a/lib/pipeline/rte_table_action.c +++ b/lib/pipeline/rte_table_action.c @@ -60,9 +60,9 @@ lb_cfg_check(struct rte_table_action_lb_config *cfg) return 0; } -struct lb_data { +__rte_packed_begin struct lb_data { uint32_t out[RTE_TABLE_ACTION_LB_TABLE_SIZE]; -} __rte_packed; +} __rte_packed_end; static int lb_apply(struct lb_data *data, @@ -356,10 +356,10 @@ tm_cfg_check(struct rte_table_action_tm_config *tm) return 0; } -struct tm_data { +__rte_packed_begin struct tm_data { uint32_t queue_id; uint32_t reserved; -} __rte_packed; +} __rte_packed_end; static int tm_apply_check(struct rte_table_action_tm_params *p, @@ -465,11 +465,11 @@ struct encap_qinq_data { ((((uint64_t)(s)) & 0x1LLU) << 8) | \ (((uint64_t)(ttl)) & 0xFFLLU))) -struct __rte_aligned(2) encap_mpls_data { +__rte_packed_begin struct __rte_aligned(2) encap_mpls_data { struct rte_ether_hdr ether; uint32_t mpls[RTE_TABLE_ACTION_MPLS_LABELS_MAX]; uint32_t mpls_count; -} __rte_packed; +} __rte_packed_end; #define PPP_PROTOCOL_IP 0x0021 @@ -487,42 +487,42 @@ struct encap_pppoe_data { #define IP_PROTO_UDP 17 -struct __rte_aligned(2) encap_vxlan_ipv4_data { +__rte_packed_begin struct __rte_aligned(2) encap_vxlan_ipv4_data { struct rte_ether_hdr ether; struct rte_ipv4_hdr ipv4; struct rte_udp_hdr udp; struct rte_vxlan_hdr vxlan; -} __rte_packed; +} __rte_packed_end; -struct __rte_aligned(2) encap_vxlan_ipv4_vlan_data { +__rte_packed_begin struct __rte_aligned(2) encap_vxlan_ipv4_vlan_data { struct rte_ether_hdr ether; struct rte_vlan_hdr vlan; struct rte_ipv4_hdr ipv4; struct rte_udp_hdr udp; struct rte_vxlan_hdr vxlan; -} __rte_packed; +} __rte_packed_end; -struct __rte_aligned(2) encap_vxlan_ipv6_data { +__rte_packed_begin struct __rte_aligned(2) encap_vxlan_ipv6_data { struct rte_ether_hdr ether; struct rte_ipv6_hdr ipv6; struct rte_udp_hdr udp; struct rte_vxlan_hdr vxlan; -} __rte_packed; +} __rte_packed_end; -struct __rte_aligned(2) encap_vxlan_ipv6_vlan_data { +__rte_packed_begin struct __rte_aligned(2) encap_vxlan_ipv6_vlan_data { struct rte_ether_hdr ether; struct rte_vlan_hdr vlan; struct rte_ipv6_hdr ipv6; struct rte_udp_hdr udp; struct rte_vxlan_hdr vxlan; -} __rte_packed; +} __rte_packed_end; -struct __rte_aligned(2) encap_qinq_pppoe_data { +__rte_packed_begin struct __rte_aligned(2) encap_qinq_pppoe_data { struct rte_ether_hdr ether; struct rte_vlan_hdr svlan; struct rte_vlan_hdr cvlan; struct pppoe_ppp_hdr pppoe_ppp; -} __rte_packed; +} __rte_packed_end; static size_t encap_data_size(struct rte_table_action_encap_config *encap) @@ -1196,15 +1196,15 @@ nat_cfg_check(struct rte_table_action_nat_config *nat) return 0; } -struct nat_ipv4_data { +__rte_packed_begin struct nat_ipv4_data { uint32_t addr; uint16_t port; -} __rte_packed; +} __rte_packed_end; -struct nat_ipv6_data { +__rte_packed_begin struct nat_ipv6_data { struct rte_ipv6_addr addr; uint16_t port; -} __rte_packed; +} __rte_packed_end; static size_t nat_data_size(struct rte_table_action_nat_config *nat __rte_unused, @@ -1493,9 +1493,9 @@ ttl_cfg_check(struct rte_table_action_ttl_config *ttl) return 0; } -struct ttl_data { +__rte_packed_begin struct ttl_data { uint32_t n_packets; -} __rte_packed; +} __rte_packed_end; #define TTL_INIT(data, decrement) \ ((data)->n_packets = (decrement) ? 1 : 0) @@ -1576,10 +1576,10 @@ stats_cfg_check(struct rte_table_action_stats_config *stats) return 0; } -struct stats_data { +__rte_packed_begin struct stats_data { uint64_t n_packets; uint64_t n_bytes; -} __rte_packed; +} __rte_packed_end; static int stats_apply(struct stats_data *data, @@ -1602,9 +1602,9 @@ pkt_work_stats(struct stats_data *data, /** * RTE_TABLE_ACTION_TIME */ -struct time_data { +__rte_packed_begin struct time_data { uint64_t time; -} __rte_packed; +} __rte_packed_end; static int time_apply(struct time_data *data, @@ -1649,7 +1649,7 @@ struct crypto_op_sym_iv_aad { } iv_aad; }; -struct sym_crypto_data { +__rte_packed_begin struct sym_crypto_data { union { struct { @@ -1717,7 +1717,7 @@ struct sym_crypto_data { /** Private data size to store cipher iv / aad. */ uint8_t iv_aad_data[32]; -} __rte_packed; +} __rte_packed_end; static int sym_crypto_cfg_check(struct rte_table_action_sym_crypto_config *cfg) @@ -2052,9 +2052,9 @@ pkt_work_sym_crypto(struct rte_mbuf *mbuf, struct sym_crypto_data *data, /** * RTE_TABLE_ACTION_TAG */ -struct tag_data { +__rte_packed_begin struct tag_data { uint32_t tag; -} __rte_packed; +} __rte_packed_end; static int tag_apply(struct tag_data *data, @@ -2096,9 +2096,9 @@ pkt4_work_tag(struct rte_mbuf *mbuf0, /** * RTE_TABLE_ACTION_DECAP */ -struct decap_data { +__rte_packed_begin struct decap_data { uint16_t n; -} __rte_packed; +} __rte_packed_end; static int decap_apply(struct decap_data *data, From patchwork Wed Nov 27 00:52:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148886 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BF98645D31; Wed, 27 Nov 2024 01:55:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1C2BB42D28; Wed, 27 Nov 2024 01:53:30 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 95CB7427CE for ; Wed, 27 Nov 2024 01:53:04 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 19B282050D86; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 19B282050D86 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668784; bh=hX5Lvh+cQGArqOHZbfyHVs6/fVVGB/6S2bkGaZvwba4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FCF2TT/UlJyhBQZp86dmQdKM3KxjpfJhZ+yMJmv8AC9KhwXsakd4jA+E0WAPq+7/f JwFd5f1+F9SX57HCRYWeI6U/64zUTvqKu4JQN1LomSB3/RFT+YtDliTPtmwhMqICSD oInqIO9PpW3P1xeTc1YmImqIHUWgTI/ujr5WkmF0= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 29/30] lib/vhost: replace packed attributes Date: Tue, 26 Nov 2024 16:52:40 -0800 Message-Id: <1732668761-5556-30-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push. Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing. Signed-off-by: Andre Muezerie --- lib/vhost/vhost_user.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/vhost/vhost_user.h b/lib/vhost/vhost_user.h index edf7adb3c0..d48542e72f 100644 --- a/lib/vhost/vhost_user.h +++ b/lib/vhost/vhost_user.h @@ -143,7 +143,7 @@ struct vhost_user_config { uint8_t region[VHOST_USER_MAX_CONFIG_SIZE]; }; -typedef struct VhostUserMsg { +typedef __rte_packed_begin struct VhostUserMsg { union { uint32_t frontend; /* a VhostUserRequest value */ uint32_t backend; /* a VhostUserBackendRequest value*/ @@ -169,16 +169,16 @@ typedef struct VhostUserMsg { struct vhost_user_config cfg; } payload; /* Nothing should be added after the payload */ -} __rte_packed VhostUserMsg; +} __rte_packed_end VhostUserMsg; /* Note: this structure and VhostUserMsg can't be changed carelessly as * external message handlers rely on them. */ -struct __rte_packed vhu_msg_context { +__rte_packed_begin struct vhu_msg_context { VhostUserMsg msg; int fds[VHOST_MEMORY_MAX_NREGIONS]; int fd_num; -}; +} __rte_packed_end; #define VHOST_USER_HDR_SIZE offsetof(VhostUserMsg, payload.u64) From patchwork Wed Nov 27 00:52:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Muezerie X-Patchwork-Id: 148895 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 82AA745D31; Wed, 27 Nov 2024 01:55:48 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8470A42E24; Wed, 27 Nov 2024 01:53:42 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 1910D427C5 for ; Wed, 27 Nov 2024 01:53:05 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 287492050D87; Tue, 26 Nov 2024 16:53:02 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 287492050D87 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1732668784; bh=y3SC8hGj8BGDgiYHfIw3Tuo8J9mv+/ZE5qGnBoulkXA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PBrEZSDx4XplVkTU1y9BzzreYBDna3klekLR8W+/1O0FsApH7rwRsEVjLifB61kYs 10wvaDIhIPfZQvotGtVTjlKtUlaNp/hzKRivisskKKNuHjB8TRGvUTgAeNWBMjW++O BMqKn4c2i+dNjD/Ot91I9i63B+kD9nXqaveRC54Q= From: Andre Muezerie To: roretzla@linux.microsoft.com Cc: aman.deep.singh@intel.com, anatoly.burakov@intel.com, bruce.richardson@intel.com, byron.marohn@intel.com, conor.walsh@intel.com, cristian.dumitrescu@intel.com, david.hunt@intel.com, dev@dpdk.org, dsosnowski@nvidia.com, gakhil@marvell.com, jerinj@marvell.com, jingjing.wu@intel.com, kirill.rybalchenko@intel.com, konstantin.v.ananyev@yandex.ru, matan@nvidia.com, orika@nvidia.com, radu.nicolau@intel.com, ruifeng.wang@arm.com, sameh.gobriel@intel.com, sivaprasad.tummala@amd.com, skori@marvell.com, stephen@networkplumber.org, suanmingm@nvidia.com, vattunuru@marvell.com, viacheslavo@nvidia.com, vladimir.medvedkin@intel.com, yipeng1.wang@intel.com, Andre Muezerie Subject: [PATCH v6 30/30] lib/eal: remove __rte_packed Date: Tue, 26 Nov 2024 16:52:41 -0800 Message-Id: <1732668761-5556-31-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> References: <1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com> <1732668761-5556-1-git-send-email-andremue@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove macro __rte_packed now that the code was made portable using __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push when MSVC is used. Signed-off-by: Andre Muezerie Acked-by: Tyler Retzlaff --- lib/eal/include/rte_common.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/lib/eal/include/rte_common.h b/lib/eal/include/rte_common.h index affdcaf3c1..21bfd26b2b 100644 --- a/lib/eal/include/rte_common.h +++ b/lib/eal/include/rte_common.h @@ -99,15 +99,6 @@ typedef uint32_t unaligned_uint32_t; typedef uint16_t unaligned_uint16_t; #endif -/** - * Force a structure to be packed - */ -#ifdef RTE_TOOLCHAIN_MSVC -#define __rte_packed -#else -#define __rte_packed __attribute__((__packed__)) -#endif - /** * Force a structure to be packed */