From patchwork Wed Aug 7 20:44:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Gutorov X-Patchwork-Id: 143009 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D97545761; Wed, 7 Aug 2024 22:44:49 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8081140E21; Wed, 7 Aug 2024 22:44:48 +0200 (CEST) Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) by mails.dpdk.org (Postfix) with ESMTP id 7C55440E21; Wed, 7 Aug 2024 22:44:46 +0200 (CEST) Received: by mail-lj1-f177.google.com with SMTP id 38308e7fff4ca-2eeb1ba0481so2502871fa.2; Wed, 07 Aug 2024 13:44:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723063486; x=1723668286; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MWb9opsuwL/dx4s9b6UWO7I5Wis3ly/pp2dhUHx/78I=; b=IDcEOyguDwD2cjL/IqPeN0JOnFVb7PRGWAsiOVEpXoI0pmK9OZaSi91e2Nlt+4YNYa pN4sWfCtdvSL18grpLGhk7AUIpYp0oopI208x7jMMjZHeImkopN2ERu5U6L93mKhcNns lM+DUGvBl02mKva+3g/6dNBVJwo75vyyqL065tFg7aA9SA/k9VUHykx637SGUWM7tGto oO6P5Rgue++z52Ld5D4vOLtdwOw/lxGg3XdqLggp2ymg9cEKl9p3FgnNorlvlF05xQb9 vw+G8dkwD2BnvbLAvcX3S/85lutUSiuXtdFdht5Tf6yCGuG8BoBcHNzJ3VBB3Qkv/60g zsyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723063486; x=1723668286; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MWb9opsuwL/dx4s9b6UWO7I5Wis3ly/pp2dhUHx/78I=; b=PhvxKFqSwk+0biSeZBs2iSCJ2E7A2dLyM0RCJUWoMG6CaeH1MhTfLSeQ+X9F/dn/jE o7PfPFZMAEeHluso6zcCUSM0JDYcG401VOjUM9zQMPYQYX/c0SIHzwDp5n48WUfzORnY CvixekZAerg75eyWpaKNQ8T3zgEumRULrEsJpVmBgjDetI1d6JCV9Ejwr693mrMINh+4 HpO6OhE+ku/qLui6vZVMQWKr5jnSAl4uQWjKq1XOIGOfbKP89Gqez333hWeeVI2H0YHZ X5PAcO7YQpomSWwNl8nBZNYoY5ZNXUXWrYu8FNY78X3cWmZTm/NqSMZ8XFR7+QglAfpF wkoQ== X-Forwarded-Encrypted: i=1; AJvYcCXYXs/ko3O7WFwfDY19Wf6DVWLuqJHuSjQPHGzWSMXYJjmmja8WNgxPv/C9LPCkDqB3E9mZtPQ=@dpdk.org X-Gm-Message-State: AOJu0YxN2Or6rH8p6jF+OrJysYoO2jnUYU5l8QdpinNex8jpeBcu4/re yTBTY40F6fwboz1eQZBCTD6BpGcE2gJNWECsGryE+HLjMp5RwwNobtnfPg== X-Google-Smtp-Source: AGHT+IEyeaXUpHxAORoZGW2+MkoL49x2EgrlMgXV4xwIdqloKrFkk12wwlzs/4a0szpKSsQEYZ91Pg== X-Received: by 2002:a05:651c:228:b0:2ec:6639:120a with SMTP id 38308e7fff4ca-2f15aa84f11mr119656111fa.10.1723063485242; Wed, 07 Aug 2024 13:44:45 -0700 (PDT) Received: from saturn.intmts.ru ([46.175.25.246]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2f15e1c7581sm19102691fa.68.2024.08.07.13.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Aug 2024 13:44:44 -0700 (PDT) From: Igor Gutorov To: dev@dpdk.org Cc: Igor Gutorov , stable@dpdk.org Subject: [PATCH v3 1/2] net/mlx5: fix reported Rx/Tx desc limits Date: Wed, 7 Aug 2024 23:44:05 +0300 Message-ID: <20240807204406.700332-2-igootorov@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240807204406.700332-1-igootorov@gmail.com> References: <20240807204406.700332-1-igootorov@gmail.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Currently, `rte_eth_dev_info.rx_desc_lim.nb_max` as well as `rte_eth_dev_info.tx_desc_lim.nb_max` shows 65535 as the limit, which results in a few problems: * It is not the actual Rx/Tx queue limit * Allocating an Rx queue and passing `rx_desc_lim.nb_max` results in an integer overflow and 0 ring size: ``` rte_eth_rx_queue_setup(0, 0, rx_desc_lim.nb_max, 0, NULL, mb_pool); ``` Which overflows ring size and generates the following log: ``` mlx5_net: port 0 increased number of descriptors in Rx queue 0 to the next power of two (0) ``` The same holds for allocating a Tx queue. Fixes: e60fbd5b24fc ("mlx5: add device configure/start/stop") Cc: stable@dpdk.org Signed-off-by: Igor Gutorov --- drivers/common/mlx5/mlx5_devx_cmds.c | 1 + drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/net/mlx5/mlx5_ethdev.c | 4 ++++ drivers/net/mlx5/mlx5_rxq.c | 8 ++++++++ drivers/net/mlx5/mlx5_txq.c | 8 ++++++++ 5 files changed, 22 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 9710dcedd3..a75f011750 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1027,6 +1027,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); + attr->log_max_wq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_wq_sz); attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 6cf7999c46..2ad9e5414f 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -267,6 +267,7 @@ struct mlx5_hca_attr { struct mlx5_hca_flow_attr flow; struct mlx5_hca_flex_attr flex; struct mlx5_hca_crypto_mmo_attr crypto_mmo; + uint8_t log_max_wq_sz; int log_max_qp_sz; int log_max_cq_sz; int log_max_qp; diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index 6a678d6dcc..cac55f7a72 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -359,6 +359,10 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK; mlx5_set_default_params(dev, info); mlx5_set_txlimit_params(dev, info); + info->rx_desc_lim.nb_max = + 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz; + info->tx_desc_lim.nb_max = + 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz; if (priv->sh->cdev->config.hca_attr.mem_rq_rmp && priv->obj_ops.rxq_obj_new == devx_obj_ops.rxq_obj_new) info->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE; diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index f13fc3b353..7e171039eb 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -655,6 +655,14 @@ mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc, struct mlx5_rxq_priv *rxq; bool empty; + if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) { + DRV_LOG(ERR, + "port %u number of descriptors requested for Rx queue" + " %u is more than supported", + dev->data->port_id, idx); + rte_errno = EINVAL; + return -EINVAL; + } if (!rte_is_power_of_2(*desc)) { *desc = 1 << log2above(*desc); DRV_LOG(WARNING, diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index f05534e168..3e93517323 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -333,6 +333,14 @@ mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc) { struct mlx5_priv *priv = dev->data->dev_private; + if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) { + DRV_LOG(ERR, + "port %u number of descriptors requested for Tx queue" + " %u is more than supported", + dev->data->port_id, idx); + rte_errno = EINVAL; + return -EINVAL; + } if (*desc <= MLX5_TX_COMP_THRESH) { DRV_LOG(WARNING, "port %u number of descriptors requested for Tx queue" From patchwork Wed Aug 7 20:44:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Gutorov X-Patchwork-Id: 143010 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3900045761; Wed, 7 Aug 2024 22:44:56 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 11B4A41157; Wed, 7 Aug 2024 22:44:50 +0200 (CEST) Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) by mails.dpdk.org (Postfix) with ESMTP id D1F6140EE2 for ; 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Wed, 07 Aug 2024 13:44:47 -0700 (PDT) From: Igor Gutorov To: dev@dpdk.org Cc: Igor Gutorov Subject: [PATCH v3 2/2] common/mlx5: reduce HCA attribute type sizes Date: Wed, 7 Aug 2024 23:44:06 +0300 Message-ID: <20240807204406.700332-3-igootorov@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240807204406.700332-1-igootorov@gmail.com> References: <20240807204406.700332-1-igootorov@gmail.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org A number of `log_max_*` fields' types are unnecessarily large, and can be reduced to `uint8_t`. Signed-off-by: Igor Gutorov --- drivers/common/mlx5/mlx5_devx_cmds.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 2ad9e5414f..f523bf8529 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -268,10 +268,10 @@ struct mlx5_hca_attr { struct mlx5_hca_flex_attr flex; struct mlx5_hca_crypto_mmo_attr crypto_mmo; uint8_t log_max_wq_sz; - int log_max_qp_sz; - int log_max_cq_sz; - int log_max_qp; - int log_max_cq; + uint8_t log_max_qp_sz; + uint8_t log_max_cq_sz; + uint8_t log_max_qp; + uint8_t log_max_cq; uint32_t log_max_pd; uint32_t log_max_mrw_sz; uint32_t log_max_srq;