From patchwork Thu Apr 11 08:22:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 139223 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 26BDB43E42; Thu, 11 Apr 2024 10:22:58 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 11EF3402ED; Thu, 11 Apr 2024 10:22:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 26312402EB for ; Thu, 11 Apr 2024 10:22:55 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 43B5v2PU000545; Thu, 11 Apr 2024 01:22:48 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=aY+WOQPgWV8H7RXFpbm2wvD7xZZJG9cvNlvXdLaHjSw=; b=Pee 4ei76IS1P+TPYzVDUD8xlWZjvYqq9mlBsZC6AffvTXQnuIS2YKpBcfSja141N2+3 YDBPDACiAMUMOIgYhwBpk1yQZ8aQQYki4UbP8HTeUcUlgjpiFtV4fwhgt4J55daP IpTCbABTzbvyhsYxYseIPllezKOwRe9jtnwsM7bE0/2F0oVSwaWOqYGrTQwe/wpH lC8Tb7LrW2i1OyuKpgDBvw183cqrirjMxAttJ9jSoPNhpJGD+RwHUft/NxcD/lir o0XSKKsH1k9sD+d9xxt6Fjnx6f2qdF1h5e9FPFe4uxlVPmMCt5bIjAb3rY0O8s2T ihwnZq5N2Tvsftl2rIA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3xea5f1fxm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 Apr 2024 01:22:48 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 11 Apr 2024 01:22:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 11 Apr 2024 01:22:47 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 992DA3F706A; Thu, 11 Apr 2024 01:22:41 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , , , , , , , , , , , , , Akhil Goyal Subject: [PATCH 1/3] cryptodev: add API to get used queue pair depth Date: Thu, 11 Apr 2024 13:52:30 +0530 Message-ID: <20240411082232.3495883-2-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240411082232.3495883-1-gakhil@marvell.com> References: <20240411082232.3495883-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: fuQFYDEd0SwQgnxkY1KJZ2OCU3W2iRFV X-Proofpoint-ORIG-GUID: fuQFYDEd0SwQgnxkY1KJZ2OCU3W2iRFV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-11_02,2024-04-09_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added a new fast path API to get used queue pair descriptors of a specific queue pair of a device. Applications may monitor the depth used and enqueue crypto ops accordingly. Signed-off-by: Akhil Goyal --- devtools/libabigail.abignore | 3 ++ lib/cryptodev/cryptodev_pmd.c | 1 + lib/cryptodev/cryptodev_pmd.h | 2 ++ lib/cryptodev/cryptodev_trace_points.c | 3 ++ lib/cryptodev/rte_cryptodev.h | 45 ++++++++++++++++++++++++++ lib/cryptodev/rte_cryptodev_core.h | 7 +++- lib/cryptodev/rte_cryptodev_trace_fp.h | 7 ++++ 7 files changed, 67 insertions(+), 1 deletion(-) diff --git a/devtools/libabigail.abignore b/devtools/libabigail.abignore index 645d289a77..bd63f42008 100644 --- a/devtools/libabigail.abignore +++ b/devtools/libabigail.abignore @@ -37,3 +37,6 @@ [suppress_type] name = rte_eth_fp_ops has_data_member_inserted_between = {offset_of(reserved2), end} +[suppress_type] + name = rte_crypto_fp_ops + has_data_member_inserted_between = {offset_of(reserved), end} diff --git a/lib/cryptodev/cryptodev_pmd.c b/lib/cryptodev/cryptodev_pmd.c index d8073a601d..87ced122b4 100644 --- a/lib/cryptodev/cryptodev_pmd.c +++ b/lib/cryptodev/cryptodev_pmd.c @@ -236,6 +236,7 @@ cryptodev_fp_ops_set(struct rte_crypto_fp_ops *fp_ops, fp_ops->qp.data = dev->data->queue_pairs; fp_ops->qp.enq_cb = dev->enq_cbs; fp_ops->qp.deq_cb = dev->deq_cbs; + fp_ops->qp_depth_used = dev->qp_depth_used; } void * diff --git a/lib/cryptodev/cryptodev_pmd.h b/lib/cryptodev/cryptodev_pmd.h index d195b81771..c22cc0908d 100644 --- a/lib/cryptodev/cryptodev_pmd.h +++ b/lib/cryptodev/cryptodev_pmd.h @@ -117,6 +117,8 @@ struct __rte_cache_aligned rte_cryptodev { struct rte_cryptodev_cb_rcu *enq_cbs; /** User application callback for post dequeue processing */ struct rte_cryptodev_cb_rcu *deq_cbs; + /** Pointer to PMD function to get used queue pair depth */ + crypto_qp_depth_used_t qp_depth_used; }; /** Global structure used for maintaining state of allocated crypto devices */ diff --git a/lib/cryptodev/cryptodev_trace_points.c b/lib/cryptodev/cryptodev_trace_points.c index 8c47ab1e78..7403412553 100644 --- a/lib/cryptodev/cryptodev_trace_points.c +++ b/lib/cryptodev/cryptodev_trace_points.c @@ -194,3 +194,6 @@ RTE_TRACE_POINT_REGISTER(rte_cryptodev_trace_op_pool_create, RTE_TRACE_POINT_REGISTER(rte_cryptodev_trace_count, lib.cryptodev.count) + +RTE_TRACE_POINT_REGISTER(rte_cryptodev_trace_qp_depth_used, + lib.cryptodev.qp_depth_used) diff --git a/lib/cryptodev/rte_cryptodev.h b/lib/cryptodev/rte_cryptodev.h index 00ba6a234a..d6d7938f84 100644 --- a/lib/cryptodev/rte_cryptodev.h +++ b/lib/cryptodev/rte_cryptodev.h @@ -2005,6 +2005,51 @@ rte_cryptodev_enqueue_burst(uint8_t dev_id, uint16_t qp_id, return fp_ops->enqueue_burst(qp, ops, nb_ops); } +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the number of used descriptors or depth of a cryptodev queue pair. + * + * This function retrieves the number of used descriptors in a crypto queue. + * Applications can use this API in the fast path to inspect QP occupancy and + * take appropriate action. + * + * Since it is a fast-path function, no check is performed on dev_id and qp_id. + * Caller must therefore ensure that the device is enabled and queue pair is setup. + * + * @param dev_id The identifier of the device. + * @param qp_id The index of the queue pair for which used descriptor + * count is to be retrieved. The value + * must be in the range [0, nb_queue_pairs - 1] + * previously supplied to *rte_cryptodev_configure*. + * + * @return + * The number of used descriptors on the specified queue pair, or: + * - (-ENOTSUP) if the device does not support this function. + */ + +__rte_experimental +static inline int +rte_cryptodev_qp_depth_used(uint8_t dev_id, uint16_t qp_id) +{ + const struct rte_crypto_fp_ops *fp_ops; + void *qp; + int rc; + + fp_ops = &rte_crypto_fp_ops[dev_id]; + qp = fp_ops->qp.data[qp_id]; + + if (fp_ops->qp_depth_used == NULL) { + rc = -ENOTSUP; + goto out; + } + + rc = fp_ops->qp_depth_used(qp); +out: + rte_cryptodev_trace_qp_depth_used(dev_id, qp_id); + return rc; +} #ifdef __cplusplus diff --git a/lib/cryptodev/rte_cryptodev_core.h b/lib/cryptodev/rte_cryptodev_core.h index 8d7e58d76d..9d68a026d9 100644 --- a/lib/cryptodev/rte_cryptodev_core.h +++ b/lib/cryptodev/rte_cryptodev_core.h @@ -24,6 +24,9 @@ typedef uint16_t (*enqueue_pkt_burst_t)(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops); /**< Enqueue packets for processing on queue pair of a device. */ +typedef uint32_t (*crypto_qp_depth_used_t)(void *qp); +/**< Get used descriptor depth in a queue pair of a device. */ + /** * @internal * Structure used to hold opaque pointers to internal ethdev Rx/Tx @@ -47,8 +50,10 @@ struct __rte_cache_aligned rte_crypto_fp_ops { dequeue_pkt_burst_t dequeue_burst; /** Internal queue pair data pointers. */ struct rte_cryptodev_qpdata qp; + /** Get the number of used queue pair descriptors. */ + crypto_qp_depth_used_t qp_depth_used; /** Reserved for future ops. */ - uintptr_t reserved[3]; + uintptr_t reserved[2]; }; extern struct rte_crypto_fp_ops rte_crypto_fp_ops[RTE_CRYPTO_MAX_DEVS]; diff --git a/lib/cryptodev/rte_cryptodev_trace_fp.h b/lib/cryptodev/rte_cryptodev_trace_fp.h index 9218997c14..dbfbc7b2e5 100644 --- a/lib/cryptodev/rte_cryptodev_trace_fp.h +++ b/lib/cryptodev/rte_cryptodev_trace_fp.h @@ -31,6 +31,13 @@ RTE_TRACE_POINT_FP( rte_trace_point_emit_u16(nb_ops); ) +RTE_TRACE_POINT_FP( + rte_cryptodev_trace_qp_depth_used, + RTE_TRACE_POINT_ARGS(uint8_t dev_id, uint16_t qp_id), + rte_trace_point_emit_u8(dev_id); + rte_trace_point_emit_u16(qp_id); +) + #ifdef __cplusplus } #endif From patchwork Thu Apr 11 08:22:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 139224 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9109A43E42; Thu, 11 Apr 2024 10:23:03 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D132640685; Thu, 11 Apr 2024 10:23:01 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3F170402EB for ; Thu, 11 Apr 2024 10:23:00 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 43AJ0hqB022602; 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Thu, 11 Apr 2024 01:22:53 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 11 Apr 2024 01:22:53 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 9BDD13F706A; Thu, 11 Apr 2024 01:22:47 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , , , , , , , , , , , , , Akhil Goyal Subject: [PATCH 2/3] crypto/cnxk: support queue pair depth API Date: Thu, 11 Apr 2024 13:52:31 +0530 Message-ID: <20240411082232.3495883-3-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240411082232.3495883-1-gakhil@marvell.com> References: <20240411082232.3495883-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: XooURyP6MUG-ockHge1M3AEwDZ6IwBhR X-Proofpoint-GUID: XooURyP6MUG-ockHge1M3AEwDZ6IwBhR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-11_02,2024-04-09_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added support to get the used queue pair depth for a specific queue on cn10k platform. Signed-off-by: Akhil Goyal --- drivers/crypto/cnxk/cn10k_cryptodev.c | 1 + drivers/crypto/cnxk/cn9k_cryptodev.c | 2 ++ drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 15 +++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 2 ++ 4 files changed, 20 insertions(+) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev.c b/drivers/crypto/cnxk/cn10k_cryptodev.c index 5ed918e18e..70bef13cda 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev.c @@ -99,6 +99,7 @@ cn10k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, dev->driver_id = cn10k_cryptodev_driver_id; dev->feature_flags = cnxk_cpt_default_ff_get(); + dev->qp_depth_used = cnxk_cpt_qp_depth_used; cn10k_cpt_set_enqdeq_fns(dev, vf); cn10k_sec_ops_override(); diff --git a/drivers/crypto/cnxk/cn9k_cryptodev.c b/drivers/crypto/cnxk/cn9k_cryptodev.c index 47b0874185..818458bd6f 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev.c +++ b/drivers/crypto/cnxk/cn9k_cryptodev.c @@ -15,6 +15,7 @@ #include "cn9k_ipsec.h" #include "cnxk_cryptodev.h" #include "cnxk_cryptodev_capabilities.h" +#include "cnxk_cryptodev_ops.h" #include "cnxk_cryptodev_sec.h" #include "roc_api.h" @@ -96,6 +97,7 @@ cn9k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, dev->dev_ops = &cn9k_cpt_ops; dev->driver_id = cn9k_cryptodev_driver_id; dev->feature_flags = cnxk_cpt_default_ff_get(); + dev->qp_depth_used = cnxk_cpt_qp_depth_used; cnxk_cpt_caps_populate(vf); diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 1dd1dbac9a..2af4318023 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -496,6 +496,21 @@ cnxk_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, return ret; } +uint32_t +cnxk_cpt_qp_depth_used(void *qptr) +{ + struct cnxk_cpt_qp *qp = qptr; + struct pending_queue *pend_q; + union cpt_fc_write_s fc; + + pend_q = &qp->pend_q; + + fc.u64[0] = rte_atomic_load_explicit(qp->lmtline.fc_addr, rte_memory_order_relaxed); + + return RTE_MAX(pending_queue_infl_cnt(pend_q->head, pend_q->tail, pend_q->pq_mask), + fc.s.qsize); +} + unsigned int cnxk_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused) { diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h index e7bba25cb8..708fad910d 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h @@ -142,6 +142,8 @@ int cnxk_ae_session_cfg(struct rte_cryptodev *dev, void cnxk_cpt_dump_on_err(struct cnxk_cpt_qp *qp); int cnxk_cpt_queue_pair_event_error_query(struct rte_cryptodev *dev, uint16_t qp_id); +uint32_t cnxk_cpt_qp_depth_used(void *qptr); + static __rte_always_inline void pending_queue_advance(uint64_t *index, const uint64_t mask) { From patchwork Thu Apr 11 08:22:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 139225 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 27EC743E42; Thu, 11 Apr 2024 10:23:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 76A3140697; Thu, 11 Apr 2024 10:23:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1E17140684 for ; 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Thu, 11 Apr 2024 01:23:00 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 11 Apr 2024 01:22:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 11 Apr 2024 01:22:59 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 9F8113F706A; Thu, 11 Apr 2024 01:22:53 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , , , , , , , , , , , , , Akhil Goyal Subject: [PATCH 3/3] test/crypto: add QP depth used count case Date: Thu, 11 Apr 2024 13:52:32 +0530 Message-ID: <20240411082232.3495883-4-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240411082232.3495883-1-gakhil@marvell.com> References: <20240411082232.3495883-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 8Q2rEa-XWcU7oxApQRdIKGFESoFydUl5 X-Proofpoint-ORIG-GUID: 8Q2rEa-XWcU7oxApQRdIKGFESoFydUl5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-11_02,2024-04-09_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added a test case to verify the new API rte_cryptodev_qp_depth_used() to get the used depth of a crypto device queue pair. Signed-off-by: Akhil Goyal --- app/test/test_cryptodev.c | 117 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c index 1703ebccf1..f2d249f6b8 100644 --- a/app/test/test_cryptodev.c +++ b/app/test/test_cryptodev.c @@ -2400,6 +2400,121 @@ static const uint8_t ms_hmac_digest2[] = { /* End Session 2 */ +#define MAX_OPS_PROCESSED (MAX_NUM_OPS_INFLIGHT - 1) +static int +test_queue_pair_descriptor_count(void) +{ + struct crypto_testsuite_params *ts_params = &testsuite_params; + struct crypto_unittest_params *ut_params = &unittest_params; + struct rte_crypto_op *ops_deq[MAX_OPS_PROCESSED] = { NULL }; + struct rte_crypto_op *ops[MAX_OPS_PROCESSED] = { NULL }; + struct rte_cryptodev_sym_capability_idx cap_idx; + int qp_depth = 0; + int i; + + RTE_VERIFY(gbl_action_type != RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO); + + /* Verify if the queue pair depth API is supported by driver */ + qp_depth = rte_cryptodev_qp_depth_used(ts_params->valid_devs[0], 0); + if (qp_depth == -ENOTSUP) + return TEST_SKIPPED; + + /* Verify the capabilities */ + cap_idx.type = RTE_CRYPTO_SYM_XFORM_AUTH; + cap_idx.algo.auth = RTE_CRYPTO_AUTH_SHA1_HMAC; + if (rte_cryptodev_sym_capability_get(ts_params->valid_devs[0], &cap_idx) == NULL) + return TEST_SKIPPED; + + cap_idx.type = RTE_CRYPTO_SYM_XFORM_CIPHER; + cap_idx.algo.cipher = RTE_CRYPTO_CIPHER_AES_CBC; + if (rte_cryptodev_sym_capability_get(ts_params->valid_devs[0], &cap_idx) == NULL) + return TEST_SKIPPED; + + /* Setup Cipher Parameters */ + ut_params->cipher_xform.type = RTE_CRYPTO_SYM_XFORM_CIPHER; + ut_params->cipher_xform.next = &ut_params->auth_xform; + ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_AES_CBC; + ut_params->cipher_xform.cipher.op = RTE_CRYPTO_CIPHER_OP_ENCRYPT; + ut_params->cipher_xform.cipher.key.data = aes_cbc_key; + ut_params->cipher_xform.cipher.key.length = CIPHER_KEY_LENGTH_AES_CBC; + ut_params->cipher_xform.cipher.iv.offset = IV_OFFSET; + ut_params->cipher_xform.cipher.iv.length = CIPHER_IV_LENGTH_AES_CBC; + + /* Setup HMAC Parameters */ + ut_params->auth_xform.type = RTE_CRYPTO_SYM_XFORM_AUTH; + ut_params->auth_xform.next = NULL; + ut_params->auth_xform.auth.op = RTE_CRYPTO_AUTH_OP_GENERATE; + ut_params->auth_xform.auth.algo = RTE_CRYPTO_AUTH_SHA1_HMAC; + ut_params->auth_xform.auth.key.length = HMAC_KEY_LENGTH_SHA1; + ut_params->auth_xform.auth.key.data = hmac_sha1_key; + ut_params->auth_xform.auth.digest_length = DIGEST_BYTE_LENGTH_SHA1; + + rte_errno = 0; + ut_params->sess = rte_cryptodev_sym_session_create(ts_params->valid_devs[0], + &ut_params->cipher_xform, ts_params->session_mpool); + if (rte_errno == ENOTSUP) + return TEST_SKIPPED; + + TEST_ASSERT_NOT_NULL(ut_params->sess, "Session creation failed"); + + TEST_ASSERT_EQUAL(rte_crypto_op_bulk_alloc(ts_params->op_mpool, + RTE_CRYPTO_OP_TYPE_SYMMETRIC, ops, MAX_OPS_PROCESSED), + MAX_OPS_PROCESSED, "failed to generate burst of crypto ops"); + + /* Generate crypto op data structure */ + for (i = 0; i < MAX_OPS_PROCESSED; i++) { + struct rte_mbuf *m; + uint8_t *digest; + + /* Generate test mbuf data and space for digest */ + m = setup_test_string(ts_params->mbuf_pool, catch_22_quote, QUOTE_512_BYTES, 0); + TEST_ASSERT_NOT_NULL(m, "Failed to allocate mbuf"); + + digest = (uint8_t *)rte_pktmbuf_append(m, DIGEST_BYTE_LENGTH_SHA1); + TEST_ASSERT_NOT_NULL(digest, "no room to append digest"); + + rte_crypto_op_attach_sym_session(ops[i], ut_params->sess); + + /* set crypto operation source mbuf */ + ops[i]->sym->m_src = m; + + /* Set crypto operation authentication parameters */ + ops[i]->sym->auth.digest.data = digest; + ops[i]->sym->auth.digest.phys_addr = rte_pktmbuf_iova_offset(m, QUOTE_512_BYTES); + + ops[i]->sym->auth.data.offset = 0; + ops[i]->sym->auth.data.length = QUOTE_512_BYTES; + + /* Copy IV at the end of the crypto operation */ + memcpy(rte_crypto_op_ctod_offset(ops[i], uint8_t *, IV_OFFSET), aes_cbc_iv, + CIPHER_IV_LENGTH_AES_CBC); + + /* Set crypto operation cipher parameters */ + ops[i]->sym->cipher.data.offset = 0; + ops[i]->sym->cipher.data.length = QUOTE_512_BYTES; + + TEST_ASSERT_EQUAL(rte_cryptodev_enqueue_burst(ts_params->valid_devs[0], 0, + &ops[i], 1), 1, "Error enqueuing"); + } + + for (i = 0; i < MAX_OPS_PROCESSED; i++) { + qp_depth = rte_cryptodev_qp_depth_used(ts_params->valid_devs[0], 0); + TEST_ASSERT_EQUAL(qp_depth, MAX_OPS_PROCESSED - i, + "Crypto queue pair depth used does not match with inflight ops"); + + while (rte_cryptodev_dequeue_burst(ts_params->valid_devs[0], 0, + &ops_deq[i], 1) == 0) + rte_pause(); + + TEST_ASSERT_EQUAL(ops_deq[i]->status, RTE_CRYPTO_OP_STATUS_SUCCESS, + "crypto op processing failed"); + + rte_pktmbuf_free(ops_deq[i]->sym->m_src); + rte_crypto_op_free(ops_deq[i]); + } + + return TEST_SUCCESS; +} static int test_AES_CBC_HMAC_SHA1_encrypt_digest(void) @@ -18068,6 +18183,8 @@ static struct unit_test_suite cryptodev_gen_testsuite = { test_queue_pair_descriptor_setup), TEST_CASE_ST(ut_setup, ut_teardown, test_device_configure_invalid_queue_pair_ids), + TEST_CASE_ST(ut_setup, ut_teardown, + test_queue_pair_descriptor_count), TEST_CASE_ST(ut_setup, ut_teardown, test_stats), TEST_CASE_ST(ut_setup, ut_teardown, test_enq_callback_setup), TEST_CASE_ST(ut_setup, ut_teardown, test_deq_callback_setup),