From patchwork Fri Mar 15 05:42:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 138413 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 61CFB43CA6; Fri, 15 Mar 2024 06:43:09 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B451642EB4; Fri, 15 Mar 2024 06:43:04 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7AC4A410FC for ; Fri, 15 Mar 2024 06:42:21 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42EMJhqw001277 for ; Thu, 14 Mar 2024 22:42:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=7JSvnPB0H3WkxjmMnSHOy7OOUi9298WXLFwlZLsZojg=; b=j8z hMyeD3fFXTI/0obIzR34SMsYa2hM9mucj15EFUchjJqkrTf4ocBOg1E+YDbW1HX4 9hwozeYBJJx0SI4O2nE2hez2BdGMTvbVUSSeyOslmR3glN/jVCeS7LgEDV+J6zXz RNKHPTMIk2u/l6eRZQ04aNLodPi96f9yadYFi3N2cw6ebbGmq4XaY7Fk43dO9PY4 62s684ALfLVp2qL3AplXeS/5BHs/AR8EwG7uV+cCUtyfN31CJ2UJX+B79YVKN9Qt nJkHgJ0Tc9M3DtZKJxfbbBmCQlq6L3beJTlHTVboTFYRfwbAWVX4OpvqboZah2MU /lz0aT6HCuHjqkR4JYg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wv9xa12h2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 14 Mar 2024 22:42:19 -0700 (PDT) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 22:42:19 -0700 Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 14 Mar 2024 22:42:19 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 22:42:19 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.193.69.194]) by maili.marvell.com (Postfix) with ESMTP id 06EB13F703F; Thu, 14 Mar 2024 22:42:16 -0700 (PDT) From: Vidya Sagar Velumuri To: Akhil Goyal CC: Jerin Jacob , , Aakash Sasidharan , Anoob Joseph Subject: [PATCH v3 1/8] crypto/cnxk: multi seg support block ciphers in tls Date: Fri, 15 Mar 2024 11:12:06 +0530 Message-ID: <20240315054213.540-2-vvelumuri@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240315054213.540-1-vvelumuri@marvell.com> References: <20240314131839.3362494-1-vvelumuri@marvell.com> <20240315054213.540-1-vvelumuri@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 5Rg-4KFD-AN3b8LG1P5u7fs9oZfCndeL X-Proofpoint-GUID: 5Rg-4KFD-AN3b8LG1P5u7fs9oZfCndeL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_13,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for Scatter-Gather mode for block ciphers in TLS-1.2 Signed-off-by: Vidya Sagar Velumuri --- drivers/crypto/cnxk/cn10k_cryptodev_sec.h | 3 +- drivers/crypto/cnxk/cn10k_tls.c | 5 +++ drivers/crypto/cnxk/cn10k_tls_ops.h | 48 ++++++++++++++++++----- 3 files changed, 45 insertions(+), 11 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h index 1efed3c4cf..881a0276cc 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h +++ b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h @@ -33,7 +33,8 @@ struct cn10k_sec_session { } ipsec; struct { uint8_t enable_padding : 1; - uint8_t rvsd : 7; + uint8_t tail_fetch_len : 2; + uint8_t rvsd : 5; bool is_write; } tls; }; diff --git a/drivers/crypto/cnxk/cn10k_tls.c b/drivers/crypto/cnxk/cn10k_tls.c index 879e0ea978..b46904d3f8 100644 --- a/drivers/crypto/cnxk/cn10k_tls.c +++ b/drivers/crypto/cnxk/cn10k_tls.c @@ -639,6 +639,11 @@ cn10k_tls_read_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, if ((sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_TLS_12) || (sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_DTLS_12)) { inst_w4.s.opcode_major = ROC_IE_OT_TLS_MAJOR_OP_RECORD_DEC | ROC_IE_OT_INPLACE_BIT; + sec_sess->tls.tail_fetch_len = 0; + if (sa_dptr->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_3DES) + sec_sess->tls.tail_fetch_len = 1; + else if (sa_dptr->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_AES_CBC) + sec_sess->tls.tail_fetch_len = 2; } else if (sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_TLS_13) { inst_w4.s.opcode_major = ROC_IE_OT_TLS13_MAJOR_OP_RECORD_DEC | ROC_IE_OT_INPLACE_BIT; diff --git a/drivers/crypto/cnxk/cn10k_tls_ops.h b/drivers/crypto/cnxk/cn10k_tls_ops.h index 7c8ac14ab2..6fd74927ee 100644 --- a/drivers/crypto/cnxk/cn10k_tls_ops.h +++ b/drivers/crypto/cnxk/cn10k_tls_ops.h @@ -234,7 +234,10 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, inst->w4.u64 = w4.u64; } else if (is_sg_ver2 == false) { struct roc_sglist_comp *scatter_comp, *gather_comp; + int tail_len = sess->tls.tail_fetch_len * 16; + int pkt_len = rte_pktmbuf_pkt_len(m_src); uint32_t g_size_bytes, s_size_bytes; + uint16_t *sg_hdr; uint32_t dlen; int i; @@ -244,16 +247,25 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, return -ENOMEM; } - in_buffer = (uint8_t *)m_data; - ((uint16_t *)in_buffer)[0] = 0; - ((uint16_t *)in_buffer)[1] = 0; - /* Input Gather List */ + in_buffer = (uint8_t *)m_data; + sg_hdr = (uint16_t *)(in_buffer + 32); + gather_comp = (struct roc_sglist_comp *)((uint8_t *)sg_hdr + 8); i = 0; - gather_comp = (struct roc_sglist_comp *)((uint8_t *)in_buffer + 8); + /* Add the last blocks as first gather component for tail fetch. */ + if (tail_len) { + const uint8_t *output; + + output = rte_pktmbuf_read(m_src, pkt_len - tail_len, tail_len, in_buffer); + if (output != in_buffer) + rte_memcpy(in_buffer, output, tail_len); + i = fill_sg_comp(gather_comp, i, (uint64_t)in_buffer, tail_len); + } + sg_hdr[0] = 0; + sg_hdr[1] = 0; i = fill_sg_comp_from_pkt(gather_comp, i, m_src); - ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + sg_hdr[2] = rte_cpu_to_be_16(i); g_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp); @@ -261,7 +273,7 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, scatter_comp = (struct roc_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes); i = fill_sg_comp_from_pkt(scatter_comp, i, m_src); - ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + sg_hdr[3] = rte_cpu_to_be_16(i); s_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp); @@ -273,10 +285,12 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, w4.u64 = sess->inst.w4; w4.s.dlen = dlen; w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG; - w4.s.param1 = rte_pktmbuf_pkt_len(m_src); + w4.s.param1 = pkt_len; inst->w4.u64 = w4.u64; } else { struct roc_sg2list_comp *scatter_comp, *gather_comp; + int tail_len = sess->tls.tail_fetch_len * 16; + int pkt_len = rte_pktmbuf_pkt_len(m_src); union cpt_inst_w5 cpt_inst_w5; union cpt_inst_w6 cpt_inst_w6; uint32_t g_size_bytes; @@ -292,7 +306,21 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, /* Input Gather List */ i = 0; - gather_comp = (struct roc_sg2list_comp *)((uint8_t *)in_buffer); + /* First 32 bytes in m_data are rsvd for tail fetch. + * SG list start from 32 byte onwards. + */ + gather_comp = (struct roc_sg2list_comp *)((uint8_t *)(in_buffer + 32)); + + /* Add the last blocks as first gather component for tail fetch. */ + if (tail_len) { + const uint8_t *output; + + output = rte_pktmbuf_read(m_src, pkt_len - tail_len, tail_len, in_buffer); + if (output != in_buffer) + rte_memcpy(in_buffer, output, tail_len); + i = fill_sg2_comp(gather_comp, i, (uint64_t)in_buffer, tail_len); + } + i = fill_sg2_comp_from_pkt(gather_comp, i, m_src); cpt_inst_w5.s.gather_sz = ((i + 2) / 3); @@ -311,7 +339,7 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, inst->w5.u64 = cpt_inst_w5.u64; inst->w6.u64 = cpt_inst_w6.u64; w4.u64 = sess->inst.w4; - w4.s.dlen = rte_pktmbuf_pkt_len(m_src); + w4.s.dlen = pkt_len + tail_len; w4.s.param1 = w4.s.dlen; w4.s.opcode_major &= (~(ROC_IE_OT_INPLACE_BIT)); inst->w4.u64 = w4.u64; From patchwork Fri Mar 15 05:42:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 138414 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B4BF843CA6; Fri, 15 Mar 2024 06:43:15 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C60E942EBB; Fri, 15 Mar 2024 06:43:05 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 76AA1410FC for ; Fri, 15 Mar 2024 06:42:23 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42F0ahnB019063 for ; Thu, 14 Mar 2024 22:42:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=Zv5cvllg8EZNEww++ZIOPHD3RjU6K5Wt9AZ7YKGn3mU=; b=eS7 4rgri+kck7bFgSCuDxco5W8zSutZhLKTc7CDjB2/suDu/cKZtTgTbnD3IldWvP01 MzfhGT7eOkKuu8mq9QCINnZax3IWSN94HwEHp8/40vwYJA8mg0+U1eEnGhOeskEJ EQV5VWJ8Zq3FFiqKrUUrkJ3eeRpCPvXpeBq7bRFkDV3K7PA6LwZSvtLZ+HgIKyps o3xMlCAAAggu5dnV4S10Q3Uk1B/+h8qPGLQvmZGuWjT77mPtoVSXtuFKrSHJtrYQ 5vGXvmGHXPCiHOMdySY9tpN+Tbep+rD0TuOYB8HAdAgv9Z6Zn10FJnH0n+E8jXbG c4gecL8DPdgk8o4EWAA== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3wvbxbrpfy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 14 Mar 2024 22:42:22 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 22:42:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 22:42:21 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.193.69.194]) by maili.marvell.com (Postfix) with ESMTP id 9D5603F703F; Thu, 14 Mar 2024 22:42:19 -0700 (PDT) From: Vidya Sagar Velumuri To: Akhil Goyal CC: Jerin Jacob , , Aakash Sasidharan , Anoob Joseph Subject: [PATCH v3 2/8] crypto/cnxk: enable sha384 and chachapoly for tls Date: Fri, 15 Mar 2024 11:12:07 +0530 Message-ID: <20240315054213.540-3-vvelumuri@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240315054213.540-1-vvelumuri@marvell.com> References: <20240314131839.3362494-1-vvelumuri@marvell.com> <20240315054213.540-1-vvelumuri@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: wSPUpRls2VOJnCkvJX1T7xXsckhgZB-2 X-Proofpoint-ORIG-GUID: wSPUpRls2VOJnCkvJX1T7xXsckhgZB-2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_13,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable SHA384-HMAC support for TLS & DTLS 1.2. Enable CHACHA20-POLY1305 support for TLS-1.3. Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_ie_ot_tls.h | 1 + drivers/crypto/cnxk/cn10k_tls.c | 56 +++++++++++++------ drivers/crypto/cnxk/cnxk_cryptodev.h | 6 +- .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 52 +++++++++++++++++ 4 files changed, 95 insertions(+), 20 deletions(-) diff --git a/drivers/common/cnxk/roc_ie_ot_tls.h b/drivers/common/cnxk/roc_ie_ot_tls.h index b85d075e86..39c42775f4 100644 --- a/drivers/common/cnxk/roc_ie_ot_tls.h +++ b/drivers/common/cnxk/roc_ie_ot_tls.h @@ -39,6 +39,7 @@ enum roc_ie_ot_tls_cipher_type { ROC_IE_OT_TLS_CIPHER_AES_CBC = 3, ROC_IE_OT_TLS_CIPHER_AES_GCM = 7, ROC_IE_OT_TLS_CIPHER_AES_CCM = 10, + ROC_IE_OT_TLS_CIPHER_CHACHA_POLY = 9, }; enum roc_ie_ot_tls_ver { diff --git a/drivers/crypto/cnxk/cn10k_tls.c b/drivers/crypto/cnxk/cn10k_tls.c index b46904d3f8..c95fcfdfa7 100644 --- a/drivers/crypto/cnxk/cn10k_tls.c +++ b/drivers/crypto/cnxk/cn10k_tls.c @@ -28,7 +28,8 @@ tls_xform_cipher_auth_verify(struct rte_crypto_sym_xform *cipher_xform, switch (c_algo) { case RTE_CRYPTO_CIPHER_NULL: if ((a_algo == RTE_CRYPTO_AUTH_MD5_HMAC) || (a_algo == RTE_CRYPTO_AUTH_SHA1_HMAC) || - (a_algo == RTE_CRYPTO_AUTH_SHA256_HMAC)) + (a_algo == RTE_CRYPTO_AUTH_SHA256_HMAC) || + (a_algo == RTE_CRYPTO_AUTH_SHA384_HMAC)) ret = 0; break; case RTE_CRYPTO_CIPHER_3DES_CBC: @@ -37,7 +38,8 @@ tls_xform_cipher_auth_verify(struct rte_crypto_sym_xform *cipher_xform, break; case RTE_CRYPTO_CIPHER_AES_CBC: if ((a_algo == RTE_CRYPTO_AUTH_SHA1_HMAC) || - (a_algo == RTE_CRYPTO_AUTH_SHA256_HMAC)) + (a_algo == RTE_CRYPTO_AUTH_SHA256_HMAC) || + (a_algo == RTE_CRYPTO_AUTH_SHA384_HMAC)) ret = 0; break; default: @@ -69,7 +71,8 @@ tls_xform_auth_verify(struct rte_crypto_sym_xform *crypto_xform) if (((a_algo == RTE_CRYPTO_AUTH_MD5_HMAC) && (keylen == 16)) || ((a_algo == RTE_CRYPTO_AUTH_SHA1_HMAC) && (keylen == 20)) || - ((a_algo == RTE_CRYPTO_AUTH_SHA256_HMAC) && (keylen == 32))) + ((a_algo == RTE_CRYPTO_AUTH_SHA256_HMAC) && (keylen == 32)) || + ((a_algo == RTE_CRYPTO_AUTH_SHA384_HMAC) && (keylen == 48))) return 0; return -EINVAL; @@ -94,6 +97,9 @@ tls_xform_aead_verify(struct rte_security_tls_record_xform *tls_xform, return 0; } + if ((crypto_xform->aead.algo == RTE_CRYPTO_AEAD_CHACHA20_POLY1305) && (keylen == 32)) + return 0; + return -EINVAL; } @@ -251,6 +257,9 @@ tls_write_rlens_get(struct rte_security_tls_record_xform *tls_xfrm, case RTE_CRYPTO_AUTH_SHA256_HMAC: mac_len = 32; break; + case RTE_CRYPTO_AUTH_SHA384_HMAC: + mac_len = 32; + break; default: mac_len = 0; break; @@ -339,15 +348,20 @@ tls_read_sa_fill(struct roc_ie_ot_tls_read_sa *read_sa, cipher_key = read_sa->cipher_key; /* Set encryption algorithm */ - if ((crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) && - (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)) { - read_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_AES_GCM; - + if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) { length = crypto_xfrm->aead.key.length; - if (length == 16) - read_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_128; - else + if (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_AES_GCM) { + read_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_AES_GCM; + if (length == 16) + read_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_128; + else + read_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_256; + } + + if (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_CHACHA20_POLY1305) { + read_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_CHACHA_POLY; read_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_256; + } key = crypto_xfrm->aead.key.data; memcpy(cipher_key, key, length); @@ -397,6 +411,8 @@ tls_read_sa_fill(struct roc_ie_ot_tls_read_sa *read_sa, read_sa->w2.s.mac_select = ROC_IE_OT_TLS_MAC_SHA1; else if (auth_xfrm->auth.algo == RTE_CRYPTO_AUTH_SHA256_HMAC) read_sa->w2.s.mac_select = ROC_IE_OT_TLS_MAC_SHA2_256; + else if (auth_xfrm->auth.algo == RTE_CRYPTO_AUTH_SHA384_HMAC) + read_sa->w2.s.mac_select = ROC_IE_OT_TLS_MAC_SHA2_384; else return -EINVAL; @@ -476,15 +492,19 @@ tls_write_sa_fill(struct roc_ie_ot_tls_write_sa *write_sa, cipher_key = write_sa->cipher_key; /* Set encryption algorithm */ - if ((crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) && - (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)) { - write_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_AES_GCM; - + if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) { length = crypto_xfrm->aead.key.length; - if (length == 16) - write_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_128; - else + if (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_AES_GCM) { + write_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_AES_GCM; + if (length == 16) + write_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_128; + else + write_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_256; + } + if (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_CHACHA20_POLY1305) { + write_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_CHACHA_POLY; write_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_256; + } key = crypto_xfrm->aead.key.data; memcpy(cipher_key, key, length); @@ -538,6 +558,8 @@ tls_write_sa_fill(struct roc_ie_ot_tls_write_sa *write_sa, write_sa->w2.s.mac_select = ROC_IE_OT_TLS_MAC_SHA1; else if (auth_xfrm->auth.algo == RTE_CRYPTO_AUTH_SHA256_HMAC) write_sa->w2.s.mac_select = ROC_IE_OT_TLS_MAC_SHA2_256; + else if (auth_xfrm->auth.algo == RTE_CRYPTO_AUTH_SHA384_HMAC) + write_sa->w2.s.mac_select = ROC_IE_OT_TLS_MAC_SHA2_384; else return -EINVAL; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h index 45d01b94b3..fffc4a47b4 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev.h @@ -13,9 +13,9 @@ #define CNXK_CPT_MAX_CAPS 55 #define CNXK_SEC_IPSEC_CRYPTO_MAX_CAPS 16 -#define CNXK_SEC_TLS_1_3_CRYPTO_MAX_CAPS 2 -#define CNXK_SEC_TLS_1_2_CRYPTO_MAX_CAPS 6 -#define CNXK_SEC_MAX_CAPS 17 +#define CNXK_SEC_TLS_1_3_CRYPTO_MAX_CAPS 3 +#define CNXK_SEC_TLS_1_2_CRYPTO_MAX_CAPS 7 +#define CNXK_SEC_MAX_CAPS 19 /** * Device private data diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c index db50de5d58..0d5d64b6e7 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c @@ -1639,6 +1639,27 @@ static const struct rte_cryptodev_capabilities sec_tls12_caps_sha1_sha2[] = { }, } }, } }, + { /* SHA384 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA384_HMAC, + .block_size = 64, + .key_size = { + .min = 48, + .max = 48, + .increment = 0 + }, + .digest_size = { + .min = 48, + .max = 48, + .increment = 0 + }, + }, } + }, } + }, + }; static const struct rte_cryptodev_capabilities sec_tls13_caps_aes[] = { @@ -1672,6 +1693,37 @@ static const struct rte_cryptodev_capabilities sec_tls13_caps_aes[] = { }, } }, } }, + { /* CHACHA POLY */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD, + {.aead = { + .algo = RTE_CRYPTO_AEAD_CHACHA20_POLY1305, + .block_size = 64, + .key_size = { + .min = 32, + .max = 32, + .increment = 0 + }, + .digest_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .aad_size = { + .min = 5, + .max = 5, + .increment = 0 + }, + .iv_size = { + .min = 0, + .max = 0, + .increment = 0 + } + }, } + }, } + }, + }; From patchwork Fri Mar 15 05:42:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 138415 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 471DC43CA6; Fri, 15 Mar 2024 06:43:22 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0B9D742EB3; Fri, 15 Mar 2024 06:43:07 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 90336410FC for ; Fri, 15 Mar 2024 06:42:26 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42F0aS23018658 for ; Thu, 14 Mar 2024 22:42:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=fWb8Oj1kmLLTnjOjeDot5qrkZFKKfqT5aPjKO7EC8co=; b=i9e igfUAzkmGakmXKb+dKcLmzguWuLwoaetWNTWYV9O1+C1e1SvtMNcZ1hDSzrF7+Wq Vz6rixnK3/wQCjgNUcbbIO8b0ffm8NR5zNCVlI4Rf6XL5etil/dBJYwZzvaW3wVK KrAa9CSCrBhD22qbdBpBHivv+D54rUbGYIXlCKlR2kI5Sk8xkAE99qpJtYGQ/Dqm MAJ4ujh1FykPXsfaodNouAWZlpVmusMJt+MxhavXL7i5WajkzybNP2kQNoFm5b45 0Y0Pib6nQD7AcAisJJ3Z214T0TZ2uGvAu33m5FusonSK+TQ2TQTjhOS4SXs6dF4B A2V7q64V6ahDRvd1Lsw== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3wvbxbrpg2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 14 Mar 2024 22:42:25 -0700 (PDT) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 22:42:24 -0700 Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 14 Mar 2024 22:42:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 22:42:24 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.193.69.194]) by maili.marvell.com (Postfix) with ESMTP id 3E97D3F703F; Thu, 14 Mar 2024 22:42:21 -0700 (PDT) From: Vidya Sagar Velumuri To: Akhil Goyal CC: Jerin Jacob , , Aakash Sasidharan , Anoob Joseph Subject: [PATCH v3 3/8] crypto/cnxk: add support for session update for TLS Date: Fri, 15 Mar 2024 11:12:08 +0530 Message-ID: <20240315054213.540-4-vvelumuri@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240315054213.540-1-vvelumuri@marvell.com> References: <20240314131839.3362494-1-vvelumuri@marvell.com> <20240315054213.540-1-vvelumuri@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: MUKSkbqS2MVc3o-zwwn0FUkbE-k6v4Gg X-Proofpoint-ORIG-GUID: MUKSkbqS2MVc3o-zwwn0FUkbE-k6v4Gg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_13,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add session update support for TLS Signed-off-by: Vidya Sagar Velumuri --- drivers/crypto/cnxk/cn10k_cryptodev_sec.c | 3 +++ drivers/crypto/cnxk/cn10k_tls.c | 17 +++++++++++++++++ drivers/crypto/cnxk/cn10k_tls.h | 4 ++++ 3 files changed, 24 insertions(+) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_sec.c b/drivers/crypto/cnxk/cn10k_cryptodev_sec.c index cb013986c4..775104b765 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_sec.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_sec.c @@ -116,6 +116,9 @@ cn10k_sec_session_update(void *dev, struct rte_security_session *sec_sess, if (cn10k_sec_sess->proto == RTE_SECURITY_PROTOCOL_IPSEC) return cn10k_ipsec_session_update(vf, qp, cn10k_sec_sess, conf); + if (conf->protocol == RTE_SECURITY_PROTOCOL_TLS_RECORD) + return cn10k_tls_record_session_update(vf, qp, cn10k_sec_sess, conf); + return -ENOTSUP; } diff --git a/drivers/crypto/cnxk/cn10k_tls.c b/drivers/crypto/cnxk/cn10k_tls.c index c95fcfdfa7..11279dac46 100644 --- a/drivers/crypto/cnxk/cn10k_tls.c +++ b/drivers/crypto/cnxk/cn10k_tls.c @@ -781,6 +781,23 @@ cn10k_tls_write_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, return ret; } +int +cn10k_tls_record_session_update(struct cnxk_cpt_vf *vf, struct cnxk_cpt_qp *qp, + struct cn10k_sec_session *sess, + struct rte_security_session_conf *conf) +{ + struct roc_cpt *roc_cpt; + int ret; + + if (conf->tls_record.type == RTE_SECURITY_TLS_SESS_TYPE_READ) + return -ENOTSUP; + + roc_cpt = &vf->cpt; + ret = cn10k_tls_write_sa_create(roc_cpt, &qp->lf, &conf->tls_record, conf->crypto_xform, + (struct cn10k_sec_session *)sess); + return ret; +} + int cn10k_tls_record_session_create(struct cnxk_cpt_vf *vf, struct cnxk_cpt_qp *qp, struct rte_security_tls_record_xform *tls_xfrm, diff --git a/drivers/crypto/cnxk/cn10k_tls.h b/drivers/crypto/cnxk/cn10k_tls.h index 19772655da..9635bdd4c9 100644 --- a/drivers/crypto/cnxk/cn10k_tls.h +++ b/drivers/crypto/cnxk/cn10k_tls.h @@ -25,6 +25,10 @@ struct cn10k_tls_record { }; } __rte_aligned(ROC_ALIGN); +int cn10k_tls_record_session_update(struct cnxk_cpt_vf *vf, struct cnxk_cpt_qp *qp, + struct cn10k_sec_session *sess, + struct rte_security_session_conf *conf); + int cn10k_tls_record_session_create(struct cnxk_cpt_vf *vf, struct cnxk_cpt_qp *qp, struct rte_security_tls_record_xform *tls_xfrm, struct rte_crypto_sym_xform *crypto_xfrm, From patchwork Fri Mar 15 05:42:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 138416 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9BA7643CA6; Fri, 15 Mar 2024 06:43:31 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AFD7F42ED0; Fri, 15 Mar 2024 06:43:13 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3ACF6410FC for ; Fri, 15 Mar 2024 06:42:29 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42EMJOr1032321 for ; Thu, 14 Mar 2024 22:42:28 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=SqBBJXvWJDUBiRPegMFST9LtVd+H9gcji1w5LepsODQ=; b=cil XnT+6wLHN++xoShmkPq+ZIhvtS7C74ZuhvNVtiEQYy48Mg7aOV8KXt1wB+7LRS4R L9bcvlh+CCUlGn9WIsCy6TMdT1KHVRZMgOjl3Fgzm60SCtp3AHTjG1WtUTBJeI5W 2TJfGEuJavSkU0NTXkrD9KUm5tmgEICOC9ySMMjHo3UYd8LxfcUGO5wC8dF7mXp8 Sna6GKmqhI6hdLp8Fd6LVLq0pjwNeWRuX49dxCPLuPkhbjodrhzWBJYWYdBveKvW kEipM28Lzcb9IogwYnuXWhwJU4K88oBliY8a4RDh0IlcHTGxGu64zwha3cRCAB9C UvQXgGOKevFxgYBMZAw== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wv9xa12ha-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 14 Mar 2024 22:42:28 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 22:42:27 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 22:42:27 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.193.69.194]) by maili.marvell.com (Postfix) with ESMTP id D31D23F704D; Thu, 14 Mar 2024 22:42:24 -0700 (PDT) From: Vidya Sagar Velumuri To: Akhil Goyal CC: Anoob Joseph , Jerin Jacob , , Aakash Sasidharan Subject: [PATCH v3 4/8] crypto/cnxk: avoid branches in datapath Date: Fri, 15 Mar 2024 11:12:09 +0530 Message-ID: <20240315054213.540-5-vvelumuri@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240315054213.540-1-vvelumuri@marvell.com> References: <20240314131839.3362494-1-vvelumuri@marvell.com> <20240315054213.540-1-vvelumuri@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: EI2wwOVhvP75lZd69zRNphbKHfpHiZ7U X-Proofpoint-GUID: EI2wwOVhvP75lZd69zRNphbKHfpHiZ7U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_13,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph Avoid branches in datapath. Signed-off-by: Anoob Joseph --- drivers/crypto/cnxk/cn10k_ipsec_la_ops.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h index a30b8e413d..4e95fbb6eb 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h +++ b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h @@ -73,12 +73,10 @@ process_outb_sa(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k_s roc_cpt_lf_ctx_reload(lf, &sess->sa.out_sa); rte_delay_ms(1); #endif + const uint64_t ol_flags = m_src->ol_flags; - if (m_src->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) - inst_w4_u64 &= ~BIT_ULL(33); - - if (m_src->ol_flags & RTE_MBUF_F_TX_L4_MASK) - inst_w4_u64 &= ~BIT_ULL(32); + inst_w4_u64 &= ~(((uint64_t)(!!(ol_flags & RTE_MBUF_F_TX_IP_CKSUM)) << 33) | + ((uint64_t)(!!(ol_flags & RTE_MBUF_F_TX_L4_MASK)) << 32)); if (likely(m_src->next == NULL)) { if (unlikely(rte_pktmbuf_tailroom(m_src) < sess->max_extended_len)) { From patchwork Fri Mar 15 05:42:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 138417 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A0B1243CA6; Fri, 15 Mar 2024 06:43:38 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3754342ECB; Fri, 15 Mar 2024 06:43:15 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 1CE9E410FC for ; Fri, 15 Mar 2024 06:42:31 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42F0aS24018658 for ; Thu, 14 Mar 2024 22:42:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=pnRqFUugNY9z/K+q6dpb9JUYgBPHBjAENHt+JA+Bo5M=; b=fMb vC90EQUmb/8nlxopmpLoaYOxmffg5lh2O5AZS4c/MRjgWiPujWpJjvuohaeAAPAi 0Mc12oHS4NhC9bf6d/TNFO7x6tO8n8aYzY8SvJ+cd0Efj9I1fx+cIDBaOjp37FfY btgf1h6AVCnl9o9E9Y7upNFr1J7NNaH85isdNUNnYvdA9wDMIq7Zqor+L3uvqQPF Wbz4kei0hPqZTHXQv4rPTuiRDPDKvgNKNRFoBmt19SfnYDZC6KeTZ4Yy0Gm/GGbi QzeS1wBv/A23kWaHJCOmc7m65g3MrQwypbYG7VpZFHvpy7NdVmQxgohTHWXFk35P dF00z9zroGonyd0G2vA== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3wvbxbrpg6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 14 Mar 2024 22:42:30 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 22:42:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 22:42:29 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.193.69.194]) by maili.marvell.com (Postfix) with ESMTP id 7B4A85B6939; Thu, 14 Mar 2024 22:42:27 -0700 (PDT) From: Vidya Sagar Velumuri To: Akhil Goyal CC: Anoob Joseph , Jerin Jacob , , Aakash Sasidharan Subject: [PATCH v3 5/8] crypto/cnxk: move metadata to second cacheline Date: Fri, 15 Mar 2024 11:12:10 +0530 Message-ID: <20240315054213.540-6-vvelumuri@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240315054213.540-1-vvelumuri@marvell.com> References: <20240314131839.3362494-1-vvelumuri@marvell.com> <20240315054213.540-1-vvelumuri@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: TV3oDokyhsuzSM3IHWsJ_n4G7ci3aKk1 X-Proofpoint-ORIG-GUID: TV3oDokyhsuzSM3IHWsJ_n4G7ci3aKk1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_13,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph In security session, move PMD metadata to second cacheline. Also optimize the fields to minimize the memory usage. Signed-off-by: Anoob Joseph Signed-off-by: Vidya Sagar Velumuri --- drivers/crypto/cnxk/cn10k_cryptodev_sec.h | 10 ++++++---- drivers/crypto/cnxk/cn10k_ipsec.c | 4 ++-- drivers/crypto/cnxk/cn10k_tls.c | 2 +- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h index 881a0276cc..230c0f7c1c 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h +++ b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h @@ -5,6 +5,7 @@ #ifndef __CN10K_CRYPTODEV_SEC_H__ #define __CN10K_CRYPTODEV_SEC_H__ +#include #include #include "roc_constants.h" @@ -19,23 +20,24 @@ struct cn10k_sec_session { uint8_t rte_sess[SEC_SESS_SIZE]; /** PMD private space */ + RTE_MARKER cacheline1 __rte_cache_aligned; - enum rte_security_session_protocol proto; /** Pre-populated CPT inst words */ struct cnxk_cpt_inst_tmpl inst; uint16_t max_extended_len; uint16_t iv_offset; + uint8_t proto; uint8_t iv_length; union { struct { uint8_t ip_csum; - bool is_outbound; + uint8_t is_outbound : 1; } ipsec; struct { uint8_t enable_padding : 1; uint8_t tail_fetch_len : 2; - uint8_t rvsd : 5; - bool is_write; + uint8_t is_write : 1; + uint8_t rvsd : 4; } tls; }; /** Queue pair */ diff --git a/drivers/crypto/cnxk/cn10k_ipsec.c b/drivers/crypto/cnxk/cn10k_ipsec.c index 74d6cd70d1..ef5f0ff4aa 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec.c +++ b/drivers/crypto/cnxk/cn10k_ipsec.c @@ -76,7 +76,7 @@ cn10k_ipsec_outb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, } #endif - sec_sess->ipsec.is_outbound = true; + sec_sess->ipsec.is_outbound = 1; /* Get Rlen calculation data */ ret = cnxk_ipsec_outb_rlens_get(&rlens, ipsec_xfrm, crypto_xfrm); @@ -177,7 +177,7 @@ cn10k_ipsec_inb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, goto sa_dptr_free; } - sec_sess->ipsec.is_outbound = false; + sec_sess->ipsec.is_outbound = 0; sec_sess->inst.w7 = cpt_inst_w7_get(roc_cpt, in_sa); /* Save index/SPI in cookie, specific required for Rx Inject */ diff --git a/drivers/crypto/cnxk/cn10k_tls.c b/drivers/crypto/cnxk/cn10k_tls.c index 11279dac46..ae3ed3176c 100644 --- a/drivers/crypto/cnxk/cn10k_tls.c +++ b/drivers/crypto/cnxk/cn10k_tls.c @@ -739,7 +739,7 @@ cn10k_tls_write_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, sec_sess->iv_length = crypto_xfrm->next->cipher.iv.length; } - sec_sess->tls.is_write = true; + sec_sess->tls.is_write = 1; sec_sess->tls.enable_padding = tls_xfrm->options.extra_padding_enable; sec_sess->max_extended_len = tls_write_rlens_get(tls_xfrm, crypto_xfrm); sec_sess->proto = RTE_SECURITY_PROTOCOL_TLS_RECORD; From patchwork Fri Mar 15 05:42:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 138418 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8850643CA6; Fri, 15 Mar 2024 06:43:45 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BF95942EDD; Fri, 15 Mar 2024 06:43:16 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 8C607410FC for ; Fri, 15 Mar 2024 06:42:34 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42EMJNY6032193 for ; Thu, 14 Mar 2024 22:42:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=9zbvW3ogQ/si8/97KBPZhIsl8DfHaFYjMlchAa4hvGE=; b=JDg FW/J6LVGZ9VmARSusd6JLy6wag5BoB0QJVPt5fNI/Muq2xcstRfuBlcDi1yqDwlF wJW04dx1FXMqU1XtIAeJ/j812IAkNpA/dJR/M3Y7ONxOmf89+qK74SeUeZsLVuAH 9PuzSbVhZTa1V0QeVbbjI/Ysdv3WPCbLFXBPRt+zly1EURDt/0RGcp2imEF34/S+ kGeYlVdkayL9lB8//WQGE5lUjg+DqoDYMdumGQH7Sgo0pFDHqLDfAxMnjTRa0KSL hHbAnrq5MK3hlzP7xiDroPoNe5cOtWEWMDODu2MCLFWSwn+iKzKv/FQ6J3sLzUsy TdvT0tycetDeLnYYNfQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wv9xa12he-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 14 Mar 2024 22:42:33 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 22:42:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 22:42:32 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.193.69.194]) by maili.marvell.com (Postfix) with ESMTP id 1D2E23F704A; Thu, 14 Mar 2024 22:42:29 -0700 (PDT) From: Vidya Sagar Velumuri To: Akhil Goyal CC: Jerin Jacob , , Aakash Sasidharan , Anoob Joseph Subject: [PATCH v3 6/8] crypto/cnxk: add support for padding verification in TLS Date: Fri, 15 Mar 2024 11:12:11 +0530 Message-ID: <20240315054213.540-7-vvelumuri@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240315054213.540-1-vvelumuri@marvell.com> References: <20240314131839.3362494-1-vvelumuri@marvell.com> <20240315054213.540-1-vvelumuri@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: hFs2DmFwi0FmcXRUjYLeOEq0EgTPb_AJ X-Proofpoint-GUID: hFs2DmFwi0FmcXRUjYLeOEq0EgTPb_AJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_13,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For TLS-1.2: - Verify that the padding bytes are having pad len as the value. - Report error in case of discrepancies. - Trim the padding and MAC from the tls-1.2 records For TLS-1.3: - Find the content type as the last non-zero byte in the record. - Return the content type as the inner content type. Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_se.h | 1 + drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 151 +++++++++++++++++++++- drivers/crypto/cnxk/cn10k_cryptodev_sec.h | 17 ++- drivers/crypto/cnxk/cn10k_tls.c | 65 +++++++--- drivers/crypto/cnxk/cn10k_tls_ops.h | 19 ++- 5 files changed, 215 insertions(+), 38 deletions(-) diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h index ddcf6bdb44..50741a0b81 100644 --- a/drivers/common/cnxk/roc_se.h +++ b/drivers/common/cnxk/roc_se.h @@ -169,6 +169,7 @@ typedef enum { ROC_SE_ERR_SSL_CIPHER_UNSUPPORTED = 0x84, ROC_SE_ERR_SSL_MAC_UNSUPPORTED = 0x85, ROC_SE_ERR_SSL_VERSION_UNSUPPORTED = 0x86, + ROC_SE_ERR_SSL_POST_PROCESS = 0x88, ROC_SE_ERR_SSL_MAC_MISMATCH = 0x89, ROC_SE_ERR_SSL_PKT_REPLAY_SEQ_OUT_OF_WINDOW = 0xC1, ROC_SE_ERR_SSL_PKT_REPLAY_SEQ = 0xC9, diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 8991150c05..720b756001 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -207,7 +207,7 @@ cpt_sec_tls_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, struct cn10k_sec_session *sess, struct cpt_inst_s *inst, struct cpt_inflight_req *infl_req, const bool is_sg_ver2) { - if (sess->tls.is_write) + if (sess->tls_opt.is_write) return process_tls_write(&qp->lf, op, sess, &qp->meta_info, infl_req, inst, is_sg_ver2); else @@ -989,20 +989,161 @@ cn10k_cpt_ipsec_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s * } static inline void -cn10k_cpt_tls_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *res) +cn10k_cpt_tls12_trim_mac(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *res, uint8_t mac_len) { + struct rte_mbuf *mac_prev_seg = NULL, *mac_seg = NULL, *seg; + uint32_t pad_len, trim_len, mac_offset, pad_offset; struct rte_mbuf *mbuf = cop->sym->m_src; - const uint16_t m_len = res->rlen; + uint16_t m_len = res->rlen; + uint32_t i, nb_segs = 1; + uint8_t pad_res = 0; + uint8_t pad_val; + + pad_val = ((res->spi >> 16) & 0xff); + pad_len = pad_val + 1; + trim_len = pad_len + mac_len; + mac_offset = m_len - trim_len; + pad_offset = mac_offset + mac_len; + + /* Handle Direct Mode */ + if (mbuf->next == NULL) { + uint8_t *ptr = rte_pktmbuf_mtod_offset(mbuf, uint8_t *, pad_offset); + + for (i = 0; i < pad_len; i++) + pad_res |= ptr[i] ^ pad_val; + + if (pad_res) { + cop->status = RTE_CRYPTO_OP_STATUS_ERROR; + cop->aux_flags = res->uc_compcode; + } + mbuf->pkt_len = m_len - trim_len; + mbuf->data_len = m_len - trim_len; + + return; + } + + /* Handle SG mode */ + seg = mbuf; + while (mac_offset >= seg->data_len) { + mac_offset -= seg->data_len; + mac_prev_seg = seg; + seg = seg->next; + nb_segs++; + } + mac_seg = seg; + + pad_offset = mac_offset + mac_len; + while (pad_offset >= seg->data_len) { + pad_offset -= seg->data_len; + seg = seg->next; + } + + while (pad_len != 0) { + uint8_t *ptr = rte_pktmbuf_mtod_offset(seg, uint8_t *, pad_offset); + uint8_t len = RTE_MIN(seg->data_len - pad_offset, pad_len); + + for (i = 0; i < len; i++) + pad_res |= ptr[i] ^ pad_val; + + pad_offset = 0; + pad_len -= len; + seg = seg->next; + } + + if (pad_res) { + cop->status = RTE_CRYPTO_OP_STATUS_ERROR; + cop->aux_flags = res->uc_compcode; + } + + mbuf->pkt_len = m_len - trim_len; + if (mac_offset) { + rte_pktmbuf_free(mac_seg->next); + mac_seg->next = NULL; + mac_seg->data_len = mac_offset; + mbuf->nb_segs = nb_segs; + } else { + rte_pktmbuf_free(mac_seg); + mac_prev_seg->next = NULL; + mbuf->nb_segs = nb_segs - 1; + } +} + +/* TLS-1.3: + * Read from last until a non-zero value is encountered. + * Return the non zero value as the content type. + * Remove the MAC and content type and padding bytes. + */ +static inline void +cn10k_cpt_tls13_trim_mac(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *res) +{ + struct rte_mbuf *mbuf = cop->sym->m_src; + struct rte_mbuf *seg = mbuf; + uint16_t m_len = res->rlen; + uint8_t *ptr, type = 0x0; + int len, i, nb_segs = 1; + + while (m_len && !type) { + len = m_len; + seg = mbuf; + + /* get the last seg */ + while (len > seg->data_len) { + len -= seg->data_len; + seg = seg->next; + nb_segs++; + } + + /* walkthrough from last until a non zero value is found */ + ptr = rte_pktmbuf_mtod(seg, uint8_t *); + i = len; + while (i && (ptr[--i] == 0)) + ; + + type = ptr[i]; + m_len -= len; + } + + if (type) { + cop->param1.tls_record.content_type = type; + mbuf->pkt_len = m_len + i; + mbuf->nb_segs = nb_segs; + seg->data_len = i; + rte_pktmbuf_free(seg->next); + seg->next = NULL; + } else { + cop->status = RTE_CRYPTO_OP_STATUS_ERROR; + } +} + +static inline void +cn10k_cpt_tls_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *res, + struct cn10k_sec_session *sess) +{ + struct cn10k_tls_opt tls_opt = sess->tls_opt; + struct rte_mbuf *mbuf = cop->sym->m_src; + uint16_t m_len = res->rlen; if (!res->uc_compcode) { if (mbuf->next == NULL) mbuf->data_len = m_len; mbuf->pkt_len = m_len; - } else { + cop->param1.tls_record.content_type = (res->spi >> 24) & 0xff; + return; + } + + /* Any error other than post process */ + if (res->uc_compcode != ROC_SE_ERR_SSL_POST_PROCESS) { cop->status = RTE_CRYPTO_OP_STATUS_ERROR; cop->aux_flags = res->uc_compcode; plt_err("crypto op failed with UC compcode: 0x%x", res->uc_compcode); + return; } + + /* Extra padding scenario: Verify padding. Remove padding and MAC */ + if (tls_opt.tls_ver != RTE_SECURITY_VERSION_TLS_1_3) + cn10k_cpt_tls12_trim_mac(cop, res, (uint8_t)tls_opt.mac_len); + else + cn10k_cpt_tls13_trim_mac(cop, res); } static inline void @@ -1015,7 +1156,7 @@ cn10k_cpt_sec_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *re if (sess->proto == RTE_SECURITY_PROTOCOL_IPSEC) cn10k_cpt_ipsec_post_process(cop, res); else if (sess->proto == RTE_SECURITY_PROTOCOL_TLS_RECORD) - cn10k_cpt_tls_post_process(cop, res); + cn10k_cpt_tls_post_process(cop, res, sess); } static inline void diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h index 230c0f7c1c..1637a9a25c 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h +++ b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h @@ -16,6 +16,15 @@ #define SEC_SESS_SIZE sizeof(struct rte_security_session) +struct cn10k_tls_opt { + uint16_t pad_shift : 3; + uint16_t enable_padding : 1; + uint16_t tail_fetch_len : 2; + uint16_t tls_ver : 2; + uint16_t is_write : 1; + uint16_t mac_len : 7; +}; + struct cn10k_sec_session { uint8_t rte_sess[SEC_SESS_SIZE]; @@ -29,16 +38,12 @@ struct cn10k_sec_session { uint8_t proto; uint8_t iv_length; union { + uint16_t u16; + struct cn10k_tls_opt tls_opt; struct { uint8_t ip_csum; uint8_t is_outbound : 1; } ipsec; - struct { - uint8_t enable_padding : 1; - uint8_t tail_fetch_len : 2; - uint8_t is_write : 1; - uint8_t rvsd : 4; - } tls; }; /** Queue pair */ struct cnxk_cpt_qp *qp; diff --git a/drivers/crypto/cnxk/cn10k_tls.c b/drivers/crypto/cnxk/cn10k_tls.c index ae3ed3176c..3505a71a6c 100644 --- a/drivers/crypto/cnxk/cn10k_tls.c +++ b/drivers/crypto/cnxk/cn10k_tls.c @@ -119,8 +119,14 @@ cnxk_tls_xform_verify(struct rte_security_tls_record_xform *tls_xform, (tls_xform->type != RTE_SECURITY_TLS_SESS_TYPE_WRITE)) return -EINVAL; - if (crypto_xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) + if (crypto_xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) { + /* optional padding is not allowed in TLS-1.2 for AEAD */ + if ((tls_xform->ver == RTE_SECURITY_VERSION_TLS_1_2) && + (tls_xform->options.extra_padding_enable == 1)) + return -EINVAL; + return tls_xform_aead_verify(tls_xform, crypto_xform); + } /* TLS-1.3 only support AEAD. * Control should not reach here for TLS-1.3 @@ -321,7 +327,7 @@ tls_read_ctx_size(struct roc_ie_ot_tls_read_sa *sa, enum rte_security_tls_versio static int tls_read_sa_fill(struct roc_ie_ot_tls_read_sa *read_sa, struct rte_security_tls_record_xform *tls_xfrm, - struct rte_crypto_sym_xform *crypto_xfrm) + struct rte_crypto_sym_xform *crypto_xfrm, struct cn10k_tls_opt *tls_opt) { enum rte_security_tls_version tls_ver = tls_xfrm->ver; struct rte_crypto_sym_xform *auth_xfrm, *cipher_xfrm; @@ -405,16 +411,26 @@ tls_read_sa_fill(struct roc_ie_ot_tls_read_sa *read_sa, memcpy(cipher_key, key, length); } - if (auth_xfrm->auth.algo == RTE_CRYPTO_AUTH_MD5_HMAC) + switch (auth_xfrm->auth.algo) { + case RTE_CRYPTO_AUTH_MD5_HMAC: read_sa->w2.s.mac_select = ROC_IE_OT_TLS_MAC_MD5; - else if (auth_xfrm->auth.algo == RTE_CRYPTO_AUTH_SHA1_HMAC) + tls_opt->mac_len = 0; + break; + case RTE_CRYPTO_AUTH_SHA1_HMAC: read_sa->w2.s.mac_select = ROC_IE_OT_TLS_MAC_SHA1; - else if (auth_xfrm->auth.algo == RTE_CRYPTO_AUTH_SHA256_HMAC) + tls_opt->mac_len = 20; + break; + case RTE_CRYPTO_AUTH_SHA256_HMAC: read_sa->w2.s.mac_select = ROC_IE_OT_TLS_MAC_SHA2_256; - else if (auth_xfrm->auth.algo == RTE_CRYPTO_AUTH_SHA384_HMAC) + tls_opt->mac_len = 32; + break; + case RTE_CRYPTO_AUTH_SHA384_HMAC: read_sa->w2.s.mac_select = ROC_IE_OT_TLS_MAC_SHA2_384; - else + tls_opt->mac_len = 48; + break; + default: return -EINVAL; + } roc_se_hmac_opad_ipad_gen(read_sa->w2.s.mac_select, auth_xfrm->auth.key.data, auth_xfrm->auth.key.length, read_sa->tls_12.opad_ipad, @@ -622,6 +638,7 @@ cn10k_tls_read_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, struct cn10k_sec_session *sec_sess) { struct roc_ie_ot_tls_read_sa *sa_dptr; + uint8_t tls_ver = tls_xfrm->ver; struct cn10k_tls_record *tls; union cpt_inst_w4 inst_w4; void *read_sa; @@ -638,7 +655,7 @@ cn10k_tls_read_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, } /* Translate security parameters to SA */ - ret = tls_read_sa_fill(sa_dptr, tls_xfrm, crypto_xfrm); + ret = tls_read_sa_fill(sa_dptr, tls_xfrm, crypto_xfrm, &sec_sess->tls_opt); if (ret) { plt_err("Could not fill read session parameters"); goto sa_dptr_free; @@ -658,19 +675,20 @@ cn10k_tls_read_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, /* pre-populate CPT INST word 4 */ inst_w4.u64 = 0; - if ((sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_TLS_12) || - (sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_DTLS_12)) { + if ((tls_ver == RTE_SECURITY_VERSION_TLS_1_2) || + (tls_ver == RTE_SECURITY_VERSION_DTLS_1_2)) { inst_w4.s.opcode_major = ROC_IE_OT_TLS_MAJOR_OP_RECORD_DEC | ROC_IE_OT_INPLACE_BIT; - sec_sess->tls.tail_fetch_len = 0; + sec_sess->tls_opt.tail_fetch_len = 0; if (sa_dptr->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_3DES) - sec_sess->tls.tail_fetch_len = 1; + sec_sess->tls_opt.tail_fetch_len = 1; else if (sa_dptr->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_AES_CBC) - sec_sess->tls.tail_fetch_len = 2; - } else if (sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_TLS_13) { + sec_sess->tls_opt.tail_fetch_len = 2; + } else if (tls_xfrm->ver == RTE_SECURITY_VERSION_TLS_1_3) { inst_w4.s.opcode_major = ROC_IE_OT_TLS13_MAJOR_OP_RECORD_DEC | ROC_IE_OT_INPLACE_BIT; } + sec_sess->tls_opt.tls_ver = tls_ver; sec_sess->inst.w4 = inst_w4.u64; sec_sess->inst.w7 = cpt_inst_w7_get(roc_cpt, read_sa); @@ -706,6 +724,7 @@ cn10k_tls_write_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, struct cn10k_sec_session *sec_sess) { struct roc_ie_ot_tls_write_sa *sa_dptr; + uint8_t tls_ver = tls_xfrm->ver; struct cn10k_tls_record *tls; union cpt_inst_w4 inst_w4; void *write_sa; @@ -739,17 +758,23 @@ cn10k_tls_write_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, sec_sess->iv_length = crypto_xfrm->next->cipher.iv.length; } - sec_sess->tls.is_write = 1; - sec_sess->tls.enable_padding = tls_xfrm->options.extra_padding_enable; + sec_sess->tls_opt.is_write = 1; + sec_sess->tls_opt.pad_shift = 0; + sec_sess->tls_opt.tls_ver = tls_ver; + sec_sess->tls_opt.enable_padding = tls_xfrm->options.extra_padding_enable; sec_sess->max_extended_len = tls_write_rlens_get(tls_xfrm, crypto_xfrm); sec_sess->proto = RTE_SECURITY_PROTOCOL_TLS_RECORD; /* pre-populate CPT INST word 4 */ inst_w4.u64 = 0; - if ((sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_TLS_12) || - (sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_DTLS_12)) { + if ((tls_ver == RTE_SECURITY_VERSION_TLS_1_2) || + (tls_ver == RTE_SECURITY_VERSION_DTLS_1_2)) { inst_w4.s.opcode_major = ROC_IE_OT_TLS_MAJOR_OP_RECORD_ENC | ROC_IE_OT_INPLACE_BIT; - } else if (sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_TLS_13) { + if (sa_dptr->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_3DES) + sec_sess->tls_opt.pad_shift = 3; + else + sec_sess->tls_opt.pad_shift = 4; + } else if (tls_ver == RTE_SECURITY_VERSION_TLS_1_3) { inst_w4.s.opcode_major = ROC_IE_OT_TLS13_MAJOR_OP_RECORD_ENC | ROC_IE_OT_INPLACE_BIT; } @@ -838,7 +863,7 @@ cn10k_sec_tls_session_destroy(struct cnxk_cpt_qp *qp, struct cn10k_sec_session * ret = -1; - if (sess->tls.is_write) { + if (sess->tls_opt.is_write) { sa_dptr = plt_zmalloc(sizeof(struct roc_ie_ot_tls_write_sa), 8); if (sa_dptr != NULL) { tls_write_sa_init(sa_dptr); diff --git a/drivers/crypto/cnxk/cn10k_tls_ops.h b/drivers/crypto/cnxk/cn10k_tls_ops.h index 6fd74927ee..64f94a4e8b 100644 --- a/drivers/crypto/cnxk/cn10k_tls_ops.h +++ b/drivers/crypto/cnxk/cn10k_tls_ops.h @@ -21,16 +21,21 @@ process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k struct cpt_qp_meta_info *m_info, struct cpt_inflight_req *infl_req, struct cpt_inst_s *inst, const bool is_sg_ver2) { + struct cn10k_tls_opt tls_opt = sess->tls_opt; struct rte_crypto_sym_op *sym_op = cop->sym; #ifdef LA_IPSEC_DEBUG struct roc_ie_ot_tls_write_sa *write_sa; #endif struct rte_mbuf *m_src = sym_op->m_src; + uint32_t pad_len, pad_bytes; struct rte_mbuf *last_seg; union cpt_inst_w4 w4; void *m_data = NULL; uint8_t *in_buffer; + pad_bytes = (cop->aux_flags * 8) > 0xff ? 0xff : (cop->aux_flags * 8); + pad_len = (pad_bytes >> tls_opt.pad_shift) * tls_opt.enable_padding; + #ifdef LA_IPSEC_DEBUG write_sa = &sess->tls_rec.write_sa; if (write_sa->w2.s.iv_at_cptr == ROC_IE_OT_TLS_IV_SRC_FROM_SA) { @@ -94,7 +99,7 @@ process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k w4.s.dlen = m_src->data_len; w4.s.param2 = cop->param1.tls_record.content_type; - w4.s.opcode_minor = sess->tls.enable_padding * cop->aux_flags * 8; + w4.s.opcode_minor = pad_len; inst->w4.u64 = w4.u64; } else if (is_sg_ver2 == false) { @@ -148,10 +153,10 @@ process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k w4.s.param1 = rte_pktmbuf_pkt_len(m_src); w4.s.param2 = cop->param1.tls_record.content_type; w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG; - w4.s.opcode_minor = sess->tls.enable_padding * cop->aux_flags * 8; + w4.s.opcode_minor = pad_len; /* Output Scatter List */ - last_seg->data_len += sess->max_extended_len; + last_seg->data_len += sess->max_extended_len + pad_bytes; inst->w4.u64 = w4.u64; } else { struct roc_sg2list_comp *scatter_comp, *gather_comp; @@ -198,11 +203,11 @@ process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k w4.u64 = sess->inst.w4; w4.s.dlen = rte_pktmbuf_pkt_len(m_src); w4.s.opcode_major &= (~(ROC_IE_OT_INPLACE_BIT)); - w4.s.opcode_minor = sess->tls.enable_padding * cop->aux_flags * 8; + w4.s.opcode_minor = pad_len; w4.s.param1 = w4.s.dlen; w4.s.param2 = cop->param1.tls_record.content_type; /* Output Scatter List */ - last_seg->data_len += sess->max_extended_len; + last_seg->data_len += sess->max_extended_len + pad_bytes; inst->w4.u64 = w4.u64; } @@ -234,7 +239,7 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, inst->w4.u64 = w4.u64; } else if (is_sg_ver2 == false) { struct roc_sglist_comp *scatter_comp, *gather_comp; - int tail_len = sess->tls.tail_fetch_len * 16; + int tail_len = sess->tls_opt.tail_fetch_len * 16; int pkt_len = rte_pktmbuf_pkt_len(m_src); uint32_t g_size_bytes, s_size_bytes; uint16_t *sg_hdr; @@ -289,7 +294,7 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, inst->w4.u64 = w4.u64; } else { struct roc_sg2list_comp *scatter_comp, *gather_comp; - int tail_len = sess->tls.tail_fetch_len * 16; + int tail_len = sess->tls_opt.tail_fetch_len * 16; int pkt_len = rte_pktmbuf_pkt_len(m_src); union cpt_inst_w5 cpt_inst_w5; union cpt_inst_w6 cpt_inst_w6; From patchwork Fri Mar 15 05:42:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 138419 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6467E43CA6; Fri, 15 Mar 2024 06:43:52 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1063342EE5; Fri, 15 Mar 2024 06:43:18 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 49E46410FC for ; Fri, 15 Mar 2024 06:42:36 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42F0aS25018658 for ; Thu, 14 Mar 2024 22:42:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=Em5DnOLvXu8ha4dwGbEBJh4ut/jTijn2y0zmLNq4iOI=; b=OSs en4Dqp/4y5mc9u/cboxS6LMSBjOWi6GMiWUdzQ3MHyEgFrttnb02MvU+f9U7Qmk2 eTulrvF7pAZLSGnpbfYotuPz8dXe6FGiiYD5DoYX6+E9/sYoahnZhO+Bw7pr73XX X9av2WnkHN7lDhw5P3qt3yLJ0ZaL62zTOxsJ3vGcHZXVMpBQxM9ecpasv7fMUqSK 0xbH8kRTkY1fCUDQ5OFOzFM6vJ9QjcQujU0kviDbNwpwrlpTVdb+wIBnJI798iA5 gBmF+cWE7ydn5E1T7tlhf2/c4MVqgze25cNLPpnCtnRwIkOWTk5ILS+S3mY3nL51 h0qffQIMWR1zUMiBD2Q== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3wvbxbrpga-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 14 Mar 2024 22:42:35 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 22:42:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 22:42:34 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.193.69.194]) by maili.marvell.com (Postfix) with ESMTP id B19C93F703F; Thu, 14 Mar 2024 22:42:32 -0700 (PDT) From: Vidya Sagar Velumuri To: Akhil Goyal CC: Aakash Sasidharan , Jerin Jacob , , Anoob Joseph Subject: [PATCH v3 7/8] crypto/cnxk: add support for oop processing in TLS Date: Fri, 15 Mar 2024 11:12:12 +0530 Message-ID: <20240315054213.540-8-vvelumuri@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240315054213.540-1-vvelumuri@marvell.com> References: <20240314131839.3362494-1-vvelumuri@marvell.com> <20240315054213.540-1-vvelumuri@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: qbFGY_QTUJ_b_cv3KG2MLloFFP_dMFhG X-Proofpoint-ORIG-GUID: qbFGY_QTUJ_b_cv3KG2MLloFFP_dMFhG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_13,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Aakash Sasidharan Add support for out-of-place processing in TLS. Signed-off-by: Aakash Sasidharan --- drivers/crypto/cnxk/cn10k_tls_ops.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_tls_ops.h b/drivers/crypto/cnxk/cn10k_tls_ops.h index 64f94a4e8b..e8e2547f68 100644 --- a/drivers/crypto/cnxk/cn10k_tls_ops.h +++ b/drivers/crypto/cnxk/cn10k_tls_ops.h @@ -27,6 +27,7 @@ process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k struct roc_ie_ot_tls_write_sa *write_sa; #endif struct rte_mbuf *m_src = sym_op->m_src; + struct rte_mbuf *m_dst = sym_op->m_dst; uint32_t pad_len, pad_bytes; struct rte_mbuf *last_seg; union cpt_inst_w4 w4; @@ -191,7 +192,9 @@ process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k i = 0; scatter_comp = (struct roc_sg2list_comp *)((uint8_t *)gather_comp + g_size_bytes); - i = fill_sg2_comp_from_pkt(scatter_comp, i, m_src); + if (m_dst == NULL) + m_dst = m_src; + i = fill_sg2_comp_from_pkt(scatter_comp, i, m_dst); cpt_inst_w6.s.scatter_sz = ((i + 2) / 3); @@ -221,6 +224,7 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, { struct rte_crypto_sym_op *sym_op = cop->sym; struct rte_mbuf *m_src = sym_op->m_src; + struct rte_mbuf *m_dst = sym_op->m_dst; union cpt_inst_w4 w4; uint8_t *in_buffer; void *m_data; @@ -334,7 +338,9 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, i = 0; scatter_comp = (struct roc_sg2list_comp *)((uint8_t *)gather_comp + g_size_bytes); - i = fill_sg2_comp_from_pkt(scatter_comp, i, m_src); + if (m_dst == NULL) + m_dst = m_src; + i = fill_sg2_comp_from_pkt(scatter_comp, i, m_dst); cpt_inst_w6.s.scatter_sz = ((i + 2) / 3); From patchwork Fri Mar 15 05:42:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 138420 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A252143CA6; Fri, 15 Mar 2024 06:44:02 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 47C9242EBA; Fri, 15 Mar 2024 06:43:46 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A62AC410FC for ; Fri, 15 Mar 2024 06:42:39 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42EMJOr2032321 for ; Thu, 14 Mar 2024 22:42:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=Ws3k1GuStpZg63k3NYnd3K5ZM3899P+X2XWF4+OEzNE=; b=bUD 4rsKH+I8Idt+dMWcu+KDLoNOfJm2b7VKOLMtYOVVbnasVbu43Pwzc0KysTO5j5xD L/eoBRSIbFwG/h5jG44TKZT+905H1KbqAw28qHiawnM/47GjeXuFhRkbMNuy9SYN yokeZ7gDcM1zyMxh9icEe7lzzB6xthqW5L5zzPpezIA6lH7nuaX43apYDIJfPGWZ MV+VfSucM+P2gKc1j0RXSKP6BdgWpgljFeFbtdR7902gmABaCpMPRKyYY74TWwhb SEaVQ4z59t1qqDAZb7rzzgNMUCsTSCv1+Nai1oVfoT2phZwhnH/sMaGq0tpoEqX3 i7SQR8yub6zYSzZTBmA== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wv9xa12hj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 14 Mar 2024 22:42:38 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 22:42:37 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 22:42:37 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.193.69.194]) by maili.marvell.com (Postfix) with ESMTP id 5034A3F703F; Thu, 14 Mar 2024 22:42:35 -0700 (PDT) From: Vidya Sagar Velumuri To: Akhil Goyal CC: Jerin Jacob , , Aakash Sasidharan , Anoob Joseph Subject: [PATCH v3 8/8] crypto/cnxk: update the context structure of tls Date: Fri, 15 Mar 2024 11:12:13 +0530 Message-ID: <20240315054213.540-9-vvelumuri@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240315054213.540-1-vvelumuri@marvell.com> References: <20240314131839.3362494-1-vvelumuri@marvell.com> <20240315054213.540-1-vvelumuri@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: h8DDgnO4eiaV0M9NNI0kNBYpV6DnJ1lL X-Proofpoint-GUID: h8DDgnO4eiaV0M9NNI0kNBYpV6DnJ1lL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_13,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Keep the record context for TLS-1.3 in sync with microcode structure. Report error if optional padding is enabled for AEAD case in both TLS-1.2 and DTLS-1.2. Use the proper offset for calculating the context size in case of TLS-1.3. Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_ie_ot_tls.h | 17 ++++++++++++----- drivers/crypto/cnxk/cn10k_tls.c | 6 +++--- 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/roc_ie_ot_tls.h b/drivers/common/cnxk/roc_ie_ot_tls.h index 39c42775f4..2d6a290d9b 100644 --- a/drivers/common/cnxk/roc_ie_ot_tls.h +++ b/drivers/common/cnxk/roc_ie_ot_tls.h @@ -68,6 +68,16 @@ struct roc_ie_ot_tls_read_ctx_update_reg { uint64_t ar_winbits[ROC_IE_OT_TLS_AR_WINBITS_SZ]; }; +struct roc_ie_ot_tls_1_3_read_ctx_update_reg { + uint64_t rsvd0; + uint64_t ar_valid_mask; + uint64_t hard_life; + uint64_t soft_life; + uint64_t mib_octs; + uint64_t mib_pkts; + uint64_t rsvd1; +}; + union roc_ie_ot_tls_param2 { uint16_t u16; struct { @@ -137,11 +147,8 @@ struct roc_ie_ot_tls_read_sa { union { struct { - /* Word10 */ - uint64_t w10_rsvd6; - - /* Word11 - Word25 */ - struct roc_ie_ot_tls_read_ctx_update_reg ctx; + /* Word10 - Word16 */ + struct roc_ie_ot_tls_1_3_read_ctx_update_reg ctx; } tls_13; struct { diff --git a/drivers/crypto/cnxk/cn10k_tls.c b/drivers/crypto/cnxk/cn10k_tls.c index 3505a71a6c..7b73a58d2a 100644 --- a/drivers/crypto/cnxk/cn10k_tls.c +++ b/drivers/crypto/cnxk/cn10k_tls.c @@ -121,8 +121,8 @@ cnxk_tls_xform_verify(struct rte_security_tls_record_xform *tls_xform, if (crypto_xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) { /* optional padding is not allowed in TLS-1.2 for AEAD */ - if ((tls_xform->ver == RTE_SECURITY_VERSION_TLS_1_2) && - (tls_xform->options.extra_padding_enable == 1)) + if ((tls_xform->options.extra_padding_enable == 1) && + (tls_xform->ver != RTE_SECURITY_VERSION_TLS_1_3)) return -EINVAL; return tls_xform_aead_verify(tls_xform, crypto_xform); @@ -312,7 +312,7 @@ tls_read_ctx_size(struct roc_ie_ot_tls_read_sa *sa, enum rte_security_tls_versio /* Variable based on Anti-replay Window */ if (tls_ver == RTE_SECURITY_VERSION_TLS_1_3) { size = offsetof(struct roc_ie_ot_tls_read_sa, tls_13.ctx) + - offsetof(struct roc_ie_ot_tls_read_ctx_update_reg, ar_winbits); + sizeof(struct roc_ie_ot_tls_1_3_read_ctx_update_reg); } else { size = offsetof(struct roc_ie_ot_tls_read_sa, tls_12.ctx) + offsetof(struct roc_ie_ot_tls_read_ctx_update_reg, ar_winbits);