From patchwork Fri Mar 15 01:06:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ma, WenwuX" X-Patchwork-Id: 138409 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4439143CA6; Fri, 15 Mar 2024 02:18:50 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 494F642EAE; Fri, 15 Mar 2024 02:18:49 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id 2E60E410FC; Fri, 15 Mar 2024 02:18:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1710465527; x=1742001527; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=UjZNBrDvuwYh76hSvwZStrAlgFKtDRKSOwIEJftEGg4=; b=bBswHlv1zc8vg1yF18m/EysW/ncs8pP42R5CbpxzcK8V83EgK6ehjnv5 mBcNl76xfsvXukcgNtQw+u/OQiQIoGwkWy/eG2E+GBSWAZA2XPdA9U+YE z4JJPxtPcQVT63JMOzFvYZZ/5oUhrO52PunjMzx0m9367HJQ39FyAmujP SSAvbaDYbyZGiOID+CFKm3UEsVt2XioxzhYFZLWZkpUicCDWmXHhDlkYy ljRPsMcSJoFJ4e+RpRa+g96nXORyr4jgihY+pI5tChBOlbsyh61p8nZEI lHcwJjWspjHLvw1TVMHnSfmweZMXX2mZYt5p/kDc9gVhpAYYx1tzphUpY w==; X-IronPort-AV: E=McAfee;i="6600,9927,11013"; a="5523080" X-IronPort-AV: E=Sophos;i="6.07,127,1708416000"; d="scan'208";a="5523080" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2024 18:18:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,127,1708416000"; d="scan'208";a="12413666" Received: from unknown (HELO localhost.localdomain) ([10.239.252.55]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2024 18:18:43 -0700 From: Wenwu Ma To: dev@dpdk.org, junfeng.guo@intel.com, simei.su@intel.com Cc: tingtingx.liao@intel.com, Wenwu Ma , stable@dpdk.org Subject: [PATCH] net/igc: fix disabling timesync Date: Fri, 15 Mar 2024 09:06:31 +0800 Message-Id: <20240315010631.1374624-1-wenwux.ma@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When disabling timesync, we should clear the IGC_RXPBS_CFG_TS_EN bit of IGC_RXPBS, the patch fixes this. Fixes: 4f6fbbf6f17d ("net/igc: support IEEE 1588 PTP") Cc: stable@dpdk.org Signed-off-by: Wenwu Ma Tested-by: Tingting Liao --- drivers/net/igc/igc_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/igc/igc_ethdev.c b/drivers/net/igc/igc_ethdev.c index 58c4f80927..690736b6d1 100644 --- a/drivers/net/igc/igc_ethdev.c +++ b/drivers/net/igc/igc_ethdev.c @@ -2853,7 +2853,7 @@ eth_igc_timesync_disable(struct rte_eth_dev *dev) IGC_WRITE_REG(hw, IGC_TSYNCRXCTL, 0); val = IGC_READ_REG(hw, IGC_RXPBS); - val &= IGC_RXPBS_CFG_TS_EN; + val &= ~IGC_RXPBS_CFG_TS_EN; IGC_WRITE_REG(hw, IGC_RXPBS, val); val = IGC_READ_REG(hw, IGC_SRRCTL(0));