From patchwork Tue Mar 12 07:52:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dengdui Huang X-Patchwork-Id: 138202 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 83AE243C8E; Tue, 12 Mar 2024 08:52:47 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B36784114B; Tue, 12 Mar 2024 08:52:44 +0100 (CET) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id CAC6B40C35 for ; Tue, 12 Mar 2024 08:52:40 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.88.194]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4Tv5Sp18BTzbclq; Tue, 12 Mar 2024 15:51:54 +0800 (CST) Received: from dggpeml500011.china.huawei.com (unknown [7.185.36.84]) by mail.maildlp.com (Postfix) with ESMTPS id 2F12C14040D; Tue, 12 Mar 2024 15:52:39 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Tue, 12 Mar 2024 15:52:38 +0800 From: Dengdui Huang To: CC: , , , , , , , , Subject: [PATCH 1/3] ethdev: support setting lanes Date: Tue, 12 Mar 2024 15:52:36 +0800 Message-ID: <20240312075238.3319480-2-huangdengdui@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240312075238.3319480-1-huangdengdui@huawei.com> References: <20240312075238.3319480-1-huangdengdui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500011.china.huawei.com (7.185.36.84) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some speeds can be achieved with different number of lanes. For example, 100Gbps can be achieved using two lanes of 50Gbps or four lanes of 25Gbps. When use different lanes, the port cannot be up. This patch add support for setting lanes and report lanes. Signed-off-by: Dengdui Huang --- doc/guides/rel_notes/release_24_03.rst | 8 +- drivers/net/bnxt/bnxt_ethdev.c | 3 +- drivers/net/hns3/hns3_ethdev.c | 1 + lib/ethdev/ethdev_driver.h | 1 - lib/ethdev/ethdev_linux_ethtool.c | 101 ++++++++- lib/ethdev/ethdev_private.h | 4 + lib/ethdev/ethdev_trace.h | 4 +- lib/ethdev/meson.build | 2 + lib/ethdev/rte_ethdev.c | 272 +++++++++++++++++++++++-- lib/ethdev/rte_ethdev.h | 99 +++++++-- lib/ethdev/version.map | 7 + 11 files changed, 466 insertions(+), 36 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 932688ca4d..75d93ee965 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -76,6 +76,10 @@ New Features * Added a fath path function ``rte_eth_tx_queue_count`` to get the number of used descriptors of a Tx queue. +* **Support setting lanes for ethdev.** + * Support setting lanes by extended ``RTE_ETH_LINK_SPEED_*``. + * Added function to convert bitmap flag to the struct of link speed info. + * **Added hash calculation of an encapsulated packet as done by the HW.** Added function to calculate hash when doing tunnel encapsulation: @@ -240,9 +244,11 @@ ABI Changes This section is a comment. Do not overwrite or remove it. Also, make sure to start the actual text at the margin. ======================================================= - * No ABI change that would break compatibility with 23.11. +* ethdev: Convert a numerical speed to a bitmap flag with lanes: + The function ``rte_eth_speed_bitflag`` add lanes parameters. + Known Issues ------------ diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index ba31ae9286..e881a7f3cc 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -711,7 +711,8 @@ static int bnxt_update_phy_setting(struct bnxt *bp) } /* convert to speedbit flag */ - curr_speed_bit = rte_eth_speed_bitflag((uint32_t)link->link_speed, 1); + curr_speed_bit = rte_eth_speed_bitflag((uint32_t)link->link_speed, + RTE_ETH_LANES_UNKNOWN, 1); /* * Device is not obliged link down in certain scenarios, even diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index b10d1216d2..ecd3b2ef64 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -5969,6 +5969,7 @@ hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa, for (i = 0; i < RTE_DIM(speed_fec_capa_tbl); i++) { speed_bit = rte_eth_speed_bitflag(speed_fec_capa_tbl[i].speed, + RTE_ETH_LANES_UNKNOWN, RTE_ETH_LINK_FULL_DUPLEX); if ((speed_capa & speed_bit) == 0) continue; diff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h index 0dbf2dd6a2..bb7dc7acb7 100644 --- a/lib/ethdev/ethdev_driver.h +++ b/lib/ethdev/ethdev_driver.h @@ -2003,7 +2003,6 @@ __rte_internal int rte_eth_ip_reassembly_dynfield_register(int *field_offset, int *flag); - /* * Legacy ethdev API used internally by drivers. */ diff --git a/lib/ethdev/ethdev_linux_ethtool.c b/lib/ethdev/ethdev_linux_ethtool.c index e792204b01..b776ec6173 100644 --- a/lib/ethdev/ethdev_linux_ethtool.c +++ b/lib/ethdev/ethdev_linux_ethtool.c @@ -111,10 +111,107 @@ static const uint32_t link_modes[] = { [101] = 11, /* ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT */ }; +/* + * Link modes sorted with index as defined in ethtool. + * Values are lanes. + */ +static const uint32_t link_modes_lanes[] = { + [0] = 1, /* ETHTOOL_LINK_MODE_10baseT_Half_BIT */ + [1] = 1, /* ETHTOOL_LINK_MODE_10baseT_Full_BIT */ + [2] = 1, /* ETHTOOL_LINK_MODE_100baseT_Half_BIT */ + [3] = 1, /* ETHTOOL_LINK_MODE_100baseT_Full_BIT */ + [4] = 1, /* ETHTOOL_LINK_MODE_1000baseT_Half_BIT */ + [5] = 1, /* ETHTOOL_LINK_MODE_1000baseT_Full_BIT */ + [12] = 1, /* ETHTOOL_LINK_MODE_10000baseT_Full_BIT */ + [15] = 1, /* ETHTOOL_LINK_MODE_2500baseX_Full_BIT */ + [17] = 1, /* ETHTOOL_LINK_MODE_1000baseKX_Full_BIT */ + [18] = 4, /* ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT */ + [19] = 1, /* ETHTOOL_LINK_MODE_10000baseKR_Full_BIT */ + [20] = 1, /* ETHTOOL_LINK_MODE_10000baseR_FEC_BIT */ + [21] = 2, /* ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT */ + [22] = 2, /* ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT */ + [23] = 4, /* ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT */ + [24] = 4, /* ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT */ + [25] = 4, /* ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT */ + [26] = 4, /* ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT */ + [27] = 4, /* ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT */ + [28] = 4, /* ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT */ + [29] = 4, /* ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT */ + [30] = 4, /* ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT */ + [31] = 1, /* ETHTOOL_LINK_MODE_25000baseCR_Full_BIT */ + [32] = 1, /* ETHTOOL_LINK_MODE_25000baseKR_Full_BIT */ + [33] = 1, /* ETHTOOL_LINK_MODE_25000baseSR_Full_BIT */ + [34] = 2, /* ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT */ + [35] = 2, /* ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT */ + [36] = 4, /* ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT */ + [37] = 4, /* ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT */ + [38] = 4, /* ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT */ + [39] = 4, /* ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT */ + [40] = 2, /* ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT */ + [41] = 1, /* ETHTOOL_LINK_MODE_1000baseX_Full_BIT */ + [42] = 1, /* ETHTOOL_LINK_MODE_10000baseCR_Full_BIT */ + [43] = 1, /* ETHTOOL_LINK_MODE_10000baseSR_Full_BIT */ + [44] = 1, /* ETHTOOL_LINK_MODE_10000baseLR_Full_BIT */ + [45] = 1, /* ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT */ + [46] = 1, /* ETHTOOL_LINK_MODE_10000baseER_Full_BIT */ + [47] = 1, /* ETHTOOL_LINK_MODE_2500baseT_Full_BIT */ + [48] = 1, /* ETHTOOL_LINK_MODE_5000baseT_Full_BIT */ + [52] = 1, /* ETHTOOL_LINK_MODE_50000baseKR_Full_BIT */ + [53] = 1, /* ETHTOOL_LINK_MODE_50000baseSR_Full_BIT */ + [54] = 1, /* ETHTOOL_LINK_MODE_50000baseCR_Full_BIT */ + [55] = 1, /* ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT */ + [56] = 1, /* ETHTOOL_LINK_MODE_50000baseDR_Full_BIT */ + [57] = 2, /* ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT */ + [58] = 2, /* ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT */ + [59] = 2, /* ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT */ + [60] = 2, /* ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT */ + [61] = 2, /* ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT */ + [62] = 4, /* ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT */ + [63] = 4, /* ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT */ + [64] = 4, /* ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT */ + [65] = 4, /* ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT */ + [66] = 4, /* ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT */ + [67] = 1, /* ETHTOOL_LINK_MODE_100baseT1_Full_BIT */ + [68] = 1, /* ETHTOOL_LINK_MODE_1000baseT1_Full_BIT */ + [69] = 8, /* ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT */ + [70] = 8, /* ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT */ + [71] = 8, /* ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT */ + [72] = 8, /* ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT */ + [73] = 8, /* ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT */ + [75] = 1, /* ETHTOOL_LINK_MODE_100000baseKR_Full_BIT */ + [76] = 1, /* ETHTOOL_LINK_MODE_100000baseSR_Full_BIT */ + [77] = 1, /* ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT */ + [78] = 1, /* ETHTOOL_LINK_MODE_100000baseCR_Full_BIT */ + [79] = 1, /* ETHTOOL_LINK_MODE_100000baseDR_Full_BIT */ + [80] = 2, /* ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT */ + [81] = 2, /* ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT */ + [82] = 2, /* ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT */ + [83] = 2, /* ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT */ + [84] = 2, /* ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT */ + [85] = 4, /* ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT */ + [86] = 4, /* ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT */ + [87] = 4, /* ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT */ + [88] = 4, /* ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT */ + [89] = 4, /* ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT */ + [90] = 1, /* ETHTOOL_LINK_MODE_100baseFX_Half_BIT */ + [91] = 1, /* ETHTOOL_LINK_MODE_100baseFX_Full_BIT */ + [92] = 1, /* ETHTOOL_LINK_MODE_10baseT1L_Full_BIT */ + [93] = 8, /* ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT */ + [94] = 8, /* ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT */ + [95] = 8, /* ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT */ + [96] = 8, /* ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT */ + [97] = 8, /* ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT */ + [98] = 8, /* ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT */ + [99] = 1, /* ETHTOOL_LINK_MODE_10baseT1S_Full_BIT */ + [100] = 1, /* ETHTOOL_LINK_MODE_10baseT1S_Half_BIT */ + [101] = 1, /* ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT */ +}; + uint32_t rte_eth_link_speed_ethtool(enum ethtool_link_mode_bit_indices bit) { uint32_t speed; + uint8_t lanes; int duplex; /* get mode from array */ @@ -131,7 +228,9 @@ rte_eth_link_speed_ethtool(enum ethtool_link_mode_bit_indices bit) RTE_ETH_LINK_FULL_DUPLEX; speed &= RTE_GENMASK32(31, 1); - return rte_eth_speed_bitflag(speed, duplex); + lanes = link_modes_lanes[bit]; + + return rte_eth_speed_bitflag(speed, lanes, duplex); } uint32_t diff --git a/lib/ethdev/ethdev_private.h b/lib/ethdev/ethdev_private.h index 0d36b9c30f..9092ab3a9e 100644 --- a/lib/ethdev/ethdev_private.h +++ b/lib/ethdev/ethdev_private.h @@ -79,4 +79,8 @@ void eth_dev_txq_release(struct rte_eth_dev *dev, uint16_t qid); int eth_dev_rx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues); int eth_dev_tx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues); +/* versioned functions */ +uint32_t rte_eth_speed_bitflag_v24(uint32_t speed, int duplex); +uint32_t rte_eth_speed_bitflag_v25(uint32_t speed, uint8_t lanes, int duplex); + #endif /* _ETH_PRIVATE_H_ */ diff --git a/lib/ethdev/ethdev_trace.h b/lib/ethdev/ethdev_trace.h index 3bec87bfdb..5547b49cab 100644 --- a/lib/ethdev/ethdev_trace.h +++ b/lib/ethdev/ethdev_trace.h @@ -183,8 +183,10 @@ RTE_TRACE_POINT( RTE_TRACE_POINT( rte_eth_trace_speed_bitflag, - RTE_TRACE_POINT_ARGS(uint32_t speed, int duplex, uint32_t ret), + RTE_TRACE_POINT_ARGS(uint32_t speed, uint8_t lanes, int duplex, + uint32_t ret), rte_trace_point_emit_u32(speed); + rte_trace_point_emit_u8(lanes); rte_trace_point_emit_int(duplex); rte_trace_point_emit_u32(ret); ) diff --git a/lib/ethdev/meson.build b/lib/ethdev/meson.build index f1d2586591..2c9588d0b3 100644 --- a/lib/ethdev/meson.build +++ b/lib/ethdev/meson.build @@ -62,3 +62,5 @@ endif if get_option('buildtype').contains('debug') cflags += ['-DRTE_FLOW_DEBUG'] endif + +use_function_versioning = true diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index f1c658f49e..522f8796b1 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "rte_ethdev.h" #include "rte_ethdev_trace_fp.h" @@ -991,63 +992,111 @@ rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id) return ret; } -uint32_t -rte_eth_speed_bitflag(uint32_t speed, int duplex) +uint32_t __vsym +rte_eth_speed_bitflag_v25(uint32_t speed, uint8_t lanes, int duplex) { - uint32_t ret; + uint32_t ret = 0; switch (speed) { case RTE_ETH_SPEED_NUM_10M: + if (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1) + break; ret = duplex ? RTE_ETH_LINK_SPEED_10M : RTE_ETH_LINK_SPEED_10M_HD; break; case RTE_ETH_SPEED_NUM_100M: + if (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1) + break; ret = duplex ? RTE_ETH_LINK_SPEED_100M : RTE_ETH_LINK_SPEED_100M_HD; break; case RTE_ETH_SPEED_NUM_1G: + if (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1) + break; ret = RTE_ETH_LINK_SPEED_1G; break; case RTE_ETH_SPEED_NUM_2_5G: + if (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1) + break; ret = RTE_ETH_LINK_SPEED_2_5G; break; case RTE_ETH_SPEED_NUM_5G: + if (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1) + break; ret = RTE_ETH_LINK_SPEED_5G; break; case RTE_ETH_SPEED_NUM_10G: - ret = RTE_ETH_LINK_SPEED_10G; + if (lanes == RTE_ETH_LANES_1) + ret = RTE_ETH_LINK_SPEED_10G; + if (lanes == RTE_ETH_LANES_4) + ret = RTE_ETH_LINK_SPEED_10G_4LANES; break; case RTE_ETH_SPEED_NUM_20G: - ret = RTE_ETH_LINK_SPEED_20G; + if (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_2) + break; + ret = RTE_ETH_LINK_SPEED_20G_2LANES; break; case RTE_ETH_SPEED_NUM_25G: + if (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1) + break; ret = RTE_ETH_LINK_SPEED_25G; break; case RTE_ETH_SPEED_NUM_40G: - ret = RTE_ETH_LINK_SPEED_40G; + if (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_4) + break; + ret = RTE_ETH_LINK_SPEED_40G_4LANES; break; case RTE_ETH_SPEED_NUM_50G: - ret = RTE_ETH_LINK_SPEED_50G; + if (lanes == RTE_ETH_LANES_1) + ret = RTE_ETH_LINK_SPEED_50G; + if (lanes == RTE_ETH_LANES_2) + ret = RTE_ETH_LINK_SPEED_50G_2LANES; break; case RTE_ETH_SPEED_NUM_56G: - ret = RTE_ETH_LINK_SPEED_56G; + if (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_4) + break; + ret = RTE_ETH_LINK_SPEED_56G_4LANES; break; case RTE_ETH_SPEED_NUM_100G: - ret = RTE_ETH_LINK_SPEED_100G; + if (lanes == RTE_ETH_LANES_1) + ret = RTE_ETH_LINK_SPEED_100G; + if (lanes == RTE_ETH_LANES_2) + ret = RTE_ETH_LINK_SPEED_100G_2LANES; + if (lanes == RTE_ETH_LANES_4) + ret = RTE_ETH_LINK_SPEED_100G_4LANES; break; case RTE_ETH_SPEED_NUM_200G: - ret = RTE_ETH_LINK_SPEED_200G; + if (lanes == RTE_ETH_LANES_2) + ret = RTE_ETH_LINK_SPEED_200G_2LANES; + if (lanes == RTE_ETH_LANES_4) + ret = RTE_ETH_LINK_SPEED_200G_4LANES; break; case RTE_ETH_SPEED_NUM_400G: + if (lanes == RTE_ETH_LANES_4) + ret = RTE_ETH_LINK_SPEED_400G_4LANES; + if (lanes == RTE_ETH_LANES_8) + ret = RTE_ETH_LINK_SPEED_400G_8LANES; ret = RTE_ETH_LINK_SPEED_400G; break; default: ret = 0; } - rte_eth_trace_speed_bitflag(speed, duplex, ret); + rte_eth_trace_speed_bitflag(speed, lanes, duplex, ret); return ret; } +uint32_t __vsym +rte_eth_speed_bitflag_v24(uint32_t speed, int duplex) +{ + return rte_eth_speed_bitflag_v25(speed, RTE_ETH_LANES_UNKNOWN, duplex); +} + +/* mark the v24 function as the older version, and v25 as the default version */ +VERSION_SYMBOL(rte_eth_speed_bitflag, _v24, 24); +BIND_DEFAULT_SYMBOL(rte_eth_speed_bitflag, _v25, 25); +MAP_STATIC_SYMBOL(uint32_t rte_eth_speed_bitflag(uint32_t speed, uint8_t lanes, int duplex), + rte_eth_speed_bitflag_v25); + const char * rte_eth_dev_rx_offload_name(uint64_t offload) { @@ -1066,6 +1115,204 @@ rte_eth_dev_rx_offload_name(uint64_t offload) return name; } +int +rte_eth_speed_capa_to_info(uint32_t link_speed, + struct rte_eth_speed_capa_info *capa_info) +{ + const struct { + uint32_t speed_capa; + struct rte_eth_speed_capa_info capa_info; + } speed_capa_info_map[] = { + { + RTE_ETH_LINK_SPEED_10M_HD, + { + RTE_ETH_SPEED_NUM_10M, + RTE_ETH_LANES_1, + RTE_ETH_LINK_HALF_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_10M, + { + RTE_ETH_SPEED_NUM_10M, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_100M_HD, + { + RTE_ETH_SPEED_NUM_100M, + RTE_ETH_LANES_1, + RTE_ETH_LINK_HALF_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_100M, + { + RTE_ETH_SPEED_NUM_100M, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_1G, + { + RTE_ETH_SPEED_NUM_1G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_2_5G, + { + RTE_ETH_SPEED_NUM_2_5G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_5G, + { + RTE_ETH_SPEED_NUM_5G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_10G, + { + RTE_ETH_SPEED_NUM_10G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_20G_2LANES, + { + RTE_ETH_SPEED_NUM_20G, + RTE_ETH_LANES_2, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_25G, + { + RTE_ETH_SPEED_NUM_25G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_40G_4LANES, + { + RTE_ETH_SPEED_NUM_40G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_50G, + { + RTE_ETH_SPEED_NUM_50G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_56G_4LANES, + { + RTE_ETH_SPEED_NUM_56G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_100G, + { + RTE_ETH_SPEED_NUM_100G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_200G_4LANES, + { + RTE_ETH_SPEED_NUM_200G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_400G_4LANES, + { + RTE_ETH_SPEED_NUM_400G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_10G_4LANES, + { + RTE_ETH_SPEED_NUM_10G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_50G_2LANES, + { + RTE_ETH_SPEED_NUM_50G, + RTE_ETH_LANES_2, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_100G_2LANES, + { + RTE_ETH_SPEED_NUM_100G, + RTE_ETH_LANES_2, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_100G_4LANES, + { + RTE_ETH_SPEED_NUM_100G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_200G_2LANES, + { + RTE_ETH_SPEED_NUM_200G, + RTE_ETH_LANES_2, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_400G_8LANES, + { + RTE_ETH_SPEED_NUM_400G, + RTE_ETH_LANES_8, + RTE_ETH_LINK_FULL_DUPLEX + } + } + }; + uint32_t i; + + for (i = 0; i < RTE_DIM(speed_capa_info_map); i++) + if (link_speed == speed_capa_info_map[i].speed_capa) { + capa_info->speed = speed_capa_info_map[i].capa_info.speed; + capa_info->lanes = speed_capa_info_map[i].capa_info.lanes; + capa_info->duplex = speed_capa_info_map[i].capa_info.duplex; + return 0; + } + + return -EINVAL; +} + const char * rte_eth_dev_tx_offload_name(uint64_t offload) { @@ -3111,8 +3358,9 @@ rte_eth_link_to_str(char *str, size_t len, const struct rte_eth_link *eth_link) if (eth_link->link_status == RTE_ETH_LINK_DOWN) ret = snprintf(str, len, "Link down"); else - ret = snprintf(str, len, "Link up at %s %s %s", + ret = snprintf(str, len, "Link up at %s %ulanes %s %s", rte_eth_link_speed_to_str(eth_link->link_speed), + eth_link->link_lanes, (eth_link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? "FDX" : "HDX", (eth_link->link_autoneg == RTE_ETH_LINK_AUTONEG) ? diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index 147257d6a2..3383ad8495 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -288,24 +288,40 @@ struct rte_eth_stats { /**@{@name Link speed capabilities * Device supported speeds bitmap flags */ -#define RTE_ETH_LINK_SPEED_AUTONEG 0 /**< Autonegotiate (all speeds) */ -#define RTE_ETH_LINK_SPEED_FIXED RTE_BIT32(0) /**< Disable autoneg (fixed speed) */ -#define RTE_ETH_LINK_SPEED_10M_HD RTE_BIT32(1) /**< 10 Mbps half-duplex */ -#define RTE_ETH_LINK_SPEED_10M RTE_BIT32(2) /**< 10 Mbps full-duplex */ -#define RTE_ETH_LINK_SPEED_100M_HD RTE_BIT32(3) /**< 100 Mbps half-duplex */ -#define RTE_ETH_LINK_SPEED_100M RTE_BIT32(4) /**< 100 Mbps full-duplex */ -#define RTE_ETH_LINK_SPEED_1G RTE_BIT32(5) /**< 1 Gbps */ -#define RTE_ETH_LINK_SPEED_2_5G RTE_BIT32(6) /**< 2.5 Gbps */ -#define RTE_ETH_LINK_SPEED_5G RTE_BIT32(7) /**< 5 Gbps */ -#define RTE_ETH_LINK_SPEED_10G RTE_BIT32(8) /**< 10 Gbps */ -#define RTE_ETH_LINK_SPEED_20G RTE_BIT32(9) /**< 20 Gbps */ -#define RTE_ETH_LINK_SPEED_25G RTE_BIT32(10) /**< 25 Gbps */ -#define RTE_ETH_LINK_SPEED_40G RTE_BIT32(11) /**< 40 Gbps */ -#define RTE_ETH_LINK_SPEED_50G RTE_BIT32(12) /**< 50 Gbps */ -#define RTE_ETH_LINK_SPEED_56G RTE_BIT32(13) /**< 56 Gbps */ -#define RTE_ETH_LINK_SPEED_100G RTE_BIT32(14) /**< 100 Gbps */ -#define RTE_ETH_LINK_SPEED_200G RTE_BIT32(15) /**< 200 Gbps */ -#define RTE_ETH_LINK_SPEED_400G RTE_BIT32(16) /**< 400 Gbps */ +#define RTE_ETH_LINK_SPEED_AUTONEG 0 /**< Autonegotiate (all speeds) */ +#define RTE_ETH_LINK_SPEED_FIXED RTE_BIT32(0) /**< Disable autoneg (fixed speed) */ +#define RTE_ETH_LINK_SPEED_10M_HD RTE_BIT32(1) /**< 10 Mbps half-duplex */ +#define RTE_ETH_LINK_SPEED_10M RTE_BIT32(2) /**< 10 Mbps full-duplex */ +#define RTE_ETH_LINK_SPEED_100M_HD RTE_BIT32(3) /**< 100 Mbps half-duplex */ +#define RTE_ETH_LINK_SPEED_100M RTE_BIT32(4) /**< 100 Mbps full-duplex */ +#define RTE_ETH_LINK_SPEED_1G RTE_BIT32(5) /**< 1 Gbps */ +#define RTE_ETH_LINK_SPEED_2_5G RTE_BIT32(6) /**< 2.5 Gbps */ +#define RTE_ETH_LINK_SPEED_5G RTE_BIT32(7) /**< 5 Gbps */ +#define RTE_ETH_LINK_SPEED_10G RTE_BIT32(8) /**< 10 Gbps */ +#define RTE_ETH_LINK_SPEED_20G_2LANES RTE_BIT32(9) /**< 20 Gbps 2lanes */ +#define RTE_ETH_LINK_SPEED_25G RTE_BIT32(10) /**< 25 Gbps */ +#define RTE_ETH_LINK_SPEED_40G_4LANES RTE_BIT32(11) /**< 40 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_50G RTE_BIT32(12) /**< 50 Gbps */ +#define RTE_ETH_LINK_SPEED_56G_4LANES RTE_BIT32(13) /**< 56 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_100G RTE_BIT32(14) /**< 100 Gbps */ +#define RTE_ETH_LINK_SPEED_200G_4LANES RTE_BIT32(15) /**< 200 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_400G_4LANES RTE_BIT32(16) /**< 400 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_10G_4LANES RTE_BIT32(17) /**< 10 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_50G_2LANES RTE_BIT32(18) /**< 50 Gbps 2 lanes */ +#define RTE_ETH_LINK_SPEED_100G_2LANES RTE_BIT32(19) /**< 100 Gbps 2 lanes */ +#define RTE_ETH_LINK_SPEED_100G_4LANES RTE_BIT32(20) /**< 100 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_200G_2LANES RTE_BIT32(21) /**< 200 Gbps 2lanes */ +#define RTE_ETH_LINK_SPEED_400G_8LANES RTE_BIT32(22) /**< 400 Gbps 8lanes */ +/**@}*/ + +/**@{@name Link speed capabilities + * Default lanes, use to compatible with earlier versions + */ +#define RTE_ETH_LINK_SPEED_20G RTE_ETH_LINK_SPEED_20G_2LANES +#define RTE_ETH_LINK_SPEED_40G RTE_ETH_LINK_SPEED_40G_4LANES +#define RTE_ETH_LINK_SPEED_56G RTE_ETH_LINK_SPEED_56G_4LANES +#define RTE_ETH_LINK_SPEED_200G RTE_ETH_LINK_SPEED_200G_4LANES +#define RTE_ETH_LINK_SPEED_400G RTE_ETH_LINK_SPEED_400G_4LANES /**@}*/ /**@{@name Link speed @@ -329,6 +345,25 @@ struct rte_eth_stats { #define RTE_ETH_SPEED_NUM_UNKNOWN UINT32_MAX /**< Unknown */ /**@}*/ +/**@{@name Link lane number + * Ethernet lane number + */ +#define RTE_ETH_LANES_UNKNOWN 0 /**< Unknown */ +#define RTE_ETH_LANES_1 1 /**< 1 lanes */ +#define RTE_ETH_LANES_2 2 /**< 2 lanes */ +#define RTE_ETH_LANES_4 4 /**< 4 lanes */ +#define RTE_ETH_LANES_8 8 /**< 8 lanes */ +/**@}*/ + +/** + * A structure used to store information of link speed capability. + */ +struct rte_eth_speed_capa_info { + uint32_t speed; /**< RTE_ETH_SPEED_NUM_ */ + uint8_t lanes; /**< RTE_ETH_LANES_ */ + uint8_t duplex; /**< RTE_ETH_LANES_ */ +}; + /** * A structure used to retrieve link-level information of an Ethernet port. */ @@ -338,6 +373,7 @@ struct __rte_aligned(8) rte_eth_link { /**< aligned for atomic64 read/write */ uint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */ uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */ + uint16_t link_lanes : 8; /**< RTE_ETH_LANES_ */ }; /**@{@name Link negotiation @@ -1641,6 +1677,13 @@ struct rte_eth_conf { #define RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP RTE_BIT64(3) /** Device supports keeping shared flow objects across restart. */ #define RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP RTE_BIT64(4) +/** + * Device supports setting lanes. When the driver does not support setting lane, + * the lane in the speed capability reported by the driver may be incorrect, + * for example, if the driver reports that the 200G speed capability + * (@see RTE_ETH_LINK_SPEED_200G), the number of used lanes may be 2 or 4. + */ +#define RTE_ETH_DEV_CAPA_SETTING_LANES RTE_BIT64(4) /**@}*/ /* @@ -2301,12 +2344,30 @@ uint16_t rte_eth_dev_count_total(void); * * @param speed * Numerical speed value in Mbps + * @param lanes + * RTE_ETH_LANES_x * @param duplex * RTE_ETH_LINK_[HALF/FULL]_DUPLEX (only for 10/100M speeds) * @return * 0 if the speed cannot be mapped */ -uint32_t rte_eth_speed_bitflag(uint32_t speed, int duplex); +uint32_t rte_eth_speed_bitflag(uint32_t speed, uint8_t lanes, int duplex); + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Convert bitmap flag to the struct of link speed capability info + * + * @param link_speed + * speed bitmap (RTE_ETH_LINK_SPEED_) + * @return + * - (0) if successful. + * - (-EINVAL) if bad parameter. + */ +__rte_experimental +int rte_eth_speed_capa_to_info(uint32_t link_speed, + struct rte_eth_speed_capa_info *capa_info); /** * Get RTE_ETH_RX_OFFLOAD_* flag name. diff --git a/lib/ethdev/version.map b/lib/ethdev/version.map index 79f6f5293b..0e9c560920 100644 --- a/lib/ethdev/version.map +++ b/lib/ethdev/version.map @@ -169,6 +169,12 @@ DPDK_24 { local: *; }; +DPDK_25 { + global: + + rte_eth_speed_bitflag; +} DPDK_24; + EXPERIMENTAL { global: @@ -320,6 +326,7 @@ EXPERIMENTAL { # added in 24.03 __rte_eth_trace_tx_queue_count; rte_eth_find_rss_algo; + rte_eth_speed_capa_to_info; rte_flow_async_update_resized; rte_flow_calc_encap_hash; rte_flow_template_table_resizable; From patchwork Tue Mar 12 07:52:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dengdui Huang X-Patchwork-Id: 138204 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E148643C8E; Tue, 12 Mar 2024 08:53:01 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 39D11406FF; Tue, 12 Mar 2024 08:52:47 +0100 (CET) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id 09480410E3 for ; Tue, 12 Mar 2024 08:52:41 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.162.112]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4Tv5Qs0Dhcz2BfkR; Tue, 12 Mar 2024 15:50:13 +0800 (CST) Received: from dggpeml500011.china.huawei.com (unknown [7.185.36.84]) by mail.maildlp.com (Postfix) with ESMTPS id 51AA4140485; Tue, 12 Mar 2024 15:52:39 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Tue, 12 Mar 2024 15:52:39 +0800 From: Dengdui Huang To: CC: , , , , , , , , Subject: [PATCH 2/3] net/hns3: support setting lanes Date: Tue, 12 Mar 2024 15:52:37 +0800 Message-ID: <20240312075238.3319480-3-huangdengdui@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240312075238.3319480-1-huangdengdui@huawei.com> References: <20240312075238.3319480-1-huangdengdui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500011.china.huawei.com (7.185.36.84) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some speeds can be achieved with different number of lanes. For example, 100Gbps can be achieved using two lanes of 50Gbps or four lanes of 25Gbps. When use different lanes, the port cannot be up. This patch add support for setting lanes and report lanes. Signed-off-by: Dengdui Huang --- doc/guides/rel_notes/release_24_03.rst | 2 + drivers/net/hns3/hns3_cmd.h | 15 ++-- drivers/net/hns3/hns3_common.c | 3 +- drivers/net/hns3/hns3_ethdev.c | 111 +++++++++++-------------- drivers/net/hns3/hns3_ethdev.h | 2 + 5 files changed, 66 insertions(+), 67 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 75d93ee965..c17334ac25 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -180,6 +180,8 @@ New Features * Added power-saving during polling within the ``rte_event_dequeue_burst()`` API. * Added support for DMA adapter. +* **Added setting lanes for hns3 PF driver.** + * This feature add support for setting lanes and report lanes. Removed Items ------------- diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index 79a8c1edad..31ff7b35d8 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -753,7 +753,9 @@ struct hns3_config_mac_mode_cmd { struct hns3_config_mac_speed_dup_cmd { uint8_t speed_dup; uint8_t mac_change_fec_en; - uint8_t rsv[22]; + uint8_t rsv[4]; + uint8_t lanes; + uint8_t rsv1[17]; }; #define HNS3_TQP_ENABLE_B 0 @@ -789,12 +791,15 @@ struct hns3_sfp_type { #define HNS3_FIBER_LINK_SPEED_1G_BIT BIT(0) #define HNS3_FIBER_LINK_SPEED_10G_BIT BIT(1) #define HNS3_FIBER_LINK_SPEED_25G_BIT BIT(2) -#define HNS3_FIBER_LINK_SPEED_50G_BIT BIT(3) -#define HNS3_FIBER_LINK_SPEED_100G_BIT BIT(4) +#define HNS3_FIBER_LINK_SPEED_50G_R2_BIT BIT(3) +#define HNS3_FIBER_LINK_SPEED_100G_R4_BIT BIT(4) #define HNS3_FIBER_LINK_SPEED_40G_BIT BIT(5) #define HNS3_FIBER_LINK_SPEED_100M_BIT BIT(6) #define HNS3_FIBER_LINK_SPEED_10M_BIT BIT(7) -#define HNS3_FIBER_LINK_SPEED_200G_BIT BIT(8) +#define HNS3_FIBER_LINK_SPEED_200G_EXT_BIT BIT(8) +#define HNS3_FIBER_LINK_SPEED_50G_R1_BIT BIT(9) +#define HNS3_FIBER_LINK_SPEED_100G_R2_BIT BIT(10) +#define HNS3_FIBER_LINK_SPEED_200G_R4_BIT BIT(11) #define HNS3_FIBER_FEC_AUTO_BIT BIT(0) #define HNS3_FIBER_FEC_BASER_BIT BIT(1) @@ -823,7 +828,7 @@ struct hns3_sfp_info_cmd { uint32_t supported_speed; /* speed supported by current media */ uint32_t module_type; uint8_t fec_ability; /* supported fec modes, see HNS3_FIBER_FEC_XXX_BIT */ - uint8_t rsv0; + uint8_t lanes; uint8_t pause_status; uint8_t rsv1[5]; }; diff --git a/drivers/net/hns3/hns3_common.c b/drivers/net/hns3/hns3_common.c index 28c26b049c..cccb441780 100644 --- a/drivers/net/hns3/hns3_common.c +++ b/drivers/net/hns3/hns3_common.c @@ -92,7 +92,8 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM; info->dev_capa = RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP | - RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP; + RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP | + RTE_ETH_DEV_CAPA_SETTING_LANES; if (hns3_dev_get_support(hw, INDEP_TXRX)) info->dev_capa |= RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index ecd3b2ef64..8a19c3ddd9 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2235,12 +2235,16 @@ hns3_get_firber_port_speed_capa(uint32_t supported_speed) speed_capa |= RTE_ETH_LINK_SPEED_25G; if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT) speed_capa |= RTE_ETH_LINK_SPEED_40G; - if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT) + if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_R1_BIT) speed_capa |= RTE_ETH_LINK_SPEED_50G; - if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT) - speed_capa |= RTE_ETH_LINK_SPEED_100G; - if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT) - speed_capa |= RTE_ETH_LINK_SPEED_200G; + if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_R2_BIT) + speed_capa |= RTE_ETH_LINK_SPEED_50G_2LANES; + if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_R4_BIT) + speed_capa |= RTE_ETH_LINK_SPEED_100G_4LANES; + if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_R2_BIT) + speed_capa |= RTE_ETH_LINK_SPEED_100G_2LANES; + if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_R4_BIT) + speed_capa |= RTE_ETH_LINK_SPEED_200G_4LANES; return speed_capa; } @@ -2308,6 +2312,7 @@ hns3_setup_linkstatus(struct rte_eth_dev *eth_dev, if (!mac->link_status) new_link->link_speed = RTE_ETH_SPEED_NUM_NONE; + new_link->link_lanes = mac->link_lanes; new_link->link_duplex = mac->link_duplex; new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; new_link->link_autoneg = mac->link_autoneg; @@ -2934,7 +2939,8 @@ hns3_map_tqp(struct hns3_hw *hw) } static int -hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) +hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t lanes, + uint8_t duplex) { struct hns3_config_mac_speed_dup_cmd *req; struct hns3_cmd_desc desc; @@ -2989,6 +2995,7 @@ hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) } hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); + req->lanes = lanes; ret = hns3_cmd_send(hw, &desc, 1); if (ret) @@ -3643,7 +3650,9 @@ hns3_mac_init(struct hns3_hw *hw) pf->support_sfp_query = true; mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; - ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); + /* If lane is set to 0, the firmware selects the default lane.*/ + ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, 0, + mac->link_duplex); if (ret) { PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); return ret; @@ -4052,6 +4061,7 @@ hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info) return 0; mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed); + mac_info->link_lanes = resp->lanes; /* * if resp->supported_speed is 0, it means it's an old version * firmware, do not update these params. @@ -4088,16 +4098,18 @@ hns3_check_speed_dup(uint8_t duplex, uint32_t speed) } static int -hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) +hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t lanes, + uint8_t duplex) { struct hns3_mac *mac = &hw->mac; int ret; duplex = hns3_check_speed_dup(duplex, speed); - if (mac->link_speed == speed && mac->link_duplex == duplex) + if (mac->link_speed == speed && mac->link_lanes == lanes && + mac->link_duplex == duplex) return 0; - ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); + ret = hns3_cfg_mac_speed_dup_hw(hw, speed, lanes, duplex); if (ret) return ret; @@ -4106,6 +4118,7 @@ hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) return ret; mac->link_speed = speed; + mac->link_lanes = lanes; mac->link_duplex = duplex; return 0; @@ -4150,6 +4163,7 @@ hns3_update_fiber_link_info(struct hns3_hw *hw) } mac->link_speed = mac_info.link_speed; + mac->link_lanes = mac_info.link_lanes; mac->supported_speed = mac_info.supported_speed; mac->support_autoneg = mac_info.support_autoneg; mac->link_autoneg = mac_info.link_autoneg; @@ -4161,7 +4175,7 @@ hns3_update_fiber_link_info(struct hns3_hw *hw) } /* Config full duplex for SFP */ - return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed, + return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed, mac_info.link_lanes, RTE_ETH_LINK_FULL_DUPLEX); } @@ -4512,11 +4526,11 @@ hns3_set_firber_default_support_speed(struct hns3_hw *hw) case RTE_ETH_SPEED_NUM_40G: return HNS3_FIBER_LINK_SPEED_40G_BIT; case RTE_ETH_SPEED_NUM_50G: - return HNS3_FIBER_LINK_SPEED_50G_BIT; + return HNS3_FIBER_LINK_SPEED_50G_R2_BIT; case RTE_ETH_SPEED_NUM_100G: - return HNS3_FIBER_LINK_SPEED_100G_BIT; + return HNS3_FIBER_LINK_SPEED_100G_R4_BIT; case RTE_ETH_SPEED_NUM_200G: - return HNS3_FIBER_LINK_SPEED_200G_BIT; + return HNS3_FIBER_LINK_SPEED_200G_R4_BIT; default: hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed); return 0; @@ -4773,13 +4787,19 @@ hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds) speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT; break; case RTE_ETH_LINK_SPEED_50G: - speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT; + speed_bit = HNS3_FIBER_LINK_SPEED_50G_R1_BIT; break; - case RTE_ETH_LINK_SPEED_100G: - speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT; + case RTE_ETH_LINK_SPEED_50G_2LANES: + speed_bit = HNS3_FIBER_LINK_SPEED_50G_R2_BIT; break; - case RTE_ETH_LINK_SPEED_200G: - speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT; + case RTE_ETH_LINK_SPEED_100G_4LANES: + speed_bit = HNS3_FIBER_LINK_SPEED_100G_R4_BIT; + break; + case RTE_ETH_LINK_SPEED_100G_2LANES: + speed_bit = HNS3_FIBER_LINK_SPEED_100G_R2_BIT; + break; + case RTE_ETH_LINK_SPEED_200G_4LANES: + speed_bit = HNS3_FIBER_LINK_SPEED_200G_R4_BIT; break; default: speed_bit = 0; @@ -4810,45 +4830,6 @@ hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds) return 0; } -static uint32_t -hns3_get_link_speed(uint32_t link_speeds) -{ - uint32_t speed = RTE_ETH_SPEED_NUM_NONE; - - if (link_speeds & RTE_ETH_LINK_SPEED_10M || - link_speeds & RTE_ETH_LINK_SPEED_10M_HD) - speed = RTE_ETH_SPEED_NUM_10M; - if (link_speeds & RTE_ETH_LINK_SPEED_100M || - link_speeds & RTE_ETH_LINK_SPEED_100M_HD) - speed = RTE_ETH_SPEED_NUM_100M; - if (link_speeds & RTE_ETH_LINK_SPEED_1G) - speed = RTE_ETH_SPEED_NUM_1G; - if (link_speeds & RTE_ETH_LINK_SPEED_10G) - speed = RTE_ETH_SPEED_NUM_10G; - if (link_speeds & RTE_ETH_LINK_SPEED_25G) - speed = RTE_ETH_SPEED_NUM_25G; - if (link_speeds & RTE_ETH_LINK_SPEED_40G) - speed = RTE_ETH_SPEED_NUM_40G; - if (link_speeds & RTE_ETH_LINK_SPEED_50G) - speed = RTE_ETH_SPEED_NUM_50G; - if (link_speeds & RTE_ETH_LINK_SPEED_100G) - speed = RTE_ETH_SPEED_NUM_100G; - if (link_speeds & RTE_ETH_LINK_SPEED_200G) - speed = RTE_ETH_SPEED_NUM_200G; - - return speed; -} - -static uint8_t -hns3_get_link_duplex(uint32_t link_speeds) -{ - if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) || - (link_speeds & RTE_ETH_LINK_SPEED_100M_HD)) - return RTE_ETH_LINK_HALF_DUPLEX; - else - return RTE_ETH_LINK_FULL_DUPLEX; -} - static int hns3_set_copper_port_link_speed(struct hns3_hw *hw, struct hns3_set_link_speed_cfg *cfg) @@ -4939,7 +4920,7 @@ hns3_set_fiber_port_link_speed(struct hns3_hw *hw, return 0; } - return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex); + return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->lanes, cfg->duplex); } const char * @@ -4979,15 +4960,23 @@ hns3_set_port_link_speed(struct hns3_hw *hw, static int hns3_apply_link_speed(struct hns3_hw *hw) { + struct rte_eth_speed_capa_info capa_info = { 0 }; struct rte_eth_conf *conf = &hw->data->dev_conf; struct hns3_set_link_speed_cfg cfg; + int ret; memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg)); cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ? RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED; if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) { - cfg.speed = hns3_get_link_speed(conf->link_speeds); - cfg.duplex = hns3_get_link_duplex(conf->link_speeds); + ret = rte_eth_speed_capa_to_info(conf->link_speeds, &capa_info); + if (ret) { + hns3_err(hw, "speed capability error, ret = %d", ret); + return ret; + } + cfg.speed = capa_info.speed; + cfg.lanes = capa_info.lanes; + cfg.duplex = capa_info.duplex; } return hns3_set_port_link_speed(hw, &cfg); diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 12d8299def..eae7f4bb12 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -168,6 +168,7 @@ struct hns3_set_link_speed_cfg { uint32_t speed; uint8_t duplex : 1; uint8_t autoneg : 1; + uint8_t lanes : 6; }; /* mac media type */ @@ -190,6 +191,7 @@ struct hns3_mac { uint8_t link_autoneg : 1; /* RTE_ETH_LINK_[AUTONEG/FIXED] */ uint8_t link_status : 1; /* RTE_ETH_LINK_[DOWN/UP] */ uint32_t link_speed; /* RTE_ETH_SPEED_NUM_ */ + uint8_t link_lanes; /* RTE_ETH_LANES_ */ /* * Some firmware versions support only the SFP speed query. In addition * to the SFP speed query, some firmware supports the query of the speed From patchwork Tue Mar 12 07:52:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dengdui Huang X-Patchwork-Id: 138203 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D081043C8E; Tue, 12 Mar 2024 08:52:54 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EEBA9427E0; Tue, 12 Mar 2024 08:52:45 +0100 (CET) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id ECBD440EE3 for ; Tue, 12 Mar 2024 08:52:40 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Tv5Qs2rYWz1h20D; Tue, 12 Mar 2024 15:50:13 +0800 (CST) Received: from dggpeml500011.china.huawei.com (unknown [7.185.36.84]) by mail.maildlp.com (Postfix) with ESMTPS id 7BBBF14040F; Tue, 12 Mar 2024 15:52:39 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Tue, 12 Mar 2024 15:52:39 +0800 From: Dengdui Huang To: CC: , , , , , , , , Subject: [PATCH 3/3] app/testpmd: support setting lanes Date: Tue, 12 Mar 2024 15:52:38 +0800 Message-ID: <20240312075238.3319480-4-huangdengdui@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240312075238.3319480-1-huangdengdui@huawei.com> References: <20240312075238.3319480-1-huangdengdui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500011.china.huawei.com (7.185.36.84) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Extended speed command for setting lane number and Show info print lane number. Signed-off-by: Dengdui Huang --- app/test-pmd/cmdline.c | 110 +++++++++++--------- app/test-pmd/config.c | 60 +++++++---- doc/guides/rel_notes/release_24_03.rst | 1 + doc/guides/testpmd_app_ug/testpmd_funcs.rst | 3 +- 4 files changed, 103 insertions(+), 71 deletions(-) diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c index f521a1fe9e..e66daf4bba 100644 --- a/app/test-pmd/cmdline.c +++ b/app/test-pmd/cmdline.c @@ -1356,15 +1356,20 @@ struct cmd_config_speed_all { cmdline_fixed_string_t keyword; cmdline_fixed_string_t all; cmdline_fixed_string_t item1; + cmdline_fixed_string_t lanes_item; cmdline_fixed_string_t item2; cmdline_fixed_string_t value1; + uint8_t lanes_value; cmdline_fixed_string_t value2; }; static int -parse_and_check_speed_duplex(char *speedstr, char *duplexstr, uint32_t *speed) +parse_and_check_speed_duplex(char *speedstr, uint8_t lanes, char *duplexstr, + uint32_t *speed) { + uint32_t speed_num; + char *endptr; int duplex; if (!strcmp(duplexstr, "half")) { @@ -1378,47 +1383,22 @@ parse_and_check_speed_duplex(char *speedstr, char *duplexstr, uint32_t *speed) return -1; } - if (!strcmp(speedstr, "10")) { - *speed = (duplex == RTE_ETH_LINK_HALF_DUPLEX) ? - RTE_ETH_LINK_SPEED_10M_HD : RTE_ETH_LINK_SPEED_10M; - } else if (!strcmp(speedstr, "100")) { - *speed = (duplex == RTE_ETH_LINK_HALF_DUPLEX) ? - RTE_ETH_LINK_SPEED_100M_HD : RTE_ETH_LINK_SPEED_100M; - } else { - if (duplex != RTE_ETH_LINK_FULL_DUPLEX) { - fprintf(stderr, "Invalid speed/duplex parameters\n"); - return -1; - } - if (!strcmp(speedstr, "1000")) { - *speed = RTE_ETH_LINK_SPEED_1G; - } else if (!strcmp(speedstr, "2500")) { - *speed = RTE_ETH_LINK_SPEED_2_5G; - } else if (!strcmp(speedstr, "5000")) { - *speed = RTE_ETH_LINK_SPEED_5G; - } else if (!strcmp(speedstr, "10000")) { - *speed = RTE_ETH_LINK_SPEED_10G; - } else if (!strcmp(speedstr, "25000")) { - *speed = RTE_ETH_LINK_SPEED_25G; - } else if (!strcmp(speedstr, "40000")) { - *speed = RTE_ETH_LINK_SPEED_40G; - } else if (!strcmp(speedstr, "50000")) { - *speed = RTE_ETH_LINK_SPEED_50G; - } else if (!strcmp(speedstr, "100000")) { - *speed = RTE_ETH_LINK_SPEED_100G; - } else if (!strcmp(speedstr, "200000")) { - *speed = RTE_ETH_LINK_SPEED_200G; - } else if (!strcmp(speedstr, "400000")) { - *speed = RTE_ETH_LINK_SPEED_400G; - } else if (!strcmp(speedstr, "auto")) { - *speed = RTE_ETH_LINK_SPEED_AUTONEG; - } else { - fprintf(stderr, "Unknown speed parameter\n"); - return -1; - } + if (!strcmp(speedstr, "auto")) { + *speed = RTE_ETH_LINK_SPEED_AUTONEG; + return 0; } - if (*speed != RTE_ETH_LINK_SPEED_AUTONEG) - *speed |= RTE_ETH_LINK_SPEED_FIXED; + speed_num = strtol(speedstr, &endptr, 10); + if (*endptr != '\0') { + fprintf(stderr, "Unknown speed parameter\n"); + return -1; + } + + *speed = rte_eth_speed_bitflag(speed_num, lanes, duplex); + if (*speed == 0) { + fprintf(stderr, "param error\n"); + return -1; + } return 0; } @@ -1429,19 +1409,27 @@ cmd_config_speed_all_parsed(void *parsed_result, __rte_unused void *data) { struct cmd_config_speed_all *res = parsed_result; + struct rte_eth_dev_info dev_info; uint32_t link_speed; portid_t pid; + int ret; if (!all_ports_stopped()) { fprintf(stderr, "Please stop all ports first\n"); return; } - if (parse_and_check_speed_duplex(res->value1, res->value2, - &link_speed) < 0) + if (parse_and_check_speed_duplex(res->value1, res->lanes_value, + res->value2, &link_speed) < 0) return; RTE_ETH_FOREACH_DEV(pid) { + ret = eth_dev_info_get_print_err(pid, &dev_info); + if (ret != 0) + return; + if ((dev_info.dev_capa & RTE_ETH_DEV_CAPA_SETTING_LANES) == 0) + fprintf(stderr, "The setting lane may not take effect because " + "the port (%u) does not support it\n", pid); ports[pid].dev_conf.link_speeds = link_speed; } @@ -1460,6 +1448,11 @@ static cmdline_parse_token_string_t cmd_config_speed_all_item1 = static cmdline_parse_token_string_t cmd_config_speed_all_value1 = TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, value1, "10#100#1000#2500#5000#10000#25000#40000#50000#100000#200000#400000#auto"); +static cmdline_parse_token_string_t cmd_config_speed_all_lanes_item = + TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, lanes_item, "lanes"); +static cmdline_parse_token_num_t cmd_config_speed_all_lanes_value = + TOKEN_NUM_INITIALIZER(struct cmd_config_speed_all, lanes_value, + RTE_UINT8); static cmdline_parse_token_string_t cmd_config_speed_all_item2 = TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, item2, "duplex"); static cmdline_parse_token_string_t cmd_config_speed_all_value2 = @@ -1470,14 +1463,16 @@ static cmdline_parse_inst_t cmd_config_speed_all = { .f = cmd_config_speed_all_parsed, .data = NULL, .help_str = "port config all speed " - "10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto duplex " - "half|full|auto", + "10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto" + " lanes 1|2|4|8 duplex half|full|auto", .tokens = { (void *)&cmd_config_speed_all_port, (void *)&cmd_config_speed_all_keyword, (void *)&cmd_config_speed_all_all, (void *)&cmd_config_speed_all_item1, (void *)&cmd_config_speed_all_value1, + (void *)&cmd_config_speed_all_lanes_item, + (void *)&cmd_config_speed_all_lanes_value, (void *)&cmd_config_speed_all_item2, (void *)&cmd_config_speed_all_value2, NULL, @@ -1490,8 +1485,10 @@ struct cmd_config_speed_specific { cmdline_fixed_string_t keyword; portid_t id; cmdline_fixed_string_t item1; + cmdline_fixed_string_t lanes_item; cmdline_fixed_string_t item2; cmdline_fixed_string_t value1; + uint8_t lanes_value; cmdline_fixed_string_t value2; }; @@ -1501,7 +1498,9 @@ cmd_config_speed_specific_parsed(void *parsed_result, __rte_unused void *data) { struct cmd_config_speed_specific *res = parsed_result; + struct rte_eth_dev_info dev_info; uint32_t link_speed; + int ret; if (port_id_is_invalid(res->id, ENABLED_WARN)) return; @@ -1511,8 +1510,15 @@ cmd_config_speed_specific_parsed(void *parsed_result, return; } - if (parse_and_check_speed_duplex(res->value1, res->value2, - &link_speed) < 0) + ret = eth_dev_info_get_print_err(res->id, &dev_info); + if (ret != 0) + return; + if ((dev_info.dev_capa & RTE_ETH_DEV_CAPA_SETTING_LANES) == 0) + fprintf(stderr, "The setting lane may not take effect because " + "the port (%d) does not support it\n", res->id); + + if (parse_and_check_speed_duplex(res->value1, res->lanes_value, + res->value2, &link_speed) < 0) return; ports[res->id].dev_conf.link_speeds = link_speed; @@ -1535,6 +1541,12 @@ static cmdline_parse_token_string_t cmd_config_speed_specific_item1 = static cmdline_parse_token_string_t cmd_config_speed_specific_value1 = TOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, value1, "10#100#1000#2500#5000#10000#25000#40000#50000#100000#200000#400000#auto"); +static cmdline_parse_token_string_t cmd_config_speed_specific_lanes_item = + TOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, lanes_item, + "lanes"); +static cmdline_parse_token_num_t cmd_config_speed_specific_lanes_value = + TOKEN_NUM_INITIALIZER(struct cmd_config_speed_specific, lanes_value, + RTE_UINT8); static cmdline_parse_token_string_t cmd_config_speed_specific_item2 = TOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, item2, "duplex"); @@ -1546,14 +1558,16 @@ static cmdline_parse_inst_t cmd_config_speed_specific = { .f = cmd_config_speed_specific_parsed, .data = NULL, .help_str = "port config speed " - "10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto duplex " - "half|full|auto", + "10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto" + " lanes 1|2|4|8 duplex half|full|auto", .tokens = { (void *)&cmd_config_speed_specific_port, (void *)&cmd_config_speed_specific_keyword, (void *)&cmd_config_speed_specific_id, (void *)&cmd_config_speed_specific_item1, (void *)&cmd_config_speed_specific_value1, + (void *)&cmd_config_speed_specific_lanes_item, + (void *)&cmd_config_speed_specific_lanes_value, (void *)&cmd_config_speed_specific_item2, (void *)&cmd_config_speed_specific_value2, NULL, diff --git a/app/test-pmd/config.c b/app/test-pmd/config.c index 968d2164ab..c104327878 100644 --- a/app/test-pmd/config.c +++ b/app/test-pmd/config.c @@ -587,39 +587,51 @@ device_infos_display_speeds(uint32_t speed_capa) if (speed_capa == RTE_ETH_LINK_SPEED_AUTONEG) printf(" Autonegotiate (all speeds)"); if (speed_capa & RTE_ETH_LINK_SPEED_FIXED) - printf(" Disable autonegotiate (fixed speed) "); + printf(" Disable autonegotiate (fixed speed) /"); if (speed_capa & RTE_ETH_LINK_SPEED_10M_HD) - printf(" 10 Mbps half-duplex "); + printf(" 10Mbps_1lane_half-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_10M) - printf(" 10 Mbps full-duplex "); + printf(" 10Mbps_1lane_full-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_100M_HD) - printf(" 100 Mbps half-duplex "); + printf(" 100Mbps_lane_half-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_100M) - printf(" 100 Mbps full-duplex "); + printf(" 100Mbps_1lane_full-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_1G) - printf(" 1 Gbps "); + printf(" 1Gbps_1lane_full-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_2_5G) - printf(" 2.5 Gbps "); + printf(" 2.5Gbps_1lane_full-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_5G) - printf(" 5 Gbps "); + printf(" 5Gbps_1lane_full-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_10G) - printf(" 10 Gbps "); - if (speed_capa & RTE_ETH_LINK_SPEED_20G) - printf(" 20 Gbps "); + printf(" 10Gbps_1lane_full-duplex /"); + if (speed_capa & RTE_ETH_LINK_SPEED_10G_4LANES) + printf(" 10Gbps_4lane_full-duplex /"); + if (speed_capa & RTE_ETH_LINK_SPEED_20G_2LANES) + printf(" 20Gbps_2lane_full-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_25G) - printf(" 25 Gbps "); - if (speed_capa & RTE_ETH_LINK_SPEED_40G) - printf(" 40 Gbps "); + printf(" 25Gbps_1lane_full-duplex /"); + if (speed_capa & RTE_ETH_LINK_SPEED_40G_4LANES) + printf(" 40Gbps_4lane_full-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_50G) - printf(" 50 Gbps "); - if (speed_capa & RTE_ETH_LINK_SPEED_56G) - printf(" 56 Gbps "); + printf(" 50Gbps_1lane_full-duplex /"); + if (speed_capa & RTE_ETH_LINK_SPEED_50G_2LANES) + printf(" 50Gbps_2lane_full-duplex /"); + if (speed_capa & RTE_ETH_LINK_SPEED_56G_4LANES) + printf(" 56Gbps_4lane_full-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_100G) - printf(" 100 Gbps "); - if (speed_capa & RTE_ETH_LINK_SPEED_200G) - printf(" 200 Gbps "); - if (speed_capa & RTE_ETH_LINK_SPEED_400G) - printf(" 400 Gbps "); + printf(" 100Gbps_1lane_full-duplex /"); + if (speed_capa & RTE_ETH_LINK_SPEED_100G_2LANES) + printf(" 100Gbps_2lane_full-duplex /"); + if (speed_capa & RTE_ETH_LINK_SPEED_100G_4LANES) + printf(" 100Gbps_4lane_full-duplex /"); + if (speed_capa & RTE_ETH_LINK_SPEED_200G_4LANES) + printf(" 200Gbps_4lane_full-duplex /"); + if (speed_capa & RTE_ETH_LINK_SPEED_200G_2LANES) + printf(" 200Gbps_2lane_full-duplex /"); + if (speed_capa & RTE_ETH_LINK_SPEED_400G_4LANES) + printf(" 400Gbps_4lane_full-duplex /"); + if (speed_capa & RTE_ETH_LINK_SPEED_400G_8LANES) + printf(" 400Gbps_8lane_full-duplex /"); } void @@ -828,6 +840,10 @@ port_infos_display(portid_t port_id) printf("\nLink status: %s\n", (link.link_status) ? ("up") : ("down")); printf("Link speed: %s\n", rte_eth_link_speed_to_str(link.link_speed)); + if (link.link_lanes == 0) + printf("Link lanes: unknown\n"); + else + printf("Link lanes: %u\n", link.link_lanes); printf("Link duplex: %s\n", (link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? ("full-duplex") : ("half-duplex")); printf("Autoneg status: %s\n", (link.link_autoneg == RTE_ETH_LINK_AUTONEG) ? diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index c17334ac25..46aceeee93 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -79,6 +79,7 @@ New Features * **Support setting lanes for ethdev.** * Support setting lanes by extended ``RTE_ETH_LINK_SPEED_*``. * Added function to convert bitmap flag to the struct of link speed info. + ``rte_eth_speed_capa_to_info()`` * **Added hash calculation of an encapsulated packet as done by the HW.** diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst index 2fbf9220d8..087f7fe853 100644 --- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst +++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst @@ -190,6 +190,7 @@ For example: memory allocation on the socket: 0 Link status: up Link speed: 40000 Mbps + Link lanes: 4 Link duplex: full-duplex Promiscuous mode: enabled Allmulticast mode: disabled @@ -2065,7 +2066,7 @@ port config - speed Set the speed and duplex mode for all ports or a specific port:: testpmd> port config (port_id|all) speed (10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto) \ - duplex (half|full|auto) + lanes 1|2|4|8 duplex (half|full|auto) port config - queues/descriptors ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~