From patchwork Fri Mar 8 05:37:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ma, WenwuX" X-Patchwork-Id: 138117 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A5A2443B6A; Fri, 8 Mar 2024 06:48:47 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7178F402BB; Fri, 8 Mar 2024 06:48:47 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by mails.dpdk.org (Postfix) with ESMTP id 2FA7240298; Fri, 8 Mar 2024 06:48:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709876927; x=1741412927; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=TOTQmLi5s4JxX29vaLW2+YB6lVjXhdOuPB2P3DLI/gI=; b=fKESIuS31v5QmESlRCE1G7KZpU3fEGPI7XeSTzXwIwUAHPqPWq42c9Xc 6pRstx4G8Ex4+zRBjUUqoJHAcqb6oUPbnvhXWF5qVdOUEYvlc2zjgNHAq InYJbFuHufTJje1sC65RbIgZyDfsrfuBpdOAjw7LXBtFQzDsq8kRadJMY /zvNrRk3gKV4BtiGkCyK0V7lWFSO+IL0TPTaPMWIUBsrbMibbq/v+rUSq PBh1VZmsxK3CpAKmS46haV2Na91IKilV+Ll4pI2Orpwo8ja6HYxS6+RhE YSkEPUuej32LKkpZiRd8i/D4xVO5Ur7L+UXUhdT6B01tRZ2VkyLIkNP2w A==; X-IronPort-AV: E=McAfee;i="6600,9927,11006"; a="22109499" X-IronPort-AV: E=Sophos;i="6.07,108,1708416000"; d="scan'208";a="22109499" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2024 21:48:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,108,1708416000"; d="scan'208";a="15031911" Received: from unknown (HELO localhost.localdomain) ([10.239.252.55]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2024 21:48:42 -0800 From: Wenwu Ma To: dev@dpdk.org, fengchengwen@huawei.com Cc: songx.jiale@intel.com, Wenwu Ma , stable@dpdk.org Subject: [PATCH] dmadev: fix structure alignment Date: Fri, 8 Mar 2024 13:37:11 +0800 Message-Id: <20240308053711.1260154-1-wenwux.ma@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The structure rte_dma_dev needs cacheline alignment, but the return value of malloc may not be aligned to the cacheline. Therefore, extra memory is applied for realignment. Fixes: b36970f2e13e ("dmadev: introduce DMA device library") Cc: stable@dpdk.org Signed-off-by: Wenwu Ma Acked-by: Chengwen Feng --- lib/dmadev/rte_dmadev.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/lib/dmadev/rte_dmadev.c b/lib/dmadev/rte_dmadev.c index 5953a77bd6..61e106d574 100644 --- a/lib/dmadev/rte_dmadev.c +++ b/lib/dmadev/rte_dmadev.c @@ -160,15 +160,25 @@ static int dma_dev_data_prepare(void) { size_t size; + void *ptr; if (rte_dma_devices != NULL) return 0; - size = dma_devices_max * sizeof(struct rte_dma_dev); - rte_dma_devices = malloc(size); - if (rte_dma_devices == NULL) + /* The dma device object is expected to align cacheline, but + * the return value of malloc may not be aligned to the cache line. + * Therefore, extra memory is applied for realignment. + * note: We do not call posix_memalign/aligned_alloc because it is + * version dependent on libc. + */ + size = dma_devices_max * sizeof(struct rte_dma_dev) + + RTE_CACHE_LINE_SIZE; + ptr = malloc(size); + if (ptr == NULL) return -ENOMEM; - memset(rte_dma_devices, 0, size); + memset(ptr, 0, size); + + rte_dma_devices = RTE_PTR_ALIGN(ptr, RTE_CACHE_LINE_SIZE); return 0; }