From patchwork Thu Mar 7 03:02:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 138074 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A6B4943B5E; Thu, 7 Mar 2024 04:07:19 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D5C1342D9D; Thu, 7 Mar 2024 04:07:09 +0100 (CET) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 60B2D402EA for ; Thu, 7 Mar 2024 04:07:05 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.163.174]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4TqvKm4ZqBzwPFx; Thu, 7 Mar 2024 11:04:44 +0800 (CST) Received: from kwepemd100004.china.huawei.com (unknown [7.221.188.31]) by mail.maildlp.com (Postfix) with ESMTPS id DA4F61400D1; Thu, 7 Mar 2024 11:07:02 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemd100004.china.huawei.com (7.221.188.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Thu, 7 Mar 2024 11:07:02 +0800 From: Jie Hai To: , Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko CC: , , Subject: [PATCH v5 1/7] ethdev: support report register names and filter Date: Thu, 7 Mar 2024 11:02:41 +0800 Message-ID: <20240307030247.599394-2-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240307030247.599394-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240307030247.599394-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd100004.china.huawei.com (7.221.188.31) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds "filter" and "names" fields to "rte_dev_reg_info" structure. Names of registers in data fields can be reported and the registers can be filtered by their names. The new API rte_eth_dev_get_reg_info_ext() is added to support reporting names and filtering by names. And the original API rte_eth_dev_get_reg_info() does not use the names and filter fields. A local variable is used in rte_eth_dev_get_reg_info for compatibility. If the drivers does not report the names, set them to "offset_XXX". Signed-off-by: Jie Hai Acked-by: Huisong Li --- doc/guides/rel_notes/release_24_03.rst | 9 ++++++ lib/ethdev/rte_dev_info.h | 11 ++++++++ lib/ethdev/rte_ethdev.c | 38 ++++++++++++++++++++++++++ lib/ethdev/rte_ethdev.h | 29 ++++++++++++++++++++ lib/ethdev/version.map | 1 + 5 files changed, 88 insertions(+) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 78590c047b2e..e491579ca984 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -161,6 +161,12 @@ New Features * Added power-saving during polling within the ``rte_event_dequeue_burst()`` API. * Added support for DMA adapter. +* **Added support for dumping registers with names and filter.** + + * Added new API functions ``rte_eth_dev_get_reg_info_ext()`` to and filter + the registers by their names and get the information of registers(names, + values and other attributes). + Removed Items ------------- @@ -228,6 +234,9 @@ ABI Changes * No ABI change that would break compatibility with 23.11. +* ethdev: Added ``filter`` and ``names`` fields to ``rte_dev_reg_info`` + structure for reporting names of registers and filtering them by names. + Known Issues ------------ diff --git a/lib/ethdev/rte_dev_info.h b/lib/ethdev/rte_dev_info.h index 67cf0ae52668..0badb92432ae 100644 --- a/lib/ethdev/rte_dev_info.h +++ b/lib/ethdev/rte_dev_info.h @@ -11,6 +11,11 @@ extern "C" { #include +#define RTE_ETH_REG_NAME_SIZE 64 +struct rte_eth_reg_name { + char name[RTE_ETH_REG_NAME_SIZE]; +}; + /* * Placeholder for accessing device registers */ @@ -20,6 +25,12 @@ struct rte_dev_reg_info { uint32_t length; /**< Number of registers to fetch */ uint32_t width; /**< Size of device register */ uint32_t version; /**< Device version */ + /** + * Filter for target subset of registers. + * This field could affects register selection for data/length/names. + */ + const char *filter; + struct rte_eth_reg_name *names; /**< Registers name saver */ }; /* diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index f1c658f49e80..82d228790692 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -6388,8 +6388,37 @@ rte_eth_read_clock(uint16_t port_id, uint64_t *clock) int rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info) +{ + struct rte_dev_reg_info reg_info = { 0 }; + int ret; + + if (info == NULL) { + RTE_ETHDEV_LOG_LINE(ERR, + "Cannot get ethdev port %u register info to NULL", + port_id); + return -EINVAL; + } + + reg_info.length = info->length; + reg_info.data = info->data; + + ret = rte_eth_dev_get_reg_info_ext(port_id, ®_info); + if (ret != 0) + return ret; + + info->length = reg_info.length; + info->width = reg_info.width; + info->version = reg_info.version; + info->offset = reg_info.offset; + + return 0; +} + +int +rte_eth_dev_get_reg_info_ext(uint16_t port_id, struct rte_dev_reg_info *info) { struct rte_eth_dev *dev; + uint32_t i; int ret; RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); @@ -6402,12 +6431,21 @@ rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info) return -EINVAL; } + if (info->names != NULL && info->length != 0) + memset(info->names, 0, + sizeof(struct rte_eth_reg_name) * info->length); + if (*dev->dev_ops->get_reg == NULL) return -ENOTSUP; ret = eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info)); rte_ethdev_trace_get_reg_info(port_id, info, ret); + /* Report the default names if drivers not report. */ + if (info->names != NULL && strlen(info->names[0].name) == 0) + for (i = 0; i < info->length; i++) + snprintf(info->names[i].name, RTE_ETH_REG_NAME_SIZE, + "offset_%u", info->offset + i * info->width); return ret; } diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index ed27360447a3..cd95a0d51038 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -5066,6 +5066,35 @@ __rte_experimental int rte_eth_get_monitor_addr(uint16_t port_id, uint16_t queue_id, struct rte_power_monitor_cond *pmc); +/** + * Retrieve the filtered device registers (values and names) and + * register attributes (number of registers and register size) + * + * @param port_id + * The port identifier of the Ethernet device. + * @param info + * Pointer to rte_dev_reg_info structure to fill in. + * - If info->filter is NULL, return info for all registers (seen as filter + * none). + * - If info->filter is not NULL, return error if the driver does not support + * names or filter. + * - If info->data is NULL, the function fills in the width and length fields. + * - If info->data is not NULL, ethdev considers there are enough spaces to + * store the registers, and the values of registers whose name contains the + * filter string are put into the buffer pointed at by info->data. + * - If info->names is not NULL, drivers should fill it or the ethdev fills it + * with default names. + * @return + * - (0) if successful. + * - (-ENOTSUP) if hardware doesn't support. + * - (-EINVAL) if bad parameter. + * - (-ENODEV) if *port_id* invalid. + * - (-EIO) if device is removed. + * - others depends on the specific operations implementation. + */ +__rte_experimental +int rte_eth_dev_get_reg_info_ext(uint16_t port_id, struct rte_dev_reg_info *info); + /** * Retrieve device registers and register attributes (number of registers and * register size) diff --git a/lib/ethdev/version.map b/lib/ethdev/version.map index 79f6f5293b5c..e5ec2a2a9741 100644 --- a/lib/ethdev/version.map +++ b/lib/ethdev/version.map @@ -319,6 +319,7 @@ EXPERIMENTAL { # added in 24.03 __rte_eth_trace_tx_queue_count; + rte_eth_dev_get_reg_info_ext; rte_eth_find_rss_algo; rte_flow_async_update_resized; rte_flow_calc_encap_hash; From patchwork Thu Mar 7 03:02:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 138073 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 29C0143B5E; Thu, 7 Mar 2024 04:07:13 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8C01342D87; Thu, 7 Mar 2024 04:07:08 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id 65F52402F2 for ; Thu, 7 Mar 2024 04:07:05 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.88.234]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4TqvKj2jK4z1Q9lc; Thu, 7 Mar 2024 11:04:41 +0800 (CST) Received: from kwepemd100004.china.huawei.com (unknown [7.221.188.31]) by mail.maildlp.com (Postfix) with ESMTPS id 6D94C1402E0; Thu, 7 Mar 2024 11:07:03 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemd100004.china.huawei.com (7.221.188.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Thu, 7 Mar 2024 11:07:02 +0800 From: Jie Hai To: , Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko CC: , , Subject: [PATCH v5 2/7] ethdev: add telemetry cmd for registers Date: Thu, 7 Mar 2024 11:02:42 +0800 Message-ID: <20240307030247.599394-3-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240307030247.599394-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240307030247.599394-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd100004.china.huawei.com (7.221.188.31) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds a telemetry command for registers dump, and supports get registers with specified names. The length of the string exported by telemetry is limited by MAX_OUTPUT_LEN. Therefore, the filter should be more precise. An example usage is shown below: --> /ethdev/regs,0,INTR { "/ethdev/regs": { "registers_length": 318, "registers_width": 4, "register_offset": "0x0", "version": "0x1140011", "group_0": { "HNS3_CMDQ_INTR_STS_REG": "0x0", "HNS3_CMDQ_INTR_EN_REG": "0x2", "HNS3_CMDQ_INTR_GEN_REG": "0x0", "queue_0_HNS3_TQP_INTR_CTRL_REG": "0x0", "queue_0_HNS3_TQP_INTR_GL0_REG": "0xa", "queue_0_HNS3_TQP_INTR_GL1_REG": "0xa", "queue_0_HNS3_TQP_INTR_GL2_REG": "0x0", ... }, "group_1": { ... }, ... } or as below if the number of registers not exceed the RTE_TEL_MAX_DICT_ENTRIES: --> /ethdev/regs,0,ppp { "/ethdev/regs": { "registers_length": 156, "registers_width": 4, "register_offset": "0x0", "version": "0x1140011", "ppp_key_drop_num": "0x0", "ppp_rlt_drop_num": "0x0", "ssu_ppp_mac_key_num_l": "0x1", "ssu_ppp_mac_key_num_h": "0x0", "ssu_ppp_host_key_num_l": "0x1", "ssu_ppp_host_key_num_h": "0x0", "ppp_ssu_mac_rlt_num_l": "0x1", ... } } Signed-off-by: Jie Hai --- lib/ethdev/rte_ethdev_telemetry.c | 158 ++++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/lib/ethdev/rte_ethdev_telemetry.c b/lib/ethdev/rte_ethdev_telemetry.c index 6b873e7abe68..0c570792fb5f 100644 --- a/lib/ethdev/rte_ethdev_telemetry.c +++ b/lib/ethdev/rte_ethdev_telemetry.c @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -1395,6 +1396,161 @@ eth_dev_handle_port_tm_node_caps(const char *cmd __rte_unused, return ret; } +static void +eth_dev_add_u32_hex(struct rte_tel_data *d, const char *name, uint32_t **data) +{ + if (*data == NULL) + return; + rte_tel_data_add_dict_uint_hex(d, name, **data, 0); + (*data)++; +} + +static void +eth_dev_add_u64_hex(struct rte_tel_data *d, const char *name, uint64_t **data) +{ + if (*data == NULL) + return; + rte_tel_data_add_dict_uint_hex(d, name, **data, 0); + (*data)++; +} + +static int +eth_dev_store_regs(struct rte_tel_data *d, struct rte_dev_reg_info *reg_info) +{ + struct rte_tel_data *groups[RTE_TEL_MAX_DICT_ENTRIES]; + char group_name[RTE_TEL_MAX_STRING_LEN] = {0}; + struct rte_tel_data *group = NULL; + uint32_t *data0 = NULL; + uint64_t *data1 = NULL; + uint32_t grp_num = 0; + int ret = 0; + uint32_t i; + + rte_tel_data_start_dict(d); + rte_tel_data_add_dict_uint(d, "register_length", reg_info->length); + rte_tel_data_add_dict_uint(d, "register_width", reg_info->width); + rte_tel_data_add_dict_uint_hex(d, "register_offset", reg_info->offset, 0); + rte_tel_data_add_dict_uint_hex(d, "version", reg_info->version, 0); + + if (reg_info->width == sizeof(uint32_t)) + data0 = reg_info->data; + else + data1 = reg_info->data; + + if (reg_info->length <= RTE_TEL_MAX_DICT_ENTRIES) { + for (i = 0; i < reg_info->length; i++) { + eth_dev_add_u32_hex(d, reg_info->names[i].name, &data0); + eth_dev_add_u64_hex(d, reg_info->names[i].name, &data1); + } + return 0; + } + + for (i = 0; i < reg_info->length; i++) { + if (i % RTE_TEL_MAX_DICT_ENTRIES == 0) { + group = rte_tel_data_alloc(); + if (group == NULL) { + ret = -ENOMEM; + goto out; + } + groups[grp_num++] = group; + rte_tel_data_start_dict(group); + } + eth_dev_add_u32_hex(group, reg_info->names[i].name, &data0); + eth_dev_add_u64_hex(group, reg_info->names[i].name, &data1); + } + + for (i = 0; i < grp_num; i++) { + snprintf(group_name, RTE_TEL_MAX_STRING_LEN, + "group_%u", i); + rte_tel_data_add_dict_container(d, group_name, groups[i], 0); + } + return 0; +out: + for (i = 0; i < grp_num; i++) + rte_tel_data_free(groups[i]); + + return ret; +} + +static int +eth_dev_get_port_regs(int port_id, struct rte_tel_data *d, char *filter) +{ + struct rte_dev_reg_info reg_info; + uint32_t max_length; + int ret; + + memset(®_info, 0, sizeof(reg_info)); + reg_info.filter = filter; + + ret = rte_eth_dev_get_reg_info_ext(port_id, ®_info); + if (ret != 0) { + RTE_ETHDEV_LOG_LINE(ERR, + "Error getting device reg info: %d", ret); + return ret; + } + + /* 4 is space for other information of registers. */ + max_length = RTE_TEL_MAX_DICT_ENTRIES * + (RTE_TEL_MAX_DICT_ENTRIES - 4); + if (reg_info.length > max_length) { + RTE_ETHDEV_LOG_LINE(WARNING, + "Reduced register number to be obtained from %u to %u due to limited memory", + reg_info.length, max_length); + reg_info.length = max_length; + } + + reg_info.data = calloc(reg_info.length, reg_info.width); + if (reg_info.data == NULL) { + RTE_ETHDEV_LOG_LINE(ERR, + "Fail to allocate memory for reg_info.data"); + return -ENOMEM; + } + + reg_info.names = calloc(reg_info.length, sizeof(struct rte_eth_reg_name)); + if (reg_info.names == NULL) { + RTE_ETHDEV_LOG_LINE(ERR, + "Fail to allocate memory for reg_info.names"); + free(reg_info.data); + return -ENOMEM; + } + + ret = rte_eth_dev_get_reg_info_ext(port_id, ®_info); + if (ret != 0) { + RTE_ETHDEV_LOG_LINE(ERR, + "Error getting regs from device: %d", ret); + ret = -EINVAL; + goto out; + } + + ret = eth_dev_store_regs(d, ®_info); +out: + free(reg_info.data); + free(reg_info.names); + + return ret; +} + +static int +eth_dev_handle_port_regs(const char *cmd __rte_unused, + const char *params, + struct rte_tel_data *d) +{ + char *filter = NULL; + uint16_t port_id; + char *end_param; + int ret; + + ret = eth_dev_parse_port_params(params, &port_id, &end_param, true); + if (ret != 0) + return ret; + + filter = strtok(end_param, ","); + if (filter != NULL && strlen(filter) == 0) + filter = NULL; + + return eth_dev_get_port_regs(port_id, d, filter); +} + RTE_INIT(ethdev_init_telemetry) { rte_telemetry_register_cmd("/ethdev/list", eth_dev_handle_port_list, @@ -1436,4 +1592,6 @@ RTE_INIT(ethdev_init_telemetry) "Returns TM Level Capabilities info for a port. Parameters: int port_id, int level_id (see tm_capability for the max)"); rte_telemetry_register_cmd("/ethdev/tm_node_capability", eth_dev_handle_port_tm_node_caps, "Returns TM Node Capabilities info for a port. Parameters: int port_id, int node_id (see tm_capability for the max)"); + rte_telemetry_register_cmd("/ethdev/regs", eth_dev_handle_port_regs, + "Returns regs for a port. Parameters: int port_id, string filter"); } From patchwork Thu Mar 7 03:02:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 138075 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2E67543B5E; Thu, 7 Mar 2024 04:07:26 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1EC1642E5B; Thu, 7 Mar 2024 04:07:11 +0100 (CET) Received: from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32]) by mails.dpdk.org (Postfix) with ESMTP id C9BCC42D87 for ; Thu, 7 Mar 2024 04:07:05 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4TqvMg4Vrwz27g4P for ; Thu, 7 Mar 2024 11:06:23 +0800 (CST) Received: from kwepemd100004.china.huawei.com (unknown [7.221.188.31]) by mail.maildlp.com (Postfix) with ESMTPS id 2371C1A016C for ; Thu, 7 Mar 2024 11:07:04 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemd100004.china.huawei.com (7.221.188.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Thu, 7 Mar 2024 11:07:03 +0800 From: Jie Hai To: , Yisen Zhuang , Chengchang Tang , Lijun Ou , Chunsong Feng , "Wei Hu (Xavier)" , "Min Hu (Connor)" , Ferruh Yigit , Huisong Li CC: , Subject: [PATCH v5 3/7] net/hns3: fix dump counter of registers Date: Thu, 7 Mar 2024 11:02:43 +0800 Message-ID: <20240307030247.599394-4-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240307030247.599394-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240307030247.599394-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd100004.china.huawei.com (7.221.188.31) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Since the driver dumps the queue interrupt registers according to the intr_tqps_num, the counter should be the same. Fixes: acb3260fac5c ("net/hns3: fix dump register out of range") Fixes: 936eda25e8da ("net/hns3: support dump register") Signed-off-by: Jie Hai Cc: stable@dpdk.org Acked-by: Huisong Li --- drivers/net/hns3/hns3_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index be1be6a89c94..d77170481a3d 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -135,7 +135,7 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1; len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num + - tqp_intr_lines * hw->num_msi) * REG_NUM_PER_LINE; + tqp_intr_lines * hw->intr_tqps_num) * REG_NUM_PER_LINE; if (!hns->is_vf) { ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); From patchwork Thu Mar 7 03:02:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 138076 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A029543B62; Thu, 7 Mar 2024 04:07:35 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1845C42E7C; Thu, 7 Mar 2024 04:07:13 +0100 (CET) Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by mails.dpdk.org (Postfix) with ESMTP id 84234402EA for ; Thu, 7 Mar 2024 04:07:06 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.163.48]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4TqvLB0Q8Nz1Q9NL for ; Thu, 7 Mar 2024 11:05:06 +0800 (CST) Received: from kwepemd100004.china.huawei.com (unknown [7.221.188.31]) by mail.maildlp.com (Postfix) with ESMTPS id 9EDF4180068 for ; Thu, 7 Mar 2024 11:07:04 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemd100004.china.huawei.com (7.221.188.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Thu, 7 Mar 2024 11:07:04 +0800 From: Jie Hai To: , Yisen Zhuang CC: , , Subject: [PATCH v5 4/7] net/hns3: remove dump format of registers Date: Thu, 7 Mar 2024 11:02:44 +0800 Message-ID: <20240307030247.599394-5-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240307030247.599394-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240307030247.599394-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd100004.china.huawei.com (7.221.188.31) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Since the driver is going to support reporting names of all registers, remove the counter and insert of separators between different register modules. Signed-off-by: Jie Hai Reviewed-by: Huisong Li --- drivers/net/hns3/hns3_regs.c | 67 ++++++++++-------------------------- 1 file changed, 18 insertions(+), 49 deletions(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index d77170481a3d..b1c0d538a3c8 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -10,12 +10,9 @@ #include "hns3_rxtx.h" #include "hns3_regs.h" -#define MAX_SEPARATE_NUM 4 -#define SEPARATOR_VALUE 0xFFFFFFFF -#define REG_NUM_PER_LINE 4 -#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(uint32_t)) +#define HNS3_64_BIT_REG_SIZE (sizeof(uint64_t) / sizeof(uint32_t)) -static int hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines); +static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count); static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG, HNS3_CMDQ_TX_ADDR_H_REG, @@ -119,23 +116,22 @@ static int hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) { struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); - uint32_t cmdq_lines, common_lines, ring_lines, tqp_intr_lines; + uint32_t cmdq_cnt, common_cnt, ring_cnt, tqp_intr_cnt; uint32_t regs_num_32_bit, regs_num_64_bit; - uint32_t dfx_reg_lines; + uint32_t dfx_reg_cnt; uint32_t len; int ret; - cmdq_lines = sizeof(cmdq_reg_addrs) / REG_LEN_PER_LINE + 1; + cmdq_cnt = sizeof(cmdq_reg_addrs); if (hns->is_vf) - common_lines = - sizeof(common_vf_reg_addrs) / REG_LEN_PER_LINE + 1; + common_cnt = sizeof(common_vf_reg_addrs); else - common_lines = sizeof(common_reg_addrs) / REG_LEN_PER_LINE + 1; - ring_lines = sizeof(ring_reg_addrs) / REG_LEN_PER_LINE + 1; - tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1; + common_cnt = sizeof(common_reg_addrs); + ring_cnt = sizeof(ring_reg_addrs); + tqp_intr_cnt = sizeof(tqp_intr_reg_addrs); - len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num + - tqp_intr_lines * hw->intr_tqps_num) * REG_NUM_PER_LINE; + len = cmdq_cnt + common_cnt + ring_cnt * hw->tqps_num + + tqp_intr_cnt * hw->intr_tqps_num; if (!hns->is_vf) { ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); @@ -144,18 +140,16 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) "ret = %d.", ret); return ret; } - dfx_reg_lines = regs_num_32_bit * sizeof(uint32_t) / - REG_LEN_PER_LINE + 1; - dfx_reg_lines += regs_num_64_bit * sizeof(uint64_t) / - REG_LEN_PER_LINE + 1; + dfx_reg_cnt = regs_num_32_bit + + regs_num_64_bit * HNS3_64_BIT_REG_SIZE; - ret = hns3_get_dfx_reg_line(hw, &dfx_reg_lines); + ret = hns3_get_dfx_reg_cnt(hw, &dfx_reg_cnt); if (ret) { hns3_err(hw, "fail to get the number of dfx registers, " "ret = %d.", ret); return ret; } - len += dfx_reg_lines * REG_NUM_PER_LINE; + len += dfx_reg_cnt; } *length = len; @@ -276,18 +270,6 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) return 0; } -static int -hns3_insert_reg_separator(int reg_num, uint32_t *data) -{ - int separator_num; - int i; - - separator_num = MAX_SEPARATE_NUM - reg_num % REG_NUM_PER_LINE; - for (i = 0; i < separator_num; i++) - *data++ = SEPARATOR_VALUE; - return separator_num; -} - static int hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) { @@ -302,7 +284,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) reg_num = sizeof(cmdq_reg_addrs) / sizeof(uint32_t); for (i = 0; i < reg_num; i++) *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]); - data += hns3_insert_reg_separator(reg_num, data); if (hns->is_vf) reg_num = sizeof(common_vf_reg_addrs) / sizeof(uint32_t); @@ -313,7 +294,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]); else *data++ = hns3_read_dev(hw, common_reg_addrs[i]); - data += hns3_insert_reg_separator(reg_num, data); reg_num = sizeof(ring_reg_addrs) / sizeof(uint32_t); for (j = 0; j < hw->tqps_num; j++) { @@ -321,7 +301,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) for (i = 0; i < reg_num; i++) *data++ = hns3_read_dev(hw, ring_reg_addrs[i] + reg_offset); - data += hns3_insert_reg_separator(reg_num, data); } reg_num = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t); @@ -330,7 +309,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) for (i = 0; i < reg_num; i++) *data++ = hns3_read_dev(hw, tqp_intr_reg_addrs[i] + reg_offset); - data += hns3_insert_reg_separator(reg_num, data); } return data - origin_data_ptr; } @@ -406,17 +384,15 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg) index = i % HNS3_CMD_DESC_DATA_NUM; *reg++ = desc[desc_index].data[index]; } - reg_num += hns3_insert_reg_separator(reg_num, reg); return reg_num; } static int -hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines) +hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) { int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); uint32_t bd_num_list[opcode_num]; - uint32_t bd_num, data_len; int ret; int i; @@ -424,11 +400,8 @@ hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines) if (ret) return ret; - for (i = 0; i < opcode_num; i++) { - bd_num = bd_num_list[i]; - data_len = bd_num * HNS3_CMD_DESC_DATA_NUM * sizeof(uint32_t); - *lines += data_len / REG_LEN_PER_LINE + 1; - } + for (i = 0; i < opcode_num; i++) + *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; return 0; } @@ -475,7 +448,6 @@ hns3_get_dfx_regs(struct hns3_hw *hw, void **data) int hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) { -#define HNS3_64_BIT_REG_SIZE (sizeof(uint64_t) / sizeof(uint32_t)) struct hns3_adapter *hns = eth_dev->data->dev_private; struct hns3_hw *hw = &hns->hw; uint32_t regs_num_32_bit; @@ -520,7 +492,6 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) return ret; } data += regs_num_32_bit; - data += hns3_insert_reg_separator(regs_num_32_bit, data); ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data); if (ret) { @@ -528,8 +499,6 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) return ret; } data += regs_num_64_bit * HNS3_64_BIT_REG_SIZE; - data += hns3_insert_reg_separator(regs_num_64_bit * - HNS3_64_BIT_REG_SIZE, data); return hns3_get_dfx_regs(hw, (void **)&data); } From patchwork Thu Mar 7 03:02:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 138079 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D762E43B62; Thu, 7 Mar 2024 04:07:54 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 36B5142EC7; Thu, 7 Mar 2024 04:07:17 +0100 (CET) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id E91E940A6D for ; Thu, 7 Mar 2024 04:07:06 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4TqvLZ5ZtLz1xq3x for ; Thu, 7 Mar 2024 11:05:26 +0800 (CST) Received: from kwepemd100004.china.huawei.com (unknown [7.221.188.31]) by mail.maildlp.com (Postfix) with ESMTPS id 3493F1A0172 for ; Thu, 7 Mar 2024 11:07:05 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemd100004.china.huawei.com (7.221.188.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Thu, 7 Mar 2024 11:07:04 +0800 From: Jie Hai To: , Yisen Zhuang CC: , , Subject: [PATCH v5 5/7] net/hns3: add names for registers Date: Thu, 7 Mar 2024 11:02:45 +0800 Message-ID: <20240307030247.599394-6-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240307030247.599394-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240307030247.599394-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd100004.china.huawei.com (7.221.188.31) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds names for all registers to be dumped. For those who can be directly accessed by their addresses, a new structure containing both name and address is added and the related arrays is refactored and renamed. For the remaining modules, there may be different meanings on different platforms for the same field. Therefore, two name fields are provided. There are some 64-bit registers, dump them as two 32-bit registers. Signed-off-by: Jie Hai Reviewed-by: Huisong Li --- drivers/net/hns3/hns3_regs.c | 877 ++++++++++++++++++++++++++++++++--- 1 file changed, 801 insertions(+), 76 deletions(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index b1c0d538a3c8..b7e4f78eecde 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -14,67 +14,84 @@ static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count); -static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG, - HNS3_CMDQ_TX_ADDR_H_REG, - HNS3_CMDQ_TX_DEPTH_REG, - HNS3_CMDQ_TX_TAIL_REG, - HNS3_CMDQ_TX_HEAD_REG, - HNS3_CMDQ_RX_ADDR_L_REG, - HNS3_CMDQ_RX_ADDR_H_REG, - HNS3_CMDQ_RX_DEPTH_REG, - HNS3_CMDQ_RX_TAIL_REG, - HNS3_CMDQ_RX_HEAD_REG, - HNS3_VECTOR0_CMDQ_SRC_REG, - HNS3_CMDQ_INTR_STS_REG, - HNS3_CMDQ_INTR_EN_REG, - HNS3_CMDQ_INTR_GEN_REG}; - -static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE, - HNS3_VECTOR0_OTER_EN_REG, - HNS3_MISC_RESET_STS_REG, - HNS3_VECTOR0_OTHER_INT_STS_REG, - HNS3_GLOBAL_RESET_REG, - HNS3_FUN_RST_ING, - HNS3_GRO_EN_REG}; - -static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE, - HNS3_FUN_RST_ING, - HNS3_GRO_EN_REG}; - -static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG, - HNS3_RING_RX_BASEADDR_H_REG, - HNS3_RING_RX_BD_NUM_REG, - HNS3_RING_RX_BD_LEN_REG, - HNS3_RING_RX_EN_REG, - HNS3_RING_RX_MERGE_EN_REG, - HNS3_RING_RX_TAIL_REG, - HNS3_RING_RX_HEAD_REG, - HNS3_RING_RX_FBDNUM_REG, - HNS3_RING_RX_OFFSET_REG, - HNS3_RING_RX_FBD_OFFSET_REG, - HNS3_RING_RX_STASH_REG, - HNS3_RING_RX_BD_ERR_REG, - HNS3_RING_TX_BASEADDR_L_REG, - HNS3_RING_TX_BASEADDR_H_REG, - HNS3_RING_TX_BD_NUM_REG, - HNS3_RING_TX_EN_REG, - HNS3_RING_TX_PRIORITY_REG, - HNS3_RING_TX_TC_REG, - HNS3_RING_TX_MERGE_EN_REG, - HNS3_RING_TX_TAIL_REG, - HNS3_RING_TX_HEAD_REG, - HNS3_RING_TX_FBDNUM_REG, - HNS3_RING_TX_OFFSET_REG, - HNS3_RING_TX_EBD_NUM_REG, - HNS3_RING_TX_EBD_OFFSET_REG, - HNS3_RING_TX_BD_ERR_REG, - HNS3_RING_EN_REG}; - -static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG, - HNS3_TQP_INTR_GL0_REG, - HNS3_TQP_INTR_GL1_REG, - HNS3_TQP_INTR_GL2_REG, - HNS3_TQP_INTR_RL_REG}; +struct direct_reg_list { + const char *name; + uint32_t addr; +}; + +#define STR(s) #s + +static const struct direct_reg_list cmdq_reg_list[] = { + {STR(HNS3_CMDQ_TX_ADDR_L_REG), HNS3_CMDQ_TX_ADDR_L_REG}, + {STR(HNS3_CMDQ_TX_ADDR_H_REG), HNS3_CMDQ_TX_ADDR_H_REG}, + {STR(HNS3_CMDQ_TX_DEPTH_REG), HNS3_CMDQ_TX_DEPTH_REG}, + {STR(HNS3_CMDQ_TX_TAIL_REG), HNS3_CMDQ_TX_TAIL_REG}, + {STR(HNS3_CMDQ_TX_HEAD_REG), HNS3_CMDQ_TX_HEAD_REG}, + {STR(HNS3_CMDQ_RX_ADDR_L_REG), HNS3_CMDQ_RX_ADDR_L_REG}, + {STR(HNS3_CMDQ_RX_ADDR_H_REG), HNS3_CMDQ_RX_ADDR_H_REG}, + {STR(HNS3_CMDQ_RX_DEPTH_REG), HNS3_CMDQ_RX_DEPTH_REG}, + {STR(HNS3_CMDQ_RX_TAIL_REG), HNS3_CMDQ_RX_TAIL_REG}, + {STR(HNS3_CMDQ_RX_HEAD_REG), HNS3_CMDQ_RX_HEAD_REG}, + {STR(HNS3_VECTOR0_CMDQ_SRC_REG), HNS3_VECTOR0_CMDQ_SRC_REG}, + {STR(HNS3_CMDQ_INTR_STS_REG), HNS3_CMDQ_INTR_STS_REG}, + {STR(HNS3_CMDQ_INTR_EN_REG), HNS3_CMDQ_INTR_EN_REG}, + {STR(HNS3_CMDQ_INTR_GEN_REG), HNS3_CMDQ_INTR_GEN_REG}, +}; + +static const struct direct_reg_list common_reg_list[] = { + {STR(HNS3_MISC_VECTOR_REG_BASE), HNS3_MISC_VECTOR_REG_BASE}, + {STR(HNS3_VECTOR0_OTER_EN_REG), HNS3_VECTOR0_OTER_EN_REG}, + {STR(HNS3_MISC_RESET_STS_REG), HNS3_MISC_RESET_STS_REG}, + {STR(HNS3_VECTOR0_OTHER_INT_STS_REG), HNS3_VECTOR0_OTHER_INT_STS_REG}, + {STR(HNS3_GLOBAL_RESET_REG), HNS3_GLOBAL_RESET_REG}, + {STR(HNS3_FUN_RST_ING), HNS3_FUN_RST_ING}, + {STR(HNS3_GRO_EN_REG), HNS3_GRO_EN_REG}, +}; + +static const struct direct_reg_list common_vf_reg_list[] = { + {STR(HNS3_MISC_VECTOR_REG_BASE), HNS3_MISC_VECTOR_REG_BASE}, + {STR(HNS3_FUN_RST_ING), HNS3_FUN_RST_ING}, + {STR(HNS3_GRO_EN_REG), HNS3_GRO_EN_REG}, +}; + +static const struct direct_reg_list ring_reg_list[] = { + {STR(HNS3_RING_RX_BASEADDR_L_REG), HNS3_RING_RX_BASEADDR_L_REG}, + {STR(HNS3_RING_RX_BASEADDR_H_REG), HNS3_RING_RX_BASEADDR_H_REG}, + {STR(HNS3_RING_RX_BD_NUM_REG), HNS3_RING_RX_BD_NUM_REG}, + {STR(HNS3_RING_RX_BD_LEN_REG), HNS3_RING_RX_BD_LEN_REG}, + {STR(HNS3_RING_RX_EN_REG), HNS3_RING_RX_EN_REG}, + {STR(HNS3_RING_RX_MERGE_EN_REG), HNS3_RING_RX_MERGE_EN_REG}, + {STR(HNS3_RING_RX_TAIL_REG), HNS3_RING_RX_TAIL_REG}, + {STR(HNS3_RING_RX_HEAD_REG), HNS3_RING_RX_HEAD_REG}, + {STR(HNS3_RING_RX_FBDNUM_REG), HNS3_RING_RX_FBDNUM_REG}, + {STR(HNS3_RING_RX_OFFSET_REG), HNS3_RING_RX_OFFSET_REG}, + {STR(HNS3_RING_RX_FBD_OFFSET_REG), HNS3_RING_RX_FBD_OFFSET_REG}, + {STR(HNS3_RING_RX_STASH_REG), HNS3_RING_RX_STASH_REG}, + {STR(HNS3_RING_RX_BD_ERR_REG), HNS3_RING_RX_BD_ERR_REG}, + {STR(HNS3_RING_TX_BASEADDR_L_REG), HNS3_RING_TX_BASEADDR_L_REG}, + {STR(HNS3_RING_TX_BASEADDR_H_REG), HNS3_RING_TX_BASEADDR_H_REG}, + {STR(HNS3_RING_TX_BD_NUM_REG), HNS3_RING_TX_BD_NUM_REG}, + {STR(HNS3_RING_TX_EN_REG), HNS3_RING_TX_EN_REG}, + {STR(HNS3_RING_TX_PRIORITY_REG), HNS3_RING_TX_PRIORITY_REG}, + {STR(HNS3_RING_TX_TC_REG), HNS3_RING_TX_TC_REG}, + {STR(HNS3_RING_TX_MERGE_EN_REG), HNS3_RING_TX_MERGE_EN_REG}, + {STR(HNS3_RING_TX_TAIL_REG), HNS3_RING_TX_TAIL_REG}, + {STR(HNS3_RING_TX_HEAD_REG), HNS3_RING_TX_HEAD_REG}, + {STR(HNS3_RING_TX_FBDNUM_REG), HNS3_RING_TX_FBDNUM_REG}, + {STR(HNS3_RING_TX_OFFSET_REG), HNS3_RING_TX_OFFSET_REG}, + {STR(HNS3_RING_TX_EBD_NUM_REG), HNS3_RING_TX_EBD_NUM_REG}, + {STR(HNS3_RING_TX_EBD_OFFSET_REG), HNS3_RING_TX_EBD_OFFSET_REG}, + {STR(HNS3_RING_TX_BD_ERR_REG), HNS3_RING_TX_BD_ERR_REG}, + {STR(HNS3_RING_EN_REG), HNS3_RING_EN_REG}, +}; + +static const struct direct_reg_list tqp_intr_reg_list[] = { + {STR(HNS3_TQP_INTR_CTRL_REG), HNS3_TQP_INTR_CTRL_REG}, + {STR(HNS3_TQP_INTR_GL0_REG), HNS3_TQP_INTR_GL0_REG}, + {STR(HNS3_TQP_INTR_GL1_REG), HNS3_TQP_INTR_GL1_REG}, + {STR(HNS3_TQP_INTR_GL2_REG), HNS3_TQP_INTR_GL2_REG}, + {STR(HNS3_TQP_INTR_RL_REG), HNS3_TQP_INTR_RL_REG}, +}; static const uint32_t hns3_dfx_reg_opcode_list[] = { HNS3_OPC_DFX_BIOS_COMMON_REG, @@ -91,6 +108,708 @@ static const uint32_t hns3_dfx_reg_opcode_list[] = { HNS3_OPC_DFX_SSU_REG_2 }; +struct hns3_reg_entry { + const char *new_name; + const char *old_name; +}; + +static struct hns3_reg_entry regs_32_bit_list[] = { + {"ssu_common_err_int"}, + {"ssu_port_based_err_int"}, + {"ssu_fifo_overflow_int"}, + {"ssu_ets_tcg_int"}, + {"ssu_bp_status_0"}, + {"ssu_bp_status_1"}, + + {"ssu_bp_status_2"}, + {"ssu_bp_status_3"}, + {"ssu_bp_status_4"}, + {"ssu_bp_status_5"}, + {"ssu_mac_tx_pfc_ind"}, + {"ssu_mac_rx_pfc_ind"}, + + {"ssu_rx_oq_drop_pkt_cnt"}, + {"ssu_tx_oq_drop_pkt_cnt"}, +}; + +static struct hns3_reg_entry regs_64_bit_list[] = { + {"ppp_get_rx_pkt_cnt_l"}, + {"ppp_get_rx_pkt_cnt_h"}, + {"ppp_get_tx_pkt_cnt_l"}, + {"ppp_get_tx_pkt_cnt_h"}, + {"ppp_send_uc_prt2host_pkt_cnt_l"}, + {"ppp_send_uc_prt2host_pkt_cnt_h"}, + + {"ppp_send_uc_prt2prt_pkt_cnt_l"}, + {"ppp_send_uc_prt2prt_pkt_cnt_h"}, + {"ppp_send_uc_host2host_pkt_cnt_l"}, + {"ppp_send_uc_host2host_pkt_cnt_h"}, + {"ppp_send_uc_host2prt_pkt_cnt_l"}, + {"ppp_send_uc_host2prt_pkt_cnt_h"}, + {"ppp_send_mc_from_prt_cnt_l"}, + {"ppp_send_mc_from_prt_cnt_h"}, +}; + +static struct hns3_reg_entry dfx_bios_common_reg_list[] = { + {"bios_rsv0"}, + {"bp_cpu_state"}, + {"dfx_msix_info_nic_0"}, + {"dfx_msix_info_nic_1"}, + {"dfx_msix_info_nic_2"}, + {"dfx_msix_info_nic_3"}, + + {"dfx_msix_info_roce_0"}, + {"dfx_msix_info_roce_1"}, + {"dfx_msix_info_roce_2"}, + {"dfx_msix_info_roce_3"}, + {"bios_rsv1"}, + {"bios_rsv2"}, +}; + +static struct hns3_reg_entry dfx_ssu_reg_0_list[] = { + {"dfx_ssu0_rsv0"}, + {"ssu_ets_port_status"}, + {"ssu_ets_tcg_status"}, + {"dfx_ssu0_rsv1"}, + {"dfx_ssu0_rsv2"}, + {"ssu_bp_status_0"}, + + {"ssu_bp_status_1"}, + {"ssu_bp_status_2"}, + {"ssu_bp_status_3"}, + {"ssu_bp_status_4"}, + {"ssu_bp_status_5"}, + {"ssu_mac_tx_pfc_ind"}, + + {"mac_ssu_rx_pfc_ind"}, + {"ssu_btmp_ageing_st_b0"}, + {"ssu_btmp_ageing_st_b1"}, + {"ssu_btmp_ageing_st_b2"}, + {"dfx_ssu0_rsv3"}, + {"dfx_ssu0_rsv4"}, + + {"ssu_full_drop_num"}, + {"ssu_part_drop_num"}, + {"ppp_key_drop_num"}, + {"ppp_rlt_drop_num"}, + {"ssu_lo_pri_unicast_rlt_drop_num"}, + {"ssu_hi_pri_multicast_rlt_drop_num"}, + + {"ssu_lo_pri_multicast_rlt_drop_num"}, + {"ssu_ncsi_packet_curr_buffer_cnt"}, + {"dfx_ssu0_rsv5", "ssu_btmp_ageing_rls_cnt_bank0"}, + {"dfx_ssu0_rsv6", "ssu_btmp_ageing_rls_cnt_bank1"}, + {"dfx_ssu0_rsv7", "ssu_btmp_ageing_rls_cnt_bank2"}, + {"ssu_mb_rd_rlt_drop_cnt"}, + + {"ssu_ppp_mac_key_num_l"}, + {"ssu_ppp_mac_key_num_h"}, + {"ssu_ppp_host_key_num_l"}, + {"ssu_ppp_host_key_num_h"}, + {"ppp_ssu_mac_rlt_num_l"}, + {"ppp_ssu_mac_rlt_num_h"}, + + {"ppp_ssu_host_rlt_num_l"}, + {"ppp_ssu_host_rlt_num_h"}, + {"ssu_ncsi_rx_packet_in_cnt_l"}, + {"ssu_ncsi_rx_packet_in_cnt_h"}, + {"ssu_ncsi_tx_packet_out_cnt_l"}, + {"ssu_ncsi_tx_packet_out_cnt_h"}, + + {"ssu_key_drop_num"}, + {"ssu_mb_uncopy_num"}, + {"ssu_rx_oq_drop_pkt_cnt"}, + {"ssu_tx_oq_drop_pkt_cnt"}, + {"ssu_bank_unbalance_drop_cnt"}, + {"ssu_bank_unbalance_rx_drop_cnt"}, + + {"ssu_nic_l2_eer_drop_pkt_cnt"}, + {"ssu_roc_l2_eer_drop_pkt_cnt"}, + {"ssu_nic_l2_eer_drop_pkt_cnt_rx"}, + {"ssu_roc_l2_eer_drop_pkt_cnt_rx"}, + {"ssu_rx_oq_glb_drop_pkt_cnt"}, + {"ssu_dfx_ssu0_rsv8"}, + + {"ssu_lo_pri_unicast_cur_cnt"}, + {"ssu_hi_pri_multicast_cur_cnt"}, + {"ssu_lo_pri_multicast_cur_cnt"}, + {"dfx_ssu0_rsv9"}, + {"dfx_ssu0_rsv10"}, + {"dfx_ssu0_rsv11"}, +}; + +static struct hns3_reg_entry dfx_ssu_reg_1_list[] = { + {"dfx_ssu1_prt_id"}, + {"ssu_packet_tc_curr_buffer_cnt_0"}, + {"ssu_packet_tc_curr_buffer_cnt_1"}, + {"ssu_packet_tc_curr_buffer_cnt_2"}, + {"ssu_packet_tc_curr_buffer_cnt_3"}, + {"ssu_packet_tc_curr_buffer_cnt_4"}, + + {"ssu_packet_tc_curr_buffer_cnt_5"}, + {"ssu_packet_tc_curr_buffer_cnt_6"}, + {"ssu_packet_tc_curr_buffer_cnt_7"}, + {"ssu_packet_curr_buffer_cnt"}, + {"dfx_ssu1_rsv0"}, + {"dfx_ssu1_rsv1"}, + + {"ssu_rx_packet_in_cnt_l"}, + {"ssu_rx_packet_in_cnt_h"}, + {"ssu_rx_packet_out_cnt_l"}, + {"ssu_rx_packet_out_cnt_h"}, + {"ssu_tx_packet_in_cnt_l"}, + {"ssu_tx_packet_in_cnt_h"}, + + {"ssu_tx_packet_out_cnt_l"}, + {"ssu_tx_packet_out_cnt_h"}, + {"ssu_roc_rx_packet_in_cnt_l"}, + {"ssu_roc_rx_packet_in_cnt_h"}, + {"ssu_roc_tx_packet_in_cnt_l"}, + {"ssu_roc_tx_packet_in_cnt_h"}, + + {"ssu_rx_packet_tc_in_cnt_0_l"}, + {"ssu_rx_packet_tc_in_cnt_0_h"}, + {"ssu_rx_packet_tc_in_cnt_1_l"}, + {"ssu_rx_packet_tc_in_cnt_1_h"}, + {"ssu_rx_packet_tc_in_cnt_2_l"}, + {"ssu_rx_packet_tc_in_cnt_2_h"}, + + {"ssu_rx_packet_tc_in_cnt_3_l"}, + {"ssu_rx_packet_tc_in_cnt_3_h"}, + {"ssu_rx_packet_tc_in_cnt_4_l"}, + {"ssu_rx_packet_tc_in_cnt_4_h"}, + {"ssu_rx_packet_tc_in_cnt_5_l"}, + {"ssu_rx_packet_tc_in_cnt_5_h"}, + + {"ssu_rx_packet_tc_in_cnt_6_l"}, + {"ssu_rx_packet_tc_in_cnt_6_h"}, + {"ssu_rx_packet_tc_in_cnt_7_l"}, + {"ssu_rx_packet_tc_in_cnt_7_h"}, + {"ssu_rx_packet_tc_out_cnt_0_l"}, + {"ssu_rx_packet_tc_out_cnt_0_h"}, + + {"ssu_rx_packet_tc_out_cnt_1_l"}, + {"ssu_rx_packet_tc_out_cnt_1_h"}, + {"ssu_rx_packet_tc_out_cnt_2_l"}, + {"ssu_rx_packet_tc_out_cnt_2_h"}, + {"ssu_rx_packet_tc_out_cnt_3_l"}, + {"ssu_rx_packet_tc_out_cnt_3_h"}, + + {"ssu_rx_packet_tc_out_cnt_4_l"}, + {"ssu_rx_packet_tc_out_cnt_4_h"}, + {"ssu_rx_packet_tc_out_cnt_5_l"}, + {"ssu_rx_packet_tc_out_cnt_5_h"}, + {"ssu_rx_packet_tc_out_cnt_6_l"}, + {"ssu_rx_packet_tc_out_cnt_6_h"}, + + {"ssu_rx_packet_tc_out_cnt_7_l"}, + {"ssu_rx_packet_tc_out_cnt_7_h"}, + {"ssu_tx_packet_tc_in_cnt_0_l"}, + {"ssu_tx_packet_tc_in_cnt_0_h"}, + {"ssu_tx_packet_tc_in_cnt_1_l"}, + {"ssu_tx_packet_tc_in_cnt_1_h"}, + + {"ssu_tx_packet_tc_in_cnt_2_l"}, + {"ssu_tx_packet_tc_in_cnt_2_h"}, + {"ssu_tx_packet_tc_in_cnt_3_l"}, + {"ssu_tx_packet_tc_in_cnt_3_h"}, + {"ssu_tx_packet_tc_in_cnt_4_l"}, + {"ssu_tx_packet_tc_in_cnt_4_h"}, + + {"ssu_tx_packet_tc_in_cnt_5_l"}, + {"ssu_tx_packet_tc_in_cnt_5_h"}, + {"ssu_tx_packet_tc_in_cnt_6_l"}, + {"ssu_tx_packet_tc_in_cnt_6_h"}, + {"ssu_tx_packet_tc_in_cnt_7_l"}, + {"ssu_tx_packet_tc_in_cnt_7_h"}, + + {"ssu_tx_packet_tc_out_cnt_0_l"}, + {"ssu_tx_packet_tc_out_cnt_0_h"}, + {"ssu_tx_packet_tc_out_cnt_1_l"}, + {"ssu_tx_packet_tc_out_cnt_1_h"}, + {"ssu_tx_packet_tc_out_cnt_2_l"}, + {"ssu_tx_packet_tc_out_cnt_2_h"}, + + {"ssu_tx_packet_tc_out_cnt_3_l"}, + {"ssu_tx_packet_tc_out_cnt_3_h"}, + {"ssu_tx_packet_tc_out_cnt_4_l"}, + {"ssu_tx_packet_tc_out_cnt_4_h"}, + {"ssu_tx_packet_tc_out_cnt_5_l"}, + {"ssu_tx_packet_tc_out_cnt_5_h"}, + + {"ssu_tx_packet_tc_out_cnt_6_l"}, + {"ssu_tx_packet_tc_out_cnt_6_h"}, + {"ssu_tx_packet_tc_out_cnt_7_l"}, + {"ssu_tx_packet_tc_out_cnt_7_h"}, + {"dfx_ssu1_rsv2"}, + {"dfx_ssu1_rsv3"}, +}; + +static struct hns3_reg_entry dfx_igu_egu_reg_list[] = { + {"igu_egu_prt_id"}, + {"igu_rx_err_pkt"}, + {"igu_rx_no_sof_pkt"}, + {"egu_tx_1588_short_pkt"}, + {"egu_tx_1588_pkt"}, + {"egu_tx_1588_err_pkt"}, + + {"igu_rx_out_l2_pkt"}, + {"igu_rx_out_l3_pkt"}, + {"igu_rx_out_l4_pkt"}, + {"igu_rx_in_l2_pkt"}, + {"igu_rx_in_l3_pkt"}, + {"igu_rx_in_l4_pkt"}, + + {"igu_rx_el3e_pkt"}, + {"igu_rx_el4e_pkt"}, + {"igu_rx_l3e_pkt"}, + {"igu_rx_l4e_pkt"}, + {"igu_rx_rocee_pkt"}, + {"igu_rx_out_udp0_pkt"}, + + {"igu_rx_in_udp0_pkt"}, + {"igu_egu_mul_car_drop_pkt_cnt_l", "igu_egu_rsv0"}, + {"igu_egu_mul_car_drop_pkt_cnt_h", "igu_egu_rsv1"}, + {"igu_egu_bro_car_drop_pkt_cnt_l", "igu_egu_rsv2"}, + {"igu_egu_bro_car_drop_pkt_cnt_h", "igu_egu_rsv3"}, + {"igu_egu_rsv0", "igu_egu_rsv4"}, + + {"igu_rx_oversize_pkt_l"}, + {"igu_rx_oversize_pkt_h"}, + {"igu_rx_undersize_pkt_l"}, + {"igu_rx_undersize_pkt_h"}, + {"igu_rx_out_all_pkt_l"}, + {"igu_rx_out_all_pkt_h"}, + + {"igu_tx_out_all_pkt_l"}, + {"igu_tx_out_all_pkt_h"}, + {"igu_rx_uni_pkt_l"}, + {"igu_rx_uni_pkt_h"}, + {"igu_rx_multi_pkt_l"}, + {"igu_rx_multi_pkt_h"}, + + {"igu_rx_broad_pkt_l"}, + {"igu_rx_broad_pkt_h"}, + {"egu_tx_out_all_pkt_l"}, + {"egu_tx_out_all_pkt_h"}, + {"egu_tx_uni_pkt_l"}, + {"egu_tx_uni_pkt_h"}, + + {"egu_tx_multi_pkt_l"}, + {"egu_tx_multi_pkt_h"}, + {"egu_tx_broad_pkt_l"}, + {"egu_tx_broad_pkt_h"}, + {"igu_tx_key_num_l"}, + {"igu_tx_key_num_h"}, + + {"igu_rx_non_tun_pkt_l"}, + {"igu_rx_non_tun_pkt_h"}, + {"igu_rx_tun_pkt_l"}, + {"igu_rx_tun_pkt_h"}, + {"igu_egu_rsv5"}, + {"igu_egu_rsv6"}, +}; + +static struct hns3_reg_entry dfx_rpu_reg_0_list[] = { + {"rpu_currport_tnl_index", "rpu_tc_queue_num"}, + {"rpu_fsm_dfx_st0"}, + {"rpu_fsm_dfx_st1"}, + {"rpu_rpu_rx_pkt_drop_cnt"}, + {"rpu_buf_wait_timeout"}, + {"rpu_buf_wait_timeout_qid"}, +}; + +static struct hns3_reg_entry dfx_rpu_reg_1_list[] = { + {"rpu_rsv0"}, + {"rpu_fifo_dfx_st0"}, + {"rpu_fifo_dfx_st1"}, + {"rpu_fifo_dfx_st2"}, + {"rpu_fifo_dfx_st3"}, + {"rpu_fifo_dfx_st4"}, + + {"rpu_fifo_dfx_st5"}, + {"rpu_rsv1"}, + {"rpu_rsv2"}, + {"rpu_rsv3"}, + {"rpu_rsv4"}, + {"rpu_rsv5"}, +}; + +static struct hns3_reg_entry dfx_ncsi_reg_list[] = { + {"ncsi_rsv0"}, + {"ncsi_egu_tx_fifo_sts"}, + {"ncsi_pause_status"}, + {"ncsi_rx_ctrl_dmac_err_cnt"}, + {"ncsi_rx_ctrl_smac_err_cnt"}, + {"ncsi_rx_ctrl_cks_err_cnt"}, + + {"ncsi_rx_ctrl_pkt_err_cnt"}, + {"ncsi_rx_pt_dmac_err_cnt"}, + {"ncsi_rx_pt_smac_err_cnt"}, + {"ncsi_rx_pt_pkt_cnt"}, + {"ncsi_rx_fcs_err_cnt"}, + {"ncsi_tx_ctrl_dmac_err_cnt"}, + + {"ncsi_tx_ctrl_smac_err_cnt"}, + {"ncsi_tx_ctrl_pkt_cnt"}, + {"ncsi_tx_pt_dmac_err_cnt"}, + {"ncsi_tx_pt_smac_err_cnt"}, + {"ncsi_tx_pt_pkt_cnt"}, + {"ncsi_tx_pt_pkt_trun_cnt"}, + + {"ncsi_tx_pt_pkt_err_cnt"}, + {"ncsi_tx_ctrl_pkt_err_cnt"}, + {"ncsi_rx_ctrl_pkt_trun_cnt"}, + {"ncsi_rx_ctrl_pkt_cflit_cnt"}, + {"ncsi_rsv1"}, + {"ncsi_rsv2"}, + + {"ncsi_mac_rx_octets_ok"}, + {"ncsi_mac_rx_octets_bad"}, + {"ncsi_mac_rx_uc_pkts"}, + {"ncsi_mac_rx_mc_pkts"}, + {"ncsi_mac_rx_bc_pkts"}, + {"ncsi_mac_rx_pkts_64octets"}, + + {"ncsi_mac_rx_pkts_64to127_octets"}, + {"ncsi_mac_rx_pkts_128to255_octets"}, + {"ncsi_mac_rx_pkts_256to511_octets"}, + {"ncsi_mac_rx_pkts_512to1023_octets"}, + {"ncsi_mac_rx_pkts_1024to1518_octets"}, + {"ncsi_mac_rx_pkts_1519tomax_octets"}, + + {"ncsi_mac_rx_fcs_errors"}, + {"ncsi_mac_rx_long_errors"}, + {"ncsi_mac_rx_jabber_errors"}, + {"ncsi_mac_rx_runt_err_cnt"}, + {"ncsi_mac_rx_short_err_cnt"}, + {"ncsi_mac_rx_filt_pkt_cnt"}, + + {"ncsi_mac_rx_octets_total_filt"}, + {"ncsi_mac_tx_octets_ok"}, + {"ncsi_mac_tx_octets_bad"}, + {"ncsi_mac_tx_uc_pkts"}, + {"ncsi_mac_tx_mc_pkts"}, + {"ncsi_mac_tx_bc_pkts"}, + + {"ncsi_mac_tx_pkts_64octets"}, + {"ncsi_mac_tx_pkts_64to127_octets"}, + {"ncsi_mac_tx_pkts_128to255_octets"}, + {"ncsi_mac_tx_pkts_256to511_octets"}, + {"ncsi_mac_tx_pkts_512to1023_octets"}, + {"ncsi_mac_tx_pkts_1024to1518_octets"}, + + {"ncsi_mac_tx_pkts_1519tomax_octets"}, + {"ncsi_mac_tx_underrun"}, + {"ncsi_mac_tx_crc_error"}, + {"ncsi_mac_tx_pause_frames"}, + {"ncsi_mac_rx_pad_pkts"}, + {"ncsi_mac_rx_pause_frames"}, +}; + +static struct hns3_reg_entry dfx_rtc_reg_list[] = { + {"rtc_rsv0"}, + {"lge_igu_afifo_dfx_0"}, + {"lge_igu_afifo_dfx_1"}, + {"lge_igu_afifo_dfx_2"}, + {"lge_igu_afifo_dfx_3"}, + {"lge_igu_afifo_dfx_4"}, + + {"lge_igu_afifo_dfx_5"}, + {"lge_igu_afifo_dfx_6"}, + {"lge_igu_afifo_dfx_7"}, + {"lge_egu_afifo_dfx_0"}, + {"lge_egu_afifo_dfx_1"}, + {"lge_egu_afifo_dfx_2"}, + + {"lge_egu_afifo_dfx_3"}, + {"lge_egu_afifo_dfx_4"}, + {"lge_egu_afifo_dfx_5"}, + {"lge_egu_afifo_dfx_6"}, + {"lge_egu_afifo_dfx_7"}, + {"cge_igu_afifo_dfx_0"}, + + {"cge_igu_afifo_dfx_1"}, + {"cge_egu_afifo_dfx_0"}, + {"cge_egu_afifo_dfx_i"}, + {"rtc_rsv1"}, + {"rtc_rsv2"}, + {"rtc_rsv3"}, +}; + +static struct hns3_reg_entry dfx_ppp_reg_list[] = { + {"ppp_rsv0"}, + {"ppp_drop_from_prt_pkt_cnt"}, + {"ppp_drop_from_host_pkt_cnt"}, + {"ppp_drop_tx_vlan_proc_cnt"}, + {"ppp_drop_mng_cnt"}, + {"ppp_drop_fd_cnt"}, + + {"ppp_drop_no_dst_cnt"}, + {"ppp_drop_mc_mbid_full_cnt"}, + {"ppp_drop_sc_filtered"}, + {"ppp_ppp_mc_drop_pkt_cnt"}, + {"ppp_drop_pt_cnt"}, + {"ppp_drop_mac_anti_spoof_cnt"}, + + {"ppp_drop_ig_vfv_cnt"}, + {"ppp_drop_ig_prtv_cnt"}, + {"ppp_drop_cnm_pfc_pause_cnt"}, + {"ppp_drop_torus_tc_cnt"}, + {"ppp_drop_torus_lpbk_cnt"}, + {"ppp_ppp_hfs_sts"}, + + {"ppp_mc_rslt_sts"}, + {"ppp_p3u_sts"}, + {"ppp_rsv1", "ppp_rslt_descr_sts"}, + {"ppp_umv_sts_0"}, + {"ppp_umv_sts_1"}, + {"ppp_vfv_sts"}, + + {"ppp_gro_key_cnt"}, + {"ppp_gro_info_cnt"}, + {"ppp_gro_drop_cnt"}, + {"ppp_gro_out_cnt"}, + {"ppp_gro_key_match_data_cnt"}, + {"ppp_gro_key_match_tcam_cnt"}, + + {"ppp_gro_info_match_cnt"}, + {"ppp_gro_free_entry_cnt"}, + {"ppp_gro_inner_dfx_signal"}, + {"ppp_rsv2"}, + {"ppp_rsv3"}, + {"ppp_rsv4"}, + + {"ppp_get_rx_pkt_cnt_l"}, + {"ppp_get_rx_pkt_cnt_h"}, + {"ppp_get_tx_pkt_cnt_l"}, + {"ppp_get_tx_pkt_cnt_h"}, + {"ppp_send_uc_prt2host_pkt_cnt_l"}, + {"ppp_send_uc_prt2host_pkt_cnt_h"}, + + {"ppp_send_uc_prt2prt_pkt_cnt_l"}, + {"ppp_send_uc_prt2prt_pkt_cnt_h"}, + {"ppp_send_uc_host2host_pkt_cnt_l"}, + {"ppp_send_uc_host2host_pkt_cnt_h"}, + {"ppp_send_uc_host2prt_pkt_cnt_l"}, + {"ppp_send_uc_host2prt_pkt_cnt_h"}, + + {"ppp_send_mc_from_prt_cnt_l"}, + {"ppp_send_mc_from_prt_cnt_h"}, + {"ppp_send_mc_from_host_cnt_l"}, + {"ppp_send_mc_from_host_cnt_h"}, + {"ppp_ssu_mc_rd_cnt_l"}, + {"ppp_ssu_mc_rd_cnt_h"}, + + {"ppp_ssu_mc_drop_cnt_l"}, + {"ppp_ssu_mc_drop_cnt_h"}, + {"ppp_ssu_mc_rd_pkt_cnt_l"}, + {"ppp_ssu_mc_rd_pkt_cnt_h"}, + {"ppp_mc_2host_pkt_cnt_l"}, + {"ppp_mc_2host_pkt_cnt_h"}, + + {"ppp_mc_2prt_pkt_cnt_l"}, + {"ppp_mc_2prt_pkt_cnt_h"}, + {"ppp_ntsnos_pkt_cnt_l"}, + {"ppp_ntsnos_pkt_cnt_h"}, + {"ppp_ntup_pkt_cnt_l"}, + {"ppp_ntup_pkt_cnt_h"}, + + {"ppp_ntlcl_pkt_cnt_l"}, + {"ppp_ntlcl_pkt_cnt_h"}, + {"ppp_nttgt_pkt_cnt_l"}, + {"ppp_nttgt_pkt_cnt_h"}, + {"ppp_rtns_pkt_cnt_l"}, + {"ppp_rtns_pkt_cnt_h"}, + + {"ppp_rtlpbk_pkt_cnt_l"}, + {"ppp_rtlpbk_pkt_cnt_h"}, + {"ppp_nr_pkt_cnt_l"}, + {"ppp_nr_pkt_cnt_h"}, + {"ppp_rr_pkt_cnt_l"}, + {"ppp_rr_pkt_cnt_h"}, + + {"ppp_mng_tbl_hit_cnt_l"}, + {"ppp_mng_tbl_hit_cnt_h"}, + {"ppp_fd_tbl_hit_cnt_l"}, + {"ppp_fd_tbl_hit_cnt_h"}, + {"ppp_fd_lkup_cnt_l"}, + {"ppp_fd_lkup_cnt_h"}, + + {"ppp_bc_hit_cnt"}, + {"ppp_bc_hit_cnt_h"}, + {"ppp_um_tbl_uc_hit_cnt"}, + {"ppp_um_tbl_uc_hit_cnt_h"}, + {"ppp_um_tbl_mc_hit_cnt"}, + {"ppp_um_tbl_mc_hit_cnt_h"}, + + {"ppp_um_tbl_snq_hit_cnt_l", "ppp_um_tbl_vmdq1_hit_cnt_l"}, + {"ppp_um_tbl_snq_hit_cnt_h", "ppp_um_tbl_vmdq1_hit_cnt_h"}, + {"ppp_rsv5", "ppp_mta_tbl_hit_cnt_l"}, + {"ppp_rsv6", "ppp_mta_tbl_hit_cnt_h"}, + {"ppp_fwd_bonding_hit_cnt_l"}, + {"ppp_fwd_bonding_hit_cnt_h"}, + + {"ppp_promisc_tbl_hit_cnt_l"}, + {"ppp_promisc_tbl_hit_cnt_h"}, + {"ppp_get_tunl_pkt_cnt_l"}, + {"ppp_get_tunl_pkt_cnt_h"}, + {"ppp_get_bmc_pkt_cnt_l"}, + {"ppp_get_bmc_pkt_cnt_h"}, + + {"ppp_send_uc_prt2bmc_pkt_cnt_l"}, + {"ppp_send_uc_prt2bmc_pkt_cnt_h"}, + {"ppp_send_uc_host2bmc_pkt_cnt_l"}, + {"ppp_send_uc_host2bmc_pkt_cnt_h"}, + {"ppp_send_uc_bmc2host_pkt_cnt_l"}, + {"ppp_send_uc_bmc2host_pkt_cnt_h"}, + + {"ppp_send_uc_bmc2prt_pkt_cnt_l"}, + {"ppp_send_uc_bmc2prt_pkt_cnt_h"}, + {"ppp_mc_2bmc_pkt_cnt_l"}, + {"ppp_mc_2bmc_pkt_cnt_h"}, + {"ppp_rsv7", "ppp_vlan_mirr_cnt_l"}, + {"ppp_rsv8", "ppp_vlan_mirr_cnt_h"}, + + {"ppp_rsv9", "ppp_ig_mirr_cnt_l"}, + {"ppp_rsv10", "ppp_ig_mirr_cnt_h"}, + {"ppp_rsv11", "ppp_eg_mirr_cnt_l"}, + {"ppp_rsv12", "ppp_eg_mirr_cnt_h"}, + {"ppp_rx_default_host_hit_cnt_l"}, + {"ppp_rx_default_host_hit_cnt_h"}, + + {"ppp_lan_pair_cnt_l"}, + {"ppp_lan_pair_cnt_h"}, + {"ppp_um_tbl_mc_hit_pkt_cnt_l"}, + {"ppp_um_tbl_mc_hit_pkt_cnt_h"}, + {"ppp_mta_tbl_hit_pkt_cnt_l"}, + {"ppp_mta_tbl_hit_pkt_cnt_h"}, + + {"ppp_promisc_tbl_hit_pkt_cnt_l"}, + {"ppp_promisc_tbl_hit_pkt_cnt_h"}, + {"ppp_rsv13"}, + {"ppp_rsv14"}, + {"ppp_rsv15"}, + {"ppp_rsv16"}, +}; + +static struct hns3_reg_entry dfx_rcb_reg_list[] = { + {"rcb_rsv0"}, + {"rcb_fsm_dfx_st0"}, + {"rcb_fsm_dfx_st1"}, + {"rcb_fsm_dfx_st2"}, + {"rcb_fifo_dfx_st0"}, + {"rcb_fifo_dfx_st1"}, + + {"rcb_fifo_dfx_st2"}, + {"rcb_fifo_dfx_st3"}, + {"rcb_fifo_dfx_st4"}, + {"rcb_fifo_dfx_st5"}, + {"rcb_fifo_dfx_st6"}, + {"rcb_fifo_dfx_st7"}, + + {"rcb_fifo_dfx_st8"}, + {"rcb_fifo_dfx_st9"}, + {"rcb_fifo_dfx_st10"}, + {"rcb_fifo_dfx_st11"}, + {"rcb_q_credit_vld_0"}, + {"rcb_q_credit_vld_1"}, + + {"rcb_q_credit_vld_2"}, + {"rcb_q_credit_vld_3"}, + {"rcb_q_credit_vld_4"}, + {"rcb_q_credit_vld_5"}, + {"rcb_q_credit_vld_6"}, + {"rcb_q_credit_vld_7"}, + + {"rcb_q_credit_vld_8"}, + {"rcb_q_credit_vld_9"}, + {"rcb_q_credit_vld_10"}, + {"rcb_q_credit_vld_11"}, + {"rcb_q_credit_vld_12"}, + {"rcb_q_credit_vld_13"}, + + {"rcb_q_credit_vld_14"}, + {"rcb_q_credit_vld_15"}, + {"rcb_q_credit_vld_16"}, + {"rcb_q_credit_vld_17"}, + {"rcb_q_credit_vld_18"}, + {"rcb_q_credit_vld_19"}, + + {"rcb_q_credit_vld_20"}, + {"rcb_q_credit_vld_21"}, + {"rcb_q_credit_vld_22"}, + {"rcb_q_credit_vld_23"}, + {"rcb_q_credit_vld_24"}, + {"rcb_q_credit_vld_25"}, + + {"rcb_q_credit_vld_26"}, + {"rcb_q_credit_vld_27"}, + {"rcb_q_credit_vld_28"}, + {"rcb_q_credit_vld_29"}, + {"rcb_q_credit_vld_30"}, + {"rcb_q_credit_vld_31"}, + + {"rcb_gro_bd_serr_cnt"}, + {"rcb_gro_context_serr_cnt"}, + {"rcb_rx_stash_cfg_serr_cnt"}, + {"rcb_rcb_tx_mem_serr_cnt", "rcb_axi_rd_fbd_serr_cnt"}, + {"rcb_gro_bd_merr_cnt"}, + {"rcb_gro_context_merr_cnt"}, + + {"rcb_rx_stash_cfg_merr_cnt"}, + {"rcb_axi_rd_fbd_merr_cnt"}, + {"rcb_rsv1"}, + {"rcb_rsv2"}, + {"rcb_rsv3"}, + {"rcb_rsv4"}, +}; + +static struct hns3_reg_entry dfx_tqp_reg_list[] = { + {"dfx_tqp_q_num"}, + {"rcb_cfg_rx_ring_tail"}, + {"rcb_cfg_rx_ring_head"}, + {"rcb_cfg_rx_ring_fbdnum"}, + {"rcb_cfg_rx_ring_offset"}, + {"rcb_cfg_rx_ring_fbdoffset"}, + + {"rcb_cfg_rx_ring_pktnum_record"}, + {"rcb_cfg_tx_ring_tail"}, + {"rcb_cfg_tx_ring_head"}, + {"rcb_cfg_tx_ring_fbdnum"}, + {"rcb_cfg_tx_ring_offset"}, + {"rcb_cfg_tx_ring_ebdnum"}, +}; + +static struct hns3_reg_entry dfx_ssu_reg_2_list[] = { + {"dfx_ssu2_oq_index"}, + {"dfx_ssu2_queue_cnt"}, + {"dfx_ssu2_rsv0"}, + {"dfx_ssu2_rsv1"}, + {"dfx_ssu2_rsv2"}, + {"dfx_ssu2_rsv3"}, +}; + +struct hns3_dfx_reg_entry { + const struct hns3_reg_entry *regs; + uint32_t entry_num; +}; + +struct hns3_dfx_reg_entry hns3_dfx_reg_list[] = { + {dfx_bios_common_reg_list, RTE_DIM(dfx_bios_common_reg_list)}, + {dfx_ssu_reg_0_list, RTE_DIM(dfx_ssu_reg_0_list)}, + {dfx_ssu_reg_1_list, RTE_DIM(dfx_ssu_reg_1_list)}, + {dfx_igu_egu_reg_list, RTE_DIM(dfx_igu_egu_reg_list)}, + {dfx_rpu_reg_0_list, RTE_DIM(dfx_rpu_reg_0_list)}, + {dfx_rpu_reg_1_list, RTE_DIM(dfx_rpu_reg_1_list)}, + {dfx_ncsi_reg_list, RTE_DIM(dfx_ncsi_reg_list)}, + {dfx_rtc_reg_list, RTE_DIM(dfx_rtc_reg_list)}, + {dfx_ppp_reg_list, RTE_DIM(dfx_ppp_reg_list)}, + {dfx_rcb_reg_list, RTE_DIM(dfx_rcb_reg_list)}, + {dfx_tqp_reg_list, RTE_DIM(dfx_tqp_reg_list)}, + {dfx_ssu_reg_2_list, RTE_DIM(dfx_ssu_reg_2_list)}, +}; + static int hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit, uint32_t *regs_num_64_bit) @@ -108,6 +827,12 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit, *regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]); *regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]); + if (*regs_num_32_bit != RTE_DIM(regs_32_bit_list) || + *regs_num_64_bit * HNS3_64_BIT_REG_SIZE != + RTE_DIM(regs_64_bit_list)) { + hns3_err(hw, "Query register number differ from the list!"); + return -EINVAL; + } return 0; } @@ -122,13 +847,13 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) uint32_t len; int ret; - cmdq_cnt = sizeof(cmdq_reg_addrs); + cmdq_cnt = RTE_DIM(cmdq_reg_list); if (hns->is_vf) - common_cnt = sizeof(common_vf_reg_addrs); + common_cnt = sizeof(common_vf_reg_list); else - common_cnt = sizeof(common_reg_addrs); - ring_cnt = sizeof(ring_reg_addrs); - tqp_intr_cnt = sizeof(tqp_intr_reg_addrs); + common_cnt = RTE_DIM(common_reg_list); + ring_cnt = RTE_DIM(ring_reg_list); + tqp_intr_cnt = RTE_DIM(tqp_intr_reg_list); len = cmdq_cnt + common_cnt + ring_cnt * hw->tqps_num + tqp_intr_cnt * hw->intr_tqps_num; @@ -281,33 +1006,33 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) size_t i; /* fetching per-PF registers values from PF PCIe register space */ - reg_num = sizeof(cmdq_reg_addrs) / sizeof(uint32_t); + reg_num = RTE_DIM(cmdq_reg_list); for (i = 0; i < reg_num; i++) - *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]); + *data++ = hns3_read_dev(hw, cmdq_reg_list[i].addr); if (hns->is_vf) - reg_num = sizeof(common_vf_reg_addrs) / sizeof(uint32_t); + reg_num = RTE_DIM(common_vf_reg_list); else - reg_num = sizeof(common_reg_addrs) / sizeof(uint32_t); + reg_num = RTE_DIM(common_reg_list); for (i = 0; i < reg_num; i++) if (hns->is_vf) - *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]); + *data++ = hns3_read_dev(hw, common_vf_reg_list[i].addr); else - *data++ = hns3_read_dev(hw, common_reg_addrs[i]); + *data++ = hns3_read_dev(hw, common_reg_list[i].addr); - reg_num = sizeof(ring_reg_addrs) / sizeof(uint32_t); + reg_num = RTE_DIM(ring_reg_list); for (j = 0; j < hw->tqps_num; j++) { reg_offset = hns3_get_tqp_reg_offset(j); for (i = 0; i < reg_num; i++) *data++ = hns3_read_dev(hw, - ring_reg_addrs[i] + reg_offset); + ring_reg_list[i].addr + reg_offset); } - reg_num = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t); + reg_num = RTE_DIM(tqp_intr_reg_list); for (j = 0; j < hw->intr_tqps_num; j++) { reg_offset = hns3_get_tqp_intr_reg_offset(j); for (i = 0; i < reg_num; i++) - *data++ = hns3_read_dev(hw, tqp_intr_reg_addrs[i] + + *data++ = hns3_read_dev(hw, tqp_intr_reg_list[i].addr + reg_offset); } return data - origin_data_ptr; From patchwork Thu Mar 7 03:02:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 138077 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B80A343B62; Thu, 7 Mar 2024 04:07:42 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 86D5642E94; Thu, 7 Mar 2024 04:07:14 +0100 (CET) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id D54FD402F2 for ; Thu, 7 Mar 2024 04:07:06 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4TqvLb1QHcz1xqJR for ; Thu, 7 Mar 2024 11:05:27 +0800 (CST) Received: from kwepemd100004.china.huawei.com (unknown [7.221.188.31]) by mail.maildlp.com (Postfix) with ESMTPS id A031F1A0172 for ; Thu, 7 Mar 2024 11:07:05 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemd100004.china.huawei.com (7.221.188.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Thu, 7 Mar 2024 11:07:05 +0800 From: Jie Hai To: , Yisen Zhuang CC: , , Subject: [PATCH v5 6/7] net/hns3: support filter directly accessed registers Date: Thu, 7 Mar 2024 11:02:46 +0800 Message-ID: <20240307030247.599394-7-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240307030247.599394-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240307030247.599394-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd100004.china.huawei.com (7.221.188.31) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch supports reporting names of registers which can be directly accessed by addresses and filtering them by names. Signed-off-by: Jie Hai Reviewed-by: Huisong Li --- drivers/net/hns3/hns3_regs.c | 198 +++++++++++++++++++++++++++++------ 1 file changed, 167 insertions(+), 31 deletions(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index b7e4f78eecde..7c3bd162f067 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -837,8 +837,24 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit, return 0; } +static uint32_t +hns3_get_direct_regs_cnt(const struct direct_reg_list *list, + uint32_t len, const char *filter) +{ + uint32_t i; + uint32_t count = 0; + + for (i = 0 ; i < len; i++) { + if (filter != NULL && !strstr(list[i].name, filter)) + continue; + count++; + } + + return count; +} + static int -hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) +hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length, const char *filter) { struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); uint32_t cmdq_cnt, common_cnt, ring_cnt, tqp_intr_cnt; @@ -847,13 +863,18 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) uint32_t len; int ret; - cmdq_cnt = RTE_DIM(cmdq_reg_list); + cmdq_cnt = hns3_get_direct_regs_cnt(cmdq_reg_list, + RTE_DIM(cmdq_reg_list), filter); if (hns->is_vf) - common_cnt = sizeof(common_vf_reg_list); + common_cnt = hns3_get_direct_regs_cnt(common_vf_reg_list, + RTE_DIM(common_vf_reg_list), filter); else - common_cnt = RTE_DIM(common_reg_list); - ring_cnt = RTE_DIM(ring_reg_list); - tqp_intr_cnt = RTE_DIM(tqp_intr_reg_list); + common_cnt = hns3_get_direct_regs_cnt(common_reg_list, + RTE_DIM(common_reg_list), filter); + ring_cnt = hns3_get_direct_regs_cnt(ring_reg_list, + RTE_DIM(ring_reg_list), filter); + tqp_intr_cnt = hns3_get_direct_regs_cnt(tqp_intr_reg_list, + RTE_DIM(tqp_intr_reg_list), filter); len = cmdq_cnt + common_cnt + ring_cnt * hw->tqps_num + tqp_intr_cnt * hw->intr_tqps_num; @@ -995,47 +1016,160 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) return 0; } -static int -hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) + +static uint32_t +hns3_direct_access_cmdq_reg(struct hns3_hw *hw, + struct rte_dev_reg_info *regs, + uint32_t count) { - struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); - uint32_t *origin_data_ptr = data; - uint32_t reg_offset; + uint32_t *data = regs->data; size_t reg_num; - uint16_t j; + data += count; size_t i; - /* fetching per-PF registers values from PF PCIe register space */ reg_num = RTE_DIM(cmdq_reg_list); - for (i = 0; i < reg_num; i++) + for (i = 0; i < reg_num; i++) { + if (regs->filter != NULL && + !strstr(cmdq_reg_list[i].name, regs->filter)) + continue; *data++ = hns3_read_dev(hw, cmdq_reg_list[i].addr); + if (regs->names == NULL) + continue; + snprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE, + "%s", cmdq_reg_list[i].name); + } - if (hns->is_vf) - reg_num = RTE_DIM(common_vf_reg_list); - else - reg_num = RTE_DIM(common_reg_list); - for (i = 0; i < reg_num; i++) - if (hns->is_vf) - *data++ = hns3_read_dev(hw, common_vf_reg_list[i].addr); - else - *data++ = hns3_read_dev(hw, common_reg_list[i].addr); + return count; +} +static uint32_t +hns3_direct_access_common_reg(struct hns3_hw *hw, + struct rte_dev_reg_info *regs, + uint32_t count) +{ + uint32_t *data = regs->data; + size_t reg_num; + data += count; + size_t i; + reg_num = RTE_DIM(common_reg_list); + for (i = 0; i < reg_num; i++) { + if (regs->filter != NULL && + !strstr(common_reg_list[i].name, regs->filter)) + continue; + *data++ = hns3_read_dev(hw, common_reg_list[i].addr); + if (regs->names == NULL) + continue; + snprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE, + "%s", common_reg_list[i].name); + } + + return count; +} + +static uint32_t +hns3_direct_access_vf_common_reg(struct hns3_hw *hw, + struct rte_dev_reg_info *regs, + uint32_t count) +{ + uint32_t *data = regs->data; + size_t reg_num; + data += count; + size_t i; + + reg_num = RTE_DIM(common_vf_reg_list); + for (i = 0; i < reg_num; i++) { + if (regs->filter != NULL && + !strstr(common_vf_reg_list[i].name, regs->filter)) + continue; + *data++ = hns3_read_dev(hw, common_vf_reg_list[i].addr); + if (regs->names == NULL) + continue; + snprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE, + "%s", common_vf_reg_list[i].name); + } + + return count; +} + +static uint32_t +hns3_direct_access_ring_reg(struct hns3_hw *hw, + struct rte_dev_reg_info *regs, + uint32_t count) +{ + uint32_t *data = regs->data; + uint32_t reg_offset; + size_t reg_num; + uint16_t j; + size_t i; + + data += count; reg_num = RTE_DIM(ring_reg_list); for (j = 0; j < hw->tqps_num; j++) { reg_offset = hns3_get_tqp_reg_offset(j); - for (i = 0; i < reg_num; i++) - *data++ = hns3_read_dev(hw, - ring_reg_list[i].addr + reg_offset); + for (i = 0; i < reg_num; i++) { + if (regs->filter != NULL && + !strstr(ring_reg_list[i].name, regs->filter)) + continue; + *data++ = hns3_read_dev(hw, ring_reg_list[i].addr + + reg_offset); + if (regs->names == NULL) + continue; + snprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE, + "queue_%u_%s", j, ring_reg_list[i].name); + } } + return count; +} + +static uint32_t +hns3_direct_access_tqp_intr_reg(struct hns3_hw *hw, + struct rte_dev_reg_info *regs, + uint32_t count) +{ + uint32_t *data = regs->data; + uint32_t reg_offset; + size_t reg_num; + uint16_t j; + size_t i; + + data += count; reg_num = RTE_DIM(tqp_intr_reg_list); for (j = 0; j < hw->intr_tqps_num; j++) { reg_offset = hns3_get_tqp_intr_reg_offset(j); - for (i = 0; i < reg_num; i++) + for (i = 0; i < reg_num; i++) { + if (regs->filter != NULL && + !strstr(tqp_intr_reg_list[i].name, regs->filter)) + continue; *data++ = hns3_read_dev(hw, tqp_intr_reg_list[i].addr + reg_offset); + if (regs->names == NULL) + continue; + snprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE, + "queue_%u_%s", j, tqp_intr_reg_list[i].name); + } } - return data - origin_data_ptr; + + return count; +} + +static uint32_t +hns3_direct_access_regs(struct hns3_hw *hw, + struct rte_dev_reg_info *regs, + uint32_t count) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + + count = hns3_direct_access_cmdq_reg(hw, regs, count); + if (!hns->is_vf) + count = hns3_direct_access_common_reg(hw, regs, count); + else + count = hns3_direct_access_vf_common_reg(hw, regs, count); + + count = hns3_direct_access_ring_reg(hw, regs, count); + count = hns3_direct_access_tqp_intr_reg(hw, regs, count); + + return count; } static int @@ -1177,11 +1311,12 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) struct hns3_hw *hw = &hns->hw; uint32_t regs_num_32_bit; uint32_t regs_num_64_bit; + uint32_t count = 0; uint32_t length; uint32_t *data; int ret; - ret = hns3_get_regs_length(hw, &length); + ret = hns3_get_regs_length(hw, &length, regs->filter); if (ret) return ret; @@ -1193,13 +1328,14 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) } /* Only full register dump is supported */ - if (regs->length && regs->length != length) + if ((regs->length && regs->length != length)) return -ENOTSUP; regs->version = hw->fw_version; /* fetching per-PF registers values from PF PCIe register space */ - data += hns3_direct_access_regs(hw, data); + count = hns3_direct_access_regs(hw, regs, count); + data += count; if (hns->is_vf) return 0; From patchwork Thu Mar 7 03:02:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 138078 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4349F43B62; Thu, 7 Mar 2024 04:07:49 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CAC2442EA7; Thu, 7 Mar 2024 04:07:15 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id 2954B42DD7 for ; Thu, 7 Mar 2024 04:07:07 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.162.112]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4TqvKm0Kqnz1QB0h for ; Thu, 7 Mar 2024 11:04:44 +0800 (CST) Received: from kwepemd100004.china.huawei.com (unknown [7.221.188.31]) by mail.maildlp.com (Postfix) with ESMTPS id 1BF7C1402C7 for ; Thu, 7 Mar 2024 11:07:06 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemd100004.china.huawei.com (7.221.188.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Thu, 7 Mar 2024 11:07:05 +0800 From: Jie Hai To: , Yisen Zhuang CC: , , Subject: [PATCH v5 7/7] net/hns3: support filter dump of registers Date: Thu, 7 Mar 2024 11:02:47 +0800 Message-ID: <20240307030247.599394-8-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240307030247.599394-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240307030247.599394-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd100004.china.huawei.com (7.221.188.31) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch supports reporting names of the dfx registers which filtering them by names. Signed-off-by: Jie Hai --- drivers/net/hns3/hns3_regs.c | 277 +++++++++++++++++++++++++++++------ 1 file changed, 230 insertions(+), 47 deletions(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index 7c3bd162f067..8b6bf0a513fa 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -12,7 +12,8 @@ #define HNS3_64_BIT_REG_SIZE (sizeof(uint64_t) / sizeof(uint32_t)) -static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count); +static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, + uint32_t *count, const char *filter); struct direct_reg_list { const char *name; @@ -853,12 +854,41 @@ hns3_get_direct_regs_cnt(const struct direct_reg_list *list, return count; } +static uint32_t +hns3_get_32_64_regs_cnt(struct hns3_hw *hw, const char *filter) +{ + uint32_t regs_num_32_bit, regs_num_64_bit; + int ret; + uint32_t i; + uint32_t count = 0; + + ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); + if (ret) { + hns3_err(hw, "fail to get the number of registers, " + "ret = %d.", ret); + return ret; + } + + for (i = 0 ; i < regs_num_32_bit; i++) { + if (filter != NULL && + !strstr(regs_32_bit_list[i].new_name, filter)) + continue; + count++; + } + for (i = 0 ; i < regs_num_64_bit * HNS3_64_BIT_REG_SIZE; i++) { + if (filter != NULL && + !strstr(regs_64_bit_list[i].new_name, filter)) + continue; + count++; + } + return count; +} + static int hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length, const char *filter) { struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); uint32_t cmdq_cnt, common_cnt, ring_cnt, tqp_intr_cnt; - uint32_t regs_num_32_bit, regs_num_64_bit; uint32_t dfx_reg_cnt; uint32_t len; int ret; @@ -880,16 +910,9 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length, const char *filter) tqp_intr_cnt * hw->intr_tqps_num; if (!hns->is_vf) { - ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); - if (ret) { - hns3_err(hw, "fail to get the number of registers, " - "ret = %d.", ret); - return ret; - } - dfx_reg_cnt = regs_num_32_bit + - regs_num_64_bit * HNS3_64_BIT_REG_SIZE; + dfx_reg_cnt = hns3_get_32_64_regs_cnt(hw, filter); - ret = hns3_get_dfx_reg_cnt(hw, &dfx_reg_cnt); + ret = hns3_get_dfx_reg_cnt(hw, &dfx_reg_cnt, filter); if (ret) { hns3_err(hw, "fail to get the number of dfx registers, " "ret = %d.", ret); @@ -903,19 +926,19 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length, const char *filter) } static int -hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) +hns3_get_32_bit_regs(struct hns3_hw *hw, void *data) { #define HNS3_32_BIT_REG_RTN_DATANUM 8 #define HNS3_32_BIT_DESC_NODATA_LEN 2 struct hns3_cmd_desc *desc; uint32_t *reg_val = data; uint32_t *desc_data; + uint32_t regs_num; int cmd_num; int i, k, n; int ret; - if (regs_num == 0) - return 0; + regs_num = RTE_DIM(regs_32_bit_list); cmd_num = DIV_ROUND_UP(regs_num + HNS3_32_BIT_DESC_NODATA_LEN, HNS3_32_BIT_REG_RTN_DATANUM); @@ -959,20 +982,68 @@ hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) return 0; } +static void +hns3_filter_32_bit_regs(struct rte_dev_reg_info *regs, + uint32_t *count, uint32_t *data) +{ + uint32_t *regs_data; + regs_data = regs->data; + regs_data += *count; + uint32_t i; + + for (i = 0; i < RTE_DIM(regs_32_bit_list); i++) { + if (regs->filter != NULL && + !strstr(regs_32_bit_list[i].new_name, regs->filter)) { + data++; + continue; + } + *regs_data++ = *data++; + if (regs->names == NULL) + continue; + snprintf(regs->names[(*count)++].name, RTE_ETH_REG_NAME_SIZE, + "%s", regs_32_bit_list[i].new_name); + } +} + +static int +hns3_get_32_bit_regs_filtered(struct hns3_hw *hw, + struct rte_dev_reg_info *regs, uint32_t *count) +{ + uint32_t *data; + int ret; + + if (count == NULL) + return -EINVAL; + + data = rte_zmalloc(NULL, sizeof(uint32_t) * RTE_DIM(regs_32_bit_list), 0); + if (data == NULL) + return -ENOMEM; + + ret = hns3_get_32_bit_regs(hw, data); + if (ret) { + hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); + rte_free(data); + return ret; + } + + hns3_filter_32_bit_regs(regs, count, data); + return 0; +} + static int -hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) +hns3_get_64_bit_regs(struct hns3_hw *hw, void *data) { #define HNS3_64_BIT_REG_RTN_DATANUM 4 #define HNS3_64_BIT_DESC_NODATA_LEN 1 struct hns3_cmd_desc *desc; uint64_t *reg_val = data; uint64_t *desc_data; + uint32_t regs_num; int cmd_num; int i, k, n; int ret; - if (regs_num == 0) - return 0; + regs_num = RTE_DIM(regs_64_bit_list); cmd_num = DIV_ROUND_UP(regs_num + HNS3_64_BIT_DESC_NODATA_LEN, HNS3_64_BIT_REG_RTN_DATANUM); @@ -1016,6 +1087,54 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) return 0; } +static void +hns3_filter_64_bit_regs(struct rte_dev_reg_info *regs, + uint32_t *count, uint32_t *data) +{ + uint32_t *regs_data; + regs_data = regs->data; + regs_data += *count; + uint32_t i; + + for (i = 0; i < RTE_DIM(regs_64_bit_list); i++) { + if (regs->filter != NULL && + !strstr(regs_64_bit_list[i].new_name, regs->filter)) { + data++; + continue; + } + *regs_data++ = *data++; + if (regs->names == NULL) + continue; + snprintf(regs->names[(*count)++].name, RTE_ETH_REG_NAME_SIZE, + "%s", regs_64_bit_list[i].new_name); + } +} + +static int +hns3_get_64_bit_regs_filtered(struct hns3_hw *hw, + struct rte_dev_reg_info *regs, uint32_t *count) +{ + uint32_t *data; + int ret = 0; + + if (count == NULL) + return -EINVAL; + + data = rte_zmalloc(NULL, sizeof(uint32_t) * RTE_DIM(regs_64_bit_list), 0); + if (data == NULL) + return -ENOMEM; + + ret = hns3_get_64_bit_regs(hw, data); + if (ret) { + hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); + goto out; + } + + hns3_filter_64_bit_regs(regs, count, data); +out: + rte_free(data); + return 0; +} static uint32_t hns3_direct_access_cmdq_reg(struct hns3_hw *hw, @@ -1115,7 +1234,7 @@ hns3_direct_access_ring_reg(struct hns3_hw *hw, if (regs->names == NULL) continue; snprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE, - "queue_%u_%s", j, ring_reg_list[i].name); + "queue_%u_%s", j, ring_reg_list[i].name); } } @@ -1146,7 +1265,7 @@ hns3_direct_access_tqp_intr_reg(struct hns3_hw *hw, if (regs->names == NULL) continue; snprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE, - "queue_%u_%s", j, tqp_intr_reg_list[i].name); + "queue_%u_%s", j, tqp_intr_reg_list[i].name); } } @@ -1248,31 +1367,48 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg) } static int -hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) +hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count, const char *filter) { int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); + uint32_t bd_num, data_len, reg_num = 0; + const struct hns3_reg_entry *regs; uint32_t bd_num_list[opcode_num]; + uint32_t i, j; int ret; - int i; ret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num); if (ret) return ret; - for (i = 0; i < opcode_num; i++) - *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; + for (i = 0; i < (uint32_t)opcode_num; i++) { + bd_num = bd_num_list[i]; + data_len = bd_num * HNS3_CMD_DESC_DATA_NUM; + if (data_len != hns3_dfx_reg_list[i].entry_num) { + hns3_err(hw, "The number of registers(%u) diff from registers list(%u)!\n", + data_len, hns3_dfx_reg_list[i].entry_num); + return -EINVAL; + } + regs = hns3_dfx_reg_list[i].regs; + for (j = 0; j < data_len; j++) { + if (filter != NULL && + !strstr(regs[j].new_name, filter)) + continue; + reg_num++; + } + } + + *count += reg_num; return 0; } static int -hns3_get_dfx_regs(struct hns3_hw *hw, void **data) +hns3_get_dfx_regs(struct hns3_hw *hw, uint32_t *data) { int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); uint32_t max_bd_num, bd_num, opcode; uint32_t bd_num_list[opcode_num]; struct hns3_cmd_desc *cmd_descs; - uint32_t *reg_val = (uint32_t *)*data; int ret; int i; @@ -1296,32 +1432,87 @@ hns3_get_dfx_regs(struct hns3_hw *hw, void **data) ret = hns3_dfx_reg_cmd_send(hw, cmd_descs, bd_num, opcode); if (ret) break; - reg_val += hns3_dfx_reg_fetch_data(cmd_descs, bd_num, reg_val); + data += hns3_dfx_reg_fetch_data(cmd_descs, bd_num, data); } rte_free(cmd_descs); - *data = (void *)reg_val; return ret; } +static void +hns3_filter_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, + uint32_t *count, uint32_t *data) +{ + uint32_t *regs_data = regs->data; + const char *name = NULL; + uint32_t i, j, cnt; + + cnt = *count; + regs_data += cnt; + for (i = 0; i < RTE_DIM(hns3_dfx_reg_list); i++) { + for (j = 0; j < hns3_dfx_reg_list[i].entry_num; j++) { + if (hw->revision < PCI_REVISION_ID_HIP09_A && + hns3_dfx_reg_list[i].regs[j].old_name != NULL) + name = hns3_dfx_reg_list[i].regs[j].old_name; + else + name = hns3_dfx_reg_list[i].regs[j].new_name; + + if (regs->filter != NULL && !strstr(name, regs->filter)) { + data++; + continue; + } + *regs_data++ = *data++; + + if (regs->names == NULL) + continue; + snprintf(regs->names[cnt++].name, + RTE_ETH_REG_NAME_SIZE, "%s", name); + } + } + *count = cnt; +} + +static int +hns3_get_dfx_regs_filtered(struct hns3_hw *hw, struct rte_dev_reg_info *regs, + uint32_t *count) +{ + uint32_t reg_num = 0; + uint32_t *data; + uint32_t i; + int ret; + + for (i = 0; i < RTE_DIM(hns3_dfx_reg_list); i++) + reg_num += hns3_dfx_reg_list[i].entry_num; + + data = rte_zmalloc(NULL, sizeof(uint32_t) * reg_num, 0); + if (data == NULL) { + hns3_err(hw, "No memory for dfx regs!\n"); + return -ENOMEM; + } + ret = hns3_get_dfx_regs(hw, data); + if (ret != 0) + goto out; + + hns3_filter_dfx_regs(hw, regs, count, data); +out: + rte_free(data); + return ret; +} + int hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) { struct hns3_adapter *hns = eth_dev->data->dev_private; struct hns3_hw *hw = &hns->hw; - uint32_t regs_num_32_bit; - uint32_t regs_num_64_bit; uint32_t count = 0; uint32_t length; - uint32_t *data; int ret; ret = hns3_get_regs_length(hw, &length, regs->filter); if (ret) return ret; - data = regs->data; - if (data == NULL) { + if (regs->data == NULL) { regs->length = length; regs->width = sizeof(uint32_t); return 0; @@ -1335,31 +1526,23 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) /* fetching per-PF registers values from PF PCIe register space */ count = hns3_direct_access_regs(hw, regs, count); - data += count; if (hns->is_vf) return 0; - ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); - if (ret) { - hns3_err(hw, "Get register number failed, ret = %d", ret); - return ret; - } - - /* fetching PF common registers values from firmware */ - ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data); - if (ret) { + ret = hns3_get_32_bit_regs_filtered(hw, regs, &count); + if (ret != 0) { hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); return ret; } - data += regs_num_32_bit; - ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data); - if (ret) { + ret = hns3_get_64_bit_regs_filtered(hw, regs, &count); + if (ret != 0) { hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); return ret; } - data += regs_num_64_bit * HNS3_64_BIT_REG_SIZE; - return hns3_get_dfx_regs(hw, (void **)&data); + ret = hns3_get_dfx_regs_filtered(hw, regs, &count); + regs->length = count; + return 0; }