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(seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00050.seli.gic.ericsson.se (Postfix) with ESMTP id AF30B1C006A; Sat, 2 Mar 2024 15:02:13 +0100 (CET) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , Heng Wang , =?utf-8?q?M?= =?utf-8?q?attias_R=C3=B6nnblom?= Subject: [RFC 1/7] eal: extend bit manipulation functions Date: Sat, 2 Mar 2024 14:53:22 +0100 Message-ID: <20240302135328.531940-2-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240302135328.531940-1-mattias.ronnblom@ericsson.com> References: <20240302135328.531940-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00027A69:EE_|DBAPR07MB6549:EE_ X-MS-Office365-Filtering-Correlation-Id: 615df190-2ece-4eb4-5c8f-08dc3ac15d05 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: n3VxHhbhHxwc2jqsg+JnRGOmEu+Lz5M5/o2R23Mk06I8CAhJiU/wajjoSwwMFXkYy1KzyT8dHtG0IIg2m7+R9jCkAl1WXrp7FO8VRBC5tPuVR8V1fvGVydmYv+LB/0dad4XkInK4FaWmcer6PDDW7K6JTjWjw7Kixh66NRn6ZERelisULROz3wzUl6/Lo0xm8WiRNl9yV+h4RsjyWGizBhR26spi8l6zaVbKmDCb/FvBp9IQaxjfWXTaJMZC5VnlNJDDiAs6G4F3zMLmJF7+v3Wn4pLCBP10W1nkfz+QQYcPcNBPIw6Upd6BuIzJMD2DtLCwsdoQKOnRAI7BIU+PynPasJ4jT5OLPWO+wV1T2hCVZ0CAHXI1TzldyrGBt/PiUfnnqOUfQCsKeuKPieTQ6dvjWIaOxtcm0vR9Bor+PrgK0lzoq0oqsWha/Wwy20hpNOTgOD30myuWWWWmRF/ZEHD0bNI2VwnxCQKDGmjYkXs3+Y98qRLZ4z4xs2hSoMGI4HjCRBRm9WAENraC1Qdb0wVLmQhjGONWbDsk5EM46MbMpgkklezPl4uLtd23obM/Hs5P5M3gRL7ULOGVrdf7WVM7teNe+y/n5N8J3cfwEG4iBTDM7O6Yla5O78TU/E1sHCvx9DTovasBvh/TwxNeEnQwKwomGlVpGUylUnvo1Va89GY1jM/F6wAL1olbvzs9bCJ97KlMQpDIKe8BILVTEF+IMP//ytR7lyjxbrE3AB8dOT7bsmoyoSMlbCMnYKmy X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(376005)(36860700004)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2024 14:02:14.2874 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 615df190-2ece-4eb4-5c8f-08dc3ac15d05 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A69.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR07MB6549 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add functionality to test, set, clear, and assign the value to individual bits in 32-bit or 64-bit words. These functions have no implications on memory ordering, atomicity and does not use volatile and thus does not prevent any compiler optimizations. Signed-off-by: Mattias Rönnblom --- lib/eal/include/rte_bitops.h | 194 ++++++++++++++++++++++++++++++++++- 1 file changed, 192 insertions(+), 2 deletions(-) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index 449565eeae..9a368724d5 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -2,6 +2,7 @@ * Copyright(c) 2020 Arm Limited * Copyright(c) 2010-2019 Intel Corporation * Copyright(c) 2023 Microsoft Corporation + * Copyright(c) 2024 Ericsson AB */ #ifndef _RTE_BITOPS_H_ @@ -11,8 +12,9 @@ * @file * Bit Operations * - * This file defines a family of APIs for bit operations - * without enforcing memory ordering. + * This file provides functionality for low-level, single-word + * arithmetic and bit-level operations, such as counting or + * setting individual bits. */ #include @@ -105,6 +107,194 @@ extern "C" { #define RTE_FIELD_GET64(mask, reg) \ ((typeof(mask))(((reg) & (mask)) >> rte_ctz64(mask))) +/** + * Test if a particular bit in a 32-bit word is set. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 32-bit word to query. + * @param nr + * The index of the bit (0-31). + * @return + * Returns true if the bit is set, and false otherwise. + */ +static inline bool +rte_bit_test32(const uint32_t *addr, unsigned int nr); + +/** + * Set bit in 32-bit word. + * + * Set bit specified by @c nr in the 32-bit word pointed to by + * @c addr to '1'. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 32-bit word to modify. + * @param nr + * The index of the bit (0-31). + */ +static inline void +rte_bit_set32(uint32_t *addr, unsigned int nr); + +/** + * Clear bit in 32-bit word. + * + * Set bit specified by @c nr in the 32-bit word pointed to by + * @c addr to '0'. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 32-bit word to modify. + * @param nr + * The index of the bit (0-31). + */ +static inline void +rte_bit_clear32(uint32_t *addr, unsigned int nr); + +/** + * Assign a value to bit in a 32-bit word. + * + * Set bit specified by @c nr in the 32-bit word pointed to by + * @c addr to the value indicated by @c value. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 32-bit word to modify. + * @param nr + * The index of the bit (0-31). + * @param value + * The new value of the bit - true for '1', or false for '0'. + */ +static inline void +rte_bit_assign32(uint32_t *addr, unsigned int nr, bool value) +{ + if (value) + rte_bit_set32(addr, nr); + else + rte_bit_clear32(addr, nr); +} + +/** + * Test if a particular bit in a 64-bit word is set. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 64-bit word to query. + * @param nr + * The index of the bit (0-63). + * @return + * Returns true if the bit is set, and false otherwise. + */ +static inline bool +rte_bit_test64(const uint64_t *addr, unsigned int nr); + +/** + * Set bit in 64-bit word. + * + * Set bit specified by @c nr in the 64-bit word pointed to by + * @c addr to '1'. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 64-bit word to modify. + * @param nr + * The index of the bit (0-63). + */ +static inline void +rte_bit_set64(uint64_t *addr, unsigned int nr); + +/** + * Clear bit in 64-bit word. + * + * Set bit specified by @c nr in the 64-bit word pointed to by + * @c addr to '0'. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 64-bit word to modify. + * @param nr + * The index of the bit (0-63). + */ +static inline void +rte_bit_clear64(uint64_t *addr, unsigned int nr); + +/** + * Assign a value to bit in a 64-bit word. + * + * Set bit specified by @c nr in the 64-bit word pointed to by + * @c addr to the value indicated by @c value. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 64-bit word to modify. + * @param nr + * The index of the bit (0-63). + * @param value + * The new value of the bit - true for '1', or false for '0'. + */ +static inline void +rte_bit_assign64(uint64_t *addr, unsigned int nr, bool value) +{ + if (value) + rte_bit_set64(addr, nr); + else + rte_bit_clear64(addr, nr); +} + +#define __RTE_GEN_BIT_TEST(name, size, qualifier) \ + static inline bool \ + name(const qualifier uint ## size ## _t *addr, unsigned int nr) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + return *addr & mask; \ + } + +#define __RTE_GEN_BIT_SET(name, size, qualifier) \ + static inline void \ + name(qualifier uint ## size ## _t *addr, unsigned int nr) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + *addr |= mask; \ + } \ + +#define __RTE_GEN_BIT_CLEAR(name, size, qualifier) \ + static inline void \ + name(qualifier uint ## size ## _t *addr, unsigned int nr) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = ~((uint ## size ## _t)1 << nr); \ + (*addr) &= mask; \ + } \ + +__RTE_GEN_BIT_TEST(rte_bit_test32, 32,) +__RTE_GEN_BIT_SET(rte_bit_set32, 32,) +__RTE_GEN_BIT_CLEAR(rte_bit_clear32, 32,) + +__RTE_GEN_BIT_TEST(rte_bit_test64, 64,) +__RTE_GEN_BIT_SET(rte_bit_set64, 64,) +__RTE_GEN_BIT_CLEAR(rte_bit_clear64, 64,) + /*------------------------ 32-bit relaxed operations ------------------------*/ /** From patchwork Sat Mar 2 13:53:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 137803 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2C13743C3A; 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Signed-off-by: Mattias Rönnblom Signed-off-by: Mattias Rönnblom Acked-by: Tyler Retzlaff --- lib/eal/include/rte_bitops.h | 81 ++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index 9a368724d5..afd0f11033 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -107,6 +107,87 @@ extern "C" { #define RTE_FIELD_GET64(mask, reg) \ ((typeof(mask))(((reg) & (mask)) >> rte_ctz64(mask))) +/** + * Test bit in word. + * + * Generic selection macro to test the value of a bit in a 32-bit or + * 64-bit word. The type of operation depends on the type of the @c + * addr parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_test(addr, nr) \ + _Generic((addr), \ + uint32_t *: rte_bit_test32, \ + uint64_t *: rte_bit_test64)(addr, nr) + +/** + * Set bit in word. + * + * Generic selection macro to set a bit in a 32-bit or 64-bit + * word. The type of operation depends on the type of the @c addr + * parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_set(addr, nr) \ + _Generic((addr), \ + uint32_t *: rte_bit_set32, \ + uint64_t *: rte_bit_set64)(addr, nr) + +/** + * Clear bit in word. + * + * Generic selection macro to clear a bit in a 32-bit or 64-bit + * word. The type of operation depends on the type of the @c addr + * parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_clear(addr, nr) \ + _Generic((addr), \ + uint32_t *: rte_bit_clear32, \ + uint64_t *: rte_bit_clear64)(addr, nr) + +/** + * Assign a value to a bit in word. + * + * Generic selection macro to assign a value to a bit in a 32-bit or 64-bit + * word. The type of operation depends on the type of the @c addr parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + */ +#define rte_bit_assign(addr, nr, value) \ + _Generic((addr), \ + uint32_t *: rte_bit_assign32, \ + uint64_t *: rte_bit_assign64)(addr, nr, value) + /** * Test if a particular bit in a 32-bit word is set. * From patchwork Sat Mar 2 13:53:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 137804 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9CCB143C3A; Sat, 2 Mar 2024 15:02:47 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4DFA042DC3; Sat, 2 Mar 2024 15:02:22 +0100 (CET) Received: from EUR02-VI1-obe.outbound.protection.outlook.com (mail-vi1eur02on2051.outbound.protection.outlook.com [40.107.241.51]) by mails.dpdk.org (Postfix) with ESMTP id 3981242D7D for ; Sat, 2 Mar 2024 15:02:18 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UGTK7sORqRqccFFUEz6w6CvAmnyO0FS+NMY69/YLqJ1f/jSh3DnfT9XatyAbPQKvDmg/lN3xywtXQcUi5oaVmGo7Y7PPEYxaeFXwz+JDCG/N4DC0NmOiJPY2K9lnVlPXSrspHOfwIloHOjYWxghIhVff8bS+GQ2dzx7sjNzjW1w+kJwkRX39gexI9r/w+tb9dbSc3Tp2OxSb6vT1lz0NRlHBSraU4eIFa0yCbJQmVaQtdHhb5n6aHy6TVTPz7MbJ6U4SPy199wB3jsvDGcGvZCc2dbMeeUVBf4FebqT/b8swj3izwaMtUJBegA9ozq9w4MQ5tkVVSEwNv457vbeokQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4U8aKmI7T9xrmV77i4eS/o7kXhqw+nMOJ0MHBBGteR0=; b=nxxf0YxQijIHNijx48wTewYVnuESVsOmTnh+Pwfz1nBINdqIHHuQPasaekwixUc9IHViBAxht2q4wKkAAxHqdD8dW/6oD6P9ropG8ImmrZ8zVjXfhHChaTSk3FyTCWf7kBBzgmc8aLB80t9MaH/opqs9UzlMeXVskVbgv1mQTf2r546+v53JRes1u5ILZkvx4XnkqvM7pBGISzCt+CAv1Gy0ke6YDTuuAASRRNLT0UZ3jq5Oam2wYh7FMbOd/437/nGMHzoiLEUmzuSMIe5dNn5Y3cTERgXa+gDD1XJcbjZWZgmUcLeVcBhpZ2wcnLZw7EwZiOU31qSuTXzDEYU9pQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4U8aKmI7T9xrmV77i4eS/o7kXhqw+nMOJ0MHBBGteR0=; b=CeW9AyF3maJszxozaSZfvNECOAE6FgxH+xhepQG+ogEMwBiY1wz/cp0ProDPs+22rm5Srhq0YzVJbZnDDx4ddEQiuEvf6aLZfALBJ9oprF3C+DIXkpmSnTA4m/NkJHVAmqy+B3hQltniZYS5BQ+SBz8umnVoku6Bi2IdP5vrw17pOAWDppBMq/2xwE8+13lLudijaaogbDSn6warH5S66HZtE+4M6ZmC3Rff3VofR3ortwm12DBzi3bQRU9sDppUWHyrLtY0mMvi5YerCn+6UG200QrtY9N1Ki4j5gfHBn+exu645/NaibvOBQfyH0ZrBf3AkgtLLbKRSHNsy3hPNQ== Received: from AM7PR03CA0010.eurprd03.prod.outlook.com (2603:10a6:20b:130::20) by DB8PR07MB6428.eurprd07.prod.outlook.com (2603:10a6:10:132::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.32; Sat, 2 Mar 2024 14:02:16 +0000 Received: from AMS0EPF00000197.eurprd05.prod.outlook.com (2603:10a6:20b:130:cafe::a2) by AM7PR03CA0010.outlook.office365.com (2603:10a6:20b:130::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.34 via Frontend Transport; Sat, 2 Mar 2024 14:02:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by AMS0EPF00000197.mail.protection.outlook.com (10.167.16.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7362.11 via Frontend Transport; Sat, 2 Mar 2024 14:02:15 +0000 Received: from seliicinfr00050.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.66) with Microsoft SMTP Server id 15.2.1258.12; Sat, 2 Mar 2024 15:02:15 +0100 Received: from breslau.. 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These functions are useful when interacting with memory-mapped hardware devices. The "once" family of functions does not promise atomicity and provides no memory ordering guarantees beyond the C11 relaxed memory model. Signed-off-by: Mattias Rönnblom --- lib/eal/include/rte_bitops.h | 229 +++++++++++++++++++++++++++++++++++ 1 file changed, 229 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index afd0f11033..3118c51748 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -338,6 +338,227 @@ rte_bit_assign64(uint64_t *addr, unsigned int nr, bool value) rte_bit_clear64(addr, nr); } +/** + * Test exactly once if a particular bit in a 32-bit word is set. + * + * This function is guaranteed to result in exactly one memory load + * (e.g., it may not be eliminate or merged by the compiler). + * + * \code{.c} + * rte_bit_once_set32(addr, 17); + * if (rte_bit_once_test32(addr, 17)) { + * ... + * } + * \endcode + * + * In the above example, rte_bit_once_set32() may not be removed by + * the compiler, which would be allowed in case rte_bit_set32() and + * rte_bit_test32() was used. + * + * \code{.c} + * while (rte_bit_once_test32(addr, 17); + * ; + * \endcode + * + * In case rte_bit_test32(addr, 17) was used instead, the resulting + * object code could (and in many cases would be) replaced with + * with the equivalent to + * \code{.c} + * if (rte_bit_test32(addr, 17)) { + * for (;;) // spin forever + * ; + * } + * \endcode + * + * The regular bit set operations (e.g., rte_bit_test32()) should be + * preffered over the "once" family of operations (e.g., + * rte_bit_once_test32()), since the latter may prevent optimizations + * crucial for run-time performance. + * + * This function does not give any guarantees in regards to memory + * ordering (except ordering from the same thread to the same memory + * location) or atomicity. + * + * @param addr + * A pointer to the 32-bit word to query. + * @param nr + * The index of the bit (0-31). + * @return + * Returns true if the bit is set, and false otherwise. + */ + +static inline bool +rte_bit_once_test32(const volatile uint32_t *addr, unsigned int nr); + +/** + * Set bit in 32-bit word exactly once. + * + * Set bit specified by @c nr in the 32-bit word pointed to by + * @c addr to '1'. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit set operation. + * + * See rte_bit_test_once32() for more information and uses cases for + * the "once" class of functions. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 32-bit word to modify. + * @param nr + * The index of the bit (0-31). + */ +static inline void +rte_bit_once_set32(volatile uint32_t *addr, unsigned int nr); + +/** + * Clear bit in 32-bit word exactly once. + * + * Set bit specified by @c nr in the 32-bit word pointed to by @c addr + * to '0'. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit clear operation. + * + * See rte_bit_once_test32() for more information and uses cases for the + * "once" class of functions. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 32-bit word to modify. + * @param nr + * The index of the bit (0-31). + */ +static inline void +rte_bit_once_clear32(volatile uint32_t *addr, unsigned int nr); + +/** + * Assign a value to bit in a 32-bit word exactly once. + * + * Set bit specified by @c nr in the 32-bit word pointed to by + * @c addr to the value indicated by @c value. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit clear operation. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 32-bit word to modify. + * @param nr + * The index of the bit (0-31). + * @param value + * The new value of the bit - true for '1', or false for '0'. + */ +static inline void +rte_bit_once_assign32(uint32_t *addr, unsigned int nr, bool value) +{ + if (value) + rte_bit_once_set32(addr, nr); + else + rte_bit_once_clear32(addr, nr); +} + +/** + * Test exactly once if a particular bit in a 64-bit word is set. + * + * This function is guaranteed to result in exactly one memory load. + * See rte_bit_once_test32() for more information and uses cases for the + * "once" class of functions. + * + * rte_v_bit_test64() does give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 64-bit word to query. + * @param nr + * The index of the bit (0-63). + * @return + * Returns true if the bit is set, and false otherwise. + */ + +static inline bool +rte_bit_once_test64(const volatile uint64_t *addr, unsigned int nr); + +/** + * Set bit in 64-bit word exactly once. + * + * Set bit specified by @c nr in the 64-bit word pointed to by + * @c addr to '1'. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit set operation. + * + * See rte_bit_once_test32() for more information and uses cases for the + * "once" class of functions. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 64-bit word to modify. + * @param nr + * The index of the bit (0-63). + */ +static inline void +rte_bit_once_set64(volatile uint64_t *addr, unsigned int nr); + +/** + * Clear bit in 64-bit word exactly once. + * + * Set bit specified by @c nr in the 64-bit word pointed to by @c addr + * to '0'. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit clear operation. + * + * See rte_bit_once_test32() for more information and uses cases for the + * "once" class of functions. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 64-bit word to modify. + * @param nr + * The index of the bit (0-63). + */ +static inline void +rte_bit_once_clear64(volatile uint64_t *addr, unsigned int nr); + +/** + * Assign a value to bit in a 64-bit word exactly once. + * + * Set bit specified by @c nr in the 64-bit word pointed to by + * @c addr to the value indicated by @c value. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit clear operation. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the 64-bit word to modify. + * @param nr + * The index of the bit (0-63). + * @param value + * The new value of the bit - true for '1', or false for '0'. + */ +static inline void +rte_bit_once_assign64(volatile uint64_t *addr, unsigned int nr, bool value) +{ + if (value) + rte_bit_once_set64(addr, nr); + else + rte_bit_once_clear64(addr, nr); +} + #define __RTE_GEN_BIT_TEST(name, size, qualifier) \ static inline bool \ name(const qualifier uint ## size ## _t *addr, unsigned int nr) \ @@ -376,6 +597,14 @@ __RTE_GEN_BIT_TEST(rte_bit_test64, 64,) __RTE_GEN_BIT_SET(rte_bit_set64, 64,) __RTE_GEN_BIT_CLEAR(rte_bit_clear64, 64,) +__RTE_GEN_BIT_TEST(rte_bit_once_test32, 32, volatile) +__RTE_GEN_BIT_SET(rte_bit_once_set32, 32, volatile) +__RTE_GEN_BIT_CLEAR(rte_bit_once_clear32, 32, volatile) + +__RTE_GEN_BIT_TEST(rte_bit_once_test64, 64, volatile) +__RTE_GEN_BIT_SET(rte_bit_once_set64, 64, volatile) +__RTE_GEN_BIT_CLEAR(rte_bit_once_clear64, 64, volatile) + /*------------------------ 32-bit relaxed operations ------------------------*/ /** From patchwork Sat Mar 2 13:53:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 137802 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9E87843C3A; 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(seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00050.seli.gic.ericsson.se (Postfix) with ESMTP id 1F5621C006A; Sat, 2 Mar 2024 15:02:16 +0100 (CET) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , Heng Wang , =?utf-8?q?M?= =?utf-8?q?attias_R=C3=B6nnblom?= Subject: [RFC 4/7] eal: add generic once-type bit operations macros Date: Sat, 2 Mar 2024 14:53:25 +0100 Message-ID: <20240302135328.531940-5-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240302135328.531940-1-mattias.ronnblom@ericsson.com> References: <20240302135328.531940-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AMS0EPF000001A8:EE_|AM8PR07MB8215:EE_ X-MS-Office365-Filtering-Correlation-Id: 35456850-a03f-4bba-374d-08dc3ac15e6e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UXuxOG1auY9dSvHEFHjTVNmVZvZIQ7+O8zJ+xw6Ii4O2WOYAJ76RJl9Hr+LPrL9LwJEUZJtmBnGuzJ0KM8XN1y7SkI5TWfWW05IWFV1eYc4BNt7mXC4llC2Vb94OerVZfKv8JWkqGc8IPLo53fmDhktmYBkumx/JHscgy0hA4Sb5Tp/P7K97FDJ87W0HDXkso2fAJiWcO1YR6ksSzxR0+j0xWzgdge4Hh3QLZM1nCxcr9oFBZGnq1PmngXk8L0YyiBmsXDwCYooOBlTOwcebw3wRBi8CvMQRG9hVslez5wLS3M3n+I1T2hzHvZtVoEu9s8MsbyTbLwvMeC1z6XWQbCQEtXQn8FvLy0fwfUdKZ3Bv6aRK4EzE8YghF8KWV9H5ghd0jhp/X/rFozHaoTjKOCaQEEcqaOnelW+71VedGzBrLV1rLMTVjOQLPRRdA8ntwejRpdI6BhEpJMq4/tYd5n1jC5pQaK9tC9qwpipfcf1qGB4r1YsAzU8hmp+mIbH+jaQvy8xgJ1ACLosS0VE403PJLGmXME5UvO6RIDvrLmZMmo4fg57T4W40MtlRf0J5lkzQNcZTwVUF4aTXS4/q3wp68jeJ0QR9ap/973SLL4FKX0p6dJis+U+aMpTOqBirGLN36Cb5AyNaVBij44+hkdNso3AFTpzt1iuoNH8i5Bd3O3SD877+6PSGwGynUesKl5g4KmWgEYJcGRvAI4aDu+L97T4aybrAQa77o7ChsCcO0tDpdMl+oRPJ2EeihpnT X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(376005)(36860700004)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2024 14:02:16.6523 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 35456850-a03f-4bba-374d-08dc3ac15e6e X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001A8.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR07MB8215 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add macros for once-type bit operations operating on both 32-bit and 64-bit words by means of C11 generic selection. Signed-off-by: Mattias Rönnblom --- lib/eal/include/rte_bitops.h | 101 +++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index 3118c51748..450334c751 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -188,6 +188,107 @@ extern "C" { uint32_t *: rte_bit_assign32, \ uint64_t *: rte_bit_assign64)(addr, nr, value) +/** + * Test exactly once if a particular bit in a word is set. + * + * Generic selection macro to exactly once test the value of a bit in + * a 32-bit or 64-bit word. The type of operation depends on the type + * of the @c addr parameter. + * + * This macro is guaranteed to result in exactly one memory load. See + * rte_bit_once_test32() for more information and uses cases for the + * "once" class of functions. + * + * rte_bit_once_test() does give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to query. + * @param nr + * The index of the bit. + * @return + * Returns true if the bit is set, and false otherwise. + */ + +#define rte_bit_once_test(addr, nr) \ + _Generic((addr), \ + uint32_t *: rte_bit_once_test32, \ + uint64_t *: rte_bit_once_test64)(addr, nr) + +/** + * Set bit in word exactly once. + * + * Set bit specified by @c nr in the word pointed to by @c addr to '1' + * exactly once. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit set operation. + * + * See rte_bit_test_once32() for more information and uses cases for + * the "once" class of functions. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_once_set(addr, nr) \ + _Generic((addr), \ + uint32_t *: rte_bit_once_set32, \ + uint64_t *: rte_bit_once_set64)(addr, nr) + +/** + * Clear bit in word exactly once. + * + * Set bit specified by @c nr in the word pointed to by @c addr to '0' + * exactly once. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit clear operation. + * + * See rte_bit_test_once32() for more information and uses cases for + * the "once" class of functions. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_once_clear(addr, nr) \ + _Generic((addr), \ + uint32_t *: rte_bit_once_clear32, \ + uint64_t *: rte_bit_once_clear64)(addr, nr) + +/** + * Assign a value to bit in a word exactly once. + * + * Set bit specified by @c nr in the word pointed to by @c addr to the + * value indicated by @c value exactly once. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit clear operation. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + */ +#define rte_bit_once_assign(addr, nr, value) \ + _Generic((addr), \ + uint32_t *: rte_bit_once_assign32, \ + uint64_t *: rte_bit_once_assign64)(addr, nr, value) + /** * Test if a particular bit in a 32-bit word is set. * From patchwork Sat Mar 2 13:53:26 2024 Content-Type: text/plain; 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All atomic bit functions allow (and indeed, require) the caller to specify a memory order. Signed-off-by: Mattias Rönnblom --- lib/eal/include/rte_bitops.h | 337 +++++++++++++++++++++++++++++++++++ 1 file changed, 337 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index 450334c751..7eb08bc768 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -20,6 +20,7 @@ #include #include +#include #ifdef __cplusplus extern "C" { @@ -706,6 +707,342 @@ __RTE_GEN_BIT_TEST(rte_bit_once_test64, 64, volatile) __RTE_GEN_BIT_SET(rte_bit_once_set64, 64, volatile) __RTE_GEN_BIT_CLEAR(rte_bit_once_clear64, 64, volatile) +/** + * Test if a particular bit in a 32-bit word is set with a particular + * memory order. + * + * Test a bit with the resulting memory load ordered as per the + * specified memory order. + * + * @param addr + * A pointer to the 32-bit word to query. + * @param nr + * The index of the bit (0-31). + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit is set, and false otherwise. + */ +static inline bool +rte_bit_atomic_test32(const uint32_t *addr, unsigned int nr, int memory_order); + +/** + * Atomically set bit in 32-bit word. + * + * Atomically bit specified by @c nr in the 32-bit word pointed to by + * @c addr to '1', with the memory ordering as specified by @c + * memory_order. + * + * @param addr + * A pointer to the 32-bit word to modify. + * @param nr + * The index of the bit (0-31). + * @param memory_order + * The memory order to use. See for details. + */ +static inline void +rte_bit_atomic_set32(uint32_t *addr, unsigned int nr, int memory_order); + +/** + * Atomically clear bit in 32-bit word. + * + * Atomically set bit specified by @c nr in the 32-bit word pointed to + * by @c addr to '0', with the memory ordering as specified by @c + * memory_order. + * + * @param addr + * A pointer to the 32-bit word to modify. + * @param nr + * The index of the bit (0-31). + * @param memory_order + * The memory order to use. See for details. + */ +static inline void +rte_bit_atomic_clear32(uint32_t *addr, unsigned int nr, int memory_order); + +/** + * Atomically assign a value to bit in a 32-bit word. + * + * Atomically set bit specified by @c nr in the 32-bit word pointed to + * by @c addr to the value indicated by @c value, with the memory + * ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the 32-bit word to modify. + * @param nr + * The index of the bit (0-31). + * @param value + * The new value of the bit - true for '1', or false for '0'. + * @param memory_order + * The memory order to use. See for details. + */ +static inline void +rte_bit_atomic_assign32(uint32_t *addr, unsigned int nr, bool value, + int memory_order); + +/* + * Atomic test-and-assign is not considered useful-enough to document + * and expose in the public API. + */ +static inline bool +__rte_bit_atomic_test_and_assign32(uint32_t *addr, unsigned int nr, bool value, + int memory_order); + +/** + * Atomically test and set a bit in a 32-bit word. + * + * Atomically test and set bit specified by @c nr in the 32-bit word + * pointed to by @c addr to the value indicated by @c value, with the + * memory ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the 32-bit word to modify. + * @param nr + * The index of the bit (0-31). + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +static inline bool +rte_bit_atomic_test_and_set32(uint32_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign32(addr, nr, true, memory_order); +} + +/** + * Atomically test and clear a bit in a 32-bit word. + * + * Atomically test and clear bit specified by @c nr in the 32-bit word + * pointed to by @c addr to the value indicated by @c value, with the + * memory ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the 32-bit word to modify. + * @param nr + * The index of the bit (0-31). + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +static inline bool +rte_bit_atomic_test_and_clear32(uint32_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign32(addr, nr, false, memory_order); +} + +/** + * Test if a particular bit in a 32-bit word is set with a particular + * memory order. + * + * Test a bit with the resulting memory load ordered as per the + * specified memory order. + * + * @param addr + * A pointer to the 32-bit word to query. + * @param nr + * The index of the bit (0-31). + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit is set, and false otherwise. + */ +static inline bool +rte_bit_atomic_test64(const uint64_t *addr, unsigned int nr, int memory_order); + +/** + * Atomically set bit in 64-bit word. + * + * Atomically bit specified by @c nr in the 64-bit word pointed to by + * @c addr to '1', with the memory ordering as specified by @c + * memory_order. + * + * @param addr + * A pointer to the 64-bit word to modify. + * @param nr + * The index of the bit (0-63). + * @param memory_order + * The memory order to use. See for details. + */ +static inline void +rte_bit_atomic_set64(uint64_t *addr, unsigned int nr, int memory_order); + +/** + * Atomically clear bit in 64-bit word. + * + * Atomically set bit specified by @c nr in the 64-bit word pointed to + * by @c addr to '0', with the memory ordering as specified by @c + * memory_order. + * + * @param addr + * A pointer to the 64-bit word to modify. + * @param nr + * The index of the bit (0-63). + * @param memory_order + * The memory order to use. See for details. + */ +static inline void +rte_bit_atomic_clear64(uint64_t *addr, unsigned int nr, int memory_order); + +/** + * Atomically assign a value to bit in a 64-bit word. + * + * Atomically set bit specified by @c nr in the 64-bit word pointed to + * by @c addr to the value indicated by @c value, with the memory + * ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the 64-bit word to modify. + * @param nr + * The index of the bit (0-63). + * @param value + * The new value of the bit - true for '1', or false for '0'. + * @param memory_order + * The memory order to use. See for details. + */ +static inline void +rte_bit_atomic_assign64(uint64_t *addr, unsigned int nr, bool value, + int memory_order); + +/* + * Atomic test-and-assign is not considered useful-enough to document + * and expose in the public API. + */ +static inline bool +__rte_bit_atomic_test_and_assign64(uint64_t *addr, unsigned int nr, bool value, + int memory_order); +/** + * Atomically test and set a bit in a 64-bit word. + * + * Atomically test and set bit specified by @c nr in the 64-bit word + * pointed to by @c addr to the value indicated by @c value, with the + * memory ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the 64-bit word to modify. + * @param nr + * The index of the bit (0-63). + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +static inline bool +rte_bit_atomic_test_and_set64(uint64_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign64(addr, nr, true, memory_order); +} + +/** + * Atomically test and clear a bit in a 64-bit word. + * + * Atomically test and clear bit specified by @c nr in the 64-bit word + * pointed to by @c addr to the value indicated by @c value, with the + * memory ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the 64-bit word to modify. + * @param nr + * The index of the bit (0-63). + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +static inline bool +rte_bit_atomic_test_and_clear64(uint64_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign64(addr, nr, false, memory_order); +} + +#ifndef RTE_ENABLE_STDATOMIC + +#define __RTE_GEN_BIT_ATOMIC_TEST(size) \ + static inline bool \ + rte_bit_atomic_test ## size(const uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + return __atomic_load_n(addr, memory_order) & mask; \ + } + +#define __RTE_GEN_BIT_ATOMIC_SET(size) \ + static inline void \ + rte_bit_atomic_set ## size(uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + __atomic_fetch_or(addr, mask, memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_CLEAR(size) \ + static inline void \ + rte_bit_atomic_clear ## size(uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + __atomic_fetch_and(addr, ~mask, memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_ASSIGN(size) \ + static inline void \ + rte_bit_atomic_assign ## size(uint ## size ## _t *addr, \ + unsigned int nr, bool value, \ + int memory_order) \ + { \ + if (value) \ + rte_bit_atomic_set ## size(addr, nr, memory_order); \ + else \ + rte_bit_atomic_clear ## size(addr, nr, memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size) \ + static inline bool \ + __rte_bit_atomic_test_and_assign ## size(uint ## size ## _t *addr, \ + unsigned int nr, \ + bool value, \ + int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t before; \ + uint ## size ## _t after; \ + \ + before = __atomic_load_n(addr, __ATOMIC_RELAXED); \ + \ + do { \ + rte_bit_assign ## size(&before, nr, value); \ + } while(!__atomic_compare_exchange_n(addr, &before, after, \ + true, __ATOMIC_RELAXED, \ + memory_order)); \ + return rte_bit_test ## size(&before, nr); \ + } + +#else +#error "C11 atomics (MSVC) not supported in this RFC version" +#endif + +#define __RTE_GEN_BIT_ATOMIC_OPS(size) \ + __RTE_GEN_BIT_ATOMIC_TEST(size) \ + __RTE_GEN_BIT_ATOMIC_SET(size) \ + __RTE_GEN_BIT_ATOMIC_CLEAR(size) \ + __RTE_GEN_BIT_ATOMIC_ASSIGN(size) \ + __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size) + +__RTE_GEN_BIT_ATOMIC_OPS(32) +__RTE_GEN_BIT_ATOMIC_OPS(64) + /*------------------------ 32-bit relaxed operations ------------------------*/ /** From patchwork Sat Mar 2 13:53:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 137806 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9E8E243C3A; Sat, 2 Mar 2024 15:03:03 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3A34442DD0; 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Signed-off-by: Mattias Rönnblom --- lib/eal/include/rte_bitops.h | 125 +++++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index 7eb08bc768..b5a9df5930 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -290,6 +290,131 @@ extern "C" { uint32_t *: rte_bit_once_assign32, \ uint64_t *: rte_bit_once_assign64)(addr, nr, value) +/** + * Test if a particular bit in a word is set with a particular memory + * order. + * + * Test a bit with the resulting memory load ordered as per the + * specified memory order. + * + * @param addr + * A pointer to the word to query. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit is set, and false otherwise. + */ +#define rte_bit_atomic_test(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: rte_bit_atomic_test32, \ + uint64_t *: rte_bit_atomic_test64)(addr, nr, memory_order) + +/** + * Atomically set bit in word. + * + * Atomically set bit specified by @c nr in the word pointed to by @c + * addr to '1', with the memory ordering as specified by @c + * memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + */ +#define rte_bit_atomic_set(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: rte_bit_atomic_set32, \ + uint64_t *: rte_bit_atomic_set64)(addr, nr, memory_order) + +/** + * Atomically clear bit in word. + * + * Atomically set bit specified by @c nr in the word pointed to by @c + * addr to '0', with the memory ordering as specified by @c + * memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + */ +#define rte_bit_atomic_clear(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: rte_bit_atomic_clear32, \ + uint64_t *: rte_bit_atomic_clear64)(addr, nr, memory_order) + +/** + * Atomically assign a value to bit in word. + * + * Atomically set bit specified by @c nr in the word pointed to by @c + * addr to the value indicated by @c value, with the memory ordering + * as specified with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + * @param memory_order + * The memory order to use. See for details. + */ +#define rte_bit_atomic_assign(addr, nr, value, memory_order) \ + _Generic((addr), \ + uint32_t *: rte_bit_atomic_assign32, \ + uint64_t *: rte_bit_atomic_assign64)(addr, nr, value, \ + memory_order) + +/** + * Atomically test and set a bit in word. + * + * Atomically test and set bit specified by @c nr in the word pointed + * to by @c addr to '1', with the memory ordering as specified with @c + * memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +#define rte_bit_atomic_test_and_set(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: rte_bit_atomic_test_and_set32, \ + uint64_t *: rte_bit_atomic_test_and_set64)(addr, nr, \ + memory_order)) + +/** + * Atomically test and clear a bit in word. + * + * Atomically test and clear bit specified by @c nr in the word + * pointed to by @c addr to '0', with the memory ordering as specified + * with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +#define rte_bit_atomic_test_and_clear(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: rte_bit_atomic_test_and_clear32, \ + uint64_t *: rte_bit_atomic_test_and_clear64)(addr, nr, \ + memory_order)) + /** * Test if a particular bit in a 32-bit word is set. * From patchwork Sat Mar 2 13:53:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 137807 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 35C5643C3A; Sat, 2 Mar 2024 15:03:09 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 74BE142DE7; Sat, 2 Mar 2024 15:02:26 +0100 (CET) Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2059.outbound.protection.outlook.com [40.107.6.59]) by mails.dpdk.org (Postfix) with ESMTP id 5E01642DB6 for ; Sat, 2 Mar 2024 15:02:21 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lyl5gM3x8R3NRvoUZPEZC0FJntKkfcaaDJWsSoxkzGDGL9mQ7is20tLggBY/vYkN829ktZ/J1aC0sf0PaXPAiR2F4deHSS2PZtF/C0EE9xIO/8hb7TQSW6Qz3tyBcP22Bp4w32odK3p3T/WquQNMX1EcQYDvmeMTEC37cZFs82sApGf/vleFI3REbISwccGlLF8Laqw4YxePbApYBL8B4HSAzoWHg4louz2wh6aDEPUOoMinyPsd0w4Dzfc2tSc/IU72xyft7L4FF+5/DhTHMrczN+GR38rDQronmcbzwsZ0HsYu3KsJ7yozRvm96WCvoOPzI2YOZ7y+9DXxpyBUUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/X/Y07R5vgas+EGUx5s6N1Q9VFslIyXUX7RVzHEHoUs=; b=R0trabEMRWKxTi/x9fTNKLNXh4tU8ypKus5+AFMvG9AK1CWgHMLpb0ZCSDlNSbbpKVWHkViur7JgvaxayULWme0FF2zH5euLTbXeXRA7EtGQqWpgWKVTlPNI/CavieIsPIKkTnpndXypnXvaWSGQK0IZ4CoQs/o8KGmvvTadE2m/+2Sn94Yn09gv1DUmfh2MWSB2500vcywE/TsCH9N2gE8eZRalXpruSZrYlxaZn0AnhztvwqPPmcD9rH3F0Veiqy8aLMUTz0FTjFQLHDAGIuh3NdPHu2lUad/RhBHrMDonMOzSiWQNvx9TFtH11Rfc1CtpKoiCh3hhhFKkh2N+Jw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/X/Y07R5vgas+EGUx5s6N1Q9VFslIyXUX7RVzHEHoUs=; b=aS2uNuRm6W5ld95NBaJBRpRiD8ed+kV+PmLkqg/ySbpkEnbUeViwcQa94rnMUuBdg8832SLTK0DjjA2QfteoMXHkj76IdpfGKlfjPYQtbKsVtlx5K/6GV/kSsedOsFpw+Jb3KOo5wnq9cwAD7uI0mBYtvkYcXNWe8mJ+PfhUdiXzFrMmD90wtD+GtJaYfyQcpn1EarFmcaX475q1emKYYChYvavgE4RzDSw+CvVOFPc8i8YJkCSW2JJKR9f+Z8YOSwnJ3hAj2jhXNw39LXnolvktu8Pbyjcr8C76dRdXJuUhq1AzSYhxLBXkXdGWALxUGgZza2LuibcMX6PA0vpidA== Received: from AS4PR09CA0007.eurprd09.prod.outlook.com (2603:10a6:20b:5e0::8) by AS8PR07MB7973.eurprd07.prod.outlook.com (2603:10a6:20b:396::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.37; Sat, 2 Mar 2024 14:02:19 +0000 Received: from AM4PEPF00027A6A.eurprd04.prod.outlook.com (2603:10a6:20b:5e0:cafe::4b) by AS4PR09CA0007.outlook.office365.com (2603:10a6:20b:5e0::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.34 via Frontend Transport; Sat, 2 Mar 2024 14:02:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by AM4PEPF00027A6A.mail.protection.outlook.com (10.167.16.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7362.11 via Frontend Transport; Sat, 2 Mar 2024 14:02:19 +0000 Received: from seliicinfr00050.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.62) with Microsoft SMTP Server id 15.2.1258.12; Sat, 2 Mar 2024 15:02:18 +0100 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00050.seli.gic.ericsson.se (Postfix) with ESMTP id 7EB831C006A; Sat, 2 Mar 2024 15:02:18 +0100 (CET) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , Heng Wang , =?utf-8?q?M?= =?utf-8?q?attias_R=C3=B6nnblom?= Subject: [RFC 7/7] eal: deprecate relaxed family of bit operations Date: Sat, 2 Mar 2024 14:53:28 +0100 Message-ID: <20240302135328.531940-8-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240302135328.531940-1-mattias.ronnblom@ericsson.com> References: <20240302135328.531940-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00027A6A:EE_|AS8PR07MB7973:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ed603ba-e22f-4b90-0e44-08dc3ac15fe7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8b3KaoePWhnngOvvU/2s0wKvtkl+S3EMxiwfb1GbMsds3g0GYP66uPxwYi1YP7syRyvLZv57pvJwFwqDLgA4xBLT3pvGJsmxZKMw9TO8776tCA/oZU+ujnxKa4zbU3Ogr1DU3WmkPhu9CdFPlmcVtXgZzajBMKFBd7XJmiiuoVaWguKbTwarwzU8QyRhvlo6x/C9bjL5P0Jk/h6gaadaZcyNb7rKP5M0802cwnKYG90bWiHGzCkeVZxqf81zWt1xcvcX1h5n2w9J49pprPncrlFaQWy1tzcY1Jx7dAAKIKKlFnBpOgmigcq8ySHSU29sXZcw4bszhZ0uBuEVx8cM8EUBun7wGio27kCkpX7Fcydbl6qMlzXhrQ70kq1yqaGf4NK5kee91yheGcsJExP9pu39O2iQRzaLufjM24clXWxpdMZimZe8lwuJsxxb8ggaWb5rDyXt4ihGz1qRrowmTWDHdWGjQjhHVqCEMUCejm7EtRaI3lazqr8dabIdvKWm46z+xopuNEEHtfFGp9pSFLFKpp2Xz7IzJmNriPb4Qq9QVGzqNXMdspERAPYgMQ0IxbeFhKB4mkserShM5zFTI/aCKgm4vFne7Dl4XH658K1LRVF+OdLv++r/VJtdvGEpsXHkS+LWFeYxSvH1m7RwfVzpucnuUz8TU6sb9b+b30LC5vSiBL4RuGQj/gksFCT/IsreUBSKpXv1bysHpPO0TY0YCUnNbED4p84jZY13HKaB0tL4DnsM829R3R+LiRvV X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(82310400014)(36860700004)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2024 14:02:19.1219 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ed603ba-e22f-4b90-0e44-08dc3ac15fe7 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A6A.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR07MB7973 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Informally (by means of documentation) deprecate the rte_bit_relaxed_*() family of bit-level operations. rte_bit_relaxed_*() has been replaced by three new families of bit-level query and manipulation functions. rte_bit_relaxed_*() failed to deliver the atomicity guarantees their name suggested. If deprecated, it will encourage the user to consider whether the actual, implemented behavior (e.g., non-atomic test-and-set with read/write-once semantics) or the semantics implied by their names (i.e., atomic), or something else, is what's actually needed. Bugzilla ID: 1385 Signed-off-by: Mattias Rönnblom --- lib/eal/include/rte_bitops.h | 48 ++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index b5a9df5930..783dd0e1ee 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -1179,6 +1179,10 @@ __RTE_GEN_BIT_ATOMIC_OPS(64) * The address holding the bit. * @return * The target bit. + * @note + * This function is deprecated. Use rte_bit_test32(), + * rte_bit_once_test32(), or rte_bit_atomic_test32() instead, + * depending on exactly what guarantees are required. */ static inline uint32_t rte_bit_relaxed_get32(unsigned int nr, volatile uint32_t *addr) @@ -1196,6 +1200,10 @@ rte_bit_relaxed_get32(unsigned int nr, volatile uint32_t *addr) * The target bit to set. * @param addr * The address holding the bit. + * @note + * This function is deprecated. Use rte_bit_set32(), + * rte_bit_once_set32(), or rte_bit_atomic_set32() instead, + * depending on exactly what guarantees are required. */ static inline void rte_bit_relaxed_set32(unsigned int nr, volatile uint32_t *addr) @@ -1213,6 +1221,10 @@ rte_bit_relaxed_set32(unsigned int nr, volatile uint32_t *addr) * The target bit to clear. * @param addr * The address holding the bit. + * @note + * This function is deprecated. Use rte_bit_clear32(), + * rte_bit_once_clear32(), or rte_bit_atomic_clear32() instead, + * depending on exactly what guarantees are required. */ static inline void rte_bit_relaxed_clear32(unsigned int nr, volatile uint32_t *addr) @@ -1233,6 +1245,12 @@ rte_bit_relaxed_clear32(unsigned int nr, volatile uint32_t *addr) * The address holding the bit. * @return * The original bit. + * @note + * This function is deprecated and replaced by + * rte_bit_atomic_test_and_set32(), for use cases where the + * operation needs to be atomic. For non-atomic/non-ordered use + * cases, use rte_bit_test32() + rte_bit_set32() or + * rte_bit_once_test32() + rte_bit_once_set32(). */ static inline uint32_t rte_bit_relaxed_test_and_set32(unsigned int nr, volatile uint32_t *addr) @@ -1255,6 +1273,12 @@ rte_bit_relaxed_test_and_set32(unsigned int nr, volatile uint32_t *addr) * The address holding the bit. * @return * The original bit. + * @note + * This function is deprecated and replaced by + * rte_bit_atomic_test_and_clear32(), for use cases where the + * operation needs to be atomic. For non-atomic/non-ordered use + * cases, use rte_bit_test32() + rte_bit_clear32() or + * rte_bit_once_test32() + rte_bit_once_clear32(). */ static inline uint32_t rte_bit_relaxed_test_and_clear32(unsigned int nr, volatile uint32_t *addr) @@ -1278,6 +1302,10 @@ rte_bit_relaxed_test_and_clear32(unsigned int nr, volatile uint32_t *addr) * The address holding the bit. * @return * The target bit. + * @note + * This function is deprecated. Use rte_bit_test64(), + * rte_bit_once_test64(), or rte_bit_atomic_test64() instead, + * depending on exactly what guarantees are required. */ static inline uint64_t rte_bit_relaxed_get64(unsigned int nr, volatile uint64_t *addr) @@ -1295,6 +1323,10 @@ rte_bit_relaxed_get64(unsigned int nr, volatile uint64_t *addr) * The target bit to set. * @param addr * The address holding the bit. + * @note + * This function is deprecated. Use rte_bit_set64(), + * rte_bit_once_set64(), or rte_bit_atomic_set64() instead, + * depending on exactly what guarantees are required. */ static inline void rte_bit_relaxed_set64(unsigned int nr, volatile uint64_t *addr) @@ -1312,6 +1344,10 @@ rte_bit_relaxed_set64(unsigned int nr, volatile uint64_t *addr) * The target bit to clear. * @param addr * The address holding the bit. + * @note + * This function is deprecated. Use rte_bit_clear64(), + * rte_bit_once_clear64(), or rte_bit_atomic_clear64() instead, + * depending on exactly what guarantees are required. */ static inline void rte_bit_relaxed_clear64(unsigned int nr, volatile uint64_t *addr) @@ -1332,6 +1368,12 @@ rte_bit_relaxed_clear64(unsigned int nr, volatile uint64_t *addr) * The address holding the bit. * @return * The original bit. + * @note + * This function is deprecated and replaced by + * rte_bit_atomic_test_and_set64(), for use cases where the + * operation needs to be atomic. For non-atomic/non-ordered use + * cases, use rte_bit_test64() + rte_bit_set64() or + * rte_bit_once_test64() + rte_bit_once_set64(). */ static inline uint64_t rte_bit_relaxed_test_and_set64(unsigned int nr, volatile uint64_t *addr) @@ -1354,6 +1396,12 @@ rte_bit_relaxed_test_and_set64(unsigned int nr, volatile uint64_t *addr) * The address holding the bit. * @return * The original bit. + * @note + * This function is deprecated and replaced by + * rte_bit_atomic_test_and_clear64(), for use cases where the + * operation needs to be atomic. For non-atomic/non-ordered use + * cases, use rte_bit_test64() + rte_bit_clear64() or + * rte_bit_once_test64() + rte_bit_once_clear64(). */ static inline uint64_t rte_bit_relaxed_test_and_clear64(unsigned int nr, volatile uint64_t *addr)