From patchwork Mon Feb 26 13:18:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 137208 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 86BCF43BED; Mon, 26 Feb 2024 14:19:16 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 56E8640271; Mon, 26 Feb 2024 14:19:16 +0100 (CET) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2085.outbound.protection.outlook.com [40.107.223.85]) by mails.dpdk.org (Postfix) with ESMTP id D621940144 for ; Mon, 26 Feb 2024 14:19:14 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bCaEjSGZ4aFn3zPHw/ep5RwT9ndXMaSLd4XkbSyfxPPjuC9scLoZ6v7lMRshHkN/FkwiCs6GafsZ+/MIyLAotFnHuysrU6ssOmf0UJipsPGOoBeWc6UkOTAYzSoTxbV0pnITfDZt3l4Txttn0T92AOr9J3952GdtmAQJP3QS/+kleRYJLg6TUD7DWgB3Kqc1UKIj4j7v37q4a/2sy6WNii+XpwXknb9ExGS+s9nvccTPO4yAR8a3IsQbgA7kn/fIay/JmjNxHUZ7Il+G3NHaswMPe7JtAJc23hIFLw945v6pFNuG3v0lEaiVk1+hwmhz3hEzWRIKsiR0ipQO9uVg8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Lql5G0O/Fk0x2ccZ3a3XlPzq4ioTlv/bt61ACavDjHM=; b=nmTJBctKM+J3t/Y/ow13KskXH3zABt5kYeDLmmvg2hw1ssR/ZxpRf+z/y7epaIeE95Ns7CMIeNFCjEKwASUvLwZzRxQmyj/+KIwRXY+2jtLqj61j56R+NJgihtRjislUS+P5f5uDLP/7F8Uz2z29n1LUdIW4cZkhfvv0MeYLjuGpdrMMj4DBxtWYBT4xJYOj6X9y+5V3OWHbcEPka0uAnYE9R/vqp/SqSV9d63fb5KLD6KYJa1s3K+I6cLkzQyvN2a1CQ6E3+fBQRNCul54HCJ3KHhMejdu3F14EVTcBKZ3S+rGY5fQkLyVG1DzQMKZnaTiEE8mBHGyxErwVSqeP5g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Lql5G0O/Fk0x2ccZ3a3XlPzq4ioTlv/bt61ACavDjHM=; b=Z4laZuj1nC8swSkb9ft5+hiCo1a7JIEodHdoCwkdDAMdyUrg/pkzaesRIGY419I9EJsR36Nj/AbP018d/mUkCB+VgvnM/iYF+eBJ/yjpK0RUpiMYy0EInVy2Nj3x6HChgiaftaX1htKm22rMxk4xqJ2nrS2TO8r8IIbvZLe7heLpr0PEtcbVlehC6qjf50v14YPYktrH/tMjDDp4eTSJ1ktrnWek54g8qgKIPd927m2G5ltQQsLXavXC8wzI5w0ESa8yzhPtH/KXsKmkLIS7L6QPDTzwYpHcD2SJ2gYH1CjKeV34sWL85vxgnSRVJZYT7hu7xHelohk0omnFcnilMA== Received: from BYAPR07CA0033.namprd07.prod.outlook.com (2603:10b6:a02:bc::46) by BN9PR12MB5339.namprd12.prod.outlook.com (2603:10b6:408:104::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.34; Mon, 26 Feb 2024 13:19:10 +0000 Received: from DS3PEPF000099E2.namprd04.prod.outlook.com (2603:10b6:a02:bc:cafe::9f) by BYAPR07CA0033.outlook.office365.com (2603:10b6:a02:bc::46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.49 via Frontend Transport; Mon, 26 Feb 2024 13:19:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF000099E2.mail.protection.outlook.com (10.167.17.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Mon, 26 Feb 2024 13:19:09 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 26 Feb 2024 05:18:57 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 26 Feb 2024 05:18:57 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12 via Frontend Transport; Mon, 26 Feb 2024 05:18:55 -0800 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Hamdan Igbaria Subject: [PATCH v7 1/3] net/mlx5/hws: add support for compare matcher Date: Mon, 26 Feb 2024 15:18:46 +0200 Message-ID: <20240226131848.2982242-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226131848.2982242-1-michaelba@nvidia.com> References: <20240226130324.2981025-1-michaelba@nvidia.com> <20240226131848.2982242-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E2:EE_|BN9PR12MB5339:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e645260-74d8-4542-7c1d-08dc36cd844a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4IaKxx8nUA53oNXe3zXXwX6uhy8eZJcQ9SIRK4xQ23j1p9E/+fBiS0zD1u2RNyUc9y4MJJ25A3ewCjFBnc9Dx0BClVCFJ7zYp8J2v4CuqVSUi1K6GUg2+dSAld+xJzhiI7OsraDT6v/Ena66SNv8I3X0az8slhRdwH1Y5hfpFFc+r+kntf7SoqmHRwa8nB3JkesG9IGzHWW4zjJwddnVnLpxWw45OGL5S8OlBamiFNeXn50vQ5br31iXLMxRnhUY8vtWKYZ7vAIJIXmG2/KlZHenCkYqIn7mymA9iM6Aw1EZqXKWXA4xT3NVQv87+ysF0AWX2clifvPuTSP107H9KEAw6HtGvg/O/Q87sjdvtd6TNYr+udKEHOsjeCOGSItW+9xh0TD39sn3Ck2XsrcEMzjJpNnWUOupj64ZwfsQ5dap3keo6cseIxArQd2rUu72QCFWIkGXBrO4GOXNlmwtNMJGV2F4XwEMitdgwoy4VOPSwhxZeGmo5HGyC8uh9JmzkKec3inHl1ieWNhgBe8XC/s28goPMHcqFA5FjjQkUS5/yeRLUwwKga5uff70ozaqg1z1I9baxSyNQ/eBRIHA81inaw9crwpWKwnNHwUg0+jF9L3L5FjovG2cexvZhitDPZMpf0F6R3oiDKa8v9PaH5GSLv8RHHxjchqZORLafvUIJPzHvi7OfACw2qQlGbkqzxgjw0DKZL8UhXa5+YeS03UqFDwOcQJY++6sxMX9xDtGCNCtheBIfL9bPZ+fuXci X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2024 13:19:09.4187 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e645260-74d8-4542-7c1d-08dc36cd844a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5339 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Hamdan Igbaria Add support for compare matcher, this matcher will allow direct comparison between two packet fields, or a packet field and a value, with fully masked DW. For now this matcher hash table is limited to size 1x1, thus it supports only 1 rule STE. Signed-off-by: Hamdan Igbaria Signed-off-by: Michael Baum Acked-by: Suanming Mou --- drivers/common/mlx5/mlx5_prm.h | 16 ++ drivers/net/mlx5/hws/mlx5dr_cmd.c | 9 +- drivers/net/mlx5/hws/mlx5dr_cmd.h | 1 + drivers/net/mlx5/hws/mlx5dr_debug.c | 4 +- drivers/net/mlx5/hws/mlx5dr_debug.h | 1 + drivers/net/mlx5/hws/mlx5dr_definer.c | 243 +++++++++++++++++++++++++- drivers/net/mlx5/hws/mlx5dr_definer.h | 33 ++++ drivers/net/mlx5/hws/mlx5dr_matcher.c | 53 ++++++ drivers/net/mlx5/hws/mlx5dr_matcher.h | 12 +- 9 files changed, 363 insertions(+), 9 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 282e59e52c..aceacb04d0 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3463,6 +3463,7 @@ enum mlx5_ifc_rtc_ste_format { MLX5_IFC_RTC_STE_FORMAT_8DW = 0x4, MLX5_IFC_RTC_STE_FORMAT_11DW = 0x5, MLX5_IFC_RTC_STE_FORMAT_RANGE = 0x7, + MLX5_IFC_RTC_STE_FORMAT_4DW_RANGE = 0x8, }; enum mlx5_ifc_rtc_reparse_mode { @@ -3501,6 +3502,21 @@ struct mlx5_ifc_rtc_bits { u8 reserved_at_1a0[0x260]; }; +struct mlx5_ifc_ste_match_4dw_range_ctrl_dw_bits { + u8 match[0x1]; + u8 reserved_at_1[0x2]; + u8 base1[0x1]; + u8 inverse1[0x1]; + u8 reserved_at_5[0x1]; + u8 operator1[0x2]; + u8 reserved_at_8[0x3]; + u8 base0[0x1]; + u8 inverse0[0x1]; + u8 reserved_at_a[0x1]; + u8 operator0[0x2]; + u8 compare_delta[0x10]; +}; + struct mlx5_ifc_alias_context_bits { u8 vhca_id_to_be_accessed[0x10]; u8 reserved_at_10[0xd]; diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c index fd07028e5f..0e0cc479a6 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.c +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c @@ -370,9 +370,12 @@ mlx5dr_cmd_rtc_create(struct ibv_context *ctx, attr, obj_type, MLX5_GENERAL_OBJ_TYPE_RTC); attr = MLX5_ADDR_OF(create_rtc_in, in, rtc); - MLX5_SET(rtc, attr, ste_format_0, rtc_attr->is_frst_jumbo ? - MLX5_IFC_RTC_STE_FORMAT_11DW : - MLX5_IFC_RTC_STE_FORMAT_8DW); + if (rtc_attr->is_compare) { + MLX5_SET(rtc, attr, ste_format_0, MLX5_IFC_RTC_STE_FORMAT_4DW_RANGE); + } else { + MLX5_SET(rtc, attr, ste_format_0, rtc_attr->is_frst_jumbo ? + MLX5_IFC_RTC_STE_FORMAT_11DW : MLX5_IFC_RTC_STE_FORMAT_8DW); + } if (rtc_attr->is_scnd_range) { MLX5_SET(rtc, attr, ste_format_1, MLX5_IFC_RTC_STE_FORMAT_RANGE); diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h index ee4a61b7eb..9d385fc57f 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.h +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h @@ -82,6 +82,7 @@ struct mlx5dr_cmd_rtc_create_attr { uint8_t reparse_mode; bool is_frst_jumbo; bool is_scnd_range; + bool is_compare; }; struct mlx5dr_cmd_alias_obj_create_attr { diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.c b/drivers/net/mlx5/hws/mlx5dr_debug.c index 11557bcab8..a9094cd35b 100644 --- a/drivers/net/mlx5/hws/mlx5dr_debug.c +++ b/drivers/net/mlx5/hws/mlx5dr_debug.c @@ -99,6 +99,7 @@ static int mlx5dr_debug_dump_matcher_match_template(FILE *f, struct mlx5dr_matcher *matcher) { bool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL; + bool is_compare = mlx5dr_matcher_is_compare(matcher); enum mlx5dr_debug_res_type type; int i, ret; @@ -117,7 +118,8 @@ mlx5dr_debug_dump_matcher_match_template(FILE *f, struct mlx5dr_matcher *matcher return rte_errno; } - type = MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_MATCH_DEFINER; + type = is_compare ? MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_COMPARE_MATCH_DEFINER : + MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_MATCH_DEFINER; ret = mlx5dr_debug_dump_matcher_template_definer(f, mt, mt->definer, type); if (ret) return ret; diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.h b/drivers/net/mlx5/hws/mlx5dr_debug.h index 5cffdb10b5..a89a6a0b1d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_debug.h +++ b/drivers/net/mlx5/hws/mlx5dr_debug.h @@ -24,6 +24,7 @@ enum mlx5dr_debug_res_type { MLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE = 4204, MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_HASH_DEFINER = 4205, MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_RANGE_DEFINER = 4206, + MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_COMPARE_MATCH_DEFINER = 4207, }; static inline uint64_t diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index cde41f1617..45e5bc5a61 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -411,6 +411,86 @@ mlx5dr_definer_ptype_frag_set(struct mlx5dr_definer_fc *fc, DR_SET(tag, !!packet_type, fc->byte_off, fc->bit_off, fc->bit_mask); } +static void +mlx5dr_definer_compare_base_value_set(const void *item_spec, + uint8_t *tag) +{ + uint32_t *ctrl = &(((uint32_t *)tag)[MLX5DR_DEFINER_COMPARE_STE_ARGUMENT_1]); + uint32_t *base = &(((uint32_t *)tag)[MLX5DR_DEFINER_COMPARE_STE_BASE_0]); + const struct rte_flow_item_compare *v = item_spec; + const struct rte_flow_field_data *a = &v->a; + const struct rte_flow_field_data *b = &v->b; + const uint32_t *value; + + value = (const uint32_t *)&b->value[0]; + + if (a->field == RTE_FLOW_FIELD_RANDOM) + *base = htobe32(*value << 16); + else + *base = htobe32(*value); + + MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1); +} + +static void +mlx5dr_definer_compare_op_translate(enum rte_flow_item_compare_op op, + uint8_t *tag) +{ + uint32_t *ctrl = &(((uint32_t *)tag)[MLX5DR_DEFINER_COMPARE_STE_ARGUMENT_1]); + uint8_t operator = 0; + uint8_t inverse = 0; + + switch (op) { + case RTE_FLOW_ITEM_COMPARE_EQ: + operator = 2; + break; + case RTE_FLOW_ITEM_COMPARE_NE: + operator = 2; + inverse = 1; + break; + case RTE_FLOW_ITEM_COMPARE_LT: + inverse = 1; + break; + case RTE_FLOW_ITEM_COMPARE_LE: + operator = 1; + break; + case RTE_FLOW_ITEM_COMPARE_GT: + operator = 1; + inverse = 1; + break; + case RTE_FLOW_ITEM_COMPARE_GE: + break; + default: + DR_LOG(ERR, "Invalid operation type %d", op); + assert(false); + } + + MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, inverse0, inverse); + MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, operator0, operator); +} + +static void +mlx5dr_definer_compare_arg_set(const void *item_spec, + uint8_t *tag) +{ + const struct rte_flow_item_compare *v = item_spec; + enum rte_flow_item_compare_op op = v->operation; + + mlx5dr_definer_compare_op_translate(op, tag); +} + +static void +mlx5dr_definer_compare_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + if (fc->compare_idx == MLX5DR_DEFINER_COMPARE_ARGUMENT_0) { + mlx5dr_definer_compare_arg_set(item_spec, tag); + if (fc->compare_set_base) + mlx5dr_definer_compare_base_value_set(item_spec, tag); + } +} + static void mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc, const void *item_spec, @@ -2782,10 +2862,124 @@ mlx5dr_definer_conv_item_vxlan_gpe(struct mlx5dr_definer_conv_data *cd, return 0; } +static int +mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f, + const struct rte_flow_field_data *other_f, + struct mlx5dr_definer_conv_data *cd, + int item_idx, + enum mlx5dr_definer_compare_dw_selectors dw_offset) +{ + struct mlx5dr_definer_fc *fc = NULL; + int reg; + + if (f->offset) { + DR_LOG(ERR, "field offset %u is not supported, only offset zero supported", + f->offset); + goto err_notsup; + } + + switch (f->field) { + case RTE_FLOW_FIELD_META: + reg = flow_hw_get_reg_id_from_ctx(cd->ctx, + RTE_FLOW_ITEM_TYPE_META, -1); + if (reg <= 0) { + DR_LOG(ERR, "Invalid register for compare metadata field"); + rte_errno = EINVAL; + return rte_errno; + } + + fc = mlx5dr_definer_get_register_fc(cd, reg); + if (!fc) + return rte_errno; + + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_compare_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->compare_idx = dw_offset; + break; + case RTE_FLOW_FIELD_TAG: + reg = flow_hw_get_reg_id_from_ctx(cd->ctx, + RTE_FLOW_ITEM_TYPE_TAG, + f->tag_index); + if (reg <= 0) { + DR_LOG(ERR, "Invalid register for compare tag field"); + rte_errno = EINVAL; + return rte_errno; + } + + fc = mlx5dr_definer_get_register_fc(cd, reg); + if (!fc) + return rte_errno; + + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_compare_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->compare_idx = dw_offset; + break; + case RTE_FLOW_FIELD_VALUE: + if (dw_offset == MLX5DR_DEFINER_COMPARE_ARGUMENT_0) { + DR_LOG(ERR, "Argument field does not support immediate value"); + goto err_notsup; + } + break; + case RTE_FLOW_FIELD_RANDOM: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_RANDOM_NUM]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_compare_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->compare_idx = dw_offset; + DR_CALC_SET_HDR(fc, random_number, random_number); + break; + default: + DR_LOG(ERR, "%u field is not supported", f->field); + goto err_notsup; + } + + if (fc && other_f && other_f->field == RTE_FLOW_FIELD_VALUE) + fc->compare_set_base = true; + + return 0; + +err_notsup: + rte_errno = ENOTSUP; + return rte_errno; +} + +static int +mlx5dr_definer_conv_item_compare(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_compare *m = item->mask; + const struct rte_flow_field_data *a = &m->a; + const struct rte_flow_field_data *b = &m->b; + int ret; + + if (m->width != 0xffffffff) { + DR_LOG(ERR, "compare item width of 0x%x is not supported, only full DW supported", + m->width); + rte_errno = ENOTSUP; + return rte_errno; + } + + ret = mlx5dr_definer_conv_item_compare_field(a, b, cd, item_idx, + MLX5DR_DEFINER_COMPARE_ARGUMENT_0); + if (ret) + return ret; + + ret = mlx5dr_definer_conv_item_compare_field(b, NULL, cd, item_idx, + MLX5DR_DEFINER_COMPARE_BASE_0); + if (ret) + return ret; + + return 0; +} + static int mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, struct mlx5dr_match_template *mt, - uint8_t *hl) + uint8_t *hl, + struct mlx5dr_matcher *matcher) { struct mlx5dr_definer_fc fc[MLX5DR_DEFINER_FNAME_MAX] = {{0}}; struct mlx5dr_definer_conv_data cd = {0}; @@ -2805,6 +2999,11 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, if (ret) return ret; + if (mlx5dr_matcher_is_compare(matcher)) { + DR_LOG(ERR, "Compare matcher not supported for more than one item"); + goto not_supp; + } + switch ((int)items->type) { case RTE_FLOW_ITEM_TYPE_ETH: ret = mlx5dr_definer_conv_item_eth(&cd, items, i); @@ -2950,12 +3149,20 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, ret = mlx5dr_definer_conv_item_vxlan_gpe(&cd, items, i); item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE; break; + case RTE_FLOW_ITEM_TYPE_COMPARE: + if (i) { + DR_LOG(ERR, "Compare matcher not supported for more than one item"); + goto not_supp; + } + ret = mlx5dr_definer_conv_item_compare(&cd, items, i); + item_flags |= MLX5_FLOW_ITEM_COMPARE; + matcher->flags |= MLX5DR_MATCHER_FLAGS_COMPARE; + break; case RTE_FLOW_ITEM_TYPE_VOID: break; default: DR_LOG(ERR, "Unsupported item type %d", items->type); - rte_errno = ENOTSUP; - return rte_errno; + goto not_supp; } cd.last_item = items->type; @@ -2976,6 +3183,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, } return 0; + +not_supp: + rte_errno = ENOTSUP; + return rte_errno; } static int @@ -3393,6 +3604,7 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher, { struct mlx5dr_context *ctx = matcher->tbl->ctx; struct mlx5dr_match_template *mt = matcher->mt; + struct mlx5dr_definer_fc *fc; uint8_t *match_hl; int i, ret; @@ -3410,13 +3622,35 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher, * and allocate the match and range field copy array (fc & fcr). */ for (i = 0; i < matcher->num_of_mt; i++) { - ret = mlx5dr_definer_conv_items_to_hl(ctx, &mt[i], match_hl); + ret = mlx5dr_definer_conv_items_to_hl(ctx, &mt[i], match_hl, matcher); if (ret) { DR_LOG(ERR, "Failed to convert items to header layout"); goto free_fc; } } + if (mlx5dr_matcher_is_compare(matcher)) { + ret = mlx5dr_matcher_validate_compare_attr(matcher); + if (ret) + goto free_fc; + + /* Due some HW limitation need to fill unused + * DW's 0-5 and byte selectors with 0xff. + */ + for (i = 0; i < DW_SELECTORS_MATCH; i++) + match_definer->dw_selector[i] = 0xff; + + for (i = 0; i < BYTE_SELECTORS; i++) + match_definer->byte_selector[i] = 0xff; + + for (i = 0; i < mt[0].fc_sz; i++) { + fc = &mt[0].fc[i]; + match_definer->dw_selector[fc->compare_idx] = fc->byte_off / DW_SIZE; + } + + goto out; + } + /* Find the match definer layout for header layout match union */ ret = mlx5dr_definer_find_best_match_fit(ctx, match_definer, match_hl); if (ret) { @@ -3437,6 +3671,7 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher, goto free_fc; } +out: simple_free(match_hl); return 0; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 71cc0e94de..ca530ebf30 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -17,6 +17,37 @@ #define DW_SELECTORS_RANGE 2 #define BYTE_SELECTORS_RANGE 8 +enum mlx5dr_definer_compare_ste_dw_offset { + /* In compare STE the matching DW's starts after the 3 actions */ + MLX5DR_DEFINER_COMPARE_STE_ARGUMENT_1 = 3, + MLX5DR_DEFINER_COMPARE_STE_ARGUMENT_0, + MLX5DR_DEFINER_COMPARE_STE_BASE_1, + MLX5DR_DEFINER_COMPARE_STE_BASE_0, + MLX5DR_DEFINER_COMPARE_STE_TAG_DW_3, + MLX5DR_DEFINER_COMPARE_STE_TAG_DW_2, + MLX5DR_DEFINER_COMPARE_STE_TAG_DW_1, + MLX5DR_DEFINER_COMPARE_STE_TAG_DW_0, +}; + +enum mlx5dr_definer_dw_selectors { + MLX5DR_DEFINER_SELECTOR_DW0, + MLX5DR_DEFINER_SELECTOR_DW1, + MLX5DR_DEFINER_SELECTOR_DW2, + MLX5DR_DEFINER_SELECTOR_DW3, + MLX5DR_DEFINER_SELECTOR_DW4, + MLX5DR_DEFINER_SELECTOR_DW5, + MLX5DR_DEFINER_SELECTOR_DW6, + MLX5DR_DEFINER_SELECTOR_DW7, + MLX5DR_DEFINER_SELECTOR_DW8, +}; + +enum mlx5dr_definer_compare_dw_selectors { + MLX5DR_DEFINER_COMPARE_ARGUMENT_0 = MLX5DR_DEFINER_SELECTOR_DW4, + MLX5DR_DEFINER_COMPARE_ARGUMENT_1 = MLX5DR_DEFINER_SELECTOR_DW5, + MLX5DR_DEFINER_COMPARE_BASE_0 = MLX5DR_DEFINER_SELECTOR_DW2, + MLX5DR_DEFINER_COMPARE_BASE_1 = MLX5DR_DEFINER_SELECTOR_DW3, +}; + enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_ETH_SMAC_48_16_O, MLX5DR_DEFINER_FNAME_ETH_SMAC_48_16_I, @@ -188,6 +219,8 @@ struct mlx5dr_definer_fc { uint8_t item_idx; uint8_t is_range; uint16_t extra_data; + uint8_t compare_idx; + bool compare_set_base; uint32_t byte_off; int bit_off; uint32_t bit_mask; diff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c index 402242308d..8a74a1ed7d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_matcher.c +++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c @@ -485,6 +485,7 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher, rtc_attr.log_depth = attr->table.sz_col_log; rtc_attr.is_frst_jumbo = mlx5dr_matcher_mt_is_jumbo(mt); rtc_attr.is_scnd_range = mlx5dr_matcher_mt_is_range(mt); + rtc_attr.is_compare = mlx5dr_matcher_is_compare(matcher); rtc_attr.miss_ft_id = matcher->end_ft->id; if (attr->insert_mode == MLX5DR_MATCHER_INSERT_BY_HASH) { @@ -497,6 +498,10 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher, rtc_attr.num_hash_definer = 1; rtc_attr.match_definer_0 = mlx5dr_definer_get_id(matcher->hash_definer); + } else if (mlx5dr_matcher_is_compare(matcher)) { + rtc_attr.match_definer_0 = ctx->caps->trivial_match_definer; + rtc_attr.fw_gen_wqe = true; + rtc_attr.num_hash_definer = 1; } else { /* The first mt is used since all share the same definer */ rtc_attr.match_definer_0 = mlx5dr_definer_get_id(mt->definer); @@ -1635,3 +1640,51 @@ int mlx5dr_matcher_resize_rule_move(struct mlx5dr_matcher *src_matcher, rte_errno = EINVAL; return -rte_errno; } + +int mlx5dr_matcher_validate_compare_attr(struct mlx5dr_matcher *matcher) +{ + struct mlx5dr_cmd_query_caps *caps = matcher->tbl->ctx->caps; + struct mlx5dr_matcher_attr *attr = &matcher->attr; + + if (mlx5dr_table_is_root(matcher->tbl)) { + DR_LOG(ERR, "Compare matcher is not supported for root tables"); + goto err; + } + + if (attr->mode != MLX5DR_MATCHER_RESOURCE_MODE_HTABLE) { + DR_LOG(ERR, "Compare matcher is only supported with pre-defined table size"); + goto err; + } + + if (attr->insert_mode != MLX5DR_MATCHER_INSERT_BY_HASH || + attr->distribute_mode != MLX5DR_MATCHER_DISTRIBUTE_BY_HASH) { + DR_LOG(ERR, "Gen WQE for compare matcher must be inserted and distribute by hash"); + goto err; + } + + if (matcher->num_of_mt != 1 || matcher->num_of_at != 1) { + DR_LOG(ERR, "Compare matcher match templates and action templates must be 1 for each"); + goto err; + } + + if (attr->table.sz_col_log || attr->table.sz_row_log) { + DR_LOG(ERR, "Compare matcher supports only 1x1 table size"); + goto err; + } + + if (attr->resizable) { + DR_LOG(ERR, "Compare matcher does not support resizeing"); + goto err; + } + + if (!IS_BIT_SET(caps->supp_ste_format_gen_wqe, MLX5_IFC_RTC_STE_FORMAT_4DW_RANGE)) { + DR_LOG(ERR, "Gen WQE Compare match format not supported"); + goto err; + } + + return 0; + +err: + rte_errno = ENOTSUP; + return rte_errno; +} diff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.h b/drivers/net/mlx5/hws/mlx5dr_matcher.h index 0f2bf96e8b..6dc3bf4d0d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_matcher.h +++ b/drivers/net/mlx5/hws/mlx5dr_matcher.h @@ -27,6 +27,7 @@ enum mlx5dr_matcher_flags { MLX5DR_MATCHER_FLAGS_HASH_DEFINER = 1 << 1, MLX5DR_MATCHER_FLAGS_COLLISION = 1 << 2, MLX5DR_MATCHER_FLAGS_RESIZABLE = 1 << 3, + MLX5DR_MATCHER_FLAGS_COMPARE = 1 << 4, }; struct mlx5dr_match_template { @@ -110,12 +111,19 @@ static inline bool mlx5dr_matcher_is_in_resize(struct mlx5dr_matcher *matcher) return !!matcher->resize_dst; } +static inline bool +mlx5dr_matcher_is_compare(struct mlx5dr_matcher *matcher) +{ + return !!(matcher->flags & MLX5DR_MATCHER_FLAGS_COMPARE); +} + static inline bool mlx5dr_matcher_req_fw_wqe(struct mlx5dr_matcher *matcher) { /* Currently HWS doesn't support hash different from match or range */ return unlikely(matcher->flags & (MLX5DR_MATCHER_FLAGS_HASH_DEFINER | - MLX5DR_MATCHER_FLAGS_RANGE_DEFINER)); + MLX5DR_MATCHER_FLAGS_RANGE_DEFINER | + MLX5DR_MATCHER_FLAGS_COMPARE)); } int mlx5dr_matcher_conv_items_to_prm(uint64_t *match_buf, @@ -141,4 +149,6 @@ int mlx5dr_matcher_free_rtc_pointing(struct mlx5dr_context *ctx, enum mlx5dr_table_type type, struct mlx5dr_devx_obj *devx_obj); +int mlx5dr_matcher_validate_compare_attr(struct mlx5dr_matcher *matcher); + #endif /* MLX5DR_MATCHER_H_ */ From patchwork Mon Feb 26 13:18:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 137209 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1BD6343BED; Mon, 26 Feb 2024 14:19:24 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EDF3A42E30; Mon, 26 Feb 2024 14:19:18 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2079.outbound.protection.outlook.com [40.107.94.79]) by mails.dpdk.org (Postfix) with ESMTP id BED8742E20 for ; Mon, 26 Feb 2024 14:19:16 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MVwjw4IiR8bzoI1j7WIWCEg0JW2ktJeq40AUzaVRwuTfm5OyQLvHQyJ7li9GEsGnJL3CYnHEi8747evOsAG66mnqFNeHL91YEDnWLD9X5dTu2jW14kLjE3vIDrcttfZQ6Tu3Nhz8BySTUZOlLN5lBcV2oNF1lGPGL3Q4TD6TgA0B121S9sRT8n6LpkuCA0lsSzL7+qeNFD07rCC+KWAE4n5p7A4wclgy2hItoRu8IExC1QqU3eQqT2SwJqkS4zQTDwno4oOj2UzF4YYpjS1W5yYYvZQHUsjqS5SBOEQno7+7sZ0yGcMHoG47v8aLv6cf3sCOGwEOLPaKXGZugrYdoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=lGZFxIkuX1rIjffvq6FX2PuuC4SyYV23myD8DPwkqig=; b=en0fIo5X53gcEz3hZoooV6f6ORsyHd5HHqjQqvsPBDCvaH9J0TMZ4i8rpUj3zG+i9ErDxA9eB98wP70aIX87gYhwhCdL7ejTZMG1dhY8JRVu19Tvo8dxmGbpMc2pfrGl/Kf8t5URDLeJOrcp/PfvKECJiVqkTzRtOHB1hrxtViaEhvxUfqWF+G4ZC24QHfbDnMBH5iD9oKhJYetMxj14Yxka1COEAP/lceHCc+3A2BKLYJwrD4zuca+LNEsx+5XbwYcdBzV2QzImx7lUCoIIL8ohat2S6qgzhzz2fb61u6ReCvl1b6P+u7z7QlqVp3dYHrtFt7dsPvAkjDcIZ15fcw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lGZFxIkuX1rIjffvq6FX2PuuC4SyYV23myD8DPwkqig=; b=rwXt/Gn7v0OzHWA493SYNumcF1NTTuIs4VhMsDYRbQ8ycVhW1UefV/aPK+aAh3yZAqCkLmRAK9An9DN0P//9tywG3J2Wv2xMQCq0O7a2tSFhw4E4de/Fiyo+xgfWjjGtETzsVP0rW/HzF58DG9GgeGthYnFgZYW/qSssgRx6QvO8vXGfNurTk1Te8xW3Yq/hzxXes75SutSUXEL95P1Pp8qFi3H99xCSnCrIobDHruTc2ugGtEFl22tjk6jrcmofWKEQyulg8Vh070sE5QTnagMyuoHK8UDaWBQUw0ncjMbvflCZhGuZ3zKQDXplWowF4qQGr9Z4hTLMG5y8i9prMA== Received: from CH2PR14CA0004.namprd14.prod.outlook.com (2603:10b6:610:60::14) by DM4PR12MB6301.namprd12.prod.outlook.com (2603:10b6:8:a5::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.36; Mon, 26 Feb 2024 13:19:13 +0000 Received: from DS3PEPF000099E1.namprd04.prod.outlook.com (2603:10b6:610:60:cafe::ab) by CH2PR14CA0004.outlook.office365.com (2603:10b6:610:60::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.49 via Frontend Transport; Mon, 26 Feb 2024 13:19:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF000099E1.mail.protection.outlook.com (10.167.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Mon, 26 Feb 2024 13:19:13 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 26 Feb 2024 05:19:00 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 26 Feb 2024 05:18:59 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12 via Frontend Transport; Mon, 26 Feb 2024 05:18:57 -0800 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH v7 2/3] net/mlx5: add support to compare random value Date: Mon, 26 Feb 2024 15:18:47 +0200 Message-ID: <20240226131848.2982242-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226131848.2982242-1-michaelba@nvidia.com> References: <20240226130324.2981025-1-michaelba@nvidia.com> <20240226131848.2982242-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E1:EE_|DM4PR12MB6301:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ce4f9e6-e21d-47c4-6283-08dc36cd86d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yMsYpLkjh0k57mdlF0Oy/ADPnxxFUA0p1A+AqjXH6eVmT0lmXyKTC5dZe3A71BuwYgenf2JhRLf5gyY2p2fPR/itJnno/woRiRYS0ghjVIv4i5x0fws/6caUsO9rAknXtYwotzlqOzCZ1NqVtdMDB1EGun4a8WZ3pQi/yF4AY9EHCaPei9oeiSCMmzuYwb3dsRUmc+4m4mBngbAcq5Ge1di+JzWJbhuI3QwWXd9upV2j/PJMaWZ2QJw+buGzJcXmqhsYgcNP2C25co5Z1ll3/uB/+KWQ6a67B+/lJGQdIFYbF1XaFNj2KxVmxiWzfaxn40vRI8ir/Rs7tGVN414GYc7kxjAoNYe0SLy4Q1C5Buf/VRVhCW71VD6wn8dej9r9249IQ1KCU9qzhU7eJ8Jw9xyFxldM49IQ+7zZRiBzTno3IXA1gBb+RneuE+E68Iep0CRFTDRWMFoihisWR2x6J1Bgkv+/t4mMBlSc410IIrUUuH6szbvz53GxSJa2Uo9aY+oKNmVa2FeQ/JWHcjtYuWa0rAIm3ky2VanPsVZoIhuj9qlQk6krZOOORWjxTlVQ9v+Je2yZqYR+sOYpcqNcQKB6YkFaZ+wkn5WjrqG2sqg73dqati6U4KPfdexNxSVX+hF21Duc9yBRBeWxixjtC3GX3e9XZt8wqvmQa2n3GRfUzzNUTwtHgBKc5MtVG5jTxc3LWrU2a6pz2Iensr5TYo6MS9m8rBZgWoaEi52uLewwyZb+ERkEeyW3rz7Lr4E9 X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2024 13:19:13.6622 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ce4f9e6-e21d-47c4-6283-08dc36cd86d4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6301 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support to use "RTE_FLOW_ITEM_TYPE_COMPARE" with "RTE_FLOW_FIELD_RAMDOM" as an argument. The random field is supported only when base is an immediate value, random field cannot be compared with enother field. Signed-off-by: Michael Baum Acked-by: Suanming Mou --- doc/guides/nics/mlx5.rst | 9 ++++- drivers/net/mlx5/mlx5_flow_hw.c | 70 ++++++++++++++++++++++++--------- 2 files changed, 59 insertions(+), 20 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 0d2213497a..c0a5768117 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -431,8 +431,13 @@ Limitations - Only supported in HW steering(``dv_flow_en`` = 2) mode. - Only single flow is supported to the flow table. - - Only 32-bit comparison is supported. - - Only match with compare result between packet fields is supported. + - Only single item is supported per pattern template. + - Only 32-bit comparison is supported or 16-bits for random field. + - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``, + ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``. + - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field. + - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with + ``RTE_FLOW_FIELD_VALUE``. - No Tx metadata go to the E-Switch steering domain for the Flow group 0. The flows within group 0 and set metadata action are rejected by hardware. diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 3ae1220587..f31ba2df2b 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -6721,18 +6721,55 @@ flow_hw_prepend_item(const struct rte_flow_item *items, return copied_items; } -static inline bool -flow_hw_item_compare_field_supported(enum rte_flow_field_id field) +static int +flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, + enum rte_flow_field_id base_field, + struct rte_flow_error *error) { - switch (field) { + switch (arg_field) { + case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_META: + break; + case RTE_FLOW_FIELD_RANDOM: + if (base_field == RTE_FLOW_FIELD_VALUE) + return 0; + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "compare random is supported only with immediate value"); + default: + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "compare item argument field is not supported"); + } + switch (base_field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: case RTE_FLOW_FIELD_VALUE: - return true; + break; + default: + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "compare item base field is not supported"); + } + return 0; +} + +static inline uint32_t +flow_hw_item_compare_width_supported(enum rte_flow_field_id field) +{ + switch (field) { + case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_META: + return 32; + case RTE_FLOW_FIELD_RANDOM: + return 16; default: break; } - return false; + return 0; } static int @@ -6741,6 +6778,7 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item, { const struct rte_flow_item_compare *comp_m = item->mask; const struct rte_flow_item_compare *comp_v = item->spec; + int ret; if (unlikely(!comp_m)) return rte_flow_error_set(error, EINVAL, @@ -6752,19 +6790,13 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "compare item only support full mask"); - if (!flow_hw_item_compare_field_supported(comp_m->a.field) || - !flow_hw_item_compare_field_supported(comp_m->b.field)) - return rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, - "compare item field not support"); - if (comp_m->a.field == RTE_FLOW_FIELD_VALUE && - comp_m->b.field == RTE_FLOW_FIELD_VALUE) - return rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, - "compare between value is not valid"); + ret = flow_hw_item_compare_field_validate(comp_m->a.field, + comp_m->b.field, error); + if (ret < 0) + return ret; if (comp_v) { + uint32_t width; + if (comp_v->operation != comp_m->operation || comp_v->a.field != comp_m->a.field || comp_v->b.field != comp_m->b.field) @@ -6772,7 +6804,9 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "compare item spec/mask not matching"); - if ((comp_v->width & comp_m->width) != 32) + width = flow_hw_item_compare_width_supported(comp_v->a.field); + MLX5_ASSERT(width > 0); + if ((comp_v->width & comp_m->width) != width) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, From patchwork Mon Feb 26 13:18:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 137210 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9903743BED; Mon, 26 Feb 2024 14:19:30 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2EB1542E35; Mon, 26 Feb 2024 14:19:20 +0100 (CET) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2045.outbound.protection.outlook.com [40.107.244.45]) by mails.dpdk.org (Postfix) with ESMTP id 052B942E2E for ; Mon, 26 Feb 2024 14:19:18 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FOH6pg7W0aiKKfbw5jzEt1kxoZVjcI3Q+ruNkIRMYWYIy+A9JfcseAh5xnpMEPTz9xYnGxvAuEoYo7QFJC/jPObxi/J08xnS4DOoTYGEfg1+LhGGRv+rnurxwLiF5Pr74zaw7o7+N6Xoh1CdgX/kJUV5vBjEROPe9GmD9j8BOEatIDXXr0nz0GuzD6GBqLY4a62lXp14S3a//mUyiyiiOwBjUCZNU5irMWqzZ824E/eQbCxEZTkCn4cui9IamHw8ep/mLO3H3Z0OYLx2KsICyMhlfriwZU7ZXTfz5LFo5rSR1w6CQKvfONXl0uYXzGF9/GWTOywkT4kt9OanIbew8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6gkzmxhvkLvsSugaaFnJBG6CK8JXqbzq4cTbzPRbPyM=; b=mDdS7Fy9JJ+1akZluyF5jtKWDGdJwK0EpbmjqWLPMJJjO9G0pYjjXDg6RMoVcfeD7YWEDFrw4vy1qNIebpoDxDgahlKsRQzYyXo1CgExh5Qp5RyCsZGao43fY7H3Bzeuu4MO7TrBtMW5iwiiFJDeTX7Xua37BWBeGzuZ2cVSjcUMlVPflZHn6fnEwDz22IjEXWd6G8IF0MoQqdRlstYmr81tzyYl2MVZ1Sx/s2ZbagKk7PI6pN/kY4xKGqJDM9ign4JKyf8QK/b4cZ8K27YvR+uDwuaJCn85SmEsxIkVa90qmKsTXnEoJF8LwahvOSeFy1tmVn+FO2zFzXksSiXj1w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6gkzmxhvkLvsSugaaFnJBG6CK8JXqbzq4cTbzPRbPyM=; b=cJhDn56Slmwaobg9W7ifCQ2+SuanSUzT12oN9Qc4q5wxiRSB/eDJny4mkm4aQmNp2Y9NnLMKJL3YrEDHLRp/m2ToHjQWi2VpYKXp+Ht8ZVC194XmtjZ7nxH0SPUWUXYc3lgLcqoPdhRl8RvSLbkkfj5tTvuJNQkMX+7PX0zex4G49g47mwMuJHpgYaXsrPy1893n8WOlhsuDNBd9xo9+pgdI5oFcSxvipMM77sSHeB/8VSfpOh0a+rWOl1mPqpem15IJkCQpkUOvBFnoYyhEIWItF11V3HWFf6ip7OJUGrENoRfi0hv7IfyT1UbAWwWwTcuhjVKY1+oXRWovCDf7fA== Received: from CH2PR14CA0009.namprd14.prod.outlook.com (2603:10b6:610:60::19) by BL1PR12MB5780.namprd12.prod.outlook.com (2603:10b6:208:393::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.36; Mon, 26 Feb 2024 13:19:15 +0000 Received: from DS3PEPF000099E1.namprd04.prod.outlook.com (2603:10b6:610:60:cafe::62) by CH2PR14CA0009.outlook.office365.com (2603:10b6:610:60::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.49 via Frontend Transport; Mon, 26 Feb 2024 13:19:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF000099E1.mail.protection.outlook.com (10.167.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Mon, 26 Feb 2024 13:19:14 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 26 Feb 2024 05:19:02 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 26 Feb 2024 05:19:02 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12 via Frontend Transport; Mon, 26 Feb 2024 05:19:00 -0800 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH v7 3/3] net/mlx5/hws: add compare ESP sequence number support Date: Mon, 26 Feb 2024 15:18:48 +0200 Message-ID: <20240226131848.2982242-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226131848.2982242-1-michaelba@nvidia.com> References: <20240226130324.2981025-1-michaelba@nvidia.com> <20240226131848.2982242-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E1:EE_|BL1PR12MB5780:EE_ X-MS-Office365-Filtering-Correlation-Id: de545504-03d8-425d-6d87-08dc36cd8782 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sUHzOLkR/cltx9qkMh7bKWyoxpf4nxAui6PHfg+rjpmrLAdOOVnPLzZrO6TeFNOKB5drBn0sK0TsEgLuecHquo8CjmEuHN6RDCSOpbrD54hnwq14NKK0QQg2mZLrMD9N9SdUOn3/ue6BXpd6QRF4GQjv2nu/mdu0vGar2aZC7r8uQmb5oVSkv2+7Qts50GppdG/p7ESzVoJ/FiojK+3y/jcuiw7WmeaRzIJd+X/ExP7JFi7mHwUf0DnBy+UvEjD0Hl3s+CVm/So1btMs4ZTXebHPdKJvu0vXFp3d/koIoS8+9QGM2sfYx30hYzT53vDqeKTXgRGva81+x3t+jHkRojlZA40WXFYb2UkWd+lAvgD1lSQJILpIGdUrQpzvA0wQyp1weBE9Ve7UoYQ6dyV6Q50msLoBVR7YqnuCYyLa3BI+5HcjkbOT513/eE4nFSuXmMpvAcN5deXwBIGapqigORC7TEwoGH6eF+LbzW1htp4dHODFtrAsDW/bJWYTKqAsmdQ6uEQci319i914Rff6xHf9r1+crJEX+LQxVnZXs4bh/RmXTzyetAdT8Wg0re17RbvqbmnvqjkTmMuLT9IQDOaFGjxthriT9oRmcZvISbcmFDE8XphjMmeW+yUKB+hmZWOHp1mvxXyV2tk6cYVD2Csjp8ijxBwJws3vBI3MFUIqv9cz8q8WhhaKOLbNAzNBP3LfEeYcqPk6M88qE8B92NZSxfl1GcvTEP2Qtny49+NZFBEXARSSCrGWeZCiTaOZ X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2024 13:19:14.8185 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de545504-03d8-425d-6d87-08dc36cd8782 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5780 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for compare item with "RTE_FLOW_FIELD_ESP_SEQ_NUM" field. Signed-off-by: Michael Baum Acked-by: Suanming Mou --- doc/guides/nics/mlx5.rst | 1 + drivers/net/mlx5/hws/mlx5dr_definer.c | 22 ++++++++++++++++++++-- drivers/net/mlx5/mlx5_flow_hw.c | 3 +++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index c0a5768117..d7bf81161e 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -434,6 +434,7 @@ Limitations - Only single item is supported per pattern template. - Only 32-bit comparison is supported or 16-bits for random field. - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``, + ``RTE_FLOW_FIELD_ESP_SEQ_NUM``, ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``. - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field. - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 45e5bc5a61..c1508e6b53 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -424,10 +424,20 @@ mlx5dr_definer_compare_base_value_set(const void *item_spec, value = (const uint32_t *)&b->value[0]; - if (a->field == RTE_FLOW_FIELD_RANDOM) + switch (a->field) { + case RTE_FLOW_FIELD_RANDOM: *base = htobe32(*value << 16); - else + break; + case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_META: *base = htobe32(*value); + break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + *base = *value; + break; + default: + break; + } MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1); } @@ -2930,6 +2940,14 @@ mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f, fc->compare_idx = dw_offset; DR_CALC_SET_HDR(fc, random_number, random_number); break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_compare_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->compare_idx = dw_offset; + DR_CALC_SET_HDR(fc, ipsec, sequence_number); + break; default: DR_LOG(ERR, "%u field is not supported", f->field); goto err_notsup; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index f31ba2df2b..531c90e0ee 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -6729,6 +6729,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, switch (arg_field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: break; case RTE_FLOW_FIELD_RANDOM: if (base_field == RTE_FLOW_FIELD_VALUE) @@ -6747,6 +6748,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: case RTE_FLOW_FIELD_VALUE: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: break; default: return rte_flow_error_set(error, ENOTSUP, @@ -6763,6 +6765,7 @@ flow_hw_item_compare_width_supported(enum rte_flow_field_id field) switch (field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: return 32; case RTE_FLOW_FIELD_RANDOM: return 16;