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Mon, 26 Feb 2024 05:03:30 -0800 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Hamdan Igbaria Subject: [PATCH v6 1/3] net/mlx5/hws: add support for compare matcher Date: Mon, 26 Feb 2024 15:03:22 +0200 Message-ID: <20240226130324.2981025-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226130324.2981025-1-michaelba@nvidia.com> References: <20240214073015.2060103-1-michaelba@nvidia.com> <20240226130324.2981025-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|BL3PR12MB6449:EE_ X-MS-Office365-Filtering-Correlation-Id: d39f0ea9-b179-4693-60cf-08dc36cb647d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: KslX+wOVNhPOJT6EYHX2NDz6+xGZdssVjwmOZpM5fOOJ/RSRjlxkTkoxK1fAPJ45tj3/qCIuZ8JeP1vQycH9nNvX/NYWNdPhuteAmB1FffRkoF5qt4Yy/R/IlDT0Bic+mK3JybJ84Odla03n/RgB8rgNtubqOb1TECiKA2k5nq4E9u7Y2kaBTQBGt7u0xz8jWJNtsGrUXIwta+quKaSykAMrgIRMrrOvE7QPNQVUOVgYLkL1q3IhH0t0YU/+XBpZQPu35wcho2WhlmLTDMZm1wkEqWVqs5L8qXTDc3gpmhcqjHXJ5GHfKua2zEbD7FFZVsrzhQlD07xxzLtfhrlx7LjVt4HpwuTzPiEoZ+lNiu45w5wu2hoD5F0GplSwD1aBR12DuPnUCDLYqTgiHiP4nyZhvwiKGPgC6bL909C+6VFYmxsQxZQhkGej+oTWcX3Q/7CPVXTqr83EmsgjzjD/r5rgK1z/n2WkesIH0xf7ThLRGNUPerphemXwuuee7/O0HPwHw1IBHHZUsGf6snLbuOxUGpH/7VvzmX6wZF1iKh7l9ovvyuL9Gxo84J0cpF5T8ftahCE40Vb5aTkSYcXjlY662qsCqDFe7/AYnjDDQoX3lZ3Vdd8aug0c2Zpeib2Y6/rUBbmrWjIvpVGp1pyOZ9Hdj2tlNmatTHqPM3/6IP4bPZBMDncIg53f0K5FL+iWiWUZPt08K/+YALcMf9lk73J1vU11WpjFx++yFbei6/y0SY0IKeOT7khq68YXtpNX X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2024 13:03:57.0404 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d39f0ea9-b179-4693-60cf-08dc36cb647d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6449 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Hamdan Igbaria Add support for compare matcher, this matcher will allow direct comparison between two packet fields, or a packet field and a value, with fully masked DW. For now this matcher hash table is limited to size 1x1, thus it supports only 1 rule STE. Signed-off-by: Hamdan Igbaria Signed-off-by: Michael Baum Acked-by: Suanming Mou --- drivers/common/mlx5/mlx5_prm.h | 16 ++ drivers/net/mlx5/hws/mlx5dr_cmd.c | 9 +- drivers/net/mlx5/hws/mlx5dr_cmd.h | 1 + drivers/net/mlx5/hws/mlx5dr_debug.c | 4 +- drivers/net/mlx5/hws/mlx5dr_debug.h | 1 + drivers/net/mlx5/hws/mlx5dr_definer.c | 243 +++++++++++++++++++++++++- drivers/net/mlx5/hws/mlx5dr_definer.h | 33 ++++ drivers/net/mlx5/hws/mlx5dr_matcher.c | 53 ++++++ drivers/net/mlx5/hws/mlx5dr_matcher.h | 12 +- 9 files changed, 363 insertions(+), 9 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 282e59e52c..aceacb04d0 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3463,6 +3463,7 @@ enum mlx5_ifc_rtc_ste_format { MLX5_IFC_RTC_STE_FORMAT_8DW = 0x4, MLX5_IFC_RTC_STE_FORMAT_11DW = 0x5, MLX5_IFC_RTC_STE_FORMAT_RANGE = 0x7, + MLX5_IFC_RTC_STE_FORMAT_4DW_RANGE = 0x8, }; enum mlx5_ifc_rtc_reparse_mode { @@ -3501,6 +3502,21 @@ struct mlx5_ifc_rtc_bits { u8 reserved_at_1a0[0x260]; }; +struct mlx5_ifc_ste_match_4dw_range_ctrl_dw_bits { + u8 match[0x1]; + u8 reserved_at_1[0x2]; + u8 base1[0x1]; + u8 inverse1[0x1]; + u8 reserved_at_5[0x1]; + u8 operator1[0x2]; + u8 reserved_at_8[0x3]; + u8 base0[0x1]; + u8 inverse0[0x1]; + u8 reserved_at_a[0x1]; + u8 operator0[0x2]; + u8 compare_delta[0x10]; +}; + struct mlx5_ifc_alias_context_bits { u8 vhca_id_to_be_accessed[0x10]; u8 reserved_at_10[0xd]; diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c index fd07028e5f..0e0cc479a6 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.c +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c @@ -370,9 +370,12 @@ mlx5dr_cmd_rtc_create(struct ibv_context *ctx, attr, obj_type, MLX5_GENERAL_OBJ_TYPE_RTC); attr = MLX5_ADDR_OF(create_rtc_in, in, rtc); - MLX5_SET(rtc, attr, ste_format_0, rtc_attr->is_frst_jumbo ? - MLX5_IFC_RTC_STE_FORMAT_11DW : - MLX5_IFC_RTC_STE_FORMAT_8DW); + if (rtc_attr->is_compare) { + MLX5_SET(rtc, attr, ste_format_0, MLX5_IFC_RTC_STE_FORMAT_4DW_RANGE); + } else { + MLX5_SET(rtc, attr, ste_format_0, rtc_attr->is_frst_jumbo ? + MLX5_IFC_RTC_STE_FORMAT_11DW : MLX5_IFC_RTC_STE_FORMAT_8DW); + } if (rtc_attr->is_scnd_range) { MLX5_SET(rtc, attr, ste_format_1, MLX5_IFC_RTC_STE_FORMAT_RANGE); diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h index ee4a61b7eb..9d385fc57f 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.h +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h @@ -82,6 +82,7 @@ struct mlx5dr_cmd_rtc_create_attr { uint8_t reparse_mode; bool is_frst_jumbo; bool is_scnd_range; + bool is_compare; }; struct mlx5dr_cmd_alias_obj_create_attr { diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.c b/drivers/net/mlx5/hws/mlx5dr_debug.c index 11557bcab8..a9094cd35b 100644 --- a/drivers/net/mlx5/hws/mlx5dr_debug.c +++ b/drivers/net/mlx5/hws/mlx5dr_debug.c @@ -99,6 +99,7 @@ static int mlx5dr_debug_dump_matcher_match_template(FILE *f, struct mlx5dr_matcher *matcher) { bool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL; + bool is_compare = mlx5dr_matcher_is_compare(matcher); enum mlx5dr_debug_res_type type; int i, ret; @@ -117,7 +118,8 @@ mlx5dr_debug_dump_matcher_match_template(FILE *f, struct mlx5dr_matcher *matcher return rte_errno; } - type = MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_MATCH_DEFINER; + type = is_compare ? MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_COMPARE_MATCH_DEFINER : + MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_MATCH_DEFINER; ret = mlx5dr_debug_dump_matcher_template_definer(f, mt, mt->definer, type); if (ret) return ret; diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.h b/drivers/net/mlx5/hws/mlx5dr_debug.h index 5cffdb10b5..a89a6a0b1d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_debug.h +++ b/drivers/net/mlx5/hws/mlx5dr_debug.h @@ -24,6 +24,7 @@ enum mlx5dr_debug_res_type { MLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE = 4204, MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_HASH_DEFINER = 4205, MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_RANGE_DEFINER = 4206, + MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_COMPARE_MATCH_DEFINER = 4207, }; static inline uint64_t diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index b8a546989a..da50b64fb4 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -411,6 +411,86 @@ mlx5dr_definer_ptype_frag_set(struct mlx5dr_definer_fc *fc, DR_SET(tag, !!packet_type, fc->byte_off, fc->bit_off, fc->bit_mask); } +static void +mlx5dr_definer_compare_base_value_set(const void *item_spec, + uint8_t *tag) +{ + uint32_t *ctrl = &(((uint32_t *)tag)[MLX5DR_DEFINER_COMPARE_STE_ARGUMENT_1]); + uint32_t *base = &(((uint32_t *)tag)[MLX5DR_DEFINER_COMPARE_STE_BASE_0]); + const struct rte_flow_item_compare *v = item_spec; + const struct rte_flow_field_data *a = &v->a; + const struct rte_flow_field_data *b = &v->b; + const uint32_t *value; + + value = (const uint32_t *)&b->value[0]; + + if (a->field == RTE_FLOW_FIELD_RANDOM) + *base = htobe32(*value << 16); + else + *base = htobe32(*value); + + MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1); +} + +static void +mlx5dr_definer_compare_op_translate(enum rte_flow_item_compare_op op, + uint8_t *tag) +{ + uint32_t *ctrl = &(((uint32_t *)tag)[MLX5DR_DEFINER_COMPARE_STE_ARGUMENT_1]); + uint8_t operator = 0; + uint8_t inverse = 0; + + switch (op) { + case RTE_FLOW_ITEM_COMPARE_EQ: + operator = 2; + break; + case RTE_FLOW_ITEM_COMPARE_NE: + operator = 2; + inverse = 1; + break; + case RTE_FLOW_ITEM_COMPARE_LT: + inverse = 1; + break; + case RTE_FLOW_ITEM_COMPARE_LE: + operator = 1; + break; + case RTE_FLOW_ITEM_COMPARE_GT: + operator = 1; + inverse = 1; + break; + case RTE_FLOW_ITEM_COMPARE_GE: + break; + default: + DR_LOG(ERR, "Invalid operation type %d", op); + assert(false); + } + + MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, inverse0, inverse); + MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, operator0, operator); +} + +static void +mlx5dr_definer_compare_arg_set(const void *item_spec, + uint8_t *tag) +{ + const struct rte_flow_item_compare *v = item_spec; + enum rte_flow_item_compare_op op = v->operation; + + mlx5dr_definer_compare_op_translate(op, tag); +} + +static void +mlx5dr_definer_compare_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + if (fc->compare_idx == MLX5DR_DEFINER_COMPARE_ARGUMENT_0) { + mlx5dr_definer_compare_arg_set(item_spec, tag); + if (fc->compare_set_base) + mlx5dr_definer_compare_base_value_set(item_spec, tag); + } +} + static void mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc, const void *item_spec, @@ -2782,10 +2862,124 @@ mlx5dr_definer_conv_item_vxlan_gpe(struct mlx5dr_definer_conv_data *cd, return 0; } +static int +mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f, + const struct rte_flow_field_data *other_f, + struct mlx5dr_definer_conv_data *cd, + int item_idx, + enum mlx5dr_definer_compare_dw_selectors dw_offset) +{ + struct mlx5dr_definer_fc *fc = NULL; + int reg; + + if (f->offset) { + DR_LOG(ERR, "field offset %u is not supported, only offset zero supported", + f->offset); + goto err_notsup; + } + + switch (f->field) { + case RTE_FLOW_FIELD_META: + reg = flow_hw_get_reg_id_from_ctx(cd->ctx, + RTE_FLOW_ITEM_TYPE_META, -1); + if (reg <= 0) { + DR_LOG(ERR, "Invalid register for compare metadata field"); + rte_errno = EINVAL; + return rte_errno; + } + + fc = mlx5dr_definer_get_register_fc(cd, reg); + if (!fc) + return rte_errno; + + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_compare_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->compare_idx = dw_offset; + break; + case RTE_FLOW_FIELD_TAG: + reg = flow_hw_get_reg_id_from_ctx(cd->ctx, + RTE_FLOW_ITEM_TYPE_TAG, + f->tag_index); + if (reg <= 0) { + DR_LOG(ERR, "Invalid register for compare tag field"); + rte_errno = EINVAL; + return rte_errno; + } + + fc = mlx5dr_definer_get_register_fc(cd, reg); + if (!fc) + return rte_errno; + + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_compare_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->compare_idx = dw_offset; + break; + case RTE_FLOW_FIELD_VALUE: + if (dw_offset == MLX5DR_DEFINER_COMPARE_ARGUMENT_0) { + DR_LOG(ERR, "Argument field does not support immediate value"); + goto err_notsup; + } + break; + case RTE_FLOW_FIELD_RANDOM: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_RANDOM_NUM]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_compare_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->compare_idx = dw_offset; + DR_CALC_SET_HDR(fc, random_number, random_number); + break; + default: + DR_LOG(ERR, "%u field is not supported", f->field); + goto err_notsup; + } + + if (fc && other_f && other_f->field == RTE_FLOW_FIELD_VALUE) + fc->compare_set_base = true; + + return 0; + +err_notsup: + rte_errno = ENOTSUP; + return rte_errno; +} + +static int +mlx5dr_definer_conv_item_compare(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_compare *m = item->mask; + const struct rte_flow_field_data *a = &m->a; + const struct rte_flow_field_data *b = &m->b; + int ret; + + if (m->width != 0xffffffff) { + DR_LOG(ERR, "compare item width of 0x%x is not supported, only full DW supported", + m->width); + rte_errno = ENOTSUP; + return rte_errno; + } + + ret = mlx5dr_definer_conv_item_compare_field(a, b, cd, item_idx, + MLX5DR_DEFINER_COMPARE_ARGUMENT_0); + if (ret) + return ret; + + ret = mlx5dr_definer_conv_item_compare_field(b, NULL, cd, item_idx, + MLX5DR_DEFINER_COMPARE_BASE_0); + if (ret) + return ret; + + return 0; +} + static int mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, struct mlx5dr_match_template *mt, - uint8_t *hl) + uint8_t *hl, + struct mlx5dr_matcher *matcher) { struct mlx5dr_definer_fc fc[MLX5DR_DEFINER_FNAME_MAX] = {{0}}; struct mlx5dr_definer_conv_data cd = {0}; @@ -2805,6 +2999,11 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, if (ret) return ret; + if (mlx5dr_matcher_is_compare(matcher)) { + DR_LOG(ERR, "Compare matcher not supported for more than one item"); + goto not_supp; + } + switch ((int)items->type) { case RTE_FLOW_ITEM_TYPE_ETH: ret = mlx5dr_definer_conv_item_eth(&cd, items, i); @@ -2950,10 +3149,18 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, ret = mlx5dr_definer_conv_item_vxlan_gpe(&cd, items, i); item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE; break; + case RTE_FLOW_ITEM_TYPE_COMPARE: + if (i) { + DR_LOG(ERR, "Compare matcher not supported for more than one item"); + goto not_supp; + } + ret = mlx5dr_definer_conv_item_compare(&cd, items, i); + item_flags |= MLX5_FLOW_ITEM_COMPARE; + matcher->flags |= MLX5DR_MATCHER_FLAGS_COMPARE; + break; default: DR_LOG(ERR, "Unsupported item type %d", items->type); - rte_errno = ENOTSUP; - return rte_errno; + goto not_supp; } cd.last_item = items->type; @@ -2974,6 +3181,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, } return 0; + +not_supp: + rte_errno = ENOTSUP; + return rte_errno; } static int @@ -3391,6 +3602,7 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher, { struct mlx5dr_context *ctx = matcher->tbl->ctx; struct mlx5dr_match_template *mt = matcher->mt; + struct mlx5dr_definer_fc *fc; uint8_t *match_hl; int i, ret; @@ -3408,13 +3620,35 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher, * and allocate the match and range field copy array (fc & fcr). */ for (i = 0; i < matcher->num_of_mt; i++) { - ret = mlx5dr_definer_conv_items_to_hl(ctx, &mt[i], match_hl); + ret = mlx5dr_definer_conv_items_to_hl(ctx, &mt[i], match_hl, matcher); if (ret) { DR_LOG(ERR, "Failed to convert items to header layout"); goto free_fc; } } + if (mlx5dr_matcher_is_compare(matcher)) { + ret = mlx5dr_matcher_validate_compare_attr(matcher); + if (ret) + goto free_fc; + + /* Due some HW limitation need to fill unused + * DW's 0-5 and byte selectors with 0xff. + */ + for (i = 0; i < DW_SELECTORS_MATCH; i++) + match_definer->dw_selector[i] = 0xff; + + for (i = 0; i < BYTE_SELECTORS; i++) + match_definer->byte_selector[i] = 0xff; + + for (i = 0; i < mt[0].fc_sz; i++) { + fc = &mt[0].fc[i]; + match_definer->dw_selector[fc->compare_idx] = fc->byte_off / DW_SIZE; + } + + goto out; + } + /* Find the match definer layout for header layout match union */ ret = mlx5dr_definer_find_best_match_fit(ctx, match_definer, match_hl); if (ret) { @@ -3435,6 +3669,7 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher, goto free_fc; } +out: simple_free(match_hl); return 0; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 71cc0e94de..ca530ebf30 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -17,6 +17,37 @@ #define DW_SELECTORS_RANGE 2 #define BYTE_SELECTORS_RANGE 8 +enum mlx5dr_definer_compare_ste_dw_offset { + /* In compare STE the matching DW's starts after the 3 actions */ + MLX5DR_DEFINER_COMPARE_STE_ARGUMENT_1 = 3, + MLX5DR_DEFINER_COMPARE_STE_ARGUMENT_0, + MLX5DR_DEFINER_COMPARE_STE_BASE_1, + MLX5DR_DEFINER_COMPARE_STE_BASE_0, + MLX5DR_DEFINER_COMPARE_STE_TAG_DW_3, + MLX5DR_DEFINER_COMPARE_STE_TAG_DW_2, + MLX5DR_DEFINER_COMPARE_STE_TAG_DW_1, + MLX5DR_DEFINER_COMPARE_STE_TAG_DW_0, +}; + +enum mlx5dr_definer_dw_selectors { + MLX5DR_DEFINER_SELECTOR_DW0, + MLX5DR_DEFINER_SELECTOR_DW1, + MLX5DR_DEFINER_SELECTOR_DW2, + MLX5DR_DEFINER_SELECTOR_DW3, + MLX5DR_DEFINER_SELECTOR_DW4, + MLX5DR_DEFINER_SELECTOR_DW5, + MLX5DR_DEFINER_SELECTOR_DW6, + MLX5DR_DEFINER_SELECTOR_DW7, + MLX5DR_DEFINER_SELECTOR_DW8, +}; + +enum mlx5dr_definer_compare_dw_selectors { + MLX5DR_DEFINER_COMPARE_ARGUMENT_0 = MLX5DR_DEFINER_SELECTOR_DW4, + MLX5DR_DEFINER_COMPARE_ARGUMENT_1 = MLX5DR_DEFINER_SELECTOR_DW5, + MLX5DR_DEFINER_COMPARE_BASE_0 = MLX5DR_DEFINER_SELECTOR_DW2, + MLX5DR_DEFINER_COMPARE_BASE_1 = MLX5DR_DEFINER_SELECTOR_DW3, +}; + enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_ETH_SMAC_48_16_O, MLX5DR_DEFINER_FNAME_ETH_SMAC_48_16_I, @@ -188,6 +219,8 @@ struct mlx5dr_definer_fc { uint8_t item_idx; uint8_t is_range; uint16_t extra_data; + uint8_t compare_idx; + bool compare_set_base; uint32_t byte_off; int bit_off; uint32_t bit_mask; diff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c index 402242308d..8a74a1ed7d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_matcher.c +++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c @@ -485,6 +485,7 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher, rtc_attr.log_depth = attr->table.sz_col_log; rtc_attr.is_frst_jumbo = mlx5dr_matcher_mt_is_jumbo(mt); rtc_attr.is_scnd_range = mlx5dr_matcher_mt_is_range(mt); + rtc_attr.is_compare = mlx5dr_matcher_is_compare(matcher); rtc_attr.miss_ft_id = matcher->end_ft->id; if (attr->insert_mode == MLX5DR_MATCHER_INSERT_BY_HASH) { @@ -497,6 +498,10 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher, rtc_attr.num_hash_definer = 1; rtc_attr.match_definer_0 = mlx5dr_definer_get_id(matcher->hash_definer); + } else if (mlx5dr_matcher_is_compare(matcher)) { + rtc_attr.match_definer_0 = ctx->caps->trivial_match_definer; + rtc_attr.fw_gen_wqe = true; + rtc_attr.num_hash_definer = 1; } else { /* The first mt is used since all share the same definer */ rtc_attr.match_definer_0 = mlx5dr_definer_get_id(mt->definer); @@ -1635,3 +1640,51 @@ int mlx5dr_matcher_resize_rule_move(struct mlx5dr_matcher *src_matcher, rte_errno = EINVAL; return -rte_errno; } + +int mlx5dr_matcher_validate_compare_attr(struct mlx5dr_matcher *matcher) +{ + struct mlx5dr_cmd_query_caps *caps = matcher->tbl->ctx->caps; + struct mlx5dr_matcher_attr *attr = &matcher->attr; + + if (mlx5dr_table_is_root(matcher->tbl)) { + DR_LOG(ERR, "Compare matcher is not supported for root tables"); + goto err; + } + + if (attr->mode != MLX5DR_MATCHER_RESOURCE_MODE_HTABLE) { + DR_LOG(ERR, "Compare matcher is only supported with pre-defined table size"); + goto err; + } + + if (attr->insert_mode != MLX5DR_MATCHER_INSERT_BY_HASH || + attr->distribute_mode != MLX5DR_MATCHER_DISTRIBUTE_BY_HASH) { + DR_LOG(ERR, "Gen WQE for compare matcher must be inserted and distribute by hash"); + goto err; + } + + if (matcher->num_of_mt != 1 || matcher->num_of_at != 1) { + DR_LOG(ERR, "Compare matcher match templates and action templates must be 1 for each"); + goto err; + } + + if (attr->table.sz_col_log || attr->table.sz_row_log) { + DR_LOG(ERR, "Compare matcher supports only 1x1 table size"); + goto err; + } + + if (attr->resizable) { + DR_LOG(ERR, "Compare matcher does not support resizeing"); + goto err; + } + + if (!IS_BIT_SET(caps->supp_ste_format_gen_wqe, MLX5_IFC_RTC_STE_FORMAT_4DW_RANGE)) { + DR_LOG(ERR, "Gen WQE Compare match format not supported"); + goto err; + } + + return 0; + +err: + rte_errno = ENOTSUP; + return rte_errno; +} diff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.h b/drivers/net/mlx5/hws/mlx5dr_matcher.h index 0f2bf96e8b..6dc3bf4d0d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_matcher.h +++ b/drivers/net/mlx5/hws/mlx5dr_matcher.h @@ -27,6 +27,7 @@ enum mlx5dr_matcher_flags { MLX5DR_MATCHER_FLAGS_HASH_DEFINER = 1 << 1, MLX5DR_MATCHER_FLAGS_COLLISION = 1 << 2, MLX5DR_MATCHER_FLAGS_RESIZABLE = 1 << 3, + MLX5DR_MATCHER_FLAGS_COMPARE = 1 << 4, }; struct mlx5dr_match_template { @@ -110,12 +111,19 @@ static inline bool mlx5dr_matcher_is_in_resize(struct mlx5dr_matcher *matcher) return !!matcher->resize_dst; } +static inline bool +mlx5dr_matcher_is_compare(struct mlx5dr_matcher *matcher) +{ + return !!(matcher->flags & MLX5DR_MATCHER_FLAGS_COMPARE); +} + static inline bool mlx5dr_matcher_req_fw_wqe(struct mlx5dr_matcher *matcher) { /* Currently HWS doesn't support hash different from match or range */ return unlikely(matcher->flags & (MLX5DR_MATCHER_FLAGS_HASH_DEFINER | - MLX5DR_MATCHER_FLAGS_RANGE_DEFINER)); + MLX5DR_MATCHER_FLAGS_RANGE_DEFINER | + MLX5DR_MATCHER_FLAGS_COMPARE)); } int mlx5dr_matcher_conv_items_to_prm(uint64_t *match_buf, @@ -141,4 +149,6 @@ int mlx5dr_matcher_free_rtc_pointing(struct mlx5dr_context *ctx, enum mlx5dr_table_type type, struct mlx5dr_devx_obj *devx_obj); +int mlx5dr_matcher_validate_compare_attr(struct mlx5dr_matcher *matcher); + #endif /* MLX5DR_MATCHER_H_ */ From patchwork Mon Feb 26 13:03:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 137206 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0538843BEF; Mon, 26 Feb 2024 14:04:41 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 698CF42E50; Mon, 26 Feb 2024 14:04:06 +0100 (CET) Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2052.outbound.protection.outlook.com [40.107.100.52]) by mails.dpdk.org (Postfix) with ESMTP id 5A12542E46 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2024 13:03:57.3341 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2bee9a4e-52d6-44f5-f740-08dc36cb64ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5106 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support to use "RTE_FLOW_ITEM_TYPE_COMPARE" with "RTE_FLOW_FIELD_RAMDOM" as an argument. The random field is supported only when base is an immediate value, random field cannot be compared with enother field. Signed-off-by: Michael Baum Acked-by: Suanming Mou --- doc/guides/nics/mlx5.rst | 9 ++++- drivers/net/mlx5/mlx5_flow_hw.c | 70 ++++++++++++++++++++++++--------- 2 files changed, 59 insertions(+), 20 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 0d2213497a..c0a5768117 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -431,8 +431,13 @@ Limitations - Only supported in HW steering(``dv_flow_en`` = 2) mode. - Only single flow is supported to the flow table. - - Only 32-bit comparison is supported. - - Only match with compare result between packet fields is supported. + - Only single item is supported per pattern template. + - Only 32-bit comparison is supported or 16-bits for random field. + - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``, + ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``. + - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field. + - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with + ``RTE_FLOW_FIELD_VALUE``. - No Tx metadata go to the E-Switch steering domain for the Flow group 0. The flows within group 0 and set metadata action are rejected by hardware. diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 0d09c220df..b0e93baaf2 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -6721,18 +6721,55 @@ flow_hw_prepend_item(const struct rte_flow_item *items, return copied_items; } -static inline bool -flow_hw_item_compare_field_supported(enum rte_flow_field_id field) +static int +flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, + enum rte_flow_field_id base_field, + struct rte_flow_error *error) { - switch (field) { + switch (arg_field) { + case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_META: + break; + case RTE_FLOW_FIELD_RANDOM: + if (base_field == RTE_FLOW_FIELD_VALUE) + return 0; + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "compare random is supported only with immediate value"); + default: + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "compare item argument field is not supported"); + } + switch (base_field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: case RTE_FLOW_FIELD_VALUE: - return true; + break; + default: + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "compare item base field is not supported"); + } + return 0; +} + +static inline uint32_t +flow_hw_item_compare_width_supported(enum rte_flow_field_id field) +{ + switch (field) { + case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_META: + return 32; + case RTE_FLOW_FIELD_RANDOM: + return 16; default: break; } - return false; + return 0; } static int @@ -6741,6 +6778,7 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item, { const struct rte_flow_item_compare *comp_m = item->mask; const struct rte_flow_item_compare *comp_v = item->spec; + int ret; if (unlikely(!comp_m)) return rte_flow_error_set(error, EINVAL, @@ -6752,19 +6790,13 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "compare item only support full mask"); - if (!flow_hw_item_compare_field_supported(comp_m->a.field) || - !flow_hw_item_compare_field_supported(comp_m->b.field)) - return rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, - "compare item field not support"); - if (comp_m->a.field == RTE_FLOW_FIELD_VALUE && - comp_m->b.field == RTE_FLOW_FIELD_VALUE) - return rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, - "compare between value is not valid"); + ret = flow_hw_item_compare_field_validate(comp_m->a.field, + comp_m->b.field, error); + if (ret < 0) + return ret; if (comp_v) { + uint32_t width; + if (comp_v->operation != comp_m->operation || comp_v->a.field != comp_m->a.field || comp_v->b.field != comp_m->b.field) @@ -6772,7 +6804,9 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "compare item spec/mask not matching"); - if ((comp_v->width & comp_m->width) != 32) + width = flow_hw_item_compare_width_supported(comp_v->a.field); + MLX5_ASSERT(width > 0); + if ((comp_v->width & comp_m->width) != width) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, From patchwork Mon Feb 26 13:03:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 137207 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7DB1D43BEF; Mon, 26 Feb 2024 14:04:50 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0477242E5A; Mon, 26 Feb 2024 14:04:12 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2055.outbound.protection.outlook.com [40.107.94.55]) by mails.dpdk.org (Postfix) with ESMTP id C17FE42E5F for ; Mon, 26 Feb 2024 14:04:08 +0100 (CET) ARC-Seal: i=1; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2024 13:04:05.6026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff80e11a-1a96-4b50-b46d-08dc36cb69af X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A100.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4313 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for compare item with "RTE_FLOW_FIELD_ESP_SEQ_NUM" field. Signed-off-by: Michael Baum Acked-by: Suanming Mou --- doc/guides/nics/mlx5.rst | 1 + drivers/net/mlx5/hws/mlx5dr_definer.c | 22 ++++++++++++++++++++-- drivers/net/mlx5/mlx5_flow_hw.c | 3 +++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index c0a5768117..d7bf81161e 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -434,6 +434,7 @@ Limitations - Only single item is supported per pattern template. - Only 32-bit comparison is supported or 16-bits for random field. - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``, + ``RTE_FLOW_FIELD_ESP_SEQ_NUM``, ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``. - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field. - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index da50b64fb4..39269b4ede 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -424,10 +424,20 @@ mlx5dr_definer_compare_base_value_set(const void *item_spec, value = (const uint32_t *)&b->value[0]; - if (a->field == RTE_FLOW_FIELD_RANDOM) + switch (a->field) { + case RTE_FLOW_FIELD_RANDOM: *base = htobe32(*value << 16); - else + break; + case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_META: *base = htobe32(*value); + break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + *base = *value; + break; + default: + break; + } MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1); } @@ -2930,6 +2940,14 @@ mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f, fc->compare_idx = dw_offset; DR_CALC_SET_HDR(fc, random_number, random_number); break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_compare_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->compare_idx = dw_offset; + DR_CALC_SET_HDR(fc, ipsec, sequence_number); + break; default: DR_LOG(ERR, "%u field is not supported", f->field); goto err_notsup; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index b0e93baaf2..33922bddff 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -6729,6 +6729,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, switch (arg_field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: break; case RTE_FLOW_FIELD_RANDOM: if (base_field == RTE_FLOW_FIELD_VALUE) @@ -6747,6 +6748,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: case RTE_FLOW_FIELD_VALUE: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: break; default: return rte_flow_error_set(error, ENOTSUP, @@ -6763,6 +6765,7 @@ flow_hw_item_compare_width_supported(enum rte_flow_field_id field) switch (field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: return 32; case RTE_FLOW_FIELD_RANDOM: return 16;