From patchwork Thu Oct 26 18:31:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar Muthukrishnan X-Patchwork-Id: 133437 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 924EB4320B; Thu, 26 Oct 2023 20:31:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2EB8F410FD; Thu, 26 Oct 2023 20:31:57 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id CCA6840EF0 for ; Thu, 26 Oct 2023 20:31:55 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39QI9rcv027678; Thu, 26 Oct 2023 11:31:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ACsbdnRzknyCBQQqY0h0j4vvrA2YShqI97KxzNupIfo=; b=SObxuCmtj3fHK4ZP8cPSGsot475JWhK0x1uCEWaxntq9exS1BJXpWfTpqdODmyODQe6S SbMXqnZmadjVqAcDmIAFDFPAiIszKgkmYRW/uzAyoDFLMcQDHxBsapskLbnOND1uSMtt T+CnaiQIuLuTJBrY3iT16pmg1E9+Bng7e7HF3el5A5jTegWpJ5/W3ljoPIOPw7og1YER +aWNdYea0dsc6Uv01JX31wRwjAZV4IO5ufkl+QVr4ov7aZlPKaP1aV5y6/YGnmGsudrC xYp2FZsxSUtxH5LqjIaEVJw/5jtP5ipKvMRp44zFszVgKWm9WF0gCkK1YCYWQUWDHQbV KQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3tyw5083be-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 26 Oct 2023 11:31:55 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 26 Oct 2023 11:31:53 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 26 Oct 2023 11:31:53 -0700 Received: from BG-LT91401.marvell.com (BG-LT91401.marvell.com [10.28.168.34]) by maili.marvell.com (Postfix) with ESMTP id BD2763F7054; Thu, 26 Oct 2023 11:31:50 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: , Cheng Jiang , Kevin Laatz , Bruce Richardson , "Pavan Nikhilesh" , Amit Prakash Shukla Subject: [PATCH v5 1/4] app/dma-perf: add skip support Date: Fri, 27 Oct 2023 00:01:39 +0530 Message-ID: <94813d9f9220b61d6634992d9d7ebca094a4e8d1.1698344721.git.gmuthukrishn@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: O7uqkQlAky5gJWPUBgJVz7ryiAxz0v_J X-Proofpoint-GUID: O7uqkQlAky5gJWPUBgJVz7ryiAxz0v_J X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-26_17,2023-10-26_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Amit Prakash Shukla Add support to skip running a dma-perf test-case. Signed-off-by: Amit Prakash Shukla Acked-by: Anoob Joseph --- app/test-dma-perf/config.ini | 2 ++ app/test-dma-perf/main.c | 23 +++++++++++++++++++++++ app/test-dma-perf/main.h | 1 + 3 files changed, 26 insertions(+) diff --git a/app/test-dma-perf/config.ini b/app/test-dma-perf/config.ini index b550f4b23f..4d59234b2a 100644 --- a/app/test-dma-perf/config.ini +++ b/app/test-dma-perf/config.ini @@ -36,6 +36,8 @@ ; If you do not specify a result file, one will be generated with the same name as the configuration ; file, with the addition of "_result.csv" at the end. +; "skip" To skip a test-case set skip to 1. + [case1] type=DMA_MEM_COPY mem_size=10 diff --git a/app/test-dma-perf/main.c b/app/test-dma-perf/main.c index e5bccc27da..61260fa072 100644 --- a/app/test-dma-perf/main.c +++ b/app/test-dma-perf/main.c @@ -320,6 +320,7 @@ load_configs(const char *path) const char *case_type; const char *lcore_dma; const char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str; + const char *skip; int args_nr, nb_vp; bool is_dma; @@ -339,6 +340,13 @@ load_configs(const char *path) for (i = 0; i < nb_sections; i++) { snprintf(section_name, CFG_NAME_LEN, "case%d", i + 1); test_case = &test_cases[i]; + + skip = rte_cfgfile_get_entry(cfgfile, section_name, "skip"); + if (skip && (atoi(skip) == 1)) { + test_case->is_skip = true; + continue; + } + case_type = rte_cfgfile_get_entry(cfgfile, section_name, "type"); if (case_type == NULL) { printf("Error: No case type in case %d, the test will be finished here.\n", @@ -523,6 +531,21 @@ main(int argc, char *argv[]) printf("Running cases...\n"); for (i = 0; i < case_nb; i++) { + if (test_cases[i].is_skip) { + printf("Test case %d configured to be skipped.\n\n", i + 1); + snprintf(output_str[0], MAX_OUTPUT_STR_LEN, "Skip the test-case %d\n", + i + 1); + + fd = fopen(rst_path_ptr, "a"); + if (!fd) { + printf("Open output CSV file error.\n"); + return 0; + } + output_csv(true); + fclose(fd); + continue; + } + if (!test_cases[i].is_valid) { printf("Invalid test case %d.\n\n", i + 1); snprintf(output_str[0], MAX_OUTPUT_STR_LEN, "Invalid case %d\n", i + 1); diff --git a/app/test-dma-perf/main.h b/app/test-dma-perf/main.h index f65e264378..be89cb2b65 100644 --- a/app/test-dma-perf/main.h +++ b/app/test-dma-perf/main.h @@ -41,6 +41,7 @@ struct lcore_dma_map_t { struct test_configure { bool is_valid; + bool is_skip; uint8_t test_type; const char *test_type_str; uint16_t src_numa_node; From patchwork Thu Oct 26 18:31:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar Muthukrishnan X-Patchwork-Id: 133438 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 44FA84320B; Thu, 26 Oct 2023 20:32:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5EF1A42830; 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Thu, 26 Oct 2023 11:31:58 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 26 Oct 2023 11:31:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 26 Oct 2023 11:31:56 -0700 Received: from BG-LT91401.marvell.com (BG-LT91401.marvell.com [10.28.168.34]) by maili.marvell.com (Postfix) with ESMTP id BE2A53F7057; Thu, 26 Oct 2023 11:31:53 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: , Cheng Jiang , Kevin Laatz , Bruce Richardson , "Pavan Nikhilesh" , Amit Prakash Shukla Subject: [PATCH v5 2/4] app/dma-perf: add PCI device support Date: Fri, 27 Oct 2023 00:01:40 +0530 Message-ID: <6a5e314b937637acd8fe291acb290e0c2d1151cd.1698344721.git.gmuthukrishn@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: WHAi-YzWv-qU1SbuSd8rGCGIE3z-Jtcf X-Proofpoint-GUID: WHAi-YzWv-qU1SbuSd8rGCGIE3z-Jtcf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-26_17,2023-10-26_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Amit Prakash Shukla Add support to test performance for "device to memory" and "memory to device" data transfer. Signed-off-by: Amit Prakash Shukla Acked-by: Anoob Joseph --- app/test-dma-perf/benchmark.c | 67 +++++++++++++++++++++++++++++++---- app/test-dma-perf/config.ini | 37 +++++++++++++++++++ app/test-dma-perf/main.c | 67 +++++++++++++++++++++++++++++++++++ app/test-dma-perf/main.h | 6 ++++ 4 files changed, 170 insertions(+), 7 deletions(-) diff --git a/app/test-dma-perf/benchmark.c b/app/test-dma-perf/benchmark.c index 0601e0d171..523f2fbb5a 100644 --- a/app/test-dma-perf/benchmark.c +++ b/app/test-dma-perf/benchmark.c @@ -127,17 +127,54 @@ cache_flush_buf(__rte_unused struct rte_mbuf **array, #endif } +static int +vchan_data_populate(uint32_t dev_id, struct rte_dma_vchan_conf *qconf, + struct test_configure *cfg) +{ + struct rte_dma_info info; + + qconf->direction = cfg->transfer_dir; + + rte_dma_info_get(dev_id, &info); + if (!(RTE_BIT64(qconf->direction) & info.dev_capa)) + return -1; + + qconf->nb_desc = cfg->ring_size.cur; + + switch (qconf->direction) { + case RTE_DMA_DIR_MEM_TO_DEV: + qconf->dst_port.pcie.vfen = 1; + qconf->dst_port.port_type = RTE_DMA_PORT_PCIE; + qconf->dst_port.pcie.coreid = cfg->dcoreid; + qconf->dst_port.pcie.vfid = cfg->vfid; + qconf->dst_port.pcie.pfid = cfg->pfid; + break; + case RTE_DMA_DIR_DEV_TO_MEM: + qconf->src_port.pcie.vfen = 1; + qconf->src_port.port_type = RTE_DMA_PORT_PCIE; + qconf->src_port.pcie.coreid = cfg->scoreid; + qconf->src_port.pcie.vfid = cfg->vfid; + qconf->src_port.pcie.pfid = cfg->pfid; + break; + case RTE_DMA_DIR_MEM_TO_MEM: + case RTE_DMA_DIR_DEV_TO_DEV: + break; + } + + return 0; +} + /* Configuration of device. */ static void -configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size) +configure_dmadev_queue(uint32_t dev_id, struct test_configure *cfg) { uint16_t vchan = 0; struct rte_dma_info info; struct rte_dma_conf dev_config = { .nb_vchans = 1 }; - struct rte_dma_vchan_conf qconf = { - .direction = RTE_DMA_DIR_MEM_TO_MEM, - .nb_desc = ring_size - }; + struct rte_dma_vchan_conf qconf = { 0 }; + + if (vchan_data_populate(dev_id, &qconf, cfg) != 0) + rte_exit(EXIT_FAILURE, "Error with vchan data populate.\n"); if (rte_dma_configure(dev_id, &dev_config) != 0) rte_exit(EXIT_FAILURE, "Error with dma configure.\n"); @@ -159,7 +196,6 @@ configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size) static int config_dmadevs(struct test_configure *cfg) { - uint32_t ring_size = cfg->ring_size.cur; struct lcore_dma_map_t *ldm = &cfg->lcore_dma_map; uint32_t nb_workers = ldm->cnt; uint32_t i; @@ -176,7 +212,7 @@ config_dmadevs(struct test_configure *cfg) } ldm->dma_ids[i] = dev_id; - configure_dmadev_queue(dev_id, ring_size); + configure_dmadev_queue(dev_id, cfg); ++nb_dmadevs; } @@ -308,6 +344,7 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs, unsigned int buf_size = cfg->buf_size.cur; unsigned int nr_sockets; uint32_t nr_buf = cfg->nr_buf; + uint32_t i; nr_sockets = rte_socket_count(); if (cfg->src_numa_node >= nr_sockets || @@ -360,6 +397,22 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs, return -1; } + if (cfg->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM) { + for (i = 0; i < nr_buf; i++) { + /* Using mbuf structure to hold remote iova address. */ + rte_mbuf_iova_set(*srcs[i], (rte_iova_t)cfg->raddr); + ((*srcs)[i])->data_off = 0; + } + } + + if (cfg->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV) { + for (i = 0; i < nr_buf; i++) { + /* Using mbuf structure to hold remote iova address. */ + rte_mbuf_iova_set(*dsts[i], (rte_iova_t)cfg->raddr); + ((*dsts)[i])->data_off = 0; + } + } + return 0; } diff --git a/app/test-dma-perf/config.ini b/app/test-dma-perf/config.ini index 4d59234b2a..cddcf93c6e 100644 --- a/app/test-dma-perf/config.ini +++ b/app/test-dma-perf/config.ini @@ -38,6 +38,23 @@ ; "skip" To skip a test-case set skip to 1. +; Parameters to be configured for data transfers from "mem to dev" and "dev to mem": +; ================================================================================== +; "direction" denotes the direction of data transfer. It can take 3 values: +; 0 - mem to mem transfer +; 1 - mem to dev transfer +; 2 - dev to mem transfer +; If not specified the default value is 0 (mem to mem transfer). + +; "raddr" remote iova address for "mem to dev" and "dev to mem" transfer. + +; "scoreid" denotes source PCIe core index. +; "dcoreid" denotes destination PCIe core index. +; "pfid" denotes PF-id to be used for data transfer +; "vfid" denotes VF-id of PF-id to be used for data transfer. + +; =========== End of "mem to dev" and "dev to mem" config parameters. ============== + [case1] type=DMA_MEM_COPY mem_size=10 @@ -52,6 +69,26 @@ lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3 eal_args=--in-memory --file-prefix=test [case2] +skip=1 +type=DMA_MEM_COPY +direction=2 +raddr=0x200000000 +scoreid=0 +dcoreid=0 +pfid=0 +vfid=0 +mem_size=10 +buf_size=64,4096,2,MUL +dma_ring_size=1024 +kick_batch=32 +src_numa_node=0 +dst_numa_node=0 +cache_flush=0 +test_seconds=2 +lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3 +eal_args=--in-memory --file-prefix=test + +[case3] type=CPU_MEM_COPY mem_size=10 buf_size=64,8192,2,MUL diff --git a/app/test-dma-perf/main.c b/app/test-dma-perf/main.c index 61260fa072..9640356592 100644 --- a/app/test-dma-perf/main.c +++ b/app/test-dma-perf/main.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "main.h" @@ -318,9 +319,11 @@ load_configs(const char *path) struct test_configure *test_case; char section_name[CFG_NAME_LEN]; const char *case_type; + const char *transfer_dir; const char *lcore_dma; const char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str; const char *skip; + const char *raddr, *scoreid, *dcoreid, *vfid, *pfid; int args_nr, nb_vp; bool is_dma; @@ -358,6 +361,20 @@ load_configs(const char *path) if (strcmp(case_type, DMA_MEM_COPY) == 0) { test_case->test_type = TEST_TYPE_DMA_MEM_COPY; test_case->test_type_str = DMA_MEM_COPY; + + transfer_dir = rte_cfgfile_get_entry(cfgfile, section_name, "direction"); + if (transfer_dir == NULL) { + printf("Transfer direction not configured." + " Defaulting it to MEM to MEM transfer.\n"); + test_case->transfer_dir = RTE_DMA_DIR_MEM_TO_MEM; + } else + test_case->transfer_dir = (uint8_t)atoi(transfer_dir); + + if (test_case->transfer_dir >= RTE_DMA_DIR_DEV_TO_DEV) { + printf("Error: Invalid transfer direction configured.\n"); + test_case->is_valid = false; + continue; + } is_dma = true; } else if (strcmp(case_type, CPU_MEM_COPY) == 0) { test_case->test_type = TEST_TYPE_CPU_MEM_COPY; @@ -369,6 +386,56 @@ load_configs(const char *path) continue; } + if (test_case->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV || + test_case->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM) { + char *endptr; + + raddr = rte_cfgfile_get_entry(cfgfile, section_name, "raddr"); + if (raddr == NULL) { + printf("Error: No raddr configured for case%d.\n", i + 1); + test_case->is_valid = false; + continue; + } + test_case->raddr = strtoull(raddr, &endptr, 16); + + vfid = rte_cfgfile_get_entry(cfgfile, section_name, "vfid"); + if (vfid == NULL) { + printf("Error: No vfid configured for case%d.\n", i + 1); + test_case->is_valid = false; + continue; + } + test_case->vfid = (uint16_t)atoi(vfid); + + pfid = rte_cfgfile_get_entry(cfgfile, section_name, "pfid"); + if (pfid == NULL) { + printf("Error: No pfid configured for case%d.\n", i + 1); + test_case->is_valid = false; + continue; + } + test_case->pfid = (uint8_t)atoi(pfid); + + } + + if (test_case->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM) { + scoreid = rte_cfgfile_get_entry(cfgfile, section_name, "scoreid"); + if (scoreid == NULL) { + printf("Error: No scoreid configured for case%d.\n", i + 1); + test_case->is_valid = false; + continue; + } + test_case->scoreid = (uint8_t)atoi(scoreid); + } + + if (test_case->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV) { + dcoreid = rte_cfgfile_get_entry(cfgfile, section_name, "dcoreid"); + if (dcoreid == NULL) { + printf("Error: No dcoreid configured for case%d.\n", i + 1); + test_case->is_valid = false; + continue; + } + test_case->dcoreid = (uint8_t)atoi(dcoreid); + } + test_case->src_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile, section_name, "src_numa_node")); test_case->dst_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile, diff --git a/app/test-dma-perf/main.h b/app/test-dma-perf/main.h index be89cb2b65..617f62f085 100644 --- a/app/test-dma-perf/main.h +++ b/app/test-dma-perf/main.h @@ -43,6 +43,7 @@ struct test_configure { bool is_valid; bool is_skip; uint8_t test_type; + uint8_t transfer_dir; const char *test_type_str; uint16_t src_numa_node; uint16_t dst_numa_node; @@ -58,6 +59,11 @@ struct test_configure { uint16_t test_secs; const char *eal_args; uint8_t scenario_id; + uint8_t scoreid; + uint8_t dcoreid; + uint8_t pfid; + uint16_t vfid; + uint64_t raddr; }; void mem_copy_benchmark(struct test_configure *cfg, bool is_dma); From patchwork Thu Oct 26 18:31:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar Muthukrishnan X-Patchwork-Id: 133439 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0E5E64320B; Thu, 26 Oct 2023 20:32:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DB7DF42E15; Thu, 26 Oct 2023 20:32:02 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 2365242DB2 for ; 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Thu, 26 Oct 2023 11:32:01 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 26 Oct 2023 11:31:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 26 Oct 2023 11:31:59 -0700 Received: from BG-LT91401.marvell.com (BG-LT91401.marvell.com [10.28.168.34]) by maili.marvell.com (Postfix) with ESMTP id C7C783F706D; Thu, 26 Oct 2023 11:31:56 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: , Cheng Jiang , Kevin Laatz , Bruce Richardson , "Pavan Nikhilesh" , Amit Prakash Shukla , Gowrishankar Muthukrishnan Subject: [PATCH v5 3/4] app/dma-perf: validate copied memory Date: Fri, 27 Oct 2023 00:01:41 +0530 Message-ID: <2b6527e2982aa7293225d4936eebf0ad9608d3ae.1698344721.git.gmuthukrishn@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-GUID: RGmn6pNFAyVKYAeOmYaBl-RQ86hOymvR X-Proofpoint-ORIG-GUID: RGmn6pNFAyVKYAeOmYaBl-RQ86hOymvR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-26_17,2023-10-26_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Validate copied memory to ensure DMA copy did not fail. Signed-off-by: Gowrishankar Muthukrishnan Acked-by: Anoob Joseph --- app/test-dma-perf/benchmark.c | 23 +++++++++++++++++++++-- app/test-dma-perf/main.c | 16 +++++++++++----- app/test-dma-perf/main.h | 2 +- 3 files changed, 33 insertions(+), 8 deletions(-) diff --git a/app/test-dma-perf/benchmark.c b/app/test-dma-perf/benchmark.c index 523f2fbb5a..c31f1aba93 100644 --- a/app/test-dma-perf/benchmark.c +++ b/app/test-dma-perf/benchmark.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "main.h" @@ -397,6 +398,11 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs, return -1; } + for (i = 0; i < nr_buf; i++) { + memset(rte_pktmbuf_mtod((*srcs)[i], void *), rte_rand(), buf_size); + memset(rte_pktmbuf_mtod((*dsts)[i], void *), 0, buf_size); + } + if (cfg->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM) { for (i = 0; i < nr_buf; i++) { /* Using mbuf structure to hold remote iova address. */ @@ -416,10 +422,10 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs, return 0; } -void +int mem_copy_benchmark(struct test_configure *cfg, bool is_dma) { - uint16_t i; + uint32_t i; uint32_t offset; unsigned int lcore_id = 0; struct rte_mbuf **srcs = NULL, **dsts = NULL; @@ -434,6 +440,7 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) uint32_t avg_cycles_total; float mops, mops_total; float bandwidth, bandwidth_total; + int ret = 0; if (setup_memory_env(cfg, &srcs, &dsts) < 0) goto out; @@ -507,6 +514,16 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) rte_eal_mp_wait_lcore(); + for (i = 0; i < (nr_buf / nb_workers) * nb_workers; i++) { + if (memcmp(rte_pktmbuf_mtod(srcs[i], void *), + rte_pktmbuf_mtod(dsts[i], void *), + cfg->buf_size.cur) != 0) { + printf("Copy validation fails for buffer number %d\n", i); + ret = -1; + goto out; + } + } + mops_total = 0; bandwidth_total = 0; avg_cycles_total = 0; @@ -558,4 +575,6 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) rte_dma_stop(ldm->dma_ids[i]); } } + + return ret; } diff --git a/app/test-dma-perf/main.c b/app/test-dma-perf/main.c index 9640356592..3b79694137 100644 --- a/app/test-dma-perf/main.c +++ b/app/test-dma-perf/main.c @@ -87,20 +87,24 @@ output_header(uint32_t case_id, struct test_configure *case_cfg) output_csv(true); } -static void +static int run_test_case(struct test_configure *case_cfg) { + int ret = 0; + switch (case_cfg->test_type) { case TEST_TYPE_DMA_MEM_COPY: - mem_copy_benchmark(case_cfg, true); + ret = mem_copy_benchmark(case_cfg, true); break; case TEST_TYPE_CPU_MEM_COPY: - mem_copy_benchmark(case_cfg, false); + ret = mem_copy_benchmark(case_cfg, false); break; default: printf("Unknown test type. %s\n", case_cfg->test_type_str); break; } + + return ret; } static void @@ -145,8 +149,10 @@ run_test(uint32_t case_id, struct test_configure *case_cfg) case_cfg->scenario_id++; printf("\nRunning scenario %d\n", case_cfg->scenario_id); - run_test_case(case_cfg); - output_csv(false); + if (run_test_case(case_cfg) < 0) + printf("\nTest fails! skipping this scenario.\n"); + else + output_csv(false); if (var_entry->op == OP_ADD) var_entry->cur += var_entry->incr; diff --git a/app/test-dma-perf/main.h b/app/test-dma-perf/main.h index 617f62f085..3d75edd1de 100644 --- a/app/test-dma-perf/main.h +++ b/app/test-dma-perf/main.h @@ -66,6 +66,6 @@ struct test_configure { uint64_t raddr; }; -void mem_copy_benchmark(struct test_configure *cfg, bool is_dma); +int mem_copy_benchmark(struct test_configure *cfg, bool is_dma); #endif /* MAIN_H */ From patchwork Thu Oct 26 18:31:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar Muthukrishnan X-Patchwork-Id: 133440 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E18FE4320B; Thu, 26 Oct 2023 20:32:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2714742DDB; Thu, 26 Oct 2023 20:32:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9A87240EF0 for ; Thu, 26 Oct 2023 20:32:05 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39QI9oDD027664; Thu, 26 Oct 2023 11:32:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ci1jLuGAJ/21AqlkBbFWBtgRwpASfbMSljb8Tr7MfYk=; b=NhgmKE9kV2uT+c4hho8fPvp7eg6Jlp1u3UcgfhCdMaptKb+hzGEMrjbFscFI1ZNmmpoS aTxSBexC/wVZg+vrCQlS2RqBfOQxrjJbQ3kO7j2ZPOJ7JtGwft5dOHeM/KfdN0cyBIXM kUlblgIvKccbFXOBez/Oox7Plw7rBGKflQ7prWhvKSOBCtjNB58L7MmnsGwp1p33Y3FL HeFnyQKV4g9m1uBH6tOUsXN3d5VL1FV1v8Gy9FFoqS4Xlo5VYkpCHHgkGaheX4LjohUo eV9riGwSUf1I7rwBwZiCsh32S0VzF3Zbuzx83ASzSYjYDMQKpldIc2BwP3TYJB9Hhkuv NQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3tyw5083cm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 26 Oct 2023 11:32:04 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 26 Oct 2023 11:32:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 26 Oct 2023 11:32:03 -0700 Received: from BG-LT91401.marvell.com (BG-LT91401.marvell.com [10.28.168.34]) by maili.marvell.com (Postfix) with ESMTP id 1A12F3F7054; Thu, 26 Oct 2023 11:31:59 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: , Cheng Jiang , Kevin Laatz , Bruce Richardson , "Pavan Nikhilesh" , Amit Prakash Shukla , Gowrishankar Muthukrishnan Subject: [PATCH v5 4/4] app/dma-perf: add SG copy support Date: Fri, 27 Oct 2023 00:01:42 +0530 Message-ID: <80a131c07f988f065f2c7a27ca73e57a2c1566c3.1698344721.git.gmuthukrishn@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ETHgA7cvQWzKdADvGaplJIVLghel36iy X-Proofpoint-GUID: ETHgA7cvQWzKdADvGaplJIVLghel36iy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-26_17,2023-10-26_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add SG copy support. Signed-off-by: Gowrishankar Muthukrishnan Acked-by: Anoob Joseph --- app/test-dma-perf/benchmark.c | 274 +++++++++++++++++++++++++++++----- app/test-dma-perf/config.ini | 19 ++- app/test-dma-perf/main.c | 34 ++++- app/test-dma-perf/main.h | 5 +- 4 files changed, 292 insertions(+), 40 deletions(-) diff --git a/app/test-dma-perf/benchmark.c b/app/test-dma-perf/benchmark.c index c31f1aba93..b363d28f15 100644 --- a/app/test-dma-perf/benchmark.c +++ b/app/test-dma-perf/benchmark.c @@ -46,6 +46,10 @@ struct lcore_params { uint16_t test_secs; struct rte_mbuf **srcs; struct rte_mbuf **dsts; + struct rte_dma_sge *src_sges; + struct rte_dma_sge *dst_sges; + uint8_t src_ptrs; + uint8_t dst_ptrs; volatile struct worker_info worker_info; }; @@ -86,21 +90,31 @@ calc_result(uint32_t buf_size, uint32_t nr_buf, uint16_t nb_workers, uint16_t te } static void -output_result(uint8_t scenario_id, uint32_t lcore_id, char *dma_name, uint16_t ring_size, - uint16_t kick_batch, uint64_t ave_cycle, uint32_t buf_size, uint32_t nr_buf, - float memory, float bandwidth, float mops, bool is_dma) +output_result(struct test_configure *cfg, struct lcore_params *para, + uint16_t kick_batch, uint64_t ave_cycle, uint32_t buf_size, + uint32_t nr_buf, float memory, float bandwidth, float mops) { - if (is_dma) - printf("lcore %u, DMA %s, DMA Ring Size: %u, Kick Batch Size: %u.\n", - lcore_id, dma_name, ring_size, kick_batch); - else + uint16_t ring_size = cfg->ring_size.cur; + uint8_t scenario_id = cfg->scenario_id; + uint32_t lcore_id = para->lcore_id; + char *dma_name = para->dma_name; + + if (cfg->is_dma) { + printf("lcore %u, DMA %s, DMA Ring Size: %u, Kick Batch Size: %u", lcore_id, + dma_name, ring_size, kick_batch); + if (cfg->is_sg) + printf(" DMA src ptrs: %u, dst ptrs: %u", + para->src_ptrs, para->dst_ptrs); + printf(".\n"); + } else { printf("lcore %u\n", lcore_id); + } printf("Average Cycles/op: %" PRIu64 ", Buffer Size: %u B, Buffer Number: %u, Memory: %.2lf MB, Frequency: %.3lf Ghz.\n", ave_cycle, buf_size, nr_buf, memory, rte_get_timer_hz()/1000000000.0); printf("Average Bandwidth: %.3lf Gbps, MOps: %.3lf\n", bandwidth, mops); - if (is_dma) + if (cfg->is_dma) snprintf(output_str[lcore_id], MAX_OUTPUT_STR_LEN, CSV_LINE_DMA_FMT, scenario_id, lcore_id, dma_name, ring_size, kick_batch, buf_size, nr_buf, memory, ave_cycle, bandwidth, mops); @@ -167,7 +181,7 @@ vchan_data_populate(uint32_t dev_id, struct rte_dma_vchan_conf *qconf, /* Configuration of device. */ static void -configure_dmadev_queue(uint32_t dev_id, struct test_configure *cfg) +configure_dmadev_queue(uint32_t dev_id, struct test_configure *cfg, uint8_t ptrs_max) { uint16_t vchan = 0; struct rte_dma_info info; @@ -190,6 +204,10 @@ configure_dmadev_queue(uint32_t dev_id, struct test_configure *cfg) rte_exit(EXIT_FAILURE, "Error, no configured queues reported on device id. %u\n", dev_id); + if (info.max_sges < ptrs_max) + rte_exit(EXIT_FAILURE, "Error, DMA ptrs more than supported by device id %u.\n", + dev_id); + if (rte_dma_start(dev_id) != 0) rte_exit(EXIT_FAILURE, "Error with dma start.\n"); } @@ -202,8 +220,12 @@ config_dmadevs(struct test_configure *cfg) uint32_t i; int dev_id; uint16_t nb_dmadevs = 0; + uint8_t ptrs_max = 0; char *dma_name; + if (cfg->is_sg) + ptrs_max = RTE_MAX(cfg->src_ptrs, cfg->dst_ptrs); + for (i = 0; i < ldm->cnt; i++) { dma_name = ldm->dma_names[i]; dev_id = rte_dma_get_dev_id_by_name(dma_name); @@ -213,7 +235,7 @@ config_dmadevs(struct test_configure *cfg) } ldm->dma_ids[i] = dev_id; - configure_dmadev_queue(dev_id, cfg); + configure_dmadev_queue(dev_id, cfg, ptrs_max); ++nb_dmadevs; } @@ -253,7 +275,7 @@ do_dma_submit_and_poll(uint16_t dev_id, uint64_t *async_cnt, } static inline int -do_dma_mem_copy(void *p) +do_dma_plain_mem_copy(void *p) { struct lcore_params *para = (struct lcore_params *)p; volatile struct worker_info *worker_info = &(para->worker_info); @@ -306,6 +328,65 @@ do_dma_mem_copy(void *p) return 0; } +static inline int +do_dma_sg_mem_copy(void *p) +{ + struct lcore_params *para = (struct lcore_params *)p; + volatile struct worker_info *worker_info = &(para->worker_info); + struct rte_dma_sge *src_sges = para->src_sges; + struct rte_dma_sge *dst_sges = para->dst_sges; + const uint16_t kick_batch = para->kick_batch; + const uint8_t src_ptrs = para->src_ptrs; + const uint8_t dst_ptrs = para->dst_ptrs; + const uint16_t dev_id = para->dev_id; + uint32_t nr_buf = para->nr_buf; + uint64_t async_cnt = 0; + uint32_t poll_cnt = 0; + uint16_t nr_cpl; + uint32_t i, j; + int ret; + + nr_buf /= RTE_MAX(src_ptrs, dst_ptrs); + worker_info->stop_flag = false; + worker_info->ready_flag = true; + + while (!worker_info->start_flag) + ; + + while (1) { + j = 0; + for (i = 0; i < nr_buf; i++) { +dma_copy: + ret = rte_dma_copy_sg(dev_id, 0, + &src_sges[i * src_ptrs], &dst_sges[j * dst_ptrs], + src_ptrs, dst_ptrs, 0); + if (unlikely(ret < 0)) { + if (ret == -ENOSPC) { + do_dma_submit_and_poll(dev_id, &async_cnt, worker_info); + goto dma_copy; + } else + error_exit(dev_id); + } + async_cnt++; + j++; + + if ((async_cnt % kick_batch) == 0) + do_dma_submit_and_poll(dev_id, &async_cnt, worker_info); + } + + if (worker_info->stop_flag) + break; + } + + rte_dma_submit(dev_id, 0); + while ((async_cnt > 0) && (poll_cnt++ < POLL_MAX)) { + nr_cpl = rte_dma_completed(dev_id, 0, MAX_DMA_CPL_NB, NULL, NULL); + async_cnt -= nr_cpl; + } + + return 0; +} + static inline int do_cpu_mem_copy(void *p) { @@ -339,8 +420,9 @@ do_cpu_mem_copy(void *p) } static int -setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs, - struct rte_mbuf ***dsts) +setup_memory_env(struct test_configure *cfg, + struct rte_mbuf ***srcs, struct rte_mbuf ***dsts, + struct rte_dma_sge **src_sges, struct rte_dma_sge **dst_sges) { unsigned int buf_size = cfg->buf_size.cur; unsigned int nr_sockets; @@ -419,20 +501,56 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs, } } + if (cfg->is_sg) { + uint8_t src_ptrs = cfg->src_ptrs; + uint8_t dst_ptrs = cfg->dst_ptrs; + uint32_t sglen_src, sglen_dst; + + *src_sges = rte_zmalloc(NULL, nr_buf * sizeof(struct rte_dma_sge), + RTE_CACHE_LINE_SIZE); + if (*src_sges == NULL) { + printf("Error: src_sges array malloc failed.\n"); + return -1; + } + + *dst_sges = rte_zmalloc(NULL, nr_buf * sizeof(struct rte_dma_sge), + RTE_CACHE_LINE_SIZE); + if (*dst_sges == NULL) { + printf("Error: dst_sges array malloc failed.\n"); + return -1; + } + + sglen_src = buf_size / src_ptrs; + sglen_dst = buf_size / dst_ptrs; + + for (i = 0; i < nr_buf; i++) { + (*src_sges)[i].addr = rte_pktmbuf_iova((*srcs)[i]); + (*src_sges)[i].length = sglen_src; + if (!((i+1) % src_ptrs)) + (*src_sges)[i].length += (buf_size % src_ptrs); + + (*dst_sges)[i].addr = rte_pktmbuf_iova((*dsts)[i]); + (*dst_sges)[i].length = sglen_dst; + if (!((i+1) % dst_ptrs)) + (*dst_sges)[i].length += (buf_size % dst_ptrs); + } + } + return 0; } int -mem_copy_benchmark(struct test_configure *cfg, bool is_dma) +mem_copy_benchmark(struct test_configure *cfg) { - uint32_t i; + uint32_t i, j; uint32_t offset; unsigned int lcore_id = 0; + struct rte_dma_sge *src_sges = NULL, *dst_sges = NULL; struct rte_mbuf **srcs = NULL, **dsts = NULL; struct lcore_dma_map_t *ldm = &cfg->lcore_dma_map; + const uint32_t mcore_id = rte_get_main_lcore(); unsigned int buf_size = cfg->buf_size.cur; uint16_t kick_batch = cfg->kick_batch.cur; - uint32_t nr_buf = cfg->nr_buf = (cfg->mem_size.cur * 1024 * 1024) / (cfg->buf_size.cur * 2); uint16_t nb_workers = ldm->cnt; uint16_t test_secs = cfg->test_secs; float memory = 0; @@ -440,12 +558,32 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) uint32_t avg_cycles_total; float mops, mops_total; float bandwidth, bandwidth_total; + uint32_t nr_sgsrc = 0, nr_sgdst = 0; + uint32_t nr_buf; int ret = 0; - if (setup_memory_env(cfg, &srcs, &dsts) < 0) + /* Align number of buffers according to workers count */ + nr_buf = (cfg->mem_size.cur * 1024 * 1024) / (cfg->buf_size.cur * 2); + nr_buf -= (nr_buf % nb_workers); + if (cfg->is_sg) { + nr_buf /= nb_workers; + nr_buf -= nr_buf % (cfg->src_ptrs * cfg->dst_ptrs); + nr_buf *= nb_workers; + + if (cfg->dst_ptrs > cfg->src_ptrs) { + nr_sgsrc = (nr_buf / cfg->dst_ptrs * cfg->src_ptrs); + nr_sgdst = nr_buf; + } else { + nr_sgsrc = nr_buf; + nr_sgdst = (nr_buf / cfg->src_ptrs * cfg->dst_ptrs); + } + } + + cfg->nr_buf = nr_buf; + if (setup_memory_env(cfg, &srcs, &dsts, &src_sges, &dst_sges) < 0) goto out; - if (is_dma) + if (cfg->is_dma) if (config_dmadevs(cfg) < 0) goto out; @@ -459,13 +597,23 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) for (i = 0; i < nb_workers; i++) { lcore_id = ldm->lcores[i]; + if (lcore_id == mcore_id) { + printf("lcore parameters can not use main core id %d\n", mcore_id); + goto out; + } + + if (rte_eal_lcore_role(lcore_id) == ROLE_OFF) { + printf("lcore parameters can not use offline core id %d\n", lcore_id); + goto out; + } + offset = nr_buf / nb_workers * i; lcores[i] = rte_malloc(NULL, sizeof(struct lcore_params), 0); if (lcores[i] == NULL) { printf("lcore parameters malloc failure for lcore %d\n", lcore_id); break; } - if (is_dma) { + if (cfg->is_dma) { lcores[i]->dma_name = ldm->dma_names[i]; lcores[i]->dev_id = ldm->dma_ids[i]; lcores[i]->kick_batch = kick_batch; @@ -479,10 +627,23 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) lcores[i]->scenario_id = cfg->scenario_id; lcores[i]->lcore_id = lcore_id; - if (is_dma) - rte_eal_remote_launch(do_dma_mem_copy, (void *)(lcores[i]), lcore_id); - else + if (cfg->is_sg) { + lcores[i]->src_ptrs = cfg->src_ptrs; + lcores[i]->dst_ptrs = cfg->dst_ptrs; + lcores[i]->src_sges = src_sges + (nr_sgsrc / nb_workers * i); + lcores[i]->dst_sges = dst_sges + (nr_sgdst / nb_workers * i); + } + + if (cfg->is_dma) { + if (!cfg->is_sg) + rte_eal_remote_launch(do_dma_plain_mem_copy, (void *)(lcores[i]), + lcore_id); + else + rte_eal_remote_launch(do_dma_sg_mem_copy, (void *)(lcores[i]), + lcore_id); + } else { rte_eal_remote_launch(do_cpu_mem_copy, (void *)(lcores[i]), lcore_id); + } } while (1) { @@ -514,13 +675,53 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) rte_eal_mp_wait_lcore(); - for (i = 0; i < (nr_buf / nb_workers) * nb_workers; i++) { - if (memcmp(rte_pktmbuf_mtod(srcs[i], void *), - rte_pktmbuf_mtod(dsts[i], void *), - cfg->buf_size.cur) != 0) { - printf("Copy validation fails for buffer number %d\n", i); - ret = -1; - goto out; + if (!cfg->is_sg) { + for (i = 0; i < (nr_buf / nb_workers) * nb_workers; i++) { + if (memcmp(rte_pktmbuf_mtod(srcs[i], void *), + rte_pktmbuf_mtod(dsts[i], void *), + cfg->buf_size.cur) != 0) { + printf("Copy validation fails for buffer number %d\n", i); + ret = -1; + goto out; + } + } + } else { + size_t src_remsz = buf_size % cfg->src_ptrs; + size_t dst_remsz = buf_size % cfg->dst_ptrs; + size_t src_sz = buf_size / cfg->src_ptrs; + size_t dst_sz = buf_size / cfg->dst_ptrs; + uint8_t src[buf_size], dst[buf_size]; + uint8_t *sbuf, *dbuf, *ptr; + + for (i = 0; i < (nr_buf / RTE_MAX(cfg->src_ptrs, cfg->dst_ptrs)); i++) { + sbuf = src; + dbuf = dst; + ptr = NULL; + + for (j = 0; j < cfg->src_ptrs; j++) { + ptr = rte_pktmbuf_mtod(srcs[i * cfg->src_ptrs + j], uint8_t *); + memcpy(sbuf, ptr, src_sz); + sbuf += src_sz; + } + + if (src_remsz) + memcpy(sbuf, ptr + src_sz, src_remsz); + + for (j = 0; j < cfg->dst_ptrs; j++) { + ptr = rte_pktmbuf_mtod(dsts[i * cfg->dst_ptrs + j], uint8_t *); + memcpy(dbuf, ptr, dst_sz); + dbuf += dst_sz; + } + + if (dst_remsz) + memcpy(dbuf, ptr + dst_sz, dst_remsz); + + if (memcmp(src, dst, buf_size) != 0) { + printf("SG Copy validation fails for buffer number %d\n", + i * cfg->src_ptrs); + ret = -1; + goto out; + } } } @@ -531,10 +732,8 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) calc_result(buf_size, nr_buf, nb_workers, test_secs, lcores[i]->worker_info.test_cpl, &memory, &avg_cycles, &bandwidth, &mops); - output_result(cfg->scenario_id, lcores[i]->lcore_id, - lcores[i]->dma_name, cfg->ring_size.cur, kick_batch, - avg_cycles, buf_size, nr_buf / nb_workers, memory, - bandwidth, mops, is_dma); + output_result(cfg, lcores[i], kick_batch, avg_cycles, buf_size, + nr_buf / nb_workers, memory, bandwidth, mops); mops_total += mops; bandwidth_total += bandwidth; avg_cycles_total += avg_cycles; @@ -563,13 +762,20 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) rte_mempool_free(dst_pool); dst_pool = NULL; + /* free sges for mbufs */ + rte_free(src_sges); + src_sges = NULL; + + rte_free(dst_sges); + dst_sges = NULL; + /* free the worker parameters */ for (i = 0; i < nb_workers; i++) { rte_free(lcores[i]); lcores[i] = NULL; } - if (is_dma) { + if (cfg->is_dma) { for (i = 0; i < nb_workers; i++) { printf("Stopping dmadev %d\n", ldm->dma_ids[i]); rte_dma_stop(ldm->dma_ids[i]); diff --git a/app/test-dma-perf/config.ini b/app/test-dma-perf/config.ini index cddcf93c6e..f460b93414 100644 --- a/app/test-dma-perf/config.ini +++ b/app/test-dma-perf/config.ini @@ -9,6 +9,8 @@ ; "buf_size" denotes the memory size of a single operation. ; "dma_ring_size" denotes the dma ring buffer size. It should be must be a power of two, and between ; 64 and 4096. +; "dma_ptrs_src" denotes number of source segments. +; "dma_ptrs_dst" denotes number of destination segments. ; "kick_batch" denotes the dma operation batch size, and should be greater than 1 normally. ; The format for variables is variable=first,last,increment,ADD|MUL. @@ -69,6 +71,21 @@ lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3 eal_args=--in-memory --file-prefix=test [case2] +type=DMA_MEM_COPY +mem_size=10 +buf_size=64,8192,2,MUL +dma_ring_size=1024 +dma_ptrs_src=4 +dma_ptrs_dst=1 +kick_batch=32 +src_numa_node=0 +dst_numa_node=0 +cache_flush=0 +test_seconds=2 +lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3 +eal_args=--in-memory --file-prefix=test + +[case3] skip=1 type=DMA_MEM_COPY direction=2 @@ -88,7 +105,7 @@ test_seconds=2 lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3 eal_args=--in-memory --file-prefix=test -[case3] +[case4] type=CPU_MEM_COPY mem_size=10 buf_size=64,8192,2,MUL diff --git a/app/test-dma-perf/main.c b/app/test-dma-perf/main.c index 3b79694137..36c9594f8c 100644 --- a/app/test-dma-perf/main.c +++ b/app/test-dma-perf/main.c @@ -94,10 +94,8 @@ run_test_case(struct test_configure *case_cfg) switch (case_cfg->test_type) { case TEST_TYPE_DMA_MEM_COPY: - ret = mem_copy_benchmark(case_cfg, true); - break; case TEST_TYPE_CPU_MEM_COPY: - ret = mem_copy_benchmark(case_cfg, false); + ret = mem_copy_benchmark(case_cfg); break; default: printf("Unknown test type. %s\n", case_cfg->test_type_str); @@ -327,7 +325,8 @@ load_configs(const char *path) const char *case_type; const char *transfer_dir; const char *lcore_dma; - const char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str; + const char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str, + *src_ptrs_str, *dst_ptrs_str; const char *skip; const char *raddr, *scoreid, *dcoreid, *vfid, *pfid; int args_nr, nb_vp; @@ -442,6 +441,7 @@ load_configs(const char *path) test_case->dcoreid = (uint8_t)atoi(dcoreid); } + test_case->is_dma = is_dma; test_case->src_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile, section_name, "src_numa_node")); test_case->dst_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile, @@ -476,6 +476,32 @@ load_configs(const char *path) } else if (args_nr == 4) nb_vp++; + src_ptrs_str = rte_cfgfile_get_entry(cfgfile, section_name, + "dma_ptrs_src"); + if (src_ptrs_str != NULL) { + test_case->src_ptrs = (int)atoi(rte_cfgfile_get_entry(cfgfile, + section_name, "dma_ptrs_src")); + } + + dst_ptrs_str = rte_cfgfile_get_entry(cfgfile, section_name, + "dma_ptrs_dst"); + if (dst_ptrs_str != NULL) { + test_case->dst_ptrs = (int)atoi(rte_cfgfile_get_entry(cfgfile, + section_name, "dma_ptrs_dst")); + } + + if ((src_ptrs_str != NULL && dst_ptrs_str == NULL) || + (src_ptrs_str == NULL && dst_ptrs_str != NULL)) { + printf("parse dma_ptrs_src, dma_ptrs_dst error in case %d.\n", + i + 1); + test_case->is_valid = false; + continue; + } else if (src_ptrs_str != NULL && dst_ptrs_str != NULL) { + test_case->is_sg = true; + } else { + test_case->is_sg = false; + } + kick_batch_str = rte_cfgfile_get_entry(cfgfile, section_name, "kick_batch"); args_nr = parse_entry(kick_batch_str, &test_case->kick_batch); if (args_nr < 0) { diff --git a/app/test-dma-perf/main.h b/app/test-dma-perf/main.h index 3d75edd1de..56e0c77e25 100644 --- a/app/test-dma-perf/main.h +++ b/app/test-dma-perf/main.h @@ -49,11 +49,14 @@ struct test_configure { uint16_t dst_numa_node; uint16_t opcode; bool is_dma; + bool is_sg; struct lcore_dma_map_t lcore_dma_map; struct test_configure_entry mem_size; struct test_configure_entry buf_size; struct test_configure_entry ring_size; struct test_configure_entry kick_batch; + uint8_t src_ptrs; + uint8_t dst_ptrs; uint8_t cache_flush; uint32_t nr_buf; uint16_t test_secs; @@ -66,6 +69,6 @@ struct test_configure { uint64_t raddr; }; -int mem_copy_benchmark(struct test_configure *cfg, bool is_dma); +int mem_copy_benchmark(struct test_configure *cfg); #endif /* MAIN_H */