From patchwork Tue Oct 17 18:53:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Prakash Shukla X-Patchwork-Id: 132803 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BB3C04318F; Tue, 17 Oct 2023 20:54:14 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AC37D40A8B; Tue, 17 Oct 2023 20:54:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0835140279 for ; Tue, 17 Oct 2023 20:54:12 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39HGHr5G027265; Tue, 17 Oct 2023 11:54:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ScKI4MQ3y0lwSRG5b2LfyaM0IIqdCI0K/WdcsGr9Jfk=; b=gma7KTxyf09Zh1n9M3lGfGHQZwif3FucS0j4sVHZC6aBAF1xN3U1yI03xbGWJZ3fcXD+ zVJNO2lfNhwgmqxGLf9XVMfQoYCdAzBOk+sUXAnbJm4IQj9NlbmwKBV9c+BmwRoPDjNo e4C6pbz+49iOkT+L3kAITrKElV/kqc3nSFrR7FjQVRhT+XY4CVbORqCbCYfRIJBEH/cd 4AwpSVb7RgZut//DIL95f6wZvU9Zsrk9ciZFG28+AkYT2XTuwZMvpCecy052p/YYpRZQ yzmuftA13NbT+8bbApHzk0dmWIhVTwKtN1tku+LoL+icuwtaf66KkAzL5FigNTCPGT7T 9g== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tsmj533b8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 17 Oct 2023 11:54:11 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 17 Oct 2023 11:54:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 17 Oct 2023 11:54:09 -0700 Received: from localhost.localdomain (unknown [10.28.36.157]) by maili.marvell.com (Postfix) with ESMTP id 974585B6942; Tue, 17 Oct 2023 11:54:05 -0700 (PDT) From: Amit Prakash Shukla To: Vamsi Attunuru CC: , , , , , , , , , , , , , Amit Prakash Shukla Subject: [PATCH v2] dma/cnxk: offload source buffer free Date: Wed, 18 Oct 2023 00:23:56 +0530 Message-ID: <20231017185356.2606580-1-amitprakashs@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230907082443.1002665-1-amitprakashs@marvell.com> References: <20230907082443.1002665-1-amitprakashs@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 8vrSQuZG-bTr1t6u-i-Lr0iPQz-KQqS_ X-Proofpoint-GUID: 8vrSQuZG-bTr1t6u-i-Lr0iPQz-KQqS_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-17_03,2023-10-17_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added support in driver, to offload source buffer free to hardware on completion of DMA transfer. Signed-off-by: Amit Prakash Shukla Acked-by: Vamsi Attunuru --- v2: - Patch rebased. v1: - Driver implementation from RFC. drivers/dma/cnxk/cnxk_dmadev.c | 48 +++++++++++++++++++++++++++---- drivers/dma/cnxk/cnxk_dmadev_fp.c | 8 +++--- 2 files changed, 46 insertions(+), 10 deletions(-) diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c index 26680edfde..1e7f49792c 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.c +++ b/drivers/dma/cnxk/cnxk_dmadev.c @@ -16,7 +16,8 @@ cnxk_dmadev_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *dev_inf dev_info->nb_vchans = dpivf->num_vchans; dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM | RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM | RTE_DMA_CAPA_DEV_TO_DEV | - RTE_DMA_CAPA_OPS_COPY | RTE_DMA_CAPA_OPS_COPY_SG; + RTE_DMA_CAPA_OPS_COPY | RTE_DMA_CAPA_OPS_COPY_SG | + RTE_DMA_CAPA_M2D_AUTO_FREE; dev_info->max_desc = CNXK_DPI_MAX_DESC; dev_info->min_desc = CNXK_DPI_MIN_DESC; dev_info->max_sges = CNXK_DPI_MAX_POINTER; @@ -115,9 +116,26 @@ cnxk_dmadev_configure(struct rte_dma_dev *dev, const struct rte_dma_conf *conf, return 0; } -static void +static int +dmadev_src_buf_aura_get(struct rte_mempool *sb_mp, const char *mp_ops_name) +{ + struct rte_mempool_ops *ops; + + if (sb_mp == NULL) + return 0; + + ops = rte_mempool_get_ops(sb_mp->ops_index); + if (strcmp(ops->name, mp_ops_name) != 0) + return -EINVAL; + + return roc_npa_aura_handle_to_aura(sb_mp->pool_id); +} + +static int cn9k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vchan_conf *conf) { + int aura; + header->cn9k.pt = DPI_HDR_PT_ZBW_CA; switch (conf->direction) { @@ -140,6 +158,11 @@ cn9k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vch header->cn9k.func = conf->dst_port.pcie.pfid << 12; header->cn9k.func |= conf->dst_port.pcie.vfid; } + aura = dmadev_src_buf_aura_get(conf->auto_free.m2d.pool, "cn9k_mempool_ops"); + if (aura < 0) + return aura; + header->cn9k.aura = aura; + header->cn9k.ii = 1; break; case RTE_DMA_DIR_MEM_TO_MEM: header->cn9k.xtype = DPI_XTYPE_INTERNAL_ONLY; @@ -153,11 +176,15 @@ cn9k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vch header->cn9k.fport = conf->dst_port.pcie.coreid; header->cn9k.pvfe = 0; }; + + return 0; } -static void +static int cn10k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vchan_conf *conf) { + int aura; + header->cn10k.pt = DPI_HDR_PT_ZBW_CA; switch (conf->direction) { @@ -180,6 +207,10 @@ cn10k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vc header->cn10k.func = conf->dst_port.pcie.pfid << 12; header->cn10k.func |= conf->dst_port.pcie.vfid; } + aura = dmadev_src_buf_aura_get(conf->auto_free.m2d.pool, "cn10k_mempool_ops"); + if (aura < 0) + return aura; + header->cn10k.aura = aura; break; case RTE_DMA_DIR_MEM_TO_MEM: header->cn10k.xtype = DPI_XTYPE_INTERNAL_ONLY; @@ -193,6 +224,8 @@ cn10k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vc header->cn10k.fport = conf->dst_port.pcie.coreid; header->cn10k.pvfe = 0; }; + + return 0; } static int @@ -204,16 +237,19 @@ cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, union cnxk_dpi_instr_cmd *header; uint16_t max_desc; uint32_t size; - int i; + int i, ret; RTE_SET_USED(conf_sz); header = (union cnxk_dpi_instr_cmd *)&dpi_conf->cmd.u; if (dpivf->is_cn10k) - cn10k_dmadev_setup_hdr(header, conf); + ret = cn10k_dmadev_setup_hdr(header, conf); else - cn9k_dmadev_setup_hdr(header, conf); + ret = cn9k_dmadev_setup_hdr(header, conf); + + if (ret) + return ret; /* Free up descriptor memory before allocating. */ cnxk_dmadev_vchan_free(dpivf, vchan); diff --git a/drivers/dma/cnxk/cnxk_dmadev_fp.c b/drivers/dma/cnxk/cnxk_dmadev_fp.c index 16d7b5426b..95df19a2db 100644 --- a/drivers/dma/cnxk/cnxk_dmadev_fp.c +++ b/drivers/dma/cnxk/cnxk_dmadev_fp.c @@ -252,7 +252,7 @@ cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, rte_iova_t d CNXK_DPI_STRM_INC(dpi_conf->c_desc, tail); cmd[0] = (1UL << 54) | (1UL << 48); - cmd[1] = dpi_conf->cmd.u; + cmd[1] = dpi_conf->cmd.u | ((flags & RTE_DMA_OP_FLAG_AUTO_FREE) << 37); cmd[2] = (uint64_t)comp_ptr; cmd[4] = length; cmd[6] = length; @@ -308,7 +308,7 @@ cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge comp_ptr = dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail]; CNXK_DPI_STRM_INC(dpi_conf->c_desc, tail); - hdr[1] = dpi_conf->cmd.u; + hdr[1] = dpi_conf->cmd.u | ((flags & RTE_DMA_OP_FLAG_AUTO_FREE) << 37); hdr[2] = (uint64_t)comp_ptr; /* @@ -365,7 +365,7 @@ cn10k_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, rte_iova_t cmd[0] = dpi_conf->cmd.u | (1U << 6) | 1U; cmd[1] = (uint64_t)comp_ptr; - cmd[2] = 0; + cmd[2] = (1UL << 47) | ((flags & RTE_DMA_OP_FLAG_AUTO_FREE) << 43); cmd[4] = length; cmd[5] = src; cmd[6] = length; @@ -412,7 +412,7 @@ cn10k_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge hdr[0] = dpi_conf->cmd.u | (nb_dst << 6) | nb_src; hdr[1] = (uint64_t)comp_ptr; - hdr[2] = 0; + hdr[2] = (1UL << 47) | ((flags & RTE_DMA_OP_FLAG_AUTO_FREE) << 43); rc = __dpi_queue_write_sg(dpivf, hdr, src, dst, nb_src, nb_dst); if (unlikely(rc)) {