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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS2PEPF0000343C.mail.protection.outlook.com (10.167.18.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.14 via Frontend Transport; Mon, 9 Oct 2023 16:36:46 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 9 Oct 2023 09:36:36 -0700 Received: from pegasus01.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 9 Oct 2023 09:36:34 -0700 From: Alexander Kozyrev To: CC: , , , , , Subject: [PATCH 1/5] net/mlx5: add support for ptype match in hardware steering Date: Mon, 9 Oct 2023 19:36:13 +0300 Message-ID: <20231009163617.3999365-2-akozyrev@nvidia.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20231009163617.3999365-1-akozyrev@nvidia.com> References: <20231009163617.3999365-1-akozyrev@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343C:EE_|CY5PR12MB6155:EE_ X-MS-Office365-Filtering-Correlation-Id: 29b94ad3-bd50-4d93-d156-08dbc8e5ee1f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2023 16:36:46.9779 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29b94ad3-bd50-4d93-d156-08dbc8e5ee1f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6155 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The packet type matching provides quick way of finding out L2/L3/L4 protocols in a given packet. That helps with optimized flow rules matching, eliminating the need of stacking all the packet headers in the matching criteria. Signed-off-by: Alexander Kozyrev --- drivers/net/mlx5/hws/mlx5dr_definer.c | 170 ++++++++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_definer.h | 8 ++ drivers/net/mlx5/mlx5_flow.h | 3 + drivers/net/mlx5/mlx5_flow_hw.c | 1 + 4 files changed, 182 insertions(+) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 88f22e7f70..e3f4a3c0a8 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -16,11 +16,14 @@ #define STE_NO_VLAN 0x0 #define STE_SVLAN 0x1 #define STE_CVLAN 0x2 +#define STE_NO_L3 0x0 #define STE_IPV4 0x1 #define STE_IPV6 0x2 +#define STE_NO_L4 0x0 #define STE_TCP 0x1 #define STE_UDP 0x2 #define STE_ICMP 0x3 +#define STE_ESP 0x3 #define MLX5DR_DEFINER_QUOTA_BLOCK 0 #define MLX5DR_DEFINER_QUOTA_PASS 2 @@ -276,6 +279,88 @@ mlx5dr_definer_conntrack_tag(struct mlx5dr_definer_fc *fc, DR_SET(tag, reg_value, fc->byte_off, fc->bit_off, fc->bit_mask); } +static void +mlx5dr_definer_ptype_l2_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + bool inner = (fc->fname == MLX5DR_DEFINER_FNAME_PTYPE_L2_I); + const struct rte_flow_item_ptype *v = item_spec; + uint32_t packet_type = v->packet_type & + (inner ? RTE_PTYPE_INNER_L2_MASK : RTE_PTYPE_L2_MASK); + uint8_t l2_type = STE_NO_VLAN; + + if (packet_type == (inner ? RTE_PTYPE_INNER_L2_ETHER : RTE_PTYPE_L2_ETHER)) + l2_type = STE_NO_VLAN; + else if (packet_type == (inner ? RTE_PTYPE_INNER_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER_VLAN)) + l2_type = STE_CVLAN; + else if (packet_type == (inner ? RTE_PTYPE_INNER_L2_ETHER_QINQ : RTE_PTYPE_L2_ETHER_QINQ)) + l2_type = STE_SVLAN; + + DR_SET(tag, l2_type, fc->byte_off, fc->bit_off, fc->bit_mask); +} + +static void +mlx5dr_definer_ptype_l3_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + bool inner = (fc->fname == MLX5DR_DEFINER_FNAME_PTYPE_L3_I); + const struct rte_flow_item_ptype *v = item_spec; + uint32_t packet_type = v->packet_type & + (inner ? RTE_PTYPE_INNER_L3_MASK : RTE_PTYPE_L3_MASK); + uint8_t l3_type = STE_NO_L3; + + if (packet_type == (inner ? RTE_PTYPE_INNER_L3_IPV4 : RTE_PTYPE_L3_IPV4)) + l3_type = STE_IPV4; + else if (packet_type == (inner ? RTE_PTYPE_INNER_L3_IPV6 : RTE_PTYPE_L3_IPV6)) + l3_type = STE_IPV6; + + DR_SET(tag, l3_type, fc->byte_off, fc->bit_off, fc->bit_mask); +} + +static void +mlx5dr_definer_ptype_l4_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + bool inner = (fc->fname == MLX5DR_DEFINER_FNAME_PTYPE_L4_I); + const struct rte_flow_item_ptype *v = item_spec; + uint32_t packet_type = v->packet_type & + (inner ? RTE_PTYPE_INNER_L4_MASK : RTE_PTYPE_L4_MASK); + uint8_t l4_type = STE_NO_L4; + + if (packet_type == (inner ? RTE_PTYPE_INNER_L4_TCP : RTE_PTYPE_L4_TCP)) + l4_type = STE_TCP; + else if (packet_type == (inner ? RTE_PTYPE_INNER_L4_UDP : RTE_PTYPE_L4_UDP)) + l4_type = STE_UDP; + else if (packet_type == (inner ? RTE_PTYPE_INNER_L4_ESP : RTE_PTYPE_L4_ESP)) + l4_type = STE_ESP; + + DR_SET(tag, l4_type, fc->byte_off, fc->bit_off, fc->bit_mask); +} + +static void +mlx5dr_definer_ptype_l4_ext_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + bool inner = (fc->fname == MLX5DR_DEFINER_FNAME_PTYPE_L4_EXT_I); + const struct rte_flow_item_ptype *v = item_spec; + uint32_t packet_type = v->packet_type & + (inner ? RTE_PTYPE_INNER_L4_MASK : RTE_PTYPE_L4_MASK); + uint8_t l4_type = STE_NO_L4; + + if (packet_type == (inner ? RTE_PTYPE_INNER_L4_TCP : RTE_PTYPE_L4_TCP)) + l4_type = STE_TCP; + else if (packet_type == (inner ? RTE_PTYPE_INNER_L4_UDP : RTE_PTYPE_L4_UDP)) + l4_type = STE_UDP; + else if (packet_type == (inner ? RTE_PTYPE_INNER_L4_ICMP : RTE_PTYPE_L4_ICMP)) + l4_type = STE_ICMP; + + DR_SET(tag, l4_type, fc->byte_off, fc->bit_off, fc->bit_mask); +} + static void mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc, const void *item_spec, @@ -1692,6 +1777,87 @@ mlx5dr_definer_conv_item_gre_key(struct mlx5dr_definer_conv_data *cd, return 0; } +static int +mlx5dr_definer_conv_item_ptype(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_ptype *m = item->mask; + struct mlx5dr_definer_fc *fc; + + if (!m) + return 0; + + if (!(m->packet_type & + (RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK | RTE_PTYPE_L4_MASK | + RTE_PTYPE_INNER_L2_MASK | RTE_PTYPE_INNER_L3_MASK | RTE_PTYPE_INNER_L4_MASK))) { + rte_errno = ENOTSUP; + return rte_errno; + } + + if (m->packet_type & RTE_PTYPE_L2_MASK) { + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L2, false)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l2_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, first_vlan_qualifier, false); + } + + if (m->packet_type & RTE_PTYPE_INNER_L2_MASK) { + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L2, true)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l2_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, first_vlan_qualifier, true); + } + + if (m->packet_type & RTE_PTYPE_L3_MASK) { + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L3, false)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l3_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l3_type, false); + } + + if (m->packet_type & RTE_PTYPE_INNER_L3_MASK) { + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L3, true)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l3_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l3_type, true); + } + + if (m->packet_type & RTE_PTYPE_L4_MASK) { + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, false)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l4_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l4_type_bwc, false); + + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4_EXT, false)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l4_ext_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l4_type, false); + } + + if (m->packet_type & RTE_PTYPE_INNER_L4_MASK) { + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, true)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l4_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l4_type_bwc, true); + + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4_EXT, true)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l4_ext_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l4_type, true); + } + + return 0; +} + static int mlx5dr_definer_conv_item_integrity(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, @@ -2308,6 +2474,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, ret = mlx5dr_definer_conv_item_ib_l4(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_IB_BTH; break; + case RTE_FLOW_ITEM_TYPE_PTYPE: + ret = mlx5dr_definer_conv_item_ptype(&cd, items, i); + item_flags |= MLX5_FLOW_ITEM_PTYPE; + break; default: DR_LOG(ERR, "Unsupported item type %d", items->type); rte_errno = ENOTSUP; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 6b645f4cf0..6b02161e02 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -136,6 +136,14 @@ enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_OKS2_MPLS4_I, MLX5DR_DEFINER_FNAME_IB_L4_OPCODE, MLX5DR_DEFINER_FNAME_IB_L4_QPN, + MLX5DR_DEFINER_FNAME_PTYPE_L2_O, + MLX5DR_DEFINER_FNAME_PTYPE_L2_I, + MLX5DR_DEFINER_FNAME_PTYPE_L3_O, + MLX5DR_DEFINER_FNAME_PTYPE_L3_I, + MLX5DR_DEFINER_FNAME_PTYPE_L4_O, + MLX5DR_DEFINER_FNAME_PTYPE_L4_I, + MLX5DR_DEFINER_FNAME_PTYPE_L4_EXT_O, + MLX5DR_DEFINER_FNAME_PTYPE_L4_EXT_I, MLX5DR_DEFINER_FNAME_MAX, }; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 6beac3902c..c670bf72bc 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -233,6 +233,9 @@ enum mlx5_feature_name { /* IB BTH ITEM. */ #define MLX5_FLOW_ITEM_IB_BTH (1ull << 51) +/* PTYPE ITEM */ +#define MLX5_FLOW_ITEM_PTYPE (1ull << 52) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index b7853d3379..587d55148e 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -5392,6 +5392,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_ESP: case RTE_FLOW_ITEM_TYPE_FLEX: case RTE_FLOW_ITEM_TYPE_IB_BTH: + case RTE_FLOW_ITEM_TYPE_PTYPE: break; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2023 16:36:50.6902 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a9b5965-e1c7-491c-446e-08dbc8e5f056 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7631 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Expand packet type matching with support of the Fragmented IP (Internet Protocol) packet type. Signed-off-by: Alexander Kozyrev --- drivers/net/mlx5/hws/mlx5dr_definer.c | 74 +++++++++++++++++++-------- drivers/net/mlx5/hws/mlx5dr_definer.h | 2 + 2 files changed, 56 insertions(+), 20 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index e3f4a3c0a8..b2c0655790 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -361,6 +361,19 @@ mlx5dr_definer_ptype_l4_ext_set(struct mlx5dr_definer_fc *fc, DR_SET(tag, l4_type, fc->byte_off, fc->bit_off, fc->bit_mask); } +static void +mlx5dr_definer_ptype_frag_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + bool inner = (fc->fname == MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I); + const struct rte_flow_item_ptype *v = item_spec; + uint32_t packet_type = v->packet_type & + (inner ? RTE_PTYPE_INNER_L4_FRAG : RTE_PTYPE_L4_FRAG); + + DR_SET(tag, !!packet_type, fc->byte_off, fc->bit_off, fc->bit_mask); +} + static void mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc, const void *item_spec, @@ -1828,31 +1841,52 @@ mlx5dr_definer_conv_item_ptype(struct mlx5dr_definer_conv_data *cd, } if (m->packet_type & RTE_PTYPE_L4_MASK) { - fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, false)]; - fc->item_idx = item_idx; - fc->tag_set = &mlx5dr_definer_ptype_l4_set; - fc->tag_mask_set = &mlx5dr_definer_ones_set; - DR_CALC_SET(fc, eth_l2, l4_type_bwc, false); + /* + * Fragmented IP (Internet Protocol) packet type. + * Cannot be combined with Layer 4 Types (TCP/UDP). + * The exact value must be specified in the mask. + */ + if (m->packet_type == RTE_PTYPE_L4_FRAG) { + fc = &cd->fc[DR_CALC_FNAME(PTYPE_FRAG, false)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_frag_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, ip_fragmented, false); + } else { + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, false)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l4_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l4_type_bwc, false); - fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4_EXT, false)]; - fc->item_idx = item_idx; - fc->tag_set = &mlx5dr_definer_ptype_l4_ext_set; - fc->tag_mask_set = &mlx5dr_definer_ones_set; - DR_CALC_SET(fc, eth_l2, l4_type, false); + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4_EXT, false)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l4_ext_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l4_type, false); + } } if (m->packet_type & RTE_PTYPE_INNER_L4_MASK) { - fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, true)]; - fc->item_idx = item_idx; - fc->tag_set = &mlx5dr_definer_ptype_l4_set; - fc->tag_mask_set = &mlx5dr_definer_ones_set; - DR_CALC_SET(fc, eth_l2, l4_type_bwc, true); + if (m->packet_type == RTE_PTYPE_INNER_L4_FRAG) { + fc = &cd->fc[DR_CALC_FNAME(PTYPE_FRAG, true)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_frag_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, ip_fragmented, true); + } else { + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, true)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l4_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l4_type_bwc, true); - fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4_EXT, true)]; - fc->item_idx = item_idx; - fc->tag_set = &mlx5dr_definer_ptype_l4_ext_set; - fc->tag_mask_set = &mlx5dr_definer_ones_set; - DR_CALC_SET(fc, eth_l2, l4_type, true); + fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4_EXT, true)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ptype_l4_ext_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l4_type, true); + } } return 0; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 6b02161e02..e87b4108f9 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -144,6 +144,8 @@ enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_PTYPE_L4_I, MLX5DR_DEFINER_FNAME_PTYPE_L4_EXT_O, MLX5DR_DEFINER_FNAME_PTYPE_L4_EXT_I, + MLX5DR_DEFINER_FNAME_PTYPE_FRAG_O, + MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I, MLX5DR_DEFINER_FNAME_MAX, }; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2023 16:36:52.9115 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53ad1c91-94b0-4a5f-34da-08dbc8e5f1a9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7952 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Michael Baum Add limitations for ptype item support in "mlx5.rst" file. Signed-off-by: Michael Baum --- doc/guides/nics/features/mlx5.ini | 1 + doc/guides/nics/mlx5.rst | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini index c0e0b779cf..ca23355a21 100644 --- a/doc/guides/nics/features/mlx5.ini +++ b/doc/guides/nics/features/mlx5.ini @@ -85,6 +85,7 @@ mpls = Y nvgre = Y port_id = Y port_representor = Y +ptype = Y quota = Y tag = Y tcp = Y diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 7bee57d9dd..26cf310e8e 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -646,6 +646,25 @@ Limitations - When using HWS flow engine (``dv_flow_en`` = 2), only meter mark action is supported. +- Ptype: + + - Only supports HW steering (``dv_flow_en=2``). + - The ``RTE_PTYPE_L2_ETHER_TIMESYNC``, ``RTE_PTYPE_L2_ETHER_ARP``, ``RTE_PTYPE_L2_ETHER_LLDP``, + ``RTE_PTYPE_L2_ETHER_NSH``, ``RTE_PTYPE_L2_ETHER_PPPOE``, ``RTE_PTYPE_L2_ETHER_FCOE``, + ``RTE_PTYPE_L2_ETHER_MPLS``, ``RTE_PTYPE_L3_IPV4_EXT``, ``RTE_PTYPE_L3_IPV4_EXT_UNKNOWN``, + ``RTE_PTYPE_L3_IPV6_EXT``, ``RTE_PTYPE_L3_IPV6_EXT_UNKNOWN``, ``RTE_PTYPE_L4_SCTP``, + ``RTE_PTYPE_L4_NONFRAG``, ``RTE_PTYPE_L4_IGMP``, ``RTE_PTYPE_INNER_L3_IPV4_EXT``, + ``RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN``, ``RTE_PTYPE_INNER_L3_IPV6_EXT``, + ``RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN``, ``RTE_PTYPE_INNER_L4_SCTP`` and + ``RTE_PTYPE_INNER_L4_NONFRAG`` values are not supported. + Using them as a value will cause unexpected behavior. + - The ``RTE_PTYPE_TUNNEL_XXXXX`` values are not supported. Using them as a value should fail. + - Matching on both outer and inner IP fragmented is supported using ``RTE_PTYPE_L4_FRAG`` and + ``RTE_PTYPE_INNER_L4_FRAG`` values. They are not part of L4 types, so they should be provided + explicitly as mask value during pattern template creation. Providing ``RTE_PTYPE_L4_MASK`` + during pattern template creation and ``RTE_PTYPE_L4_FRAG`` during flow rule creation, + will cause unexpected behavior. + - Integrity: - Integrity offload is enabled starting from **ConnectX-6 Dx**. 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Old behavior: the "ipv4_csum_ok" checks only IPv4 checksum and "l3_ok" checks everything is ok including IPv4 checksum. New behavior: the "l3_ok" checks everything is ok excluding IPv4 checksum. This change enables matching "l3_ok" in IPv6 packets since for IPv6 packets "ipv4_csum_ok" is always miss. For SW steering the old behavior is kept as same as for L4 ok. Signed-off-by: Michael Baum --- doc/guides/nics/mlx5.rst | 19 ++++++++++++------- drivers/net/mlx5/hws/mlx5dr_definer.c | 6 ++---- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 26cf310e8e..ddec84a9bb 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -667,18 +667,23 @@ Limitations - Integrity: - - Integrity offload is enabled starting from **ConnectX-6 Dx**. - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``. - ``level`` value 0 references outer headers. - Negative integrity item verification is not supported. - - Multiple integrity items not supported in a single flow rule. - - Flow rule items supplied by application must explicitly specify network headers referred by integrity item. - For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header, - TCP or UDP, must be in the rule pattern as well:: + - With SW steering (``dv_flow_en=1``) + - Integrity offload is enabled starting from **ConnectX-6 Dx**. + - Multiple integrity items not supported in a single flow rule. + - Flow rule items supplied by application must explicitly specify network headers referred by integrity item. + For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header, + TCP or UDP, must be in the rule pattern as well:: - flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end … + flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end … - flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec l4_ok / eth / ipv4 proto is udp / end … + flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec l4_ok / eth / ipv4 proto is udp / end … + + - With HW steering (``dv_flow_en=2``) + - The ``l3_ok`` field represents all L3 checks, but nothing about whether IPv4 checksum ok. + - The ``l4_ok`` field represents all L4 checks including L4 checksum ok. - Connection tracking: diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index b2c0655790..84d15a41df 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -384,10 +384,8 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc, uint32_t ok1_bits = 0; if (v->l3_ok) - ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) | - BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) : - BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK) | - BIT(MLX5DR_DEFINER_OKS1_FIRST_IPV4_CSUM_OK); + ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) : + BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK); if (v->ipv4_csum_ok) ok1_bits |= inner ? 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2023 16:37:04.1506 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c40c1038-49a5-47aa-ef30-08dbc8e5f860 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8232 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The level field in the integrity item is not taken into account in the current implementation of hardware steering. Use this value instead of trying to find out the encapsulation level according to the protocol items involved. Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer") Signed-off-by: Alexander Kozyrev --- drivers/net/mlx5/hws/mlx5dr_definer.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 84d15a41df..b092249c0a 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -1897,7 +1897,6 @@ mlx5dr_definer_conv_item_integrity(struct mlx5dr_definer_conv_data *cd, { const struct rte_flow_item_integrity *m = item->mask; struct mlx5dr_definer_fc *fc; - bool inner = cd->tunnel; if (!m) return 0; @@ -1908,7 +1907,7 @@ mlx5dr_definer_conv_item_integrity(struct mlx5dr_definer_conv_data *cd, } if (m->l3_ok || m->ipv4_csum_ok || m->l4_ok || m->l4_csum_ok) { - fc = &cd->fc[DR_CALC_FNAME(INTEGRITY, inner)]; + fc = &cd->fc[DR_CALC_FNAME(INTEGRITY, m->level)]; fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_integrity_set; DR_CALC_SET_HDR(fc, oks1, oks1_bits); @@ -2456,8 +2455,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, break; case RTE_FLOW_ITEM_TYPE_INTEGRITY: ret = mlx5dr_definer_conv_item_integrity(&cd, items, i); - item_flags |= cd.tunnel ? MLX5_FLOW_ITEM_INNER_INTEGRITY : - MLX5_FLOW_ITEM_OUTER_INTEGRITY; + item_flags |= MLX5_FLOW_ITEM_INTEGRITY; break; case RTE_FLOW_ITEM_TYPE_CONNTRACK: ret = mlx5dr_definer_conv_item_conntrack(&cd, items, i);