From patchwork Fri Sep 22 09:37:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Marchand X-Patchwork-Id: 131829 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E152E42616; Fri, 22 Sep 2023 11:37:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EC6C24068A; Fri, 22 Sep 2023 11:37:43 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id B8B1040685 for ; Fri, 22 Sep 2023 11:37:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1695375462; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IRpfa9LTLMcERvWDvpQKsrh+yRqpHDFZyrFp1JRInqw=; b=FW1y4GuXcpab3XY1jFkHhlKoIBMGJNETYpDAgHCkHKGk2qGK8qgeRbCrhpdBfg1d+zRnaE WZGZTmjk7uyDVdmLWBk+D9UQ5vlRFekB9tjtsMvgacLo/mnhaywaGAj9HdhIU8oI+u5YzS LQMyjicsQc9PCd42KHgCz2jbdCO5zhI= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-599-fGRyghn9PRiHfr-rXfI1zw-1; Fri, 22 Sep 2023 05:37:38 -0400 X-MC-Unique: fGRyghn9PRiHfr-rXfI1zw-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 4523D101A529; Fri, 22 Sep 2023 09:37:38 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.224.128]) by smtp.corp.redhat.com (Postfix) with ESMTP id 88FDD40C2064; Fri, 22 Sep 2023 09:37:36 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: ferruh.yigit@amd.com, thomas@monjalon.net, bruce.richardson@intel.com, konstantin.v.ananyev@yandex.ru, ruifeng.wang@arm.com, zhoumin@loongson.cn, drc@linux.vnet.ibm.com, kda@semihalf.com, roretzla@linux.microsoft.com Subject: [PATCH 1/2] eal: introduce x86 processor identification Date: Fri, 22 Sep 2023 11:37:20 +0200 Message-ID: <20230922093722.2057688-2-david.marchand@redhat.com> In-Reply-To: <20230922093722.2057688-1-david.marchand@redhat.com> References: <20230922093722.2057688-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In some really specific cases, it may be needed to get a detailed information on the processor running a DPDK application for drivers to achieve better performance, or for matters that concern only them. Those information are highly arch-specific and require a specific API. Introduce a set of functions to get brand, family and model of a x86 processor. Those functions do not make sense on other arches and a driver must first check rte_cpu_is_x86() before anything else. Signed-off-by: David Marchand --- MAINTAINERS | 1 + app/test/meson.build | 1 + app/test/test_cpu.c | 37 +++++++++ lib/eal/common/eal_common_cpu.c | 141 ++++++++++++++++++++++++++++++++ lib/eal/common/eal_cpu.h | 77 +++++++++++++++++ lib/eal/common/meson.build | 1 + lib/eal/version.map | 6 ++ 7 files changed, 264 insertions(+) create mode 100644 app/test/test_cpu.c create mode 100644 lib/eal/common/eal_common_cpu.c create mode 100644 lib/eal/common/eal_cpu.h diff --git a/MAINTAINERS b/MAINTAINERS index 698608cdb2..b87d47a1e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -158,6 +158,7 @@ F: app/test/test_barrier.c F: app/test/test_bitcount.c F: app/test/test_byteorder.c F: app/test/test_common.c +F: app/test/test_cpu.c F: app/test/test_cpuflags.c F: app/test/test_cycles.c F: app/test/test_debug.c diff --git a/app/test/meson.build b/app/test/meson.build index 05bae9216d..4b37ad02fa 100644 --- a/app/test/meson.build +++ b/app/test/meson.build @@ -44,6 +44,7 @@ source_file_deps = { 'test_cmdline_string.c': [], 'test_common.c': [], 'test_compressdev.c': ['compressdev'], + 'test_cpu.c': [], 'test_cpuflags.c': [], 'test_crc.c': ['net'], 'test_cryptodev.c': test_cryptodev_deps, diff --git a/app/test/test_cpu.c b/app/test/test_cpu.c new file mode 100644 index 0000000000..40d8bd94eb --- /dev/null +++ b/app/test/test_cpu.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Red Hat, Inc. + */ + +#include +#include + +#include "eal_cpu.h" + +#include "test.h" + +static int +test_cpu(void) +{ +#ifndef RTE_ARCH_X86 + RTE_TEST_ASSERT(!rte_cpu_is_x86(), "rte_cpu_is_x86() returned true on " RTE_STR(RTE_ARCH)); +#else + const char *vendor; + + RTE_TEST_ASSERT(rte_cpu_is_x86(), "rte_cpu_is_x86() returned false"); + + if (rte_cpu_x86_is_amd()) + vendor = "AMD"; + else if (rte_cpu_x86_is_intel()) + vendor = "Intel"; + else + vendor = "unknown"; + + printf("The processor running this program is a x86 %s processor, brand=0x%" + PRIx8", family=0x%"PRIx8", model=0x%"PRIx8"\n", vendor, rte_cpu_x86_brand(), + rte_cpu_x86_family(), rte_cpu_x86_model()); +#endif + + return TEST_SUCCESS; +} + +REGISTER_FAST_TEST(cpu_autotest, true, true, test_cpu); diff --git a/lib/eal/common/eal_common_cpu.c b/lib/eal/common/eal_common_cpu.c new file mode 100644 index 0000000000..18cdb27f75 --- /dev/null +++ b/lib/eal/common/eal_common_cpu.c @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Red Hat, Inc. + */ + +#include + +#include "eal_cpu.h" + +#ifdef RTE_ARCH_X86 +#ifndef RTE_TOOLCHAIN_MSVC +#include +#endif + +static void +x86_cpuid(uint32_t leaf, uint32_t subleaf, uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) +{ + uint32_t regs[4] = { 0 }; + +#ifdef RTE_TOOLCHAIN_MSVC + __cpuidex(regs, leaf, subleaf); +#else + __cpuid_count(leaf, subleaf, regs[0], regs[1], regs[2], regs[3]); +#endif + + *eax = regs[0]; + *ebx = regs[1]; + *ecx = regs[2]; + *edx = regs[3]; +} +#endif /* RTE_ARCH_X86 */ + +bool +rte_cpu_is_x86(void) +{ +#ifndef RTE_ARCH_X86 + return false; +#else + return true; +#endif +} + +bool +rte_cpu_x86_is_amd(void) +{ +#ifndef RTE_ARCH_X86 + rte_panic("Calling %s does not make sense on %s architecture.\n", + __func__, RTE_STR(RTE_ARCH)); +#else + uint32_t eax, ebx, ecx, edx; + + x86_cpuid(0x0, 0x0, &eax, &ebx, &ecx, &edx); + /* ascii_to_little_endian("Auth enti cAMD") */ + return ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65; +#endif +} + +bool +rte_cpu_x86_is_intel(void) +{ +#ifndef RTE_ARCH_X86 + rte_panic("Calling %s does not make sense on %s architecture.\n", + __func__, RTE_STR(RTE_ARCH)); +#else + uint32_t eax, ebx, ecx, edx; + + x86_cpuid(0x0, 0x0, &eax, &ebx, &ecx, &edx); + /* ascii_to_little_endian("Genu ineI ntel") */ + return ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69; +#endif +} + +uint8_t +rte_cpu_x86_brand(void) +{ +#ifndef RTE_ARCH_X86 + rte_panic("Calling %s does not make sense on %s architecture.\n", + __func__, RTE_STR(RTE_ARCH)); +#else + uint32_t eax, ebx, ecx, edx; + uint8_t brand = 0; + + x86_cpuid(0x0, 0x0, &eax, &ebx, &ecx, &edx); + if (eax >= 1) { + x86_cpuid(0x1, 0x0, &eax, &ebx, &ecx, &edx); + brand = ebx & 0xff; + } + + return brand; +#endif +} + +uint8_t +rte_cpu_x86_family(void) +{ +#ifndef RTE_ARCH_X86 + rte_panic("Calling %s does not make sense on %s architecture.\n", + __func__, RTE_STR(RTE_ARCH)); +#else + uint32_t eax, ebx, ecx, edx; + uint8_t family = 0; + + x86_cpuid(0x0, 0x0, &eax, &ebx, &ecx, &edx); + if (eax >= 1) { + uint8_t family_id; + + x86_cpuid(0x1, 0x0, &eax, &ebx, &ecx, &edx); + family_id = (eax >> 8) & 0x0f; + family = family_id; + if (family_id == 0xf) + family += (eax >> 20) & 0xff; + } + + return family; +#endif +} + +uint8_t +rte_cpu_x86_model(void) +{ +#ifndef RTE_ARCH_X86 + rte_panic("Calling %s does not make sense on %s architecture.\n", + __func__, RTE_STR(RTE_ARCH)); +#else + uint32_t eax, ebx, ecx, edx; + uint8_t model = 0; + + x86_cpuid(0x0, 0x0, &eax, &ebx, &ecx, &edx); + if (eax >= 1) { + uint8_t family_id; + + x86_cpuid(0x1, 0x0, &eax, &ebx, &ecx, &edx); + family_id = (eax >> 8) & 0x0f; + model = (eax >> 4) & 0x0f; + if (family_id == 0x6 || family_id == 0xf) + model += (eax >> 12) & 0xf0; + } + + return model; +#endif +} diff --git a/lib/eal/common/eal_cpu.h b/lib/eal/common/eal_cpu.h new file mode 100644 index 0000000000..26d8e06bf0 --- /dev/null +++ b/lib/eal/common/eal_cpu.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Red Hat, Inc. + */ + +#ifndef EAL_CPU_H +#define EAL_CPU_H + +#include +#include + +#include + +/** + * Returns whether the processor running this program is a x86 one. + * + * @return + * true or false + */ +__rte_internal +bool rte_cpu_is_x86(void); + +/** + * Returns whether the processor running this program is a AMD x86 one. + * + * Note: calling this function only makes sense if rte_cpu_is_x86() == true. + * + * @return + * true or false + */ +__rte_internal +bool rte_cpu_x86_is_amd(void); + +/** + * Returns whether the processor running this program is a Intel x86 one. + * + * Note: calling this function only makes sense if rte_cpu_is_x86() == true. + * + * @return + * true or false + */ +__rte_internal +bool rte_cpu_x86_is_intel(void); + +/** + * Returns the processor brand (as returned by CPUID). + * + * Note: calling this function only makes sense if rte_cpu_is_x86() == true. + * + * @return + * x86 processor brand + */ +__rte_internal +uint8_t rte_cpu_x86_brand(void); + +/** + * Returns the processor family (as returned by CPUID). + * + * Note: calling this function only makes sense if rte_cpu_is_x86() == true. + * + * @return + * x86 processor family + */ +__rte_internal +uint8_t rte_cpu_x86_family(void); + +/** + * Returns the processor model (as returned by CPUID). + * + * Note: calling this function only makes sense if rte_cpu_is_x86() == true. + * + * @return + * x86 processor model + */ +__rte_internal +uint8_t rte_cpu_x86_model(void); + +#endif /* EAL_CPU_H */ diff --git a/lib/eal/common/meson.build b/lib/eal/common/meson.build index 22a626ba6f..bef5b2575b 100644 --- a/lib/eal/common/meson.build +++ b/lib/eal/common/meson.build @@ -9,6 +9,7 @@ sources += files( 'eal_common_bus.c', 'eal_common_class.c', 'eal_common_config.c', + 'eal_common_cpu.c', 'eal_common_debug.c', 'eal_common_dev.c', 'eal_common_devargs.c', diff --git a/lib/eal/version.map b/lib/eal/version.map index 7940431e5a..62632202c5 100644 --- a/lib/eal/version.map +++ b/lib/eal/version.map @@ -424,6 +424,12 @@ INTERNAL { rte_bus_register; rte_bus_unregister; + rte_cpu_is_x86; + rte_cpu_x86_brand; + rte_cpu_x86_family; + rte_cpu_x86_is_amd; + rte_cpu_x86_is_intel; + rte_cpu_x86_model; rte_eal_get_baseaddr; rte_eal_parse_coremask; rte_firmware_read; From patchwork Fri Sep 22 09:37:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Marchand X-Patchwork-Id: 131830 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2FE8A42616; Fri, 22 Sep 2023 11:37:50 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 21B60406B8; Fri, 22 Sep 2023 11:37:50 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mails.dpdk.org (Postfix) with ESMTP id 99AED402DC for ; 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Fri, 22 Sep 2023 09:37:42 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.224.128]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2B21210005D4; Fri, 22 Sep 2023 09:37:40 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: ferruh.yigit@amd.com, thomas@monjalon.net, bruce.richardson@intel.com, konstantin.v.ananyev@yandex.ru, ruifeng.wang@arm.com, zhoumin@loongson.cn, drc@linux.vnet.ibm.com, kda@semihalf.com, roretzla@linux.microsoft.com, Matan Azrad , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH 2/2] common/mlx5: use EAL x86 processor identification Date: Fri, 22 Sep 2023 11:37:21 +0200 Message-ID: <20230922093722.2057688-3-david.marchand@redhat.com> In-Reply-To: <20230922093722.2057688-1-david.marchand@redhat.com> References: <20230922093722.2057688-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Rather than use an ugly asm thing, use newly introduced EAL x86 API. Signed-off-by: David Marchand --- drivers/common/mlx5/mlx5_common.c | 81 ++++++++----------------------- 1 file changed, 21 insertions(+), 60 deletions(-) diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c index 0ad14a48c7..99adcd960e 100644 --- a/drivers/common/mlx5/mlx5_common.c +++ b/drivers/common/mlx5/mlx5_common.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -52,29 +53,6 @@ uint8_t haswell_broadwell_cpu; */ #define MLX5_SQ_DB_NC "sq_db_nc" -/* In case this is an x86_64 intel processor to check if - * we should use relaxed ordering. - */ -#ifdef RTE_ARCH_X86_64 -/** - * This function returns processor identification and feature information - * into the registers. - * - * @param eax, ebx, ecx, edx - * Pointers to the registers that will hold cpu information. - * @param level - * The main category of information returned. - */ -static inline void mlx5_cpu_id(unsigned int level, - unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) -{ - __asm__("cpuid\n\t" - : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) - : "0" (level)); -} -#endif - RTE_LOG_REGISTER_DEFAULT(mlx5_common_logtype, NOTICE) /* Head of list of drivers. */ @@ -1246,46 +1224,29 @@ mlx5_common_init(void) RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG) { #ifdef RTE_ARCH_X86_64 - unsigned int broadwell_models[4] = {0x3d, 0x47, 0x4F, 0x56}; - unsigned int haswell_models[4] = {0x3c, 0x3f, 0x45, 0x46}; - unsigned int i, model, family, brand_id, vendor; - unsigned int signature_intel_ebx = 0x756e6547; - unsigned int extended_model; - unsigned int eax = 0; - unsigned int ebx = 0; - unsigned int ecx = 0; - unsigned int edx = 0; - int max_level; - - mlx5_cpu_id(0, &eax, &ebx, &ecx, &edx); - vendor = ebx; - max_level = eax; - if (max_level < 1) { - haswell_broadwell_cpu = 0; + uint8_t broadwell_models[] = {0x3d, 0x47, 0x4f, 0x56}; + uint8_t haswell_models[] = {0x3c, 0x3f, 0x45, 0x46}; + unsigned int i; + uint8_t model; + + if (!rte_cpu_is_x86() || !rte_cpu_x86_is_intel() || rte_cpu_x86_brand() != 0x0 || + rte_cpu_x86_family() != 0x6) + goto out; + + model = rte_cpu_x86_model(); + for (i = 0; i < RTE_DIM(broadwell_models); i++) { + if (model != broadwell_models[i]) + continue; + haswell_broadwell_cpu = 1; return; } - mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx); - model = (eax >> 4) & 0x0f; - family = (eax >> 8) & 0x0f; - brand_id = ebx & 0xff; - extended_model = (eax >> 12) & 0xf0; - /* Check if the processor is Haswell or Broadwell */ - if (vendor == signature_intel_ebx) { - if (family == 0x06) - model += extended_model; - if (brand_id == 0 && family == 0x6) { - for (i = 0; i < RTE_DIM(broadwell_models); i++) - if (model == broadwell_models[i]) { - haswell_broadwell_cpu = 1; - return; - } - for (i = 0; i < RTE_DIM(haswell_models); i++) - if (model == haswell_models[i]) { - haswell_broadwell_cpu = 1; - return; - } - } + for (i = 0; i < RTE_DIM(haswell_models); i++) { + if (model != haswell_models[i]) + continue; + haswell_broadwell_cpu = 1; + return; } +out: #endif haswell_broadwell_cpu = 0; }