From patchwork Wed Sep 20 06:22:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131658 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DC2A2425E9; Wed, 20 Sep 2023 08:22:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA51F406FF; Wed, 20 Sep 2023 08:22:19 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 8CB6E4067E for ; Wed, 20 Sep 2023 08:22:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695190937; x=1726726937; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m+IMsHG98LbjDQPwKiHHKbmvUyW+mX/3lTAY3rMs61M=; b=n9ZVDQ1LlMIQqL9+N33J63U5utQsa5YDo9B5giAZQdlNxILr+WmipcxD 5QdjDgB3p6u3gcazRlUDisj1JPEu1X+DNotlqHc+BDEcbCSmJ3aje9osr nI5UkEvXSFO/3bdXEPCZUp6RkJtp+j5u/N1PuSBYMzyPezJOk7lulKJea lCwtVgqKFRW92V/4UkSBWpcvNgVlSZ6ZCwHzAjvwSRbQPOqSskRif9f+h MMvaGaMPmHVubwd7OJx5dD+a+i3avTKr35+pSRPwBOfYCWGWT7CVosWOf vdQiQ/mbcUrJfaRV8I5qXa/Oof+R8fPFiMUht40TiXsJgs/ilVU0zb+xU w==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="466453221" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="466453221" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 23:22:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="920154550" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="920154550" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:13 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su Subject: [PATCH v5 01/11] common/idpf: refactor single queue Tx data path Date: Wed, 20 Sep 2023 14:22:26 +0800 Message-Id: <20230920062236.375308-2-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Currently, single queue Tx data path uses flex Tx data descriptor(DTYPE3) which is removed in the latest idpf spec. This patch replaces flex Tx data descriptor with base Tx data descriptor for single queue Tx data path and refines Tx single queue setup to align with Tx data path. Signed-off-by: Simei Su Acked-by: Wenjun Wu Acked-by: Beilei Xing --- drivers/common/idpf/idpf_common_rxtx.c | 39 +++++++++---------- drivers/common/idpf/idpf_common_rxtx.h | 2 +- drivers/common/idpf/idpf_common_rxtx_avx512.c | 37 +++++++++--------- drivers/net/cpfl/cpfl_rxtx.c | 2 +- drivers/net/idpf/idpf_rxtx.c | 2 +- 5 files changed, 40 insertions(+), 42 deletions(-) diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c index fc87e3e243..e6d2486272 100644 --- a/drivers/common/idpf/idpf_common_rxtx.c +++ b/drivers/common/idpf/idpf_common_rxtx.c @@ -276,14 +276,14 @@ idpf_qc_single_tx_queue_reset(struct idpf_tx_queue *txq) } txe = txq->sw_ring; - size = sizeof(struct idpf_flex_tx_desc) * txq->nb_tx_desc; + size = sizeof(struct idpf_base_tx_desc) * txq->nb_tx_desc; for (i = 0; i < size; i++) ((volatile char *)txq->tx_ring)[i] = 0; prev = (uint16_t)(txq->nb_tx_desc - 1); for (i = 0; i < txq->nb_tx_desc; i++) { - txq->tx_ring[i].qw1.cmd_dtype = - rte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_DESC_DONE); + txq->tx_ring[i].qw1 = + rte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DESC_DONE); txe[i].mbuf = NULL; txe[i].last_id = i; txe[prev].next_id = i; @@ -1307,17 +1307,16 @@ idpf_xmit_cleanup(struct idpf_tx_queue *txq) uint16_t nb_tx_to_clean; uint16_t i; - volatile struct idpf_flex_tx_desc *txd = txq->tx_ring; + volatile struct idpf_base_tx_desc *txd = txq->tx_ring; desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh); if (desc_to_clean_to >= nb_tx_desc) desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc); desc_to_clean_to = sw_ring[desc_to_clean_to].last_id; - /* In the writeback Tx desccriptor, the only significant fields are the 4-bit DTYPE */ - if ((txd[desc_to_clean_to].qw1.cmd_dtype & - rte_cpu_to_le_16(IDPF_TXD_QW1_DTYPE_M)) != - rte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_DESC_DONE)) { + if ((txd[desc_to_clean_to].qw1 & + rte_cpu_to_le_64(IDPF_TXD_QW1_DTYPE_M)) != + rte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DESC_DONE)) { TX_LOG(DEBUG, "TX descriptor %4u is not done " "(port=%d queue=%d)", desc_to_clean_to, txq->port_id, txq->queue_id); @@ -1331,10 +1330,7 @@ idpf_xmit_cleanup(struct idpf_tx_queue *txq) nb_tx_to_clean = (uint16_t)(desc_to_clean_to - last_desc_cleaned); - txd[desc_to_clean_to].qw1.cmd_dtype = 0; - txd[desc_to_clean_to].qw1.buf_size = 0; - for (i = 0; i < RTE_DIM(txd[desc_to_clean_to].qw1.flex.raw); i++) - txd[desc_to_clean_to].qw1.flex.raw[i] = 0; + txd[desc_to_clean_to].qw1 = 0; txq->last_desc_cleaned = desc_to_clean_to; txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean); @@ -1347,8 +1343,8 @@ uint16_t idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) { - volatile struct idpf_flex_tx_desc *txd; - volatile struct idpf_flex_tx_desc *txr; + volatile struct idpf_base_tx_desc *txd; + volatile struct idpf_base_tx_desc *txr; union idpf_tx_offload tx_offload = {0}; struct idpf_tx_entry *txe, *txn; struct idpf_tx_entry *sw_ring; @@ -1356,6 +1352,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, struct rte_mbuf *tx_pkt; struct rte_mbuf *m_seg; uint64_t buf_dma_addr; + uint32_t td_offset; uint64_t ol_flags; uint16_t tx_last; uint16_t nb_used; @@ -1382,6 +1379,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) { td_cmd = 0; + td_offset = 0; tx_pkt = *tx_pkts++; RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf); @@ -1462,9 +1460,10 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, slen = m_seg->data_len; buf_dma_addr = rte_mbuf_data_iova(m_seg); txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr); - txd->qw1.buf_size = slen; - txd->qw1.cmd_dtype = rte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_FLEX_DATA << - IDPF_FLEX_TXD_QW1_DTYPE_S); + txd->qw1 = rte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DATA | + ((uint64_t)td_cmd << IDPF_TXD_QW1_CMD_S) | + ((uint64_t)td_offset << IDPF_TXD_QW1_OFFSET_S) | + ((uint64_t)slen << IDPF_TXD_QW1_TX_BUF_SZ_S)); txe->last_id = tx_last; tx_id = txe->next_id; @@ -1473,7 +1472,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, } while (m_seg); /* The last packet data descriptor needs End Of Packet (EOP) */ - td_cmd |= IDPF_TX_FLEX_DESC_CMD_EOP; + td_cmd |= IDPF_TX_DESC_CMD_EOP; txq->nb_used = (uint16_t)(txq->nb_used + nb_used); txq->nb_free = (uint16_t)(txq->nb_free - nb_used); @@ -1482,7 +1481,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, "%4u (port=%d queue=%d)", tx_last, txq->port_id, txq->queue_id); - td_cmd |= IDPF_TX_FLEX_DESC_CMD_RS; + td_cmd |= IDPF_TX_DESC_CMD_RS; /* Update txq RS bit counters */ txq->nb_used = 0; @@ -1491,7 +1490,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, if (ol_flags & IDPF_TX_CKSUM_OFFLOAD_MASK) td_cmd |= IDPF_TX_FLEX_DESC_CMD_CS_EN; - txd->qw1.cmd_dtype |= rte_cpu_to_le_16(td_cmd << IDPF_FLEX_TXD_QW1_CMD_S); + txd->qw1 |= rte_cpu_to_le_16(td_cmd << IDPF_TXD_QW1_CMD_S); } end_of_tx: diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h index 6cb83fc0a6..b49b1ed737 100644 --- a/drivers/common/idpf/idpf_common_rxtx.h +++ b/drivers/common/idpf/idpf_common_rxtx.h @@ -157,7 +157,7 @@ struct idpf_tx_entry { /* Structure associated with each TX queue. */ struct idpf_tx_queue { const struct rte_memzone *mz; /* memzone for Tx ring */ - volatile struct idpf_flex_tx_desc *tx_ring; /* Tx ring virtual address */ + volatile struct idpf_base_tx_desc *tx_ring; /* Tx ring virtual address */ volatile union { struct idpf_flex_tx_sched_desc *desc_ring; struct idpf_splitq_tx_compl_desc *compl_ring; diff --git a/drivers/common/idpf/idpf_common_rxtx_avx512.c b/drivers/common/idpf/idpf_common_rxtx_avx512.c index 2ac46fb1d2..f65e8d512b 100644 --- a/drivers/common/idpf/idpf_common_rxtx_avx512.c +++ b/drivers/common/idpf/idpf_common_rxtx_avx512.c @@ -1005,7 +1005,7 @@ idpf_tx_singleq_free_bufs_avx512(struct idpf_tx_queue *txq) struct rte_mbuf *m, *free[txq->rs_thresh]; /* check DD bits on threshold descriptor */ - if ((txq->tx_ring[txq->next_dd].qw1.cmd_dtype & + if ((txq->tx_ring[txq->next_dd].qw1 & rte_cpu_to_le_64(IDPF_TXD_QW1_DTYPE_M)) != rte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DESC_DONE)) return 0; @@ -1113,15 +1113,14 @@ tx_backlog_entry_avx512(struct idpf_tx_vec_entry *txep, txep[i].mbuf = tx_pkts[i]; } -#define IDPF_FLEX_TXD_QW1_BUF_SZ_S 48 static __rte_always_inline void -idpf_singleq_vtx1(volatile struct idpf_flex_tx_desc *txdp, +idpf_singleq_vtx1(volatile struct idpf_base_tx_desc *txdp, struct rte_mbuf *pkt, uint64_t flags) { uint64_t high_qw = - (IDPF_TX_DESC_DTYPE_FLEX_DATA << IDPF_FLEX_TXD_QW1_DTYPE_S | - ((uint64_t)flags << IDPF_FLEX_TXD_QW1_CMD_S) | - ((uint64_t)pkt->data_len << IDPF_FLEX_TXD_QW1_BUF_SZ_S)); + (IDPF_TX_DESC_DTYPE_DATA | + ((uint64_t)flags << IDPF_TXD_QW1_CMD_S) | + ((uint64_t)pkt->data_len << IDPF_TXD_QW1_TX_BUF_SZ_S)); __m128i descriptor = _mm_set_epi64x(high_qw, pkt->buf_iova + pkt->data_off); @@ -1131,11 +1130,11 @@ idpf_singleq_vtx1(volatile struct idpf_flex_tx_desc *txdp, #define IDPF_TX_LEN_MASK 0xAA #define IDPF_TX_OFF_MASK 0x55 static __rte_always_inline void -idpf_singleq_vtx(volatile struct idpf_flex_tx_desc *txdp, +idpf_singleq_vtx(volatile struct idpf_base_tx_desc *txdp, struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags) { - const uint64_t hi_qw_tmpl = (IDPF_TX_DESC_DTYPE_FLEX_DATA | - ((uint64_t)flags << IDPF_FLEX_TXD_QW1_CMD_S)); + const uint64_t hi_qw_tmpl = (IDPF_TX_DESC_DTYPE_DATA | + ((uint64_t)flags << IDPF_TXD_QW1_CMD_S)); /* if unaligned on 32-bit boundary, do one to align */ if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) { @@ -1148,19 +1147,19 @@ idpf_singleq_vtx(volatile struct idpf_flex_tx_desc *txdp, uint64_t hi_qw3 = hi_qw_tmpl | ((uint64_t)pkt[3]->data_len << - IDPF_FLEX_TXD_QW1_BUF_SZ_S); + IDPF_TXD_QW1_TX_BUF_SZ_S); uint64_t hi_qw2 = hi_qw_tmpl | ((uint64_t)pkt[2]->data_len << - IDPF_FLEX_TXD_QW1_BUF_SZ_S); + IDPF_TXD_QW1_TX_BUF_SZ_S); uint64_t hi_qw1 = hi_qw_tmpl | ((uint64_t)pkt[1]->data_len << - IDPF_FLEX_TXD_QW1_BUF_SZ_S); + IDPF_TXD_QW1_TX_BUF_SZ_S); uint64_t hi_qw0 = hi_qw_tmpl | ((uint64_t)pkt[0]->data_len << - IDPF_FLEX_TXD_QW1_BUF_SZ_S); + IDPF_TXD_QW1_TX_BUF_SZ_S); __m512i desc0_3 = _mm512_set_epi64 @@ -1187,11 +1186,11 @@ idpf_singleq_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pk uint16_t nb_pkts) { struct idpf_tx_queue *txq = tx_queue; - volatile struct idpf_flex_tx_desc *txdp; + volatile struct idpf_base_tx_desc *txdp; struct idpf_tx_vec_entry *txep; uint16_t n, nb_commit, tx_id; - uint64_t flags = IDPF_TX_FLEX_DESC_CMD_EOP; - uint64_t rs = IDPF_TX_FLEX_DESC_CMD_RS | flags; + uint64_t flags = IDPF_TX_DESC_CMD_EOP; + uint64_t rs = IDPF_TX_DESC_CMD_RS | flags; /* cross rx_thresh boundary is not allowed */ nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh); @@ -1238,9 +1237,9 @@ idpf_singleq_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pk tx_id = (uint16_t)(tx_id + nb_commit); if (tx_id > txq->next_rs) { - txq->tx_ring[txq->next_rs].qw1.cmd_dtype |= - rte_cpu_to_le_64(((uint64_t)IDPF_TX_FLEX_DESC_CMD_RS) << - IDPF_FLEX_TXD_QW1_CMD_S); + txq->tx_ring[txq->next_rs].qw1 |= + rte_cpu_to_le_64(((uint64_t)IDPF_TX_DESC_CMD_RS) << + IDPF_TXD_QW1_CMD_S); txq->next_rs = (uint16_t)(txq->next_rs + txq->rs_thresh); } diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index 2ef6871a85..ab8bec4645 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -135,7 +135,7 @@ cpfl_dma_zone_reserve(struct rte_eth_dev *dev, uint16_t queue_idx, ring_size = RTE_ALIGN(len * sizeof(struct idpf_flex_tx_sched_desc), CPFL_DMA_MEM_ALIGN); else - ring_size = RTE_ALIGN(len * sizeof(struct idpf_flex_tx_desc), + ring_size = RTE_ALIGN(len * sizeof(struct idpf_base_tx_desc), CPFL_DMA_MEM_ALIGN); memcpy(ring_name, "cpfl Tx ring", sizeof("cpfl Tx ring")); break; diff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c index 3e3d81ca6d..64f2235580 100644 --- a/drivers/net/idpf/idpf_rxtx.c +++ b/drivers/net/idpf/idpf_rxtx.c @@ -74,7 +74,7 @@ idpf_dma_zone_reserve(struct rte_eth_dev *dev, uint16_t queue_idx, ring_size = RTE_ALIGN(len * sizeof(struct idpf_flex_tx_sched_desc), IDPF_DMA_MEM_ALIGN); else - ring_size = RTE_ALIGN(len * sizeof(struct idpf_flex_tx_desc), + ring_size = RTE_ALIGN(len * sizeof(struct idpf_base_tx_desc), IDPF_DMA_MEM_ALIGN); rte_memcpy(ring_name, "idpf Tx ring", sizeof("idpf Tx ring")); break; From patchwork Wed Sep 20 06:22:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131659 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 32070425E9; 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a="466453227" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="466453227" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 23:22:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="920154565" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="920154565" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:16 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Zhenning Xiao , Jayaprakash Shanmugam Subject: [PATCH v5 02/11] common/idpf/base: enable support for physical port stats Date: Wed, 20 Sep 2023 14:22:27 +0800 Message-Id: <20230920062236.375308-3-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support to indicate physical port representor and query its statistics. Signed-off-by: Zhenning Xiao Signed-off-by: Jayaprakash Shanmugam Signed-off-by: Simei Su Acked-by: Beilei Xing --- .mailmap | 2 + drivers/common/idpf/base/virtchnl2.h | 80 +++++++++++++++++++++++++++- 2 files changed, 81 insertions(+), 1 deletion(-) diff --git a/.mailmap b/.mailmap index 4dac53011b..3dfdd81797 100644 --- a/.mailmap +++ b/.mailmap @@ -1639,3 +1639,5 @@ Ziye Yang Zoltan Kiss Zorik Machulsky Zyta Szpak +Jayaprakash Shanmugam +Zhenning Xiao diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 594bc26b8c..cd47444835 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -97,6 +97,7 @@ #define VIRTCHNL2_OP_CONFIG_PROMISCUOUS_MODE 537 #define VIRTCHNL2_OP_ADD_QUEUE_GROUPS 538 #define VIRTCHNL2_OP_DEL_QUEUE_GROUPS 539 +#define VIRTCHNL2_OP_GET_PORT_STATS 540 #define VIRTCHNL2_RDMA_INVALID_QUEUE_IDX 0xFFFF @@ -582,6 +583,9 @@ struct virtchnl2_queue_reg_chunks { VIRTCHNL2_CHECK_STRUCT_LEN(40, virtchnl2_queue_reg_chunks); +/* VIRTCHNL2_VPORT_FLAGS */ +#define VIRTCHNL2_VPORT_UPLINK_PORT BIT(0) + #define VIRTCHNL2_ETH_LENGTH_OF_ADDRESS 6 /* VIRTCHNL2_OP_CREATE_VPORT @@ -620,7 +624,8 @@ struct virtchnl2_create_vport { __le16 max_mtu; __le32 vport_id; u8 default_mac_addr[VIRTCHNL2_ETH_LENGTH_OF_ADDRESS]; - __le16 pad; + /* see VIRTCHNL2_VPORT_FLAGS definitions */ + __le16 vport_flags; /* see VIRTCHNL2_RX_DESC_IDS definitions */ __le64 rx_desc_ids; /* see VIRTCHNL2_TX_DESC_IDS definitions */ @@ -1159,6 +1164,74 @@ struct virtchnl2_vport_stats { VIRTCHNL2_CHECK_STRUCT_LEN(128, virtchnl2_vport_stats); +/* physical port statistics */ +struct virtchnl2_phy_port_stats { + __le64 rx_bytes; + __le64 rx_unicast_pkts; + __le64 rx_multicast_pkts; + __le64 rx_broadcast_pkts; + __le64 rx_size_64_pkts; + __le64 rx_size_127_pkts; + __le64 rx_size_255_pkts; + __le64 rx_size_511_pkts; + __le64 rx_size_1023_pkts; + __le64 rx_size_1518_pkts; + __le64 rx_size_jumbo_pkts; + __le64 rx_xon_events; + __le64 rx_xoff_events; + __le64 rx_undersized_pkts; + __le64 rx_fragmented_pkts; + __le64 rx_oversized_pkts; + __le64 rx_jabber_pkts; + __le64 rx_csum_errors; + __le64 rx_length_errors; + __le64 rx_dropped_pkts; + __le64 rx_crc_errors; + /* Frames with length < 64 and a bad CRC */ + __le64 rx_runt_errors; + __le64 rx_illegal_bytes; + __le64 rx_total_pkts; + u8 rx_reserved[128]; + + __le64 tx_bytes; + __le64 tx_unicast_pkts; + __le64 tx_multicast_pkts; + __le64 tx_broadcast_pkts; + __le64 tx_errors; + __le64 tx_timeout_events; + __le64 tx_size_64_pkts; + __le64 tx_size_127_pkts; + __le64 tx_size_255_pkts; + __le64 tx_size_511_pkts; + __le64 tx_size_1023_pkts; + __le64 tx_size_1518_pkts; + __le64 tx_size_jumbo_pkts; + __le64 tx_xon_events; + __le64 tx_xoff_events; + __le64 tx_dropped_link_down_pkts; + __le64 tx_total_pkts; + u8 tx_reserved[128]; + __le64 mac_local_faults; + __le64 mac_remote_faults; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(600, virtchnl2_phy_port_stats); + +/* VIRTCHNL2_OP_GET_PORT_STATS + * PF/VF sends this message to CP to get the updated stats by specifying the + * vport_id. CP responds with stats in struct virtchnl2_port_stats that + * includes both physical port as well as vport statistics. + */ +struct virtchnl2_port_stats { + __le32 vport_id; + u8 pad[4]; + + struct virtchnl2_phy_port_stats phy_port_stats; + struct virtchnl2_vport_stats virt_port_stats; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(736, virtchnl2_port_stats); + /* VIRTCHNL2_OP_EVENT * CP sends this message to inform the PF/VF driver of events that may affect * it. No direct response is expected from the driver, though it may generate @@ -1384,6 +1457,8 @@ static inline const char *virtchnl2_op_str(__le32 v_opcode) return "VIRTCHNL2_OP_ADD_QUEUE_GROUPS"; case VIRTCHNL2_OP_DEL_QUEUE_GROUPS: return "VIRTCHNL2_OP_DEL_QUEUE_GROUPS"; + case VIRTCHNL2_OP_GET_PORT_STATS: + return "VIRTCHNL2_OP_GET_PORT_STATS"; default: return "Unsupported (update virtchnl2.h)"; } @@ -1648,6 +1723,9 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 case VIRTCHNL2_OP_GET_STATS: valid_len = sizeof(struct virtchnl2_vport_stats); break; + case VIRTCHNL2_OP_GET_PORT_STATS: + valid_len = sizeof(struct virtchnl2_port_stats); + break; case VIRTCHNL2_OP_RESET_VF: break; /* These are always errors coming from the VF. */ From patchwork Wed Sep 20 06:22:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131660 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 13620425E9; Wed, 20 Sep 2023 08:22:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 969DE40A80; Wed, 20 Sep 2023 08:22:23 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id EB14640A72 for ; Wed, 20 Sep 2023 08:22:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695190942; x=1726726942; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cLjQvst4+qT/DxgfTinZr75zvvJSxEBHlEtzfG4KlBk=; b=beBJv5LA8uSHJcfZk0/7ITdXPFReapOoezdr59YY8ktjCgejSSKyGuRc BhJy0u7cwMThyztFbtxVvhZZFe0mo6NARAky2VUV66UYYMXnO3z8rZvqv aw2LKQImjaHq70RQZWGbbFIeydyIL9wnz5s3RhohN3g+cIwb0MRWjJcFZ fYIMO58YlIgZxleriGvfc0jfa5Rd88pF+P9wGqYdQwDt36OhtTK1UEoVE sGXmwxYfrnGB+OL1OqXtRO5DJ7wQ2I+yZibsqhkBpub98mPUgKE6edLBx PomMzZ+LHjplmys6fWki2AUcjiBs+bLjYWQOwi2QlnxvUu43g5czbf5d4 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="466453235" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="466453235" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 23:22:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="920154573" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="920154573" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:19 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Josh Hay Subject: [PATCH v5 03/11] common/idpf/base: add miss completion capabilities Date: Wed, 20 Sep 2023 14:22:28 +0800 Message-Id: <20230920062236.375308-4-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add miss completion tag in other capability flags to indicate support for detecting a miss completion based on the upper bit of the completion tag. Signed-off-by: Josh Hay Signed-off-by: Simei Su Acked-by: Beilei Xing --- .mailmap | 1 + drivers/common/idpf/base/virtchnl2.h | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/.mailmap b/.mailmap index 3dfdd81797..91d8cca78f 100644 --- a/.mailmap +++ b/.mailmap @@ -1641,3 +1641,4 @@ Zorik Machulsky Zyta Szpak Jayaprakash Shanmugam Zhenning Xiao +Josh Hay diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index cd47444835..c49e4b943c 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -231,6 +231,10 @@ #define VIRTCHNL2_CAP_RX_FLEX_DESC BIT(17) #define VIRTCHNL2_CAP_PTYPE BIT(18) #define VIRTCHNL2_CAP_LOOPBACK BIT(19) +/* Enable miss completion types plus ability to detect a miss completion if a + * reserved bit is set in a standared completion's tag. + */ +#define VIRTCHNL2_CAP_MISS_COMPL_TAG BIT(20) /* this must be the last capability */ #define VIRTCHNL2_CAP_OEM BIT(63) From patchwork Wed Sep 20 06:22:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131661 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 26D2D425E9; Wed, 20 Sep 2023 08:22:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E19F540A76; Wed, 20 Sep 2023 08:22:26 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id DC39040A77 for ; Wed, 20 Sep 2023 08:22:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695190945; x=1726726945; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VJ6DLEPJZJQUU5ty5LHettx3qIS/NiMWCeRvoAyiHBY=; b=dE0WM6WpYvLk7/iJpBxo6gC4NkW3XLjhZ7hsZJzTsN4bexaO5rbobs3j YUXggKv1gB8d5OzK4pkeCDXyCXwMXDsMeKSKR1AXYt3U1XXp7nClS+la5 1PNZopfiuG8aMG3LHZWCb5fM2PNYGndzorxb+JSUPDyrSZqo7mm7DfAT/ q9yMrylAsKBZMhKj72Zm/wc7CqZU9metkX5UlZz+QLUx+75cyt68QXaHM 1QC5AfbsGoRaDOXoljSi5UnFXvjbf867tHdscx5Q2v4LQzLStI8IwxEqe zc1/zyboLRUHAFNWzGV+34rAmXjGhUwo4a6ISIo8E95AsM6ZRH3NoyJp9 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="466453241" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="466453241" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 23:22:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="920154597" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="920154597" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:21 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Milena Olech Subject: [PATCH v5 04/11] common/idpf/base: initialize PTP support Date: Wed, 20 Sep 2023 14:22:29 +0800 Message-Id: <20230920062236.375308-5-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add a few PTP capabilities to determine which PTP features are enabled including legacy cross time, ptm, device clock control, PTP Tx timestamp with direct registers access and PTP Tx timestamp with virtchnl messages. Also create opcodes and structures to support feautres introduced by capabilities. Signed-off-by: Milena Olech Signed-off-by: Simei Su Acked-by: Beilei Xing --- drivers/common/idpf/base/virtchnl2.h | 145 +++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index c49e4b943c..320430df6f 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -98,6 +98,9 @@ #define VIRTCHNL2_OP_ADD_QUEUE_GROUPS 538 #define VIRTCHNL2_OP_DEL_QUEUE_GROUPS 539 #define VIRTCHNL2_OP_GET_PORT_STATS 540 + /* TimeSync opcodes */ +#define VIRTCHNL2_OP_GET_PTP_CAPS 541 +#define VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES 542 #define VIRTCHNL2_RDMA_INVALID_QUEUE_IDX 0xFFFF @@ -1395,6 +1398,112 @@ struct virtchnl2_promisc_info { VIRTCHNL2_CHECK_STRUCT_LEN(8, virtchnl2_promisc_info); +/* VIRTCHNL2_PTP_CAPS + * PTP capabilities + */ +#define VIRTCHNL2_PTP_CAP_LEGACY_CROSS_TIME BIT(0) +#define VIRTCHNL2_PTP_CAP_PTM BIT(1) +#define VIRTCHNL2_PTP_CAP_DEVICE_CLOCK_CONTROL BIT(2) +#define VIRTCHNL2_PTP_CAP_TX_TSTAMPS_DIRECT BIT(3) +#define VIRTCHNL2_PTP_CAP_TX_TSTAMPS_VIRTCHNL BIT(4) + +/* Legacy cross time registers offsets */ +struct virtchnl2_ptp_legacy_cross_time_reg { + __le32 shadow_time_0; + __le32 shadow_time_l; + __le32 shadow_time_h; + __le32 cmd_sync; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_legacy_cross_time_reg); + +/* PTM cross time registers offsets */ +struct virtchnl2_ptp_ptm_cross_time_reg { + __le32 art_l; + __le32 art_h; + __le32 cmd_sync; + u8 pad[4]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_ptm_cross_time_reg); + +/* Registers needed to control the main clock */ +struct virtchnl2_ptp_device_clock_control { + __le32 cmd; + __le32 incval_l; + __le32 incval_h; + __le32 shadj_l; + __le32 shadj_h; + u8 pad[4]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_device_clock_control); + +/* Structure that defines tx tstamp entry - index and register offset */ +struct virtchnl2_ptp_tx_tstamp_entry { + __le32 tx_latch_register_base; + __le32 tx_latch_register_offset; + u8 index; + u8 pad[7]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_tx_tstamp_entry); + +/* Structure that defines tx tstamp entries - total number of latches + * and the array of entries. + */ +struct virtchnl2_ptp_tx_tstamp { + __le16 num_latches; + /* latch size expressed in bits */ + __le16 latch_size; + u8 pad[4]; + struct virtchnl2_ptp_tx_tstamp_entry ptp_tx_tstamp_entries[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_tx_tstamp); + +/* VIRTCHNL2_OP_GET_PTP_CAPS + * PV/VF sends this message to negotiate PTP capabilities. CP updates bitmap + * with supported features and fulfills appropriate structures. + */ +struct virtchnl2_get_ptp_caps { + /* PTP capability bitmap */ + /* see VIRTCHNL2_PTP_CAPS definitions */ + __le32 ptp_caps; + u8 pad[4]; + + struct virtchnl2_ptp_legacy_cross_time_reg legacy_cross_time_reg; + struct virtchnl2_ptp_ptm_cross_time_reg ptm_cross_time_reg; + struct virtchnl2_ptp_device_clock_control device_clock_control; + struct virtchnl2_ptp_tx_tstamp tx_tstamp; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(88, virtchnl2_get_ptp_caps); + +/* Structure that describes tx tstamp values, index and validity */ +struct virtchnl2_ptp_tx_tstamp_latch { + __le32 tstamp_h; + __le32 tstamp_l; + u8 index; + u8 valid; + u8 pad[6]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_tx_tstamp_latch); + +/* VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES + * PF/VF sends this message to receive a specified number of timestamps + * entries. + */ +struct virtchnl2_ptp_tx_tstamp_latches { + __le16 num_latches; + /* latch size expressed in bits */ + __le16 latch_size; + u8 pad[4]; + struct virtchnl2_ptp_tx_tstamp_latch tstamp_latches[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_tx_tstamp_latches); static inline const char *virtchnl2_op_str(__le32 v_opcode) { @@ -1463,6 +1572,10 @@ static inline const char *virtchnl2_op_str(__le32 v_opcode) return "VIRTCHNL2_OP_DEL_QUEUE_GROUPS"; case VIRTCHNL2_OP_GET_PORT_STATS: return "VIRTCHNL2_OP_GET_PORT_STATS"; + case VIRTCHNL2_OP_GET_PTP_CAPS: + return "VIRTCHNL2_OP_GET_PTP_CAPS"; + case VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES: + return "VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES"; default: return "Unsupported (update virtchnl2.h)"; } @@ -1732,6 +1845,38 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 break; case VIRTCHNL2_OP_RESET_VF: break; + case VIRTCHNL2_OP_GET_PTP_CAPS: + valid_len = sizeof(struct virtchnl2_get_ptp_caps); + + if (msglen >= valid_len) { + struct virtchnl2_get_ptp_caps *ptp_caps = + (struct virtchnl2_get_ptp_caps *)msg; + + if (ptp_caps->tx_tstamp.num_latches == 0) { + err_msg_format = true; + break; + } + + valid_len += ((ptp_caps->tx_tstamp.num_latches - 1) * + sizeof(struct virtchnl2_ptp_tx_tstamp_entry)); + } + break; + case VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES: + valid_len = sizeof(struct virtchnl2_ptp_tx_tstamp_latches); + + if (msglen >= valid_len) { + struct virtchnl2_ptp_tx_tstamp_latches *tx_tstamp_latches = + (struct virtchnl2_ptp_tx_tstamp_latches *)msg; + + if (tx_tstamp_latches->num_latches == 0) { + err_msg_format = true; + break; + } + + valid_len += ((tx_tstamp_latches->num_latches - 1) * + sizeof(struct virtchnl2_ptp_tx_tstamp_latch)); + } + break; /* These are always errors coming from the VF. */ case VIRTCHNL2_OP_EVENT: case VIRTCHNL2_OP_UNKNOWN: From patchwork Wed Sep 20 06:22:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131662 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 85332425E9; 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a="466453251" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="466453251" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 23:22:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="920154629" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="920154629" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:24 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Madhu Chittim Subject: [PATCH v5 05/11] common/idpf/base: remove mailbox registers Date: Wed, 20 Sep 2023 14:22:30 +0800 Message-Id: <20230920062236.375308-6-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove mailbox register offsets because individual drivers will define the offsets based on how registers address the registers. Signed-off-by: Madhu Chittim Signed-off-by: Simei Su Acked-by: Beilei Xing --- .mailmap | 1 + drivers/common/idpf/base/siov_regs.h | 13 ++----------- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/.mailmap b/.mailmap index 91d8cca78f..d8782cd67e 100644 --- a/.mailmap +++ b/.mailmap @@ -1642,3 +1642,4 @@ Zyta Szpak Jayaprakash Shanmugam Zhenning Xiao Josh Hay +Madhu Chittim diff --git a/drivers/common/idpf/base/siov_regs.h b/drivers/common/idpf/base/siov_regs.h index fad329601a..7e1ae2e300 100644 --- a/drivers/common/idpf/base/siov_regs.h +++ b/drivers/common/idpf/base/siov_regs.h @@ -4,16 +4,6 @@ #ifndef _SIOV_REGS_H_ #define _SIOV_REGS_H_ #define VDEV_MBX_START 0x20000 /* Begin at 128KB */ -#define VDEV_MBX_ATQBAL (VDEV_MBX_START + 0x0000) -#define VDEV_MBX_ATQBAH (VDEV_MBX_START + 0x0004) -#define VDEV_MBX_ATQLEN (VDEV_MBX_START + 0x0008) -#define VDEV_MBX_ATQH (VDEV_MBX_START + 0x000C) -#define VDEV_MBX_ATQT (VDEV_MBX_START + 0x0010) -#define VDEV_MBX_ARQBAL (VDEV_MBX_START + 0x0014) -#define VDEV_MBX_ARQBAH (VDEV_MBX_START + 0x0018) -#define VDEV_MBX_ARQLEN (VDEV_MBX_START + 0x001C) -#define VDEV_MBX_ARQH (VDEV_MBX_START + 0x0020) -#define VDEV_MBX_ARQT (VDEV_MBX_START + 0x0024) #define VDEV_GET_RSTAT 0x21000 /* 132KB for RSTAT */ /* Begin at offset after 1MB (after 256 4k pages) */ @@ -43,5 +33,6 @@ #define VDEV_INT_ITR_1(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x08) #define VDEV_INT_ITR_2(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x0C) -/* Next offset to begin at 42MB (0x2A00000) */ +#define SIOV_REG_BAR_SIZE 0x2A00000 +/* Next offset to begin at 42MB + 4K (0x2A00000 + 0x1000) */ #endif /* _SIOV_REGS_H_ */ From patchwork Wed Sep 20 06:22:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131663 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 470C1425E9; Wed, 20 Sep 2023 08:22:56 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6440840DCD; Wed, 20 Sep 2023 08:22:32 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 4606440DCE for ; Wed, 20 Sep 2023 08:22:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695190950; x=1726726950; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YIXtmR3F6j533+wnP/110K8+BIFrwlK36OSItmBKQj4=; b=Pab25MP/YQxaBjfc1aOETaYOeQRs51BH8wokSicH6g8qGCZaiu402qVc sbdZeF7nsFIhrNHaU+kCqdFFmiU0phwVt/TzkX4FN5mP2PZ0OYZFeieRL 8BnxRUJpbtOvOHG2TT9XPtkE4vq11p4fBaCGz4S0hGX/6/fCMZFTeSGDd SiDMcfimomHqxmuLJ4LR8hKbIq4G+tW1ocF3OGWMV98xOE/iUiyLFxpXu jmugkCx+smQNzp6vm16yn1s1iPZpo1wkV3F1n7cKTmrO/Bom6dhZrfzgG 1vUw7k/MAP3rmoa0KZ5f5idHStotInA+O18rezobJCFXdkNeMqxDR/fiM w==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="466453258" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="466453258" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 23:22:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="920154654" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="920154654" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:26 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Shailendra Bhatnagar , Julianx Grajkowski Subject: [PATCH v5 06/11] common/idpf/base: refine structure and necessary check Date: Wed, 20 Sep 2023 14:22:31 +0800 Message-Id: <20230920062236.375308-7-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org a) Refine queue chunk and vector chunk structures. b) Add non_flex prefix to distinguish the flex array definitions. c) Add some specific fields. d) Refine condition check. Signed-off-by: Shailendra Bhatnagar Signed-off-by: Julianx Grajkowski Signed-off-by: Simei Su Acked-by: Beilei Xing --- .mailmap | 2 + drivers/common/idpf/base/idpf_common.c | 6 ++- drivers/common/idpf/base/virtchnl2.h | 72 +++++++++++++++++--------- 3 files changed, 54 insertions(+), 26 deletions(-) diff --git a/.mailmap b/.mailmap index d8782cd67e..23aed53102 100644 --- a/.mailmap +++ b/.mailmap @@ -1643,3 +1643,5 @@ Jayaprakash Shanmugam Zhenning Xiao Josh Hay Madhu Chittim +Shailendra Bhatnagar +Julianx Grajkowski diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index fbf71416fd..9610916aa9 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -239,8 +239,10 @@ int idpf_clean_arq_element(struct idpf_hw *hw, e->desc.ret_val = msg.status; e->desc.datalen = msg.data_len; if (msg.data_len > 0) { - if (!msg.ctx.indirect.payload) - return -EINVAL; + if (!msg.ctx.indirect.payload || !msg.ctx.indirect.payload->va || + !e->msg_buf) { + return -EFAULT; + } e->buf_len = msg.data_len; msg_data_len = msg.data_len; idpf_memcpy(e->msg_buf, msg.ctx.indirect.payload->va, msg_data_len, diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 320430df6f..3900b784d0 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -89,8 +89,8 @@ * VIRTCHNL2_OP_GET_PTYPE_INFO_RAW */ /* opcodes 529, 530, and 531 are reserved */ -#define VIRTCHNL2_OP_CREATE_ADI 532 -#define VIRTCHNL2_OP_DESTROY_ADI 533 +#define VIRTCHNL2_OP_NON_FLEX_CREATE_ADI 532 +#define VIRTCHNL2_OP_NON_FLEX_DESTROY_ADI 533 #define VIRTCHNL2_OP_LOOPBACK 534 #define VIRTCHNL2_OP_ADD_MAC_ADDR 535 #define VIRTCHNL2_OP_DEL_MAC_ADDR 536 @@ -294,6 +294,7 @@ /* These messages are only sent to PF from CP */ #define VIRTCHNL2_EVENT_START_RESET_ADI 2 #define VIRTCHNL2_EVENT_FINISH_RESET_ADI 3 +#define VIRTCHNL2_EVENT_ADI_ACTIVE 4 /* VIRTCHNL2_QUEUE_TYPE * Transmit and Receive queue types are valid in legacy as well as split queue @@ -547,7 +548,8 @@ struct virtchnl2_get_capabilities { u8 max_sg_bufs_per_tx_pkt; u8 reserved1; - __le16 pad1; + /* upper bound of number of ADIs supported */ + __le16 max_adis; /* version of Control Plane that is running */ __le16 oem_cp_ver_major; @@ -1059,14 +1061,34 @@ struct virtchnl2_sriov_vfs_info { VIRTCHNL2_CHECK_STRUCT_LEN(4, virtchnl2_sriov_vfs_info); -/* VIRTCHNL2_OP_CREATE_ADI +/* structure to specify single chunk of queue */ +/* 'chunks' is fixed size(not flexible) and will be deprecated at some point */ +struct virtchnl2_non_flex_queue_reg_chunks { + __le16 num_chunks; + u8 reserved[6]; + struct virtchnl2_queue_reg_chunk chunks[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(40, virtchnl2_non_flex_queue_reg_chunks); + +/* structure to specify single chunk of interrupt vector */ +/* 'vchunks' is fixed size(not flexible) and will be deprecated at some point */ +struct virtchnl2_non_flex_vector_chunks { + __le16 num_vchunks; + u8 reserved[14]; + struct virtchnl2_vector_chunk vchunks[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(48, virtchnl2_non_flex_vector_chunks); + +/* VIRTCHNL2_OP_NON_FLEX_CREATE_ADI * PF sends this message to CP to create ADI by filling in required - * fields of virtchnl2_create_adi structure. - * CP responds with the updated virtchnl2_create_adi structure containing the - * necessary fields followed by chunks which in turn will have an array of + * fields of virtchnl2_non_flex_create_adi structure. + * CP responds with the updated virtchnl2_non_flex_create_adi structure containing + * the necessary fields followed by chunks which in turn will have an array of * num_chunks entries of virtchnl2_queue_chunk structures. */ -struct virtchnl2_create_adi { +struct virtchnl2_non_flex_create_adi { /* PF sends PASID to CP */ __le32 pasid; /* @@ -1076,29 +1098,31 @@ struct virtchnl2_create_adi { __le16 mbx_id; /* PF sends mailbox vector id to CP */ __le16 mbx_vec_id; + /* PF populates this ADI index */ + __le16 adi_index; /* CP populates ADI id */ __le16 adi_id; u8 reserved[64]; - u8 pad[6]; + u8 pad[4]; /* CP populates queue chunks */ - struct virtchnl2_queue_reg_chunks chunks; + struct virtchnl2_non_flex_queue_reg_chunks chunks; /* PF sends vector chunks to CP */ - struct virtchnl2_vector_chunks vchunks; + struct virtchnl2_non_flex_vector_chunks vchunks; }; -VIRTCHNL2_CHECK_STRUCT_LEN(168, virtchnl2_create_adi); +VIRTCHNL2_CHECK_STRUCT_LEN(168, virtchnl2_non_flex_create_adi); /* VIRTCHNL2_OP_DESTROY_ADI * PF sends this message to CP to destroy ADI by filling * in the adi_id in virtchnl2_destropy_adi structure. * CP responds with the status of the requested operation. */ -struct virtchnl2_destroy_adi { +struct virtchnl2_non_flex_destroy_adi { __le16 adi_id; u8 reserved[2]; }; -VIRTCHNL2_CHECK_STRUCT_LEN(4, virtchnl2_destroy_adi); +VIRTCHNL2_CHECK_STRUCT_LEN(4, virtchnl2_non_flex_destroy_adi); /* Based on the descriptor type the PF supports, CP fills ptype_id_10 or * ptype_id_8 for flex and base descriptor respectively. If ptype_id_10 value @@ -1562,10 +1586,10 @@ static inline const char *virtchnl2_op_str(__le32 v_opcode) return "VIRTCHNL2_OP_EVENT"; case VIRTCHNL2_OP_RESET_VF: return "VIRTCHNL2_OP_RESET_VF"; - case VIRTCHNL2_OP_CREATE_ADI: - return "VIRTCHNL2_OP_CREATE_ADI"; - case VIRTCHNL2_OP_DESTROY_ADI: - return "VIRTCHNL2_OP_DESTROY_ADI"; + case VIRTCHNL2_OP_NON_FLEX_CREATE_ADI: + return "VIRTCHNL2_OP_NON_FLEX_CREATE_ADI"; + case VIRTCHNL2_OP_NON_FLEX_DESTROY_ADI: + return "VIRTCHNL2_OP_NON_FLEX_DESTROY_ADI"; case VIRTCHNL2_OP_ADD_QUEUE_GROUPS: return "VIRTCHNL2_OP_ADD_QUEUE_GROUPS"; case VIRTCHNL2_OP_DEL_QUEUE_GROUPS: @@ -1620,11 +1644,11 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 sizeof(struct virtchnl2_queue_reg_chunk); } break; - case VIRTCHNL2_OP_CREATE_ADI: - valid_len = sizeof(struct virtchnl2_create_adi); + case VIRTCHNL2_OP_NON_FLEX_CREATE_ADI: + valid_len = sizeof(struct virtchnl2_non_flex_create_adi); if (msglen >= valid_len) { - struct virtchnl2_create_adi *cadi = - (struct virtchnl2_create_adi *)msg; + struct virtchnl2_non_flex_create_adi *cadi = + (struct virtchnl2_non_flex_create_adi *)msg; if (cadi->chunks.num_chunks == 0) { /* zero chunks is allowed as input */ @@ -1641,8 +1665,8 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 sizeof(struct virtchnl2_vector_chunk); } break; - case VIRTCHNL2_OP_DESTROY_ADI: - valid_len = sizeof(struct virtchnl2_destroy_adi); + case VIRTCHNL2_OP_NON_FLEX_DESTROY_ADI: + valid_len = sizeof(struct virtchnl2_non_flex_destroy_adi); break; case VIRTCHNL2_OP_DESTROY_VPORT: case VIRTCHNL2_OP_ENABLE_VPORT: From patchwork Wed Sep 20 06:22:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131664 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 01AC7425E9; Wed, 20 Sep 2023 08:23:03 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B5FCC40DDE; Wed, 20 Sep 2023 08:22:34 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id C53E640DDB for ; Wed, 20 Sep 2023 08:22:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695190953; x=1726726953; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2+bF33l8ETyELeXmaPFyuRTD2DdR0tuPFIDe3cnQkEU=; b=a7A9Ekunl5VYSjjghKSu4qMefMqp+dNEP+JMgEJbGgLjZZccdHvhETCQ 8rv2H0M/HBwyxl3OUXUKa+4KGrGJqQ4jfidL297pm38gC2FTWWWKh3cjl DBsmoQnyYcXkezffgR1pkd8gZ0swJIdnvM33nElDHMLdfT7bJvssAZhqU r3tU6H/do2eD5KWDY9fNPDAJEEkGWRFU/sisbSBYiDYquIU9hm3FTeBxi oJ9iG+Mn7hTuyAp5E65FSXCMXVo+TlEr0g9WJk5I6HNdbm6dw7c9tkOi6 oxmS+brOVGk7XmOQUyZDvmJ8wb4RkvzjSGj4lG8NgIiBbep8A82b9nUc9 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="466453262" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="466453262" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 23:22:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="920154693" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="920154693" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:29 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Alan Brady Subject: [PATCH v5 07/11] common/idpf/base: add union for SW cookie fields Date: Wed, 20 Sep 2023 14:22:32 +0800 Message-Id: <20230920062236.375308-8-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Instead of using something like a byte offset, we can add a union to the struct to enable direct addressing. Signed-off-by: Alan Brady Signed-off-by: Simei Su Acked-by: Beilei Xing --- .mailmap | 1 + drivers/common/idpf/base/idpf_controlq_api.h | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/.mailmap b/.mailmap index 23aed53102..2fcadb4e4c 100644 --- a/.mailmap +++ b/.mailmap @@ -1645,3 +1645,4 @@ Josh Hay Madhu Chittim Shailendra Bhatnagar Julianx Grajkowski +Alan Brady diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index 3780304256..f4e7b53ac9 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -77,6 +77,11 @@ struct idpf_ctlq_msg { u8 context[IDPF_INDIRECT_CTX_SIZE]; struct idpf_dma_mem *payload; } indirect; + struct { + u32 rsvd; + u16 data; + u16 flags; + } sw_cookie; } ctx; }; From patchwork Wed Sep 20 06:22:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131665 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 243BC425E9; Wed, 20 Sep 2023 08:23:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A8E8440E2D; Wed, 20 Sep 2023 08:22:37 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id BFC7A40DFD for ; Wed, 20 Sep 2023 08:22:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695190955; x=1726726955; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2YADc4NirdxRm8Nym/PH3jVe9h4hmbfH8HqDCLfJqVA=; b=ZXLmo5Z30xbBVRrDTJE23wbzz9kq3/QdKORpLnxIgQTDwYxvMTTzFftl bgs+7V4QkleNOwx3OmncNag6RCwQsMJlSvjWDveMCenBo/NDduHcR5PCk taLc4QNcCl6AxxGCS6ztWWuIdcy8AG3c2vEkQYWCcObLlQCXPzswhaBGG AB9sgZJs7JLqX5HpQ5ZTsDqhSq2EDqRSxsA4c9aA5zp077MxnI5f65ndm 70iFh46XTLFYAZ0GSvcbh+qXIMwTdxkSjIoYQGMm9kBXBvNepQGMozYee Y4zecRy+Yu8waP0uofBBrg0vqrKQl4Fft1HBIjf7DCIryDON91tUCCVd+ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="466453269" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="466453269" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 23:22:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="920154732" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="920154732" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:32 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Pavan Kumar Linga Subject: [PATCH v5 08/11] common/idpf/base: refine code and alignments Date: Wed, 20 Sep 2023 14:22:33 +0800 Message-Id: <20230920062236.375308-9-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org a) Refine double pointer with a local pointer. b) Refine return type for function instead of only returning success. c) Remove unnecessary check and comments. d) Use tab spaces and new lines wherever necessary. Signed-off-by: Pavan Kumar Linga Signed-off-by: Simei Su Acked-by: Beilei Xing --- drivers/common/idpf/base/idpf_common.c | 4 +- drivers/common/idpf/base/idpf_controlq.c | 64 +++++++++---------- drivers/common/idpf/base/idpf_controlq_api.h | 12 +--- .../common/idpf/base/idpf_controlq_setup.c | 5 +- drivers/common/idpf/base/idpf_lan_pf_regs.h | 7 +- drivers/common/idpf/base/idpf_lan_txrx.h | 46 ++++++------- drivers/common/idpf/base/idpf_lan_vf_regs.h | 25 +++++--- drivers/common/idpf/base/idpf_prototype.h | 2 +- 8 files changed, 80 insertions(+), 85 deletions(-) diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index 9610916aa9..7181a7f14c 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -262,12 +262,12 @@ int idpf_clean_arq_element(struct idpf_hw *hw, * idpf_deinit_hw - shutdown routine * @hw: pointer to the hardware structure */ -int idpf_deinit_hw(struct idpf_hw *hw) +void idpf_deinit_hw(struct idpf_hw *hw) { hw->asq = NULL; hw->arq = NULL; - return idpf_ctlq_deinit(hw); + idpf_ctlq_deinit(hw); } /** diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 6815153e1d..a82ca628de 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -9,11 +9,10 @@ * @cq: pointer to the specific control queue * @q_create_info: structs containing info for each queue to be initialized */ -static void -idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq, - struct idpf_ctlq_create_info *q_create_info) +static void idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq, + struct idpf_ctlq_create_info *q_create_info) { - /* set head and tail registers in our local struct */ + /* set control queue registers in our local struct */ cq->reg.head = q_create_info->reg.head; cq->reg.tail = q_create_info->reg.tail; cq->reg.len = q_create_info->reg.len; @@ -75,7 +74,7 @@ static void idpf_ctlq_init_rxq_bufs(struct idpf_ctlq_info *cq) desc->flags = CPU_TO_LE16(IDPF_CTLQ_FLAG_BUF | IDPF_CTLQ_FLAG_RD); desc->opcode = 0; - desc->datalen = (__le16)CPU_TO_LE16(bi->size); + desc->datalen = CPU_TO_LE16(bi->size); desc->ret_val = 0; desc->cookie_high = 0; desc->cookie_low = 0; @@ -137,6 +136,7 @@ int idpf_ctlq_add(struct idpf_hw *hw, struct idpf_ctlq_create_info *qinfo, struct idpf_ctlq_info **cq_out) { + struct idpf_ctlq_info *cq; bool is_rxq = false; int status = 0; @@ -145,26 +145,26 @@ int idpf_ctlq_add(struct idpf_hw *hw, qinfo->buf_size > IDPF_CTLQ_MAX_BUF_LEN) return -EINVAL; - *cq_out = (struct idpf_ctlq_info *) - idpf_calloc(hw, 1, sizeof(struct idpf_ctlq_info)); - if (!(*cq_out)) + cq = (struct idpf_ctlq_info *) + idpf_calloc(hw, 1, sizeof(struct idpf_ctlq_info)); + if (!cq) return -ENOMEM; - (*cq_out)->cq_type = qinfo->type; - (*cq_out)->q_id = qinfo->id; - (*cq_out)->buf_size = qinfo->buf_size; - (*cq_out)->ring_size = qinfo->len; + cq->cq_type = qinfo->type; + cq->q_id = qinfo->id; + cq->buf_size = qinfo->buf_size; + cq->ring_size = qinfo->len; - (*cq_out)->next_to_use = 0; - (*cq_out)->next_to_clean = 0; - (*cq_out)->next_to_post = (*cq_out)->ring_size - 1; + cq->next_to_use = 0; + cq->next_to_clean = 0; + cq->next_to_post = cq->ring_size - 1; switch (qinfo->type) { case IDPF_CTLQ_TYPE_MAILBOX_RX: is_rxq = true; /* fallthrough */ case IDPF_CTLQ_TYPE_MAILBOX_TX: - status = idpf_ctlq_alloc_ring_res(hw, *cq_out); + status = idpf_ctlq_alloc_ring_res(hw, cq); break; default: status = -EINVAL; @@ -175,33 +175,35 @@ int idpf_ctlq_add(struct idpf_hw *hw, goto init_free_q; if (is_rxq) { - idpf_ctlq_init_rxq_bufs(*cq_out); + idpf_ctlq_init_rxq_bufs(cq); } else { /* Allocate the array of msg pointers for TX queues */ - (*cq_out)->bi.tx_msg = (struct idpf_ctlq_msg **) + cq->bi.tx_msg = (struct idpf_ctlq_msg **) idpf_calloc(hw, qinfo->len, sizeof(struct idpf_ctlq_msg *)); - if (!(*cq_out)->bi.tx_msg) { + if (!cq->bi.tx_msg) { status = -ENOMEM; goto init_dealloc_q_mem; } } - idpf_ctlq_setup_regs(*cq_out, qinfo); + idpf_ctlq_setup_regs(cq, qinfo); - idpf_ctlq_init_regs(hw, *cq_out, is_rxq); + idpf_ctlq_init_regs(hw, cq, is_rxq); - idpf_init_lock(&(*cq_out)->cq_lock); + idpf_init_lock(&(cq->cq_lock)); - LIST_INSERT_HEAD(&hw->cq_list_head, (*cq_out), cq_list); + LIST_INSERT_HEAD(&hw->cq_list_head, cq, cq_list); + *cq_out = cq; return status; init_dealloc_q_mem: /* free ring buffers and the ring itself */ - idpf_ctlq_dealloc_ring_res(hw, *cq_out); + idpf_ctlq_dealloc_ring_res(hw, cq); init_free_q: - idpf_free(hw, *cq_out); + idpf_free(hw, cq); + cq = NULL; return status; } @@ -261,16 +263,13 @@ int idpf_ctlq_init(struct idpf_hw *hw, u8 num_q, * idpf_ctlq_deinit - destroy all control queues * @hw: pointer to hw struct */ -int idpf_ctlq_deinit(struct idpf_hw *hw) +void idpf_ctlq_deinit(struct idpf_hw *hw) { struct idpf_ctlq_info *cq = NULL, *tmp = NULL; - int ret_code = 0; LIST_FOR_EACH_ENTRY_SAFE(cq, tmp, &hw->cq_list_head, idpf_ctlq_info, cq_list) idpf_ctlq_remove(hw, cq); - - return ret_code; } /** @@ -426,11 +425,8 @@ static int __idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, if (!force && !(LE16_TO_CPU(desc->flags) & IDPF_CTLQ_FLAG_DD)) break; - desc_err = LE16_TO_CPU(desc->ret_val); - if (desc_err) { - /* strip off FW internal code */ - desc_err &= 0xff; - } + /* strip off FW internal code */ + desc_err = LE16_TO_CPU(desc->ret_val) & 0xff; msg_status[i] = cq->bi.tx_msg[ntc]; if (!msg_status[i]) diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index f4e7b53ac9..38f5d2df3c 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -21,10 +21,7 @@ enum idpf_ctlq_type { IDPF_CTLQ_TYPE_RDMA_COMPL = 7 }; -/* - * Generic Control Queue Structures - */ - +/* Generic Control Queue Structures */ struct idpf_ctlq_reg { /* used for queue tracking */ u32 head; @@ -157,10 +154,7 @@ enum idpf_mbx_opc { idpf_mbq_opc_send_msg_to_peer_drv = 0x0804, }; -/* - * API supported for control queue management - */ - +/* API supported for control queue management */ /* Will init all required q including default mb. "q_info" is an array of * create_info structs equal to the number of control queues to be created. */ @@ -205,6 +199,6 @@ int idpf_ctlq_post_rx_buffs(struct idpf_hw *hw, struct idpf_dma_mem **buffs); /* Will destroy all q including the default mb */ -int idpf_ctlq_deinit(struct idpf_hw *hw); +void idpf_ctlq_deinit(struct idpf_hw *hw); #endif /* _IDPF_CONTROLQ_API_H_ */ diff --git a/drivers/common/idpf/base/idpf_controlq_setup.c b/drivers/common/idpf/base/idpf_controlq_setup.c index 0f1b52a7e9..21f43c74f5 100644 --- a/drivers/common/idpf/base/idpf_controlq_setup.c +++ b/drivers/common/idpf/base/idpf_controlq_setup.c @@ -11,9 +11,8 @@ * @hw: pointer to hw struct * @cq: pointer to the specific Control queue */ -static int -idpf_ctlq_alloc_desc_ring(struct idpf_hw *hw, - struct idpf_ctlq_info *cq) +static int idpf_ctlq_alloc_desc_ring(struct idpf_hw *hw, + struct idpf_ctlq_info *cq) { size_t size = cq->ring_size * sizeof(struct idpf_ctlq_desc); diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index 8542620e01..eab23f279a 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -80,10 +80,11 @@ /* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is * spacing b/w itrn registers of the same vector. */ -#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ - ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing))) +#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ + ((_reg_start) + ((_ITR) * (_itrn_indx_spacing))) /* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */ -#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) +#define PF_GLINT_ITR(_ITR, _INT) \ + (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) #define PF_GLINT_ITR_MAX_INDEX 2 #define PF_GLINT_ITR_INTERVAL_S 0 #define PF_GLINT_ITR_INTERVAL_M IDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S) diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h index 7b03693eb1..aec6422c15 100644 --- a/drivers/common/idpf/base/idpf_lan_txrx.h +++ b/drivers/common/idpf/base/idpf_lan_txrx.h @@ -8,9 +8,9 @@ #include "idpf_osdep.h" enum idpf_rss_hash { - /* Values 0 - 28 are reserved for future use */ - IDPF_HASH_INVALID = 0, - IDPF_HASH_NONF_UNICAST_IPV4_UDP = 29, + IDPF_HASH_INVALID = 0, + /* Values 1 - 28 are reserved for future use */ + IDPF_HASH_NONF_UNICAST_IPV4_UDP = 29, IDPF_HASH_NONF_MULTICAST_IPV4_UDP, IDPF_HASH_NONF_IPV4_UDP, IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK, @@ -19,7 +19,7 @@ enum idpf_rss_hash { IDPF_HASH_NONF_IPV4_OTHER, IDPF_HASH_FRAG_IPV4, /* Values 37-38 are reserved */ - IDPF_HASH_NONF_UNICAST_IPV6_UDP = 39, + IDPF_HASH_NONF_UNICAST_IPV6_UDP = 39, IDPF_HASH_NONF_MULTICAST_IPV6_UDP, IDPF_HASH_NONF_IPV6_UDP, IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK, @@ -32,34 +32,30 @@ enum idpf_rss_hash { IDPF_HASH_NONF_FCOE_RX, IDPF_HASH_NONF_FCOE_OTHER, /* Values 51-62 are reserved */ - IDPF_HASH_L2_PAYLOAD = 63, + IDPF_HASH_L2_PAYLOAD = 63, IDPF_HASH_MAX }; /* Supported RSS offloads */ -#define IDPF_DEFAULT_RSS_HASH ( \ - BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \ - BIT_ULL(IDPF_HASH_FRAG_IPV4) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \ - BIT_ULL(IDPF_HASH_FRAG_IPV6) | \ +#define IDPF_DEFAULT_RSS_HASH \ + (BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \ + BIT_ULL(IDPF_HASH_FRAG_IPV4) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \ + BIT_ULL(IDPF_HASH_FRAG_IPV6) | \ BIT_ULL(IDPF_HASH_L2_PAYLOAD)) - /* TODO: Wrap below comment under internal flag - * Below 6 pcktypes are not supported by FVL or older products - * They are supported by FPK and future products - */ #define IDPF_DEFAULT_RSS_HASH_EXPANDED (IDPF_DEFAULT_RSS_HASH | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \ - BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \ - BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \ + BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \ + BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \ BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP)) /* For idpf_splitq_base_tx_compl_desc */ diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index b5ff9b2cc9..2caa07fdfd 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -94,14 +94,23 @@ * b/w itrn registers of the same vector */ #define VF_INT_ITR0(_ITR) (0x00004C00 + ((_ITR) * 4)) -#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ - ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing))) -/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */ -#define VF_INT_ITRN(_INT, _ITR) (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40)) -/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */ -#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100)) -/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */ -#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) +#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ + ((_reg_start) + ((_ITR) * (_itrn_indx_spacing))) +/* For VF with 16 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing + * is 0x40 and base register offset is 0x00002800 + */ +#define VF_INT_ITRN(_INT, _ITR) \ + (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40)) +/* For VF with 64 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing + * is 0x100 and base register offset is 0x00002C00 + */ +#define VF_INT_ITRN_64(_INT, _ITR) \ + (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100)) +/* For VF with 2k vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing + * is 0x2000 and base register offset is 0x00072000 + */ +#define VF_INT_ITRN_2K(_INT, _ITR) \ + (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) #define VF_INT_ITRN_MAX_INDEX 2 #define VF_INT_ITRN_INTERVAL_S 0 #define VF_INT_ITRN_INTERVAL_M IDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S) diff --git a/drivers/common/idpf/base/idpf_prototype.h b/drivers/common/idpf/base/idpf_prototype.h index 988ff00506..e2f090a9e3 100644 --- a/drivers/common/idpf/base/idpf_prototype.h +++ b/drivers/common/idpf/base/idpf_prototype.h @@ -20,7 +20,7 @@ #define APF int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size ctlq_size); -int idpf_deinit_hw(struct idpf_hw *hw); +void idpf_deinit_hw(struct idpf_hw *hw); int idpf_clean_arq_element(struct idpf_hw *hw, struct idpf_arq_event_info *e, From patchwork Wed Sep 20 06:22:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131666 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5F538425E9; Wed, 20 Sep 2023 08:23:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E36D140A7F; Wed, 20 Sep 2023 08:22:40 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id D299640E64 for ; Wed, 20 Sep 2023 08:22:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; 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19 Sep 2023 23:22:35 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Pavan Kumar Linga Subject: [PATCH v5 09/11] common/idpf/base: use GENMASK macro Date: Wed, 20 Sep 2023 14:22:34 +0800 Message-Id: <20230920062236.375308-10-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Instead of using a custom defined macro for generating a mask, use the standard GENMASK macro. Signed-off-by: Pavan Kumar Linga Signed-off-by: Simei Su Acked-by: Beilei Xing --- drivers/common/idpf/base/idpf_lan_pf_regs.h | 26 ++--- drivers/common/idpf/base/idpf_lan_txrx.h | 116 +++++++++----------- drivers/common/idpf/base/idpf_lan_vf_regs.h | 16 +-- drivers/common/idpf/base/idpf_osdep.h | 7 ++ 4 files changed, 80 insertions(+), 85 deletions(-) diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index eab23f279a..a51e39a502 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -24,7 +24,7 @@ #define PF_FW_ARQBAH (PF_FW_BASE + 0x4) #define PF_FW_ARQLEN (PF_FW_BASE + 0x8) #define PF_FW_ARQLEN_ARQLEN_S 0 -#define PF_FW_ARQLEN_ARQLEN_M IDPF_M(0x1FFF, PF_FW_ARQLEN_ARQLEN_S) +#define PF_FW_ARQLEN_ARQLEN_M GENMASK(12, 0) #define PF_FW_ARQLEN_ARQVFE_S 28 #define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S) #define PF_FW_ARQLEN_ARQOVFL_S 29 @@ -35,14 +35,14 @@ #define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S) #define PF_FW_ARQH (PF_FW_BASE + 0xC) #define PF_FW_ARQH_ARQH_S 0 -#define PF_FW_ARQH_ARQH_M IDPF_M(0x1FFF, PF_FW_ARQH_ARQH_S) +#define PF_FW_ARQH_ARQH_M GENMASK(12, 0) #define PF_FW_ARQT (PF_FW_BASE + 0x10) #define PF_FW_ATQBAL (PF_FW_BASE + 0x14) #define PF_FW_ATQBAH (PF_FW_BASE + 0x18) #define PF_FW_ATQLEN (PF_FW_BASE + 0x1C) #define PF_FW_ATQLEN_ATQLEN_S 0 -#define PF_FW_ATQLEN_ATQLEN_M IDPF_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S) +#define PF_FW_ATQLEN_ATQLEN_M GENMASK(9, 0) #define PF_FW_ATQLEN_ATQVFE_S 28 #define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S) #define PF_FW_ATQLEN_ATQOVFL_S 29 @@ -53,7 +53,7 @@ #define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S) #define PF_FW_ATQH (PF_FW_BASE + 0x20) #define PF_FW_ATQH_ATQH_S 0 -#define PF_FW_ATQH_ATQH_M IDPF_M(0x3FF, PF_FW_ATQH_ATQH_S) +#define PF_FW_ATQH_ATQH_M GENMASK(9, 0) #define PF_FW_ATQT (PF_FW_BASE + 0x24) /* Interrupts */ @@ -66,7 +66,7 @@ #define PF_GLINT_DYN_CTL_SWINT_TRIG_S 2 #define PF_GLINT_DYN_CTL_SWINT_TRIG_M BIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S) #define PF_GLINT_DYN_CTL_ITR_INDX_S 3 -#define PF_GLINT_DYN_CTL_ITR_INDX_M IDPF_M(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S) +#define PF_GLINT_DYN_CTL_ITR_INDX_M GENMASK(4, 3) #define PF_GLINT_DYN_CTL_INTERVAL_S 5 #define PF_GLINT_DYN_CTL_INTERVAL_M BIT(PF_GLINT_DYN_CTL_INTERVAL_S) #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 24 @@ -87,13 +87,13 @@ (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) #define PF_GLINT_ITR_MAX_INDEX 2 #define PF_GLINT_ITR_INTERVAL_S 0 -#define PF_GLINT_ITR_INTERVAL_M IDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S) +#define PF_GLINT_ITR_INTERVAL_M GENMASK(11, 0) /* Timesync registers */ #define PF_TIMESYNC_BASE 0x08404000 #define PF_GLTSYN_CMD_SYNC (PF_TIMESYNC_BASE) #define PF_GLTSYN_CMD_SYNC_EXEC_CMD_S 0 -#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M IDPF_M(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S) +#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M GENMASK(1, 0) #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_S 2 #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_M BIT(PF_GLTSYN_CMD_SYNC_SHTIME_EN_S) #define PF_GLTSYN_SHTIME_0 (PF_TIMESYNC_BASE + 0x4) @@ -105,23 +105,23 @@ /* Generic registers */ #define PF_INT_DIR_OICR_ENA 0x08406000 #define PF_INT_DIR_OICR_ENA_S 0 -#define PF_INT_DIR_OICR_ENA_M IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S) +#define PF_INT_DIR_OICR_ENA_M GENMASK(31, 0) #define PF_INT_DIR_OICR 0x08406004 #define PF_INT_DIR_OICR_TSYN_EVNT 0 #define PF_INT_DIR_OICR_PHY_TS_0 BIT(1) #define PF_INT_DIR_OICR_PHY_TS_1 BIT(2) #define PF_INT_DIR_OICR_CAUSE 0x08406008 #define PF_INT_DIR_OICR_CAUSE_CAUSE_S 0 -#define PF_INT_DIR_OICR_CAUSE_CAUSE_M IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S) +#define PF_INT_DIR_OICR_CAUSE_CAUSE_M GENMASK(31, 0) #define PF_INT_PBA_CLEAR 0x0840600C #define PF_FUNC_RID 0x08406010 #define PF_FUNC_RID_FUNCTION_NUMBER_S 0 -#define PF_FUNC_RID_FUNCTION_NUMBER_M IDPF_M(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S) +#define PF_FUNC_RID_FUNCTION_NUMBER_M GENMASK(2, 0) #define PF_FUNC_RID_DEVICE_NUMBER_S 3 -#define PF_FUNC_RID_DEVICE_NUMBER_M IDPF_M(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S) +#define PF_FUNC_RID_DEVICE_NUMBER_M GENMASK(7, 3) #define PF_FUNC_RID_BUS_NUMBER_S 8 -#define PF_FUNC_RID_BUS_NUMBER_M IDPF_M(0xFF, PF_FUNC_RID_BUS_NUMBER_S) +#define PF_FUNC_RID_BUS_NUMBER_M GENMASK(15, 8) /* Reset registers */ #define PFGEN_RTRIG 0x08407000 @@ -133,7 +133,7 @@ #define PFGEN_RTRIG_IMCR_M BIT(2) #define PFGEN_RSTAT 0x08407008 /* PFR Status */ #define PFGEN_RSTAT_PFR_STATE_S 0 -#define PFGEN_RSTAT_PFR_STATE_M IDPF_M(0x3, PFGEN_RSTAT_PFR_STATE_S) +#define PFGEN_RSTAT_PFR_STATE_M GENMASK(1, 0) #define PFGEN_CTRL 0x0840700C #define PFGEN_CTRL_PFSWR BIT(0) diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h index aec6422c15..c39930654a 100644 --- a/drivers/common/idpf/base/idpf_lan_txrx.h +++ b/drivers/common/idpf/base/idpf_lan_txrx.h @@ -59,65 +59,54 @@ enum idpf_rss_hash { BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP)) /* For idpf_splitq_base_tx_compl_desc */ -#define IDPF_TXD_COMPLQ_GEN_S 15 +#define IDPF_TXD_COMPLQ_GEN_S 15 #define IDPF_TXD_COMPLQ_GEN_M BIT_ULL(IDPF_TXD_COMPLQ_GEN_S) #define IDPF_TXD_COMPLQ_COMPL_TYPE_S 11 -#define IDPF_TXD_COMPLQ_COMPL_TYPE_M \ - IDPF_M(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S) -#define IDPF_TXD_COMPLQ_QID_S 0 -#define IDPF_TXD_COMPLQ_QID_M IDPF_M(0x3FFUL, IDPF_TXD_COMPLQ_QID_S) +#define IDPF_TXD_COMPLQ_COMPL_TYPE_M GENMASK_ULL(13, 11) +#define IDPF_TXD_COMPLQ_QID_S 0 +#define IDPF_TXD_COMPLQ_QID_M GENMASK_ULL(9, 0) /* For base mode TX descriptors */ -#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S 23 -#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S) -#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S 19 -#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M \ - (0xFULL << IDPF_TXD_CTX_QW0_TUNN_DECTTL_S) -#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S 12 -#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M \ - (0X7FULL << IDPF_TXD_CTX_QW0_TUNN_NATLEN_S) +#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S 23 +#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M \ + BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S) +#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S 19 +#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M GENMASK_ULL(22, 19) +#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S 12 +#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M GENMASK_ULL(18, 12) #define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S 11 -#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \ +#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \ BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S) #define IDPF_TXD_CTX_EIP_NOINC_IPID_CONST \ IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M -#define IDPF_TXD_CTX_QW0_TUNN_NATT_S 9 -#define IDPF_TXD_CTX_QW0_TUNN_NATT_M (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S) -#define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_NATT_S) -#define IDPF_TXD_CTX_GRE_TUNNELING (0x2ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S) +#define IDPF_TXD_CTX_QW0_TUNN_NATT_S 9 +#define IDPF_TXD_CTX_QW0_TUNN_NATT_M GENMASK_ULL(10, 9) +#define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(9) +#define IDPF_TXD_CTX_GRE_TUNNELING BIT_ULL(10) #define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S 2 -#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M \ - (0x3FULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S) -#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S 0 -#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M \ - (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S) - -#define IDPF_TXD_CTX_QW1_MSS_S 50 -#define IDPF_TXD_CTX_QW1_MSS_M \ - IDPF_M(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S) -#define IDPF_TXD_CTX_QW1_TSO_LEN_S 30 -#define IDPF_TXD_CTX_QW1_TSO_LEN_M \ - IDPF_M(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S) -#define IDPF_TXD_CTX_QW1_CMD_S 4 -#define IDPF_TXD_CTX_QW1_CMD_M \ - IDPF_M(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S) -#define IDPF_TXD_CTX_QW1_DTYPE_S 0 -#define IDPF_TXD_CTX_QW1_DTYPE_M \ - IDPF_M(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S) -#define IDPF_TXD_QW1_L2TAG1_S 48 -#define IDPF_TXD_QW1_L2TAG1_M \ - IDPF_M(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S) -#define IDPF_TXD_QW1_TX_BUF_SZ_S 34 -#define IDPF_TXD_QW1_TX_BUF_SZ_M \ - IDPF_M(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S) -#define IDPF_TXD_QW1_OFFSET_S 16 -#define IDPF_TXD_QW1_OFFSET_M \ - IDPF_M(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S) -#define IDPF_TXD_QW1_CMD_S 4 -#define IDPF_TXD_QW1_CMD_M IDPF_M(0xFFFUL, IDPF_TXD_QW1_CMD_S) -#define IDPF_TXD_QW1_DTYPE_S 0 -#define IDPF_TXD_QW1_DTYPE_M IDPF_M(0xFUL, IDPF_TXD_QW1_DTYPE_S) +#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M GENMASK_ULL(7, 2) +#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S 0 +#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M GENMASK_ULL(1, 0) + +#define IDPF_TXD_CTX_QW1_MSS_S 50 +#define IDPF_TXD_CTX_QW1_MSS_M GENMASK_ULL(63, 50) +#define IDPF_TXD_CTX_QW1_TSO_LEN_S 30 +#define IDPF_TXD_CTX_QW1_TSO_LEN_M GENMASK_ULL(47, 30) +#define IDPF_TXD_CTX_QW1_CMD_S 4 +#define IDPF_TXD_CTX_QW1_CMD_M GENMASK_ULL(15, 4) +#define IDPF_TXD_CTX_QW1_DTYPE_S 0 +#define IDPF_TXD_CTX_QW1_DTYPE_M GENMASK_ULL(3, 0) +#define IDPF_TXD_QW1_L2TAG1_S 48 +#define IDPF_TXD_QW1_L2TAG1_M GENMASK_ULL(63, 48) +#define IDPF_TXD_QW1_TX_BUF_SZ_S 34 +#define IDPF_TXD_QW1_TX_BUF_SZ_M GENMASK_ULL(47, 34) +#define IDPF_TXD_QW1_OFFSET_S 16 +#define IDPF_TXD_QW1_OFFSET_M GENMASK_ULL(33, 16) +#define IDPF_TXD_QW1_CMD_S 4 +#define IDPF_TXD_QW1_CMD_M GENMASK_ULL(15, 4) +#define IDPF_TXD_QW1_DTYPE_S 0 +#define IDPF_TXD_QW1_DTYPE_M GENMASK_ULL(3, 0) /* TX Completion Descriptor Completion Types */ #define IDPF_TXD_COMPLT_ITR_FLUSH 0 @@ -168,10 +157,10 @@ enum idpf_tx_desc_len_fields { IDPF_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ }; -#define IDPF_TXD_QW1_MACLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S) -#define IDPF_TXD_QW1_IPLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S) -#define IDPF_TXD_QW1_L4LEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) -#define IDPF_TXD_QW1_FCLEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) +#define IDPF_TXD_QW1_MACLEN_M GENMASK_ULL(6, 0) +#define IDPF_TXD_QW1_IPLEN_M GENMASK_ULL(13, 7) +#define IDPF_TXD_QW1_L4LEN_M GENMASK_ULL(17, 14) +#define IDPF_TXD_QW1_FCLEN_M GENMASK_ULL(17, 14) enum idpf_tx_base_desc_cmd_bits { IDPF_TX_DESC_CMD_EOP = 0x0001, @@ -237,11 +226,10 @@ struct idpf_flex_tx_desc { __le64 buf_addr; /* Packet buffer address */ struct { __le16 cmd_dtype; -#define IDPF_FLEX_TXD_QW1_DTYPE_S 0 -#define IDPF_FLEX_TXD_QW1_DTYPE_M \ - IDPF_M(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S) +#define IDPF_FLEX_TXD_QW1_DTYPE_S 0 +#define IDPF_FLEX_TXD_QW1_DTYPE_M GENMASK(4, 0) #define IDPF_FLEX_TXD_QW1_CMD_S 5 -#define IDPF_FLEX_TXD_QW1_CMD_M IDPF_M(0x7FFUL, IDPF_TXD_QW1_CMD_S) +#define IDPF_FLEX_TXD_QW1_CMD_M GENMASK(15, 5) union { /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_DATA_(0x03) */ u8 raw[4]; @@ -383,9 +371,9 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_MSS_RT_0 0 #define IDPF_TXD_FLEX_CTX_MSS_RT_M 0x3FFF #define IDPF_TXD_FLEX_CTX_FTYPE_S 14 -#define IDPF_TXD_FLEX_CTX_FTYPE_VF IDPF_M(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S) -#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV IDPF_M(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S) -#define IDPF_TXD_FLEX_CTX_FTYPE_PF IDPF_M(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S) +#define IDPF_TXD_FLEX_CTX_FTYPE_VF 0 +#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV BIT(14) +#define IDPF_TXD_FLEX_CTX_FTYPE_PF BIT(15) u8 hdr_len; u8 ptag; } tso; @@ -402,10 +390,10 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_QW1_PASID_M 0xFFFFF #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S 36 #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID \ - IDPF_M(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S) + BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S) #define IDPF_TXD_FLEX_CTX_QW1_TPH_S 37 -#define IDPF_TXD_FLEX_CTX_QW1_TPH \ - IDPF_M(0x1, IDPF_TXD_FLEX_CTX_TPH_S) +#define IDPF_TXD_FLEX_CTX_QW1_TPH \ + BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_TPH_S) #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_S 38 #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_M 0xF /* The following are only valid for DTYPE = 0x09 and DTYPE = 0x0A */ @@ -413,7 +401,7 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_M 0x1FFFFF #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S 63 #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VALID \ - IDPF_M(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S) + BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S) /* The following are only valid for DTYPE = 0x0D and DTYPE = 0x0E */ #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_S 48 #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_M 0xFF diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index 2caa07fdfd..eae28478ff 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -9,7 +9,7 @@ /* Reset */ #define VFGEN_RSTAT 0x00008800 #define VFGEN_RSTAT_VFR_STATE_S 0 -#define VFGEN_RSTAT_VFR_STATE_M IDPF_M(0x3, VFGEN_RSTAT_VFR_STATE_S) +#define VFGEN_RSTAT_VFR_STATE_M GENMASK(1, 0) /* Control(VF Mailbox) Queue */ #define VF_BASE 0x00006000 @@ -18,7 +18,7 @@ #define VF_ATQBAH (VF_BASE + 0x1800) #define VF_ATQLEN (VF_BASE + 0x0800) #define VF_ATQLEN_ATQLEN_S 0 -#define VF_ATQLEN_ATQLEN_M IDPF_M(0x3FF, VF_ATQLEN_ATQLEN_S) +#define VF_ATQLEN_ATQLEN_M GENMASK(9, 0) #define VF_ATQLEN_ATQVFE_S 28 #define VF_ATQLEN_ATQVFE_M BIT(VF_ATQLEN_ATQVFE_S) #define VF_ATQLEN_ATQOVFL_S 29 @@ -29,14 +29,14 @@ #define VF_ATQLEN_ATQENABLE_M BIT(VF_ATQLEN_ATQENABLE_S) #define VF_ATQH (VF_BASE + 0x0400) #define VF_ATQH_ATQH_S 0 -#define VF_ATQH_ATQH_M IDPF_M(0x3FF, VF_ATQH_ATQH_S) +#define VF_ATQH_ATQH_M GENMASK(9, 0) #define VF_ATQT (VF_BASE + 0x2400) #define VF_ARQBAL (VF_BASE + 0x0C00) #define VF_ARQBAH (VF_BASE) #define VF_ARQLEN (VF_BASE + 0x2000) #define VF_ARQLEN_ARQLEN_S 0 -#define VF_ARQLEN_ARQLEN_M IDPF_M(0x3FF, VF_ARQLEN_ARQLEN_S) +#define VF_ARQLEN_ARQLEN_M GENMASK(9, 0) #define VF_ARQLEN_ARQVFE_S 28 #define VF_ARQLEN_ARQVFE_M BIT(VF_ARQLEN_ARQVFE_S) #define VF_ARQLEN_ARQOVFL_S 29 @@ -47,7 +47,7 @@ #define VF_ARQLEN_ARQENABLE_M BIT(VF_ARQLEN_ARQENABLE_S) #define VF_ARQH (VF_BASE + 0x1400) #define VF_ARQH_ARQH_S 0 -#define VF_ARQH_ARQH_M IDPF_M(0x1FFF, VF_ARQH_ARQH_S) +#define VF_ARQH_ARQH_M GENMASK(12, 0) #define VF_ARQT (VF_BASE + 0x1000) /* Transmit queues */ @@ -69,7 +69,7 @@ #define VF_INT_DYN_CTL0_INTENA_S 0 #define VF_INT_DYN_CTL0_INTENA_M BIT(VF_INT_DYN_CTL0_INTENA_S) #define VF_INT_DYN_CTL0_ITR_INDX_S 3 -#define VF_INT_DYN_CTL0_ITR_INDX_M IDPF_M(0x3, VF_INT_DYN_CTL0_ITR_INDX_S) +#define VF_INT_DYN_CTL0_ITR_INDX_M GENMASK(4, 3) #define VF_INT_DYN_CTLN(_INT) (0x00003800 + ((_INT) * 4)) #define VF_INT_DYN_CTLN_EXT(_INT) (0x00070000 + ((_INT) * 4)) #define VF_INT_DYN_CTLN_INTENA_S 0 @@ -79,7 +79,7 @@ #define VF_INT_DYN_CTLN_SWINT_TRIG_S 2 #define VF_INT_DYN_CTLN_SWINT_TRIG_M BIT(VF_INT_DYN_CTLN_SWINT_TRIG_S) #define VF_INT_DYN_CTLN_ITR_INDX_S 3 -#define VF_INT_DYN_CTLN_ITR_INDX_M IDPF_M(0x3, VF_INT_DYN_CTLN_ITR_INDX_S) +#define VF_INT_DYN_CTLN_ITR_INDX_M GENMASK(4, 3) #define VF_INT_DYN_CTLN_INTERVAL_S 5 #define VF_INT_DYN_CTLN_INTERVAL_M BIT(VF_INT_DYN_CTLN_INTERVAL_S) #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S 24 @@ -113,7 +113,7 @@ (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) #define VF_INT_ITRN_MAX_INDEX 2 #define VF_INT_ITRN_INTERVAL_S 0 -#define VF_INT_ITRN_INTERVAL_M IDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S) +#define VF_INT_ITRN_INTERVAL_M GENMASK(11, 0) #define VF_INT_PBA_CLEAR 0x00008900 #define VF_INT_ICR0_ENA1 0x00005000 diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h index 2a817a9807..74a376cb13 100644 --- a/drivers/common/idpf/base/idpf_osdep.h +++ b/drivers/common/idpf/base/idpf_osdep.h @@ -48,6 +48,13 @@ typedef struct idpf_lock idpf_lock; #define IDPF_M(m, s) ((m) << (s)) +#define BITS_PER_LONG (8 * sizeof(long)) +#define BITS_PER_LONG_LONG (8 * sizeof(long long)) +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#define GENMASK_ULL(h, l) \ + (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + #ifndef ETH_ADDR_LEN #define ETH_ADDR_LEN 6 #endif From patchwork Wed Sep 20 06:22:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 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mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Pavan Kumar Linga Subject: [PATCH v5 10/11] common/idpf/base: remove unused Tx descriptor types Date: Wed, 20 Sep 2023 14:22:35 +0800 Message-Id: <20230920062236.375308-11-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove the unused TX descriptor types and mark them as reserved. Signed-off-by: Pavan Kumar Linga Signed-off-by: Simei Su Acked-by: Beilei Xing --- drivers/common/idpf/base/idpf_lan_txrx.h | 136 ++--------------------- 1 file changed, 12 insertions(+), 124 deletions(-) diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h index c39930654a..c9eaeb5d3f 100644 --- a/drivers/common/idpf/base/idpf_lan_txrx.h +++ b/drivers/common/idpf/base/idpf_lan_txrx.h @@ -119,19 +119,19 @@ enum idpf_rss_hash { enum idpf_tx_desc_dtype_value { IDPF_TX_DESC_DTYPE_DATA = 0, IDPF_TX_DESC_DTYPE_CTX = 1, - IDPF_TX_DESC_DTYPE_REINJECT_CTX = 2, - IDPF_TX_DESC_DTYPE_FLEX_DATA = 3, - IDPF_TX_DESC_DTYPE_FLEX_CTX = 4, + /* DTYPE 2 is reserved + * DTYPE 3 is free for future use + * DTYPE 4 is reserved + */ IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX = 5, - IDPF_TX_DESC_DTYPE_FLEX_TSYN_L2TAG1 = 6, + /* DTYPE 6 is reserved */ IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2 = 7, - IDPF_TX_DESC_DTYPE_FLEX_TSO_L2TAG2_PARSTAG_CTX = 8, - IDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_SA_TSO_CTX = 9, - IDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_SA_CTX = 10, - IDPF_TX_DESC_DTYPE_FLEX_L2TAG2_CTX = 11, + /* DTYPE 8, 9 are free for future use + * DTYPE 10 is reserved + * DTYPE 11 is free for future use + */ IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE = 12, - IDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_TSO_CTX = 13, - IDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_CTX = 14, + /* DTYPE 13, 14 are free for future use */ /* DESC_DONE - HW has completed write-back of descriptor */ IDPF_TX_DESC_DTYPE_DESC_DONE = 15, }; @@ -225,28 +225,18 @@ enum idpf_tx_flex_desc_cmd_bits { struct idpf_flex_tx_desc { __le64 buf_addr; /* Packet buffer address */ struct { - __le16 cmd_dtype; #define IDPF_FLEX_TXD_QW1_DTYPE_S 0 #define IDPF_FLEX_TXD_QW1_DTYPE_M GENMASK(4, 0) #define IDPF_FLEX_TXD_QW1_CMD_S 5 #define IDPF_FLEX_TXD_QW1_CMD_M GENMASK(15, 5) + __le16 cmd_dtype; union { - /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_DATA_(0x03) */ - u8 raw[4]; - - /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSYN_L2TAG1 (0x06) */ - struct { - __le16 l2tag1; - u8 flex; - u8 tsync; - } tsync; - /* DTYPE=IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2 (0x07) */ struct { __le16 l2tag1; __le16 l2tag2; } l2tags; - } flex; + }; __le16 buf_size; } qw1; }; @@ -296,16 +286,6 @@ struct idpf_flex_tx_tso_ctx_qw { }; union idpf_flex_tx_ctx_desc { - /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_CTX (0x04) */ - struct { - u8 qw0_flex[8]; - struct { - __le16 cmd_dtype; - __le16 l2tag1; - u8 qw1_flex[4]; - } qw1; - } gen; - /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX (0x05) */ struct { struct idpf_flex_tx_tso_ctx_qw qw0; @@ -314,98 +294,6 @@ union idpf_flex_tx_ctx_desc { u8 flex[6]; } qw1; } tso; - - /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSO_L2TAG2_PARSTAG_CTX (0x08) */ - struct { - struct idpf_flex_tx_tso_ctx_qw qw0; - struct { - __le16 cmd_dtype; - __le16 l2tag2; - u8 flex0; - u8 ptag; - u8 flex1[2]; - } qw1; - } tso_l2tag2_ptag; - - /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_L2TAG2_CTX (0x0B) */ - struct { - u8 qw0_flex[8]; - struct { - __le16 cmd_dtype; - __le16 l2tag2; - u8 flex[4]; - } qw1; - } l2tag2; - - /* DTYPE = IDPF_TX_DESC_DTYPE_REINJECT_CTX (0x02) */ - struct { - struct { - __le32 sa_domain; -#define IDPF_TXD_FLEX_CTX_SA_DOM_M 0xFFFF -#define IDPF_TXD_FLEX_CTX_SA_DOM_VAL 0x10000 - __le32 sa_idx; -#define IDPF_TXD_FLEX_CTX_SAIDX_M 0x1FFFFF - } qw0; - struct { - __le16 cmd_dtype; - __le16 txr2comp; -#define IDPF_TXD_FLEX_CTX_TXR2COMP 0x1 - __le16 miss_txq_comp_tag; - __le16 miss_txq_id; - } qw1; - } reinjection_pkt; }; -/* Host Split Context Descriptors */ -struct idpf_flex_tx_hs_ctx_desc { - union { - struct { - __le32 host_fnum_tlen; -#define IDPF_TXD_FLEX_CTX_TLEN_S 0 -/* see IDPF_TXD_FLEX_CTX_TLEN_M for mask definition */ -#define IDPF_TXD_FLEX_CTX_FNUM_S 18 -#define IDPF_TXD_FLEX_CTX_FNUM_M 0x7FF -#define IDPF_TXD_FLEX_CTX_HOST_S 29 -#define IDPF_TXD_FLEX_CTX_HOST_M 0x7 - __le16 ftype_mss_rt; -#define IDPF_TXD_FLEX_CTX_MSS_RT_0 0 -#define IDPF_TXD_FLEX_CTX_MSS_RT_M 0x3FFF -#define IDPF_TXD_FLEX_CTX_FTYPE_S 14 -#define IDPF_TXD_FLEX_CTX_FTYPE_VF 0 -#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV BIT(14) -#define IDPF_TXD_FLEX_CTX_FTYPE_PF BIT(15) - u8 hdr_len; - u8 ptag; - } tso; - struct { - u8 flex0[2]; - __le16 host_fnum_ftype; - u8 flex1[3]; - u8 ptag; - } no_tso; - } qw0; - - __le64 qw1_cmd_dtype; -#define IDPF_TXD_FLEX_CTX_QW1_PASID_S 16 -#define IDPF_TXD_FLEX_CTX_QW1_PASID_M 0xFFFFF -#define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S 36 -#define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID \ - BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S) -#define IDPF_TXD_FLEX_CTX_QW1_TPH_S 37 -#define IDPF_TXD_FLEX_CTX_QW1_TPH \ - BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_TPH_S) -#define IDPF_TXD_FLEX_CTX_QW1_PFNUM_S 38 -#define IDPF_TXD_FLEX_CTX_QW1_PFNUM_M 0xF -/* The following are only valid for DTYPE = 0x09 and DTYPE = 0x0A */ -#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_S 42 -#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_M 0x1FFFFF -#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S 63 -#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VALID \ - BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S) -/* The following are only valid for DTYPE = 0x0D and DTYPE = 0x0E */ -#define IDPF_TXD_FLEX_CTX_QW1_FLEX0_S 48 -#define IDPF_TXD_FLEX_CTX_QW1_FLEX0_M 0xFF -#define IDPF_TXD_FLEX_CTX_QW1_FLEX1_S 56 -#define IDPF_TXD_FLEX_CTX_QW1_FLEX1_M 0xFF -}; #endif /* _IDPF_LAN_TXRX_H_ */ From patchwork Wed Sep 20 06:22:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131668 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 25C10425E9; Wed, 20 Sep 2023 08:23:29 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EDC7E40E68; Wed, 20 Sep 2023 08:22:45 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id E67B240E64 for ; Wed, 20 Sep 2023 08:22:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695190964; x=1726726964; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7ORP+AYEhkVt6MSloa7zQXfJFZUPM413xmhs000g5Bo=; b=elsAuUZDp9YSZ9Erl+ZKZWeI0C1ogAqy2Mvtg3lq1QEnK87WcgaCPp0w PKm8YUmKupHTA402Z3jB8EFMqhgYqNTKrMk6ypjZgtimiVmDvxqCynQZa GqiX3c9acfHkHl65UFhEG3tUBFDCTmDs1QQp83HOIfUhyHE0O5t0Y4NBD +143EKatZP8IpnFLyJ/G4Kaw9kCZ+mfzhGKHFqMAzSWdP/TtB4oSPd0Hy NTFx9SuAarNVCQ3OH0ARrwwYSzmcBaaS3nnYmAbzrU1H5Fx/Nt4yJl3um OZ/yRmoUlGU4S3Nejl59bt7m72AivexUXRhoKlzPDRGl3DGoa7udaOYTI w==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="466453306" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="466453306" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 23:22:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="920154780" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="920154780" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:41 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su Subject: [PATCH v5 11/11] common/idpf/base: update version Date: Wed, 20 Sep 2023 14:22:36 +0800 Message-Id: <20230920062236.375308-12-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920062236.375308-1-simei.su@intel.com> References: <20230918021130.192982-1-simei.su@intel.com> <20230920062236.375308-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update README Signed-off-by: Simei Su Acked-by: Beilei Xing --- drivers/common/idpf/base/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/idpf/base/README b/drivers/common/idpf/base/README index 693049c057..ff26f736ec 100644 --- a/drivers/common/idpf/base/README +++ b/drivers/common/idpf/base/README @@ -6,7 +6,7 @@ Intel® IDPF driver ================== This directory contains source code of BSD-3-Clause idpf driver of version -2023.02.23 released by the team which develops basic drivers for Intel IPU. +2023.07.25 released by the team which develops basic drivers for Intel IPU. The directory of base/ contains the original source package. This driver is valid for the product(s) listed below